Chapter 10 Transistor amplifier design

10.1 Stability considerations

unconditionally stable, conditionally stable, stability factor, source
stability circle, load stability circle
10.2 Amplifier design for maximum gain
unilateral case, bilateral case, simultaneously conjugate match,
unilateral figure of merit
10.3 Constant gain circles
unilateral case, bilateral case
10.4 Constant noise figure circles
10.5 Broadband amplifiers
negative feedback amplifier, balanced amplifier, traveling wave
amplifier
10.6 Small signal equivalent circuit models of transistors
BJT, MESFET
10.7 DC bias circuits for transistors

10-1 微波工程講義
10.1 Stability considerations
Basics
1. Unconditionally stable Zs
two-port
ZL
for all Γs < 1, ΓL < 1 Vs network
 S 21ΓL S12
Γ
 in = S + <1 Γs Γin, Γout, ΓL
1 − S 22 ΓL
11
 Zin Zout

 Γ = S + S 21Γs S12 < 1
 out 22
1 − S11Γs

 1 − S11 − S 22 + ∆
2 2 2

k = >1
⇔ 2 S12 S 21
 ∆ = S S − S S <1
 11 22 12 21

2. Conditionally stable: there exists some Γs and ΓL, such that one
or both of these conditions violated.

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Discussion
1. Stability circles
S 12 S 21 Γ L
Γin = S 11 + = 1 → load stability circle ΓL − C L = rL
1 − S 22 Γ L

( S 22 − ∆ S 11* ) * S 12 S 21
in Γ L - plane with C L = , rL =
− ∆ − ∆
2 2 2 2
S 22 S 22
S 12 S 21 Γ s
Γout = S 22 + = 1 → source stability circle Γs − C s = rs
1 − S 11 Γ s

( S 11 − ∆ S 22
* *
) S 12 S 21
in Γ s - plane with C s = , rs =
− ∆ − ∆
2 2 2 2
S 11 S 11

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2. If ΓL=0→Γin=S11, the center of Smith chart represent a stable
point if ∣S11∣<1
|S11|<1 |Γin|=1 |S11|>1
ΓL-plane ΓL-plane
|Γin|<1
CL RL

|Γin|<1

3. If Γs=0→Γout=S22, the center of Smith chart represent a stable

point if ∣S22∣<1
|S22|<1 |Γout|=1 |S22|>1
Γs-plane Γs-plane
|Γout|<1
Cs Rs

|Γout|<1
10-4 微波工程講義
4. Ex.10.1 A transistor has S11=0.894∠-60.6°, S12=0.02 ∠62.4,
S21=3.122∠123.6°, S22=0.781∠-27.6° at 2GHz

1 − S11 − S 22 + ∆
2 2 2

∆ = S11 S 22 − S12 S 21 = 0.6964 < 1, k = = 0.607 < 1

2 S12 S 21
C L = 1.36∠46.7°, rL = 0.5
C s = 1.13∠68.5°, rs = 0.2

rs

Cs CL rL

stable region

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10.2 Amplifier design for maximum gain
Basics

Input [S] Output

Zo
matching Go matching
circuit Gs circuit GL

Γs Γin Γout ΓL
1.Unilateral case: S12=0
stability condition: ∣S11∣<1, ∣S22∣<1
maximum gain: Γs=S11*, ΓL=S22*
unilateral transducer gain
1 − Γs 1 − ΓL
2 2
1 1
GTU = → GTU max =
2 2
S 21 S 21
1 − S11Γs 1 − S 22 ΓL 1 − S11 1 − S 22
2 2 2 2

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2. Bilateral case (simultaneously conjugate match)
if ∆ < 1, K > 1
→ input and output simultaneously conjugate match Γin = Γs* , Γout = ΓL*
1 − ΓL 1 − Γs
2 2
1 1
→ GT = GT max = =
2 2
S 21 S 21
1 − Γs 1 − S 22 ΓL 1 − ΓL 1 − S11Γs
2 2 2 2

S 21 S
= ( K − K 2 − 1), GMSG = 21 : maximum stable gain as k = 1
S12 S12

B2 − B22 − 4 C 2
2
S12 S 21ΓL
Γs* = Γin = S11 + → ΓML =
1 − S 22 ΓL 2C 2

B1 − B12 − 4 C1
2
S12 S 21Γs
ΓL* = Γout = S 22 + → ΓMs =
1 − S11Γs 2C1
B1 = 1 + S11 − S 22 − ∆ , B2 = 1 + S 22 − S11 − ∆
2 2 2 2 2 2

C1 = S11 − ∆S 22
*
, C 2 = S 22 − ∆S11*
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3. Unilateral figure of merit
1 GT 1
< <
(1 + U ) 2 GTU (1 − U ) 2
S11 S 21 S12 S 22
U=
(1 − S11 )(1 − S 22 )
2 2

Discussion
1. Linear amplifier design procedure
(1) if |∆|<1, K>1, use input and output simultaneously conjugate
matches for GTmax
(2) if K<1, plot source and load stability circles to see if input and
output simultaneously conjugate matches possible, otherwise select
the proper Γs and ΓL for gain or noise figure considerations (to be
discussed in the following sections).

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2. Ex.10.2 A transistor has (Zo=50Ω), S11=0.606∠-155°, S12=0,
S21=6∠180°, S22=0.48∠-20° at 1GHz → design an amplifier to
give GTUmax
S11 = 0.606 < 1, S 22 = 0.48 < 1
∗
Γs = S11 = 0.606∠155°, ΓL = S∗22 = 0.48∠20°
1 1 1 1
GTU max = =
2 2
S 21 6
1 − S11 1 − S 22 1 − 0.606 1 − 0.48
2 2 2 2

= 1.58 × 36 × 1.3 = 73.9 = 18.69dB

1: y=j1.7, or z=-j0.45
2: z=j0.2
ΓL 3: z=-j1.38, or y=j0.48
Γs 2 4 4: y=-j0.16

3
1
Γs ΓL

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3. Ex.10.2 A transistor has (Zo=50Ω), S11=0.614∠-167.4°,
S12=0.046∠65°, S21=2.187∠32.4°, S22=0.716∠-83° at 6GHz →
design an amplifier to give GTmax

∆ = 0.3419 < 1, K = 1.1296 > 1

 B − B 2
− 4 C
2
Γ = Γ * → Γ = 2 2 2
= 0.8673∠169.76°
 in s ML
2C 2
→
− −
2
 B B 2
4 C
Γ = Γ → Γ = = 0.9011∠84.48°
* 1 1 1
 out L Ms
 2C1
S 21
→ GT max = ( K − K 2 − 1) = 28.728 = 14.58dB
S12

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 3 ΓML
2
4 1: ΓMS=0.8673∠169.76°
G ΓMS 1 2: y=-j2.7
3: ΓML=0.9011∠84.48°
4: z=j3.4

0.093λ
0.194λ
0.065λ

Ζo Γs ΓL Ζo

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4. Ex.10.4 transistor A: S11=0.45∠150°, S12=0.01∠-10°,
S21=2.05∠10°, S22=0.4∠-10°
transistor B: S11=0.641∠-171.3°, S12=0.057∠16.3°,
S21=2.058∠28.5°, S22=0.572∠-95.7°→compare their Us

S11 S 21 S12 S 22 U A = 0.00551

U= →
(1 − S11 )(1 − S 22  U B = 0.1085
2 2
)
 GT
 0.9891 < < 1.0055
1 GT 1  GTU
< < → 
A
(1 + U ) 2 GTU (1 − U ) 2 0.8238 < GT
< 1.2582
 GTU
 B

 GT
− 0.0476 dB < < 0.0238dB
 GTU
→ A

− 0.8948dB < GT
< 0.9976 dB
 GTU
 B

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10.3 Constant gain circles
Basics
1. Unilateral case (S12=0)
1 − Γs 1 − ΓL
2 2

GTU = = G s Go G L
2
S 21
1 − S11 Γs 1 − S 22 ΓL
2 2

1 − Γs 1 − ΓL
2 2
1 1
Gs = , G s max = , GL = , G L max =
1 − S 11 Γs 1 − S 11 1 − S 22 ΓL 1 − S 22
2 2 2 2

Gs
gs ≡ → constant gain circles in ΓS plane ΓS − d s = R s
G s max
1 − g s (1 − S11 )
2
g s S11*
ds = , Rs =
1 − (1 − g s ) S11 1 − (1 − g s ) S 11
2 2

GL
gL ≡ → constant gain circles in ΓL plane ΓL − d L = R L
G L max
1 − g L (1 − S 22 )
2
g L S 22
*
dL = , RL =
1 − (1 − g L ) S 22 1 − (1 − g L ) S 22
2 2

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2. Bilateral case (S12≠0)
(1) Unconditionally stable case, use GP or GA
1 − ΓL
2
1 S12 S 21 ΓL S − ∆ΓL
GP = , Γin = S11 + = 11
2
S 21
1 − Γin
2
1 − S 22 ΓL
2
1 − S 22 ΓL 1 − S 22 ΓL

G P = S 21 g P
2

1 − ΓL
2

gP ≡ → constant gain circles in ΓL plane ΓL − c P = R P

1 − S 22 ΓL − S11 − ∆ΓL
2 2

1 − 2 K S12 S 21 g P + S 12 S 21 g P2
2
g P C 2*
cP = , RP = , C 2 = S 22 − S 11∗ ∆
1 + g P ( S 22 −∆ ) 1 + g P ( S 22 −∆ )
2 2 2 2

RP = 0
1
→ g P = g P max = ( K − K 2 − 1)
S 12 S 21
S 21
G P = G P max = ( K − K 2 − 1) = GT max
S 12

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 1 − Γs
2
1 S12 S 21 Γs S 22 − ∆Γs
GA = , Γout = S 22 + =
2
S 21
1 − S11 Γs
2
1 − Γout
2
1 − S 11 Γs 1 − S 11 Γs

G P = S 21 g A
2

1 − Γs
2

gA ≡ → constant gain circles in Γs plane Γs − c s = R s

1 − S 11 Γs − S 22 − ∆Γs
2 2

1 − 2 K S12 S 21 g A + S 12 S 21 g A2
2
g A C1* ∗
cs = , Rs = , C1 = S 11 − S 22 ∆
1 + g A ( S 11 − ∆ ) 1 + g A ( S 11 − ∆ )
2 2 2 2

Rs = 0
1
→ g A = g A max = ( K − K 2 − 1)
S12 S 21
S 21
G A = G A max = ( K − K 2 − 1) = GT max
S 12

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 (2) Potentially unstable case
use GP to plot constant gain circles in ΓL-plane and plot load stability
circles → properly select ΓL, calculate Γs= Γ∗in
use GA to plot constant gain circles in Γs-plane and plot source stability
circles → properly select Γs, calculate ΓL= Γ∗out
Discussion
1. Ex. 10.5 A MESFET with S-parameters (Zo=50Ω)
S11 S21 S12 S22
3GHz 0.8∠-90° 2.8∠100° 0 0.66∠-50°
4GHz 0.75∠-120° 2.5∠80° 0 0.6∠-70°
5GHz 0.71∠-140° 2.3∠60° 0 0.68∠-85°
→ plot constant gain circles @4GHz for GL=0, 1dB, and Gs=2, 3dB
design an amplifier of 11dB gain
1 − Γs 1 − ΓL
2 2

GTU = = G s Go G L
2
S 21
1 − S11 Γs 1 − S 22 ΓL
2 2

1 1
@ 4GHz , G s max = = 2.288 = 3.59 dB , G L max = = 1.5625 = 1.92 dB
1 − S11 1 − S 22
2 2

G o = S 21 = 6.25 = 7.96 dB , GTU max = 3.59 + 7.96 + 1.92 = 13 .47 dB

2

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 ­ 3dB = 2 ­0.875 ­0.706 ∠120 ° ­0.166
GS = ® → gS = ® → dS = ® , RS = ®
¯2dB = 1.58 ¯ 0.691 ¯0.627 ∠120 ° ¯0.294
­1dB = 1.26 ­0.8064 ­0.52∠70° ­0.303
GL = ® → gL = ® → dL = ® , RL = ®
¯ 0 dB = 1 ¯ 0 . 64 ¯ 0 . 44 ∠ 70 ° ¯ 0.44

chose GTU(4GHz) 11dB=2dB+8dB+1dB to design the circuit

→ GTU(3GHz)=7.33dB, GTU(5GHz)=6.96dB

GL=1dB
Gs=2dB GL=0dB
0.044λ
Gs=3dB 0.09λ

B 0.183λ
A 0.431λ

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2. Ex. 10.6 A GaAs FET with S-parameters (Zo=50Ω, 1GHz)
S11=2.27∠-120°, S21=4∠50°, S12=0, S22=0.6∠-80°
→ (1) calculate Zin, plot unstable region in Γs-plane
(2) plot constant gain circles for Gs=3, 5dB
(3) find Zs for Gs=3dB with maximum degree of stable, determine ZL to
give maximum GL, then design the amplifier
(4) calculate GTU
Z in − Z o
(1) S11 = 2.27 ∠ − 120 ° = Γin = → Z in = −24.5 − j 23Ω
Z in + Z o
→ R s < 24.5Ω to be unstable

rs=0.49

Γs-plane

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 ­5dB = 3.16 ­− 13.13 ­0.45∠120 ° ­0.2174
( 2 )G S = ® → gS = ® → dS = ® , RS = ®
¯ 3dB = 2 ¯ − 8.3 ¯ 0.4∠120 ° ¯0.2698

C
Gs=3dB
0.067λ
Gs=5dB A 0.436λ
0.036λ
0.342λ

(3) Select A for Zs to give a maximum possible Rs

A : Γs = 0.24∠76° → Z s = 50 + j 25
∗
For maximum GL, select C: ΓL = S 22 = 0.6∠80° → Z L = 27 + j 51.5
1
( 4)G L max = = 1 . 56 , G TU = 2 × 4 2
× 1.56 = 50 = 17 dB
1 − S 22
2

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 3. Ex. 10.7 A GaAs FET with S-parameters (Zo=50Ω, 6GHz)
S11=0.641∠-171.3°, S21=2.058∠28.5°, S12=0.057∠16.3°,
S22=0.572∠-95.7°→ design an amplifier to give GP=9dB
S 21
K = 1.5, ∆ = 0.3 → G P = G P max = ( K − K 2 − 1) = 11 .38 dB
S12
G P = 9 dB → constant gain circles in ΓL plane ΓL − c P = R P ,
c P = 0.5∠104 °, R P = 0.43
select C : Γ L = 0.36 ∠50 ° → Γin = 0.63∠ − 175 .6° → A : Γs = 0.63∠175 .6°

GP=9dB
C
A

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4. Ex. 10.8 A GaAs FET with S-parameters (Zo=50Ω, 8GHz) S11=0.5
∠-180°, S21=2.5∠70°, S12=0.08∠30°, S22=0.8∠-100°
→ design an amplifier to give GP=10dB
source stability circle C s = 1.67 ∠170 .6°, rs = 0.998
K = 0.399 , ∆ = 0.2228 → 
 load stability circle C L = 1.17 ∠97°, rL = 0.3388
G P = 10 dB → constant gain circles in ΓL plane ΓL − c P = R P ,
c P = 0.57 ∠97 .2°, R P = 0.4733
select C : Γ L = 0.1∠97 ° → Γin = 0.52 ∠ − 179 .3° → A : Γs = 0.52 ∠179 .3°

load stability circle

GP=10dB
A
C
source stability circle

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5. Ex. 10.9 A BJT with S-parameters (Zo=50Ω, 750MHz) S11=0.277∠-
59°, S21=1.92∠64°, S12=0.078∠93°, S22=0.848∠-31°
→ design an amplifier to give GTmax
K = 1.0325, ∆ = 0.3242 → simutaneou ly conjugate match
Γ MS = 0.7298 ∠135 °,Γ ML = 0.9511∠33 .85 °

6. Ex. 10.10 use the BJT in Ex.10.9 → design an amplifier to give

GP=10dB, determine Gs, GL for GPmax

G P = 10 dB → constant gain circles in ΓL plane ΓL − c P = R P , GP=10dB

c P = 0.78∠33 .8°, R P = 0.2142
select C : Γ L = 0.56 ∠34 ° → Γin = 0.3455 ∠ − 56 .45 °
A
→ A : Γs = 0.3455 ∠56 .45 °
C
G P max = 12.8dB → Γ L = 0.9511∠33 .84 ° = Γ ML
→ Γs = 0.7298 ∠135 ° = ΓMS

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10.4 Constant noise figure circles
Basics
For a two - port amplifier
2
Rn 2 4 Rn Γs − Γopt
F = Fmin + Ys − Yopt = Fmin +
Gs Z o (1 − Γ 2 ) 1 + Γ 2
s opt

noise parameter : Fmin , Yopt , Rn equivalent noise resistance of transistor

2
Γs − Γopt F − Fmin 2
N≡ = 1 + Γopt : noise figure parameter
1 − Γs
2
4 Rn / Z o
→ constant noise figure circle Γs − C NF = R NF
2
Γopt N ( N + 1) − N Γopt
C NF = , R NF =
N +1 N +1

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Discussion
1. Ex. 10.11 A BJT with S-parameters (Zo=50Ω, 1GHz) S11=0.707∠-
155°, S21=5∠180°, S12=0, S22=0.51∠-20°, Fmin=3dB, Rn=4Ω, Γopt=
=0.45∠180° → design an amplifier to give GT=16dB, F<3.5dB
GTU max = 3 + 13.98 + 1.31 = 18.29dB
G s = 1.22dB → d s = 0.56∠155°, Rs = 0.345
GTU = 16dB → 
G L = 0.78dB → d L = 0.46∠20°, R L = 0.258
F = 3.5dB → C NF = 0.3658∠180°, R NF = 0.3953
select B : Γ s , D : ΓL
Gs=1.22dB GL=0.78dB

D
F=3.5dB
Γ s ΓL
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 2. Ex. 10.12 A GaAs FET with S-parameters (Zo=50Ω, 4GHz)
S11=0.6∠-60°, S21=1.9∠81°, S12=0.05∠26°, S22=0.5∠-60°,
Fmin=1.6dB, Rn=20Ω, Γopt= =0.62∠100°
→ (1) assume S12=0, design an amplifier to give GTUmax, F<2dB
(2) repeat for S12≠0
GT
(1) K = 2.778, ∆ = 0.3713, U = 0.0594 → −0.5dB < < 0.59 dB
GTU
G TUmax = 1.938 + 5.57 + 1.25 = 8.76 dB
∗
select C : Γ L = S 22 = 0.5∠60 °
Gs=1.7dB
F = 2dB → C NF = 0.56 ∠100 °, R NF = 0.245 
 F=2dB B
 1.5dB → d s = 0.56 ∠60 °, R s = 0.2  → select A : Γ s
Gs =  
1.7 dB → d s = 0.586 ∠60°, R s = 0.15 
C

Gs=1.5dB

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( 2) use G A → constant gain circles in Γs plane Γs − c s = R s
G A = 8dB → c s = 0.527 ∠64.7°, R s = 0.234
select Γ s = 0.535 ∠90° → Γout = 0.504 ∠ − 67.8° → ΓL = 0.504 ∠67.8°

F=2dB GA=8dB
Γs
ΓL

3. Low noise amplifier design procedure:

if unconditionally stable, use GA constant gain circles and constant
noise figure circles to determine Γs , and ΓL= Γ*out
if potentionally unstable, consider source and load stability circles
in addition

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4. Ex. 10.13 A BJT with S-parameters (Zo=50Ω, 1GHz) S11=0.6∠-
130°, S21=7.12∠86°, S12=0.039∠35°, S22=0.5∠-38°, Fmin=1.3dB,
Rn=8Ω, Γopt= =0.06∠49° → design an amplifier to give 16dB
power gain, F<2.5dB
source stability circle C s = 1.74∠171 .7°, rs = 0.8566
K = 0.7667 , ∆ = 0.189 → 
 load stability circle C L = 2.16∠50.8°, rL = 1.296
G A = 16 dB → constant gain circles in Γs plane Γs − c a = R a ,
c a = 0.3542 ∠172 °, R a = 0.6731 source stability
F = 2.5 → C NF = 0.0346 ∠ 40 °, R NF = 0.65 circle
select B : Γ s = 0.13∠0° F=2.5dB
ΓL
→ Γout = 0.469 ∠ − 36 .45 ° GA=16dB
→ D : ΓL = 0.469 ∠36 .45 °

Γs
load stability
circle

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10.5 Broadband amplifiers
Basics
1. Negative feedback amplifier

β
Vi Vo
AV

Vo AV
GV = =
Vi 1 + βAV
Ao
Ao 1 + Ao β
AV = → GV =
f f
1+ j 1+ j
fc f c (1 + Ao β )
Ao
f ' c = f c (1 + Ao β ), A' o =
1 + Ao β
Ao f c = A' o f ' c

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2. Balanced amplifier

input 90° hybrid 90° hybrid

G1
∠0° ∠0°
Zo
∠-180°
G2
∠-90°
Zo ∠-90° output
∠-90°

Bandwidth is limited by the 90° hybrids and amplifier gain.

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2. Traveling wave amplifier (distributed amplifier)
TEM line “extreme wide operation bandwidth”

FET equivalent circuit

drain line

gate line

Bandwidth is limited by the FET and line loss.

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10.6 Small-signal equivalent circuit models of transistor
Basics
1. BJT rbe: due to base
C B
C doping
+ C be Cbe: due to p-n
rbe Vbe junction
B
- gme-jτVbe
E E

Vb(+) Vc(+)
Ice
Ib=+ mA

Vce

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 2. MESFET
Vg(-) Vd(+)
Ids
Vgs = 0V
D
Vgs = - 1V
G
Vgs = Vp
S
gate length
G Cgd D
S G D gate
width Ig
Ri
+ Cds
Cgs Rds
Vgs gmVgs
gate length ↓ ⇒ f ↑ -
S
gate width ↑ ⇒ power ↑

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 10.7 DC bias circuits for transistors
Discussion
1. Resistive bias with voltage feedback for BJT

+Vcc
Vcc = Rc I E + R B I B + V BE ,
IB Rc
I C = βI E , I E = I B + I C
Vcc − V BE
RB
Lc → IE =
RF block R
RC + B
LB IC
1+ β
DC block
RB
→ Vcc >> V BE , RC >>
IE
1+ β
matching
circuit GND to have I E less sensitive to changes in V BE ,β

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 2. Bias circuit with emitter bypassed resistor for BJT
+Vcc
R2 R1 R 2
Rc VTh = Vcc , RTh =
R1 IC R1 + R 2 R1 + R 2
IB
Lc RTh
VTh = RTh I B + V BE + R E I E = ( + R E ) I E + V BE
LB1
1+ β
VTh − V BE
→ IE =
IE R
R E + Th
LB2 1+ β
R2 RE CE RTh
→ VTh >> V BE , R E >>
1+ β
to have I E less sensitive to changes in V BE ,β
+Vcc
IC VTh ↑→ VCB , VCE ↓ limited output swing,
Rc usually VTh ≈ 15% ~ 20%Vcc
IB RTh RTh ↓→ Rin ↓

IE
VTh
RE

10-34 微波工程講義
 3. Unipolar bias circuits for MESFET
+VD

Ids high-power CD RF block

Vgs = 0V LD
high-gain Cc2
low-noise matching IC
DC block Cc1 circuit
high-power Vgs = - 1V
LG CS LS +VS
Vgs = Vp
GND
low-noise high-power
low-power high-efficiency +VD

CD RF block
LD
Cc2
matching IC
DC block Cc1 circuit

Hw #8 (due 2 weeks) LG CS RS
5, 11, 15

10-35 微波工程講義