Proceedings of International Conference on Circuits, Communication, Control and Computing (I4C 2014)
High Speed Energy Efficient Level Shifter for multi
Core Processors
Srinivasulu Gundala
Dept. of ECE
SITAMS
Chittoor,India
sri_reddy46@yahoo.co.in
Padmapriya Kesari
Dept. of ECE
JNTUK UCE
Vizianagaram, India
kesaripadmapriya@yahoo.com
Abstract— The energy efficiency and power consumption are
the two primary and major concerns in present emerging
applications like miniaturized bio medical sensors, pace makers,
multimedia processors, etc. The energy and power consumption
may decreases by multiple ways. The multiple power supply
voltage design is an efficient and dominant technique for the
reduction of energy and power consumption at processor level.
The multi core processors uses level shifters and this level shifter
may become burden, when its own energy and power
consumption is high, at the same time there is area overhead also.
In this paper a high speed Energy efficient level shifter circuit is
proposed that performs level up shifting & Level down shifting.
The design is designed & simulated using 90nm model files. The
proposed one is a unique design, is encompass a level shifter and
provision for auto selection of type of shift (Level up/Level
down). The proposed level shifter strength has study at signal
frequency of 1 MHz, 500 KHz, and 100 KHz with a load
capacitance variation from 10fF - 60fF. The proposed design has
an average delay of 2.8 ns & power consumption is 36.4 nW at
0.4V VIN and 0.18 ns & 16 nW at 1V VIN.
Key words— delay; Energy efficiency; Level shifter; multi
core; power dissipation
I. INTRODUCTION
The delay, energy per transition and Power dissipation are
the three most important design parameters need to be
discussed. Various power reduction methodologies are studied
from the literature for the reduction of power consumption, the
methodologies which involves power supply voltage
reductions is the efficient technique. As the reduction in
supply voltages will reduces the speed performance and power
consumptions of the design [1]. Alternative technique known
as clustered voltage scaling. It means the entire system can
partition different voltage blocks, and speed sensitive cores
can operate with higher power supply voltage (VDDH) to
increase the speed of the circuit & bit compromises in power
consumption penalty and non speed sensitive cores can
operate with lower power supply voltage (VDDL) to minimize
the power consumption and bit compromises need to be in
delay penalty. Level shifters are interfacing blocks, will be
used to drive high VDD core by a low VDD core and vice
versa.
MSRIT, BANGALORE, India, 21-22 NOVEMBER 2014
Venkata K.Ramanaiah
Dept. of ECE
YSR Engineering college of Yogi Vemana University
Proddatur,India
ramanaiahkota@rediffmail.com
Level Shifter is a driving device; a level shifter can be low
voltage to high voltage driver or high voltage to low voltage
driver. The possible level shifters are level up shifter or level
down shifter. For up shifting, level shifters are generally
employed & for down shifting CMOS inverters are sufficient
[2], [3].The cascading of two CMOS inverters will results
more delay and area overhead [4]. Therefore, the main
challenges in multi core processors are the identification of
correct level shifter, correct level shifter means it has to be
good in all respects like power, delay and area.. In the
proposed high speed energy efficient level shifter for multi
core processors we have used 8 numbers of MOS transistors to
achieve low delay, energy and power. The paper has arranged
in the following order. Segment II describes about the existing
designs and other available designs. Segment III in the article
deals with new design, Segment IV is simulation results and
comparison with other designs, and Segment V ends with
conclusion.
II. REVIEW ON EXISTING LEVEL SHIFTERS
A. Basic Level Shifter
The very basic form of level shifter configuration is the
Differential Cascade Voltage Switch logic, is viewed in the
Fig. 1. It is half latch type, constructed by using two p channel
MOSFETs MP2 and MP3 & two n channel MOSFETs MN2
and MN3, and these devices are controlled by the level
shifting low input voltage (VIN) and its complement. While
the input voltage (VIN) transition from low voltage to high
voltage, the transistor MN2 will becomes ON and transistor
MN3 becomes OFF, As a result, the node voltages at NH and
NL are pulled down and pulled up respectively, leading to
MP3 becomes ON and MP2 becomes OFF. When MP3
becomes on, the voltage at NL become equal to VDDH and
MP2 become turned OFF, and the voltage at NH stats to be
discharged. There may be impedance problem between the
devices. As a result pull up network strengths and pull down
network strengths should be precisely balanced [2]. It is
tedious task to achieve when the level shifting signals are at
sub threshold voltage level to obtain the optimized speed and
power consumption parameters.
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Proceedings of International Conference on Circuits, Communication, Control and Computing (I4C 2014)
Fig. 1. Basic level shifter
B. Existing level shifter circuits.
A design invented by Stuart N. Wooters et al. [5] have
constructed with two parts. The primary part is a Differential
Cascade Voltage Switch circuit with NMOS ON diode at top,
and the second part is a customary Differential Cascade
Voltage Switch circuit to attain the power rail swing. It can
avoid in-between power rails; unfortunately it is very poor in
speed constraint.
Another technique invented & developed by N.B. Romli et
al. [6] has designed a level shifter for the reduction of the
dynamic power (PD) by optimizing the widths and lengths of
the MOSFETs. It may reduce the dynamic power but there
will be poor performance at leakage power and delay.
The novel design proposed by Yuji Osaki et al. [7]
performs logic error correction but requires more no. of
transistor and can perform only level up shift.
III. ENERGY EFFICIENT LEVEL SHIFTER
The proposed high speed Energy Efficient Level Shifter
(EELS) for multi core processors block diagram is shown in
the fig. 2 The VDDH and VDDL are the supply voltages of
the High VDD core and Low VDD cores respectively.
The EELS performs level down shift when VDDH core
produces logic HIGH output, and level up shift when VDDL
core produces logic HIGH output. In both cases EELS will
drive the cores.
Fig. 2. Basic block diagram of proposed level shifter
MSRIT, BANGALORE, India, 21-22 NOVEMBER 2014
Fig. 3. Proposed high speed EELS.
The proposed high speed EELS circuit shown in the fig. 3
comprising with 8 no. of MOS transistors, 4 are PMOSFETs
type, namely MP1, MP2, MP3, & MP4 and the remaining 4
are NMOSFETs type, namely MN1, MN2, MN3, & MN4.The
proposed design is totally different from the conventional
level shifters. The conventional level up shifter performs only
level up shift and level down shifter performs only down shift.
Our proposed level shifter performs both up shift and down
shift with no additional transistors. The design has configured
such that, While level up shift the VDDH will appears at VDD
and while level down shift the VDDL will appears at VDD.
The voltage at VDD determines the kind of shifting operation.
The design can be viewed as two parts. 1) The transistors
MP4, MN4 and its connections act as a 2X1 Multiplexer, its
inputs are VDDH and VDDL & VIN act as a select line. 2)
The remaining 6 transistors and its connections will perform
level shifting operation.
As an illustration VDDH is 1V, VDDL is 0.4V and the
possible values of VIN is 0V, 0.4V and 1V are taken.
When Vin is 0.4V, MP4 become ON, hence the VDDH
will appears at VDD and the circuit will act as up shifter, at
the same time MN1, and MN2 become ON, hence VOUT
node will be charged to 1V through MP3 ON transistor.
When Vin is 1V, MN4 become ON, hence the VDDL will
appears at VDD and the circuit will act as down shifter, at the
same time MN1, and MN2 becomes ON, hence VOUT node
will be charged to 0.4V through MP3 ON transistor.
When Vin is 0V, MP4 become ON, hence the VDDH will
appears at VDD, at the same time MN1, & MP2 become ON
and MN2 becomes OFF and VOUT node will be charged to
0V through MN3 ON transistor.
It can be conclude that when VIN is 0.4V, VOUT is 1V,
when VIN is 1V, VOUT is 0.4V and when VIN is 0V, and
VOUT is 0V has produced by the level shifter. The level
shifter has performed level up shift/down shift based on
voltage at its VIN node.
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Proceedings of International Conference on Circuits, Communication, Control and Computing (I4C 2014)

IV. SIMULATION RESULTS AND ANALYSIS

The high speed EELS has developed and simulated by
Synopsys HSPICE tools at 90nm process technology. The
transistor threshold voltage of the P devices is - 0.3V and N
devices 0.3V has taken. The design has simulated with
different frequencies of 100 KHz, 500 KHz, and 1 MHz & the
simulated waveforms have are shown in figure 4 and 5. Fig. 4
is the level up shifter output for the given VIN is 0.4V, and
Fig.5 is the level down shifter output for the given VIN is 1V.
The time period of 1µsec is equivalent to 1MHz frequency
with stabled output is depict in the figure.

A. Waveforms of the high speed EELS

Fig. 6. Energy per transition of high speed EELS as a function of VDDH

Fig. 4. Level Up shift

Fig. 7. Energy per transition of high speed EELS as a function of VDDL

Fig. 5. Level down shift

B. Performance analysis of the high speed EELS

Performance analysis of high speed EELS have shown in
figures 6 - 9. Fig. 6 illustrates the energy per transition of the
proposed high speed EELS when level up shift, the energy
required for a transition is calculated and plotted, the x- axis
parameter is VDDH and y- axis parameter is Energy per
transition at VDDL=0.4V. Fig. 7 illustrates the energy per
transition of the proposed high speed EELS when level down
shift, the energy required for a transition is calculated and
plotted, the x- axis parameter is VDDL and y parameter is
energy at VDDH=1V. The design supports to conserve lower
energy per transition at higher frequencies and it can be
viewed in the plots. Hence it has named as EELS. Fig. 8 and 9
shows the delay of the high speed EELS. Fig. 8. Delay of high speed EELS as a function of VDDH.

MSRIT, BANGALORE, India, 21-22 NOVEMBER 2014 395

Proceedings of International Conference on Circuits, Communication, Control and Computing (I4C 2014)
Fig. 9. Delay of high speed EELS as a function of VDDL.
C. Characterization of high speed EELS
The characteristics of the high speed EELS is analyzed and
its activities are plotted with different VDDH and VDDL
variations at a temperature of 27 oC and with the varying load
capacitance (CL) of 10fF to 60fF. It is very much essential to
analyze, and study the performance of the EELS with 3 types
of analytical parameters. As a analytical parameter the VDDL
is varied, by keeping VDDH constant & VDDH is varied, by
keeping VDDL constant, and a very stable output voltage has
obtained. As an energy and delay analysis, the energy per
transition has estimated with varying load capacitance (CL)
from 10fF - 60fF at an applied signal frequency of 1MHz with
an input signal having rise time 10ns and fall time 10ns has
taken as shown in the figures 10 and 11. It can be observed
that the delay and energy are directly influenced by the load
capacitance. The delay is slightly affected by the load
capacitance, at the same time the full rail to rail swing has
achieved.
Fig. 10. Energy per transition of high speed EELS as a function of CL
MSRIT, BANGALORE, India, 21-22 NOVEMBER 2014
Fig. 11. Delay of high speed EELS as a function of CL
D. Comparison with other design
As a comparative analysis, the proposed EELS and other
six designs are taken to analyse with different parameters like
type of shift, technology, frequency of operation, level shifting
voltages, power, and delay. Table I shows a comparison with
other designs.
The circuit design in ref. [5] performs level up shift only
and it has consumed the average power of 90nW and delay
10ns at 130nm CMOS technology, it exbits a very low delay
but power consumption is bit high. The design in ref. [6] also
performs level up shift only & it has consumed an average
power of 1.49nW with a delay of 15ns at 180nm CMOS
technology with a signal frequency of 1 KHz. The design in
ref. [7] performs level up shift only and it has consumed the
ave. power of 58nW with delay of 100ns at 350 nm
technology and it has very low static power consumption and
it uses dynamic threshold MOS topology. The design in ref.
[8] performs only level up shift and it has incurred the static
power consumption of 6.6nW and delay 18.4ns at 90nm
technology operated at 1 MHz. The design in ref. [9] performs
only level up shift and it has incurred the static power
consumption of 6.4nW and delay 22ns at 90nm technology
operated at 1 MHz. The above design is useful to perform only
level up shifts, and to perform level down shifts, the design
modifications like circuit topology or VDDs need to be
changed. In ref. [10] the design performs level up shift and
level down shift with a VDDL of 0.4V to VDDH of 1.2V and
1.2V to 0.4V respectively; unfortunately it requires additional
2X1 multiplexer with auto selection of required level shifting
operation.
The proposed design has simulated for its functionality to
perform level up shift from 0.4V to 1V & level down shift
from 1V to 0.4V at an operated frequency of 1 MHz, it
performs both level up and level down shift and an average
level up and level down active power consumption is only
26.2 nW at a frequency of 1 MHz, average delay of level up
and level down shift is only 1.49 ns and it is comparable with
designs.
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TABLE I. COMPARATIVE ANALYSIS OF THE LEVEL SHIFTERS

*Ref. [10] and proposed design performs level up and level down by the same circuit.
Ref. [7] performs level up as well as logic error corrections
Pa - Average power or Active Power
Ps - Static power

V. CONCLUSION [7] Yuji Osaki, Hirose T, and N. Kuroki “A low power level shifter with
logic error correction for extremely low voltage digital CMOS LSIs,”
The high speed EELS have designed and simulated with IEEE Journal of Solid State Circuits, vol. 47, no. 7, pp. 776 - 783, July
eight no. of transistors to perform level shift & level down 2012
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automatic selection of level up or level down shift. The design level shifter comprising a Wilson current mirror,” proc. of IEEE trans.
offers level up & level down average delay of 1.49ns & on circuites and systems II, Volume 57, no. 9, p p. 721 - 724, Sept.
energy per transition of 3.00E-14 J. Simulation results show 2010.
that proposed circuit is able to shift from 0.4V to 1V & 1V to [9] Marco Lanuzza, P. Corsonello, and S. Perri, “Low-Power Level Shifter
0.4V. The comparative table shows, high speed EELS for Multi-Supply Voltage Designs,” in Proc. IEEE Transaction on circuit
and system-II, vol .59, no 12, Dec 2012.
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[10] Shien-Chun Luo, Ching-Ji Huang, and Yuan-Hua Chu, “a wide-range
level shifter using a modified wilson current mirror hybrid buffer,” in
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