1. What are phases in UVM?

 UVM Phases are a synchronizing mechanism for the environment

 Phases are represented by callback methods, A set of predefined phases
and corresponding callbacks are provided in uvm_component. The
Method can be either a function or task.
 Any class deriving from uvm_component may implement any or all of
these callbacks, which are executed in a particular order

The UVM Phases are,

 build
 connect
 end of elaboration
 start of simulation
 run
 extract
 check
 report

2. How to start simulation?

3. Clean up phases ?
Clean up Phases extract, check, report and final belong to this category.
where the results of the testcase are collected and reported. example: the
number of error’s during the simulation is reported.

4. Semaphores ?

Semaphore is a SystemVerilog built-in class, used for access control to shared

resources, and for basic synchronization.

A semaphore is like a bucket with the number of keys. processes using

semaphores must first procure a key from the bucket before they can continue to
execute, All other processes must wait until a sufficient number of keys are
returned to the bucket.
 Imagine a situation where two processes try to access a shared memory area.
where one process tries to write and the other process is trying to read the same
memory location. this leads to an unexpected result. A semaphore can be used to
overcome this situation.

Semaphore methods
Semaphore is a built-in class that provides the following methods,

 new(); Create a semaphore with a specified number of keys

 get(); Obtain one or more keys from the bucket
 put(); Return one or more keys into the bucket
 try_get(); Try to obtain one or more keys without blocking

5. Difference between RAND and RANDC?

Variables can be declared random using rand or randc keyword. They can be used on normal
variable with any data type or can be also implemented on data structures like arrays, dynamic
arrays or queues.

rand: The attributes or data structures declared as rand are standard random variables and
their values are uniformly distributed over the range. Think of a rolling dice where each roll
could be a new value or repeat the current one.

1. class Packet;
2. rand bit [2:0] data; // keyword --> rand
3. endclass
4.
5. module tb;
6. initial begin
7. Packet pkt = new;
8. for (int i=0; i<7; i++) begin
9. pkt.randomize();
10. $display("ite = %0d data = 0x%0h", i , pkt.data);
11. end
12. end
13. endmodule

randc: In case of randc, it is random cyclic, so the random solver does not repeat a random
value until every possible value has been assigned. Think of dealing cards from a deck where
you deal out every card in the deck in random order, then shuffle the deck, and deal out the
cards in a different order.
1. class Packet;
2. randc bit [2:0] data; // keyword --> randc
3. endclass
4.
5. module tb;
6. initial begin
7. Packet pkt = new;
8. for (int i=0; i<7; i++) begin
9. pkt.randomize();
10. $display("ite = %0d data = 0x%0h", i , pkt.data);
11. end
12. end
13. endmodule

Implementing randc using rand:

Code, Compile, Run, Debug online C, C++

Basic Idea or Algorithm Used:

1. typedef struct {
2. int value = 0;
3. }num[N];
4. num numbers;
5.
6. int temp = 0;
7. // This loop needs to be run for a very long time. The time of
8. // the loop will be dependent on the random generator [Rand_Range]
9. // It will be generating for a very large number of times.
10.
11. for (int i=0; i<100; i++)
12. {
13. temp=Rand_Range(); // Random
Generation
14. if (number_check[temp].valid==0)
15. {
16. number_check[temp].valid=1;
17. numbers[i].value=temp;
18. }
19. }

rand: Variable values uniformly distributed over their range

randc : randomized cyclically over their range but randomization takes places in such a
way that no value is repeated until all the values in their range are assigned

example: rand bit [1:0]top; randc bit[1:0]top;

 rand: 00 01 10 11 valid ; 00 01 00 10 valid;

randc :00 01 10 11 valid ; 00 01 00 01 invalid : after 01 either 11 or 10 will be randomized.

rand are standard random variables. When there are no other control on distrubution, these variables
are uniformly distributed across valid values.

randc are random cyclic that randomly iterates over all the values in the range and no value is repeated
with in an iteration until every possible value has been assigned.

6. Types of forks?
Fork Join None: The parent process continues to execute concurrently with all the processes spawned by
the fork. The spawned processes do not start executing until the parent thread executes a blocking
statement.

Fork Join Any: The parent process blocks until any one of the processes spawned by this fork completes.

For Join All: The parent process blocks until all the processes spawned by this fork complete.

7. What is difference between code and functional coverage?

There are two types of coverage metrics commonly used in Functional
Verification to measure the completeness and efficiency of verification process.

1) Code Coverage: Code coverage is a metric used to measure the degree to

which the design code (HDL model) is tested by a given test suite. Code coverage
is automatically extracted by the simulator when enabled.

2) Functional Coverage: Functional coverage is a user-defined metric that

measures how much of the design specification, as enumerated by features in
the test plan, has been exercised. It can be used to measure whether interesting
scenarios, corner cases, specification invariants, or other applicable design
conditions — captured as features of the test plan — have been observed,
validated, and tested. It is user-defined and not automatically inferred. It is also
not dependent on the design code as it is implemented based on design
specification.

8. What are different types of code coverage?

Code coverage is a metric that measures how well the HDL code has been
exercised by the test suite. Based on the different program constructs, code
coverage is of the following types:
1) Statement/Line coverage: This measures how many statements (lines) are
covered during simulation of tests. This is generally considered important and is
targeted to be 100% covered for verification closure. In the following example
code, you can see there are 4 lines or statements which will be measure in
statement/line coverage.

always @ (posedge clk) begin

if( X > Y) begin //Line 1

Result = X - Y; //Line 2

end else begin //Line 3

Result = X + Y; //Line 4

end

end

2) Block coverage: A group of statements between a begin-end or if-else or case

statement or while loop or for loop is called a block. Block coverage measures
whether these types of block codes are covered during simulation. Block
coverage looks similar to statement coverage with the difference being that block
coverage looks for coverage on a group of statements. In the same example code
as shown below you can see there are three blocks of code (Enclosed in the begin
… end)

always @ (posedge clk) begin //always block

if( X > Y) begin // if block

Result = X - Y;

end else begin // else block

Result = X + Y;

end

end

3) Branch/Decision coverage: Branch/Decision coverage evaluates conditions

like if-else, case statements and the ternary operator (?: ) statements in the HDL
code and measures if both true and false cases are covered. In the same example
above there is a single branch (if X > Y) and the true and false conditions will be
measured in this type of coverage.

4) Conditional Coverage and Expression coverage: Conditional coverage looks at

all Boolean expressions in the HDL and counts the number of times the
expression was true or false. Expression coverage looks at the right-hand side of
an assignment, evaluates all the possible cases as a truth table, and measures
how well those cases are covered. Following is an expression of 3 Boolean
variables that can cause the Result variable to be true or false

Result = (X && Y) || (Z)

You can create a truth table as follows for all possible cases of X, Y and Z that can
cause result to be true or false. The expression coverage gives a measure of if all
the rows of this truth table are covered.

5) Toggle coverage: Toggle coverage measures how well the signals and ports in
the design are toggled during the simulation run. It will also help in identifying
any unused signals that does not change value.
6) FSM coverage: FSM coverage measures whether all of the states and all
possible transitions or arcs in a given state machine are covered during a
simulation.

9. What are ignore and illegal bins in cover group?

10. Do you know about RAL?
UVM RAL (Register Abstraction Layer) is a feature supported in UVM that
helps in verifying the registers in a design as well as in configuration of DUT using
an abstract register model.

The UVM register model provides a way of tracking the register content of a DUT
and a convenience layer for accessing register and memory locations within the
DUT. The register model abstraction reflects the structure of the design
specification for registers which is a common reference for hardware and
software engineers working on the design.

Some other features of RAL include support for both front door and back door
initialization of registers and built in functional coverage support.

11. Scripting languages

12. Test cases in Ethernet.
13. APB module in design
14. Ethernet explanation
15. Specifications of APB?
16. Role in project?
17. Driver mode
18. Driver logic
19. Monitor code
20. Scoreboard
21. Difference between APB and AXI
22. AXI channels
23. AXI burst calculation
24. AXI responses
25. Difference between OUTSTANDING and OUT OF ORDER
26. Interleaving
27. Hand shaking mechanism in AXI
28. UVM phases
29. Config-db
30. Factory
31. Objections (Raise & Drop)
32. Virtual interface
33. Virtual sequence and virtual sequencer
34. Worked components
35. Explain Ethernet
36. Fields of Ethernet
37. Ports TLM
In Transaction Level Modelling, different components or modules
communicate using transaction objects. A TLM port defines a set of methods
(API) used for a particular connection while the actual implementation of these
methods are called TLM exports. A connection between the TLM port and the
export establishes a mechanism of communication between two components.

Here is a simple example of how a producer can communicate to a consumer

using a simple TLM port. The producer can create a transaction and “put” to the
TLM port, while the implementation of “put” method which is also called TLM
export would be in the consumer that reads the transaction created by the
producer, thus establishing a channel of communication.

38. Test cases

39. Code for sequence
There are three steps needed to run a sequence as follows:

1) Creating a sequence. A sequence is created using the factory create method as

shown below:

my_sequence_c seq;

seq = my_sequence_c::type_id::create(“my_seq“)

2) Configuring or randomizing a sequence. A sequence might have several data

members that might need configuration or randomization. Accordingly, either
configure values or call seq.randomize()

3) Starting a sequence. A sequence is started using sequence.start() method. The

start method takes an argument which is the pointer to the sequencer on which
sequence has to be run. Once the sequence is started, the body() method in the
sequence gets executed and it defines how the sequence operates. The start()
method is blocking and returns only after the sequence completes execution.

40. Factory

UCM Factory is used to manufacture (create) UVM objects and components. Apart from
creating the UVM objects and components the factory concept essentially means that you
can modify or substitute the nature of the components created by the factory without
making changes to the test bench.
For example, if you have written two driver classes, and the environment uses only one of
them. By registering both the drivers with the factory, you can ask the factory to substitute
the existing driver in environment with the other type. The code needed to achieve this is
minimal, and can be written in the test.

41. Purpose of override

42. Super class
43. UVM DO
44. Pre randomization
45. Post randomization
46. How we start sequence
Start item starts the sequence
Virtual task start item (uvm_sequence_item item,
int set priority = -1,
Uvm_sequencer_base sequencer = null )
Start item and finish item together will initiate operation of a sequence item. If the item
has not already been initialized using create item, then it will be initialized here to use the
default sequencer specified by m_sequencer.

47. M-sequencer
When a sequence is started, it is always associated with a sequencer on
which it is started. The m_sequencer handle contains the reference to the
sequencer on which sequence is running. Using this handle, the sequence can
access any information and other resource handles in the UVM component
hierarchy.
48. About APB
49. Constraints for ascending order without system task
50. Polymorphism
Polymorphism is a generic term that means 'many shapes'. In C++ the simplest form of Polymorphism is
overloading of functions, for instance several functions called SortArray( arraytype ) where sortarray might be
an array of ints, or doubles.

/* A base class of Shape gives rise to

two derived classes - Circle and Square.

An application called Polygon sets up an

array of Circles and Squares, and uses a
getarea method to find the area of each.

This getarea method is defined as a virtual

method in the base class, so that an array
of shapes CAN be defined on which two
different getarea methods can be run
depending on which type of shape is the
current one at the time. */

::::::::::::::
shape.h
::::::::::::::

#ifndef SHAPE
#define SHAPE 1

class Shape {
public:
void setsize(int owbig);
virtual float getarea() {};
protected:
int givensize;
};

#endif
::::::::::::::
shape.cpp
::::::::::::::
#include "shape.h"

void Shape::setsize(int sv) {

givensize = sv;
}

::::::::::::::
square.h
::::::::::::::
#include "shape.h"

class Square: public Shape {

public:
float getarea();
};
::::::::::::::
square.cpp
::::::::::::::
#include "square.h"

float Square::getarea() {
float result = givensize * givensize;
return (result);
}
::::::::::::::
circle.h
::::::::::::::
#include "shape.h"

class Circle: public Shape {

public:
float getarea();
};
::::::::::::::
circle.cpp
::::::::::::::
#include "circle.h"

float Circle::getarea() {
float result = 3.14159265f * givensize;
return result;
}
::::::::::::::
polygon.cpp
::::::::::::::
#include
#include "circle.h"
#include "square.h"

main () {

int np = 10;
Shape *jigsaw[np];

for (int k=0; k

jigsaw[k] = new Square();
jigsaw[k+1] = new Circle();
}
for (int k=0; k
jigsaw[k]->setsize(10+k);
}
for (int k=0; k
float syze = jigsaw[k]->getarea();
cout << "this is sq " << syze << endl;
}

return (0);
}
51. Interface
52. Modport
Modport restrict interface access within a module based on the direction declared. Directions of signals
are specified as seen from the module.

e.g.
interface intf (input clk);
logic read, enable,
logic [7:0] addr,data;

modport dut (input read,enable,addr,output data);

modport tb (output read,enable,addr,input data);
endinterface :intf
53. Clock
54. About current project
55. Your contribution
56. Explain frame
57. Features of Ethernet.
58. Factory method
59. Phases
UVM uses standard phases to order the major steps that take place during
simulation. There are three groups of phases, which are executed in the following
order.

1. Build phases – In the build phases; the testbench is configured and

constructed. It has following sub-phases which are all implemented as virtual
methods in uvm_component

base class.

1) build_phase()

2) connect_phase()

3) end_of_elaboration()

2. Run time phases – These phases can consume time and this is where most of
the test execution happens.

1) start_of_simulation()

2) run_phase()

The run_phase() is further divided into 12 sub-phases as below:

1) pre_reset
2) reset

3) post_reset

4) pre_configure

5) configure

6) post_configure

7) pre_main

8) main

9) post_main

10) pre_shutdown

11) shutdown

12) post_shutdown

3. Clean up phase – This phase execute after the test ends and is used to collect,
and report results and statistics from the test. This consists of following sub
phases:

1) extract()

2) check()

3) report()

4) final()
60. Config_db
61. Difference between function and task
62. What are blocking and non-blocking assignments
63. Function coverage-90% code coverage- 100%. How to improve
functional coverage?

64. Function coverage-100% code coverage- 90%. How to improve code

coverage?
65. Difference between logic and wire

Logic and wire are almost the same except wire can be driven by multiple sources. Logic can only driven by
single source.

66. What is mailbox?

67. What are dynamic and associative arrays?
68. Inheritance
69. Polymorphism
70. Casting (Static, Dynamic)
71. Which project is familiar
72. Fatal error
73. APB and AXI
74. Regration
75. Virtual sequencer

76. AXI signals

77. Virtual interface
78. Illegal, ignore, wildcard
79. What is code coverage and functional coverage?
80. Code 80% functional 100% what will you do?
81. Code 100% functional 80% what will you do?
82. Default value of auto bin (max 64bits)
83. Difference mailbox and queue
84. Processes (fork join)
85. Difference between clocking block and program block
86. SV regions
87. Difference between reg, wire, logic
reg and wire are two data types that existed from Verilog, while logic is a new
data type that was introduced in SystemVerilog.

1. A wire is a data type that can model physical wires to connect two
elements. Wires can only be driven by continuous assignment statement
and cannot hold onto value if not driven. Wires can hence only be used to
model combinational logic.
2. A reg is a data type that can model a storage element or a state. They need
to be driven by an always block and cannot be driven by continuous
assignment statement. A reg can be used to model both sequential and
combinational logic
3. A logic is a new data type in SystemVerilog that can be used to model both
wires and state information (reg). It also is a 4 state variable and hence can
hold 0, 1, x and z values. If a wire is declared as a logic (wire logic), then it
can be used to model multiple drivers and the last assignment will take the
value.

88. Time scale

89. Difference between blocking and non-blocking assignments
90. Difference latch and flip flop
91. Test is hand what will you do?
92. Objection
93. New & create
94. Input skew and output skew

95. Fork blocks

96. Clock frequency calculator
97. Reporting on UVM
98. Coverage
99. Constraints
100. APB
101. SV architecture
102. Define parameter and defparam
103. Why are we using macros
104. How Ethernet transfers will happen
105. How many layers are there?
106. About Ethernet
107. AXI channels
108. AXI waveforms
109. Why write response channel
110. Outstanding
111. Interleaving
112. Waveforms of APB
113. UVM architecture
114. Associative array and dynamic array
115. Reg and logic
116. Polymorphism
117. Inheritance
118. Task and function
SystemVerilog language supports a number of built-in system tasks and
functions for different utilities and are generally called with a “$” prefix to the
task/function name. In addition, language also supports addition of user defined
system tasks and functions.

Following are some examples of system tasks and functions (categorized based
on functionality).
 For a complete list, one should refer to LRM.

 Simulation control tasks – $finish, $stop, $exit

 Conversion functions – $bitstoreal, $itor, $cast
 Bit vector system functions – $countones, $onehot, $isunknown
 Severity tasks – $error, $fatal, $warning
 Sampled value system functions – $rose, $fell, $changed
 Assertion control tasks – $asserton, $assertoff

119. Constraint for even number

120. Constraint for odd number
121. Latch and flip flop, where it is used?
122. How to define clock
123. Always block and forever block
124. GVIM commands
125. What is ASIC and FPGA
126. Meta stability
1. Answer :
Metastability is an unknown state that is given as neither one or zero. It is used in
designing the system that violates the setup or hole time requirements. The setup time
requirement need the data to be stable before the clock-edge and the hold time
requires the data to be stable after the clock edge has passed. There are potential
violation that can lead to setup and hold violations as well. The data that is produced in
this is totally asynchronous and clocked synchronous. This provide a way to setup the
state through which it can be known that the violations that are occuring in the system
and a proper design can be provided by the use of several other functions.
2. Question 14. What Are The Steps Involved In Preventing The Metastability?
Answer :
Metastability is the unknown state and it prevents the violations using the following
steps:
o proper synchronizers are used that can be two stage or three stage whenever
the data comes from the asynchronous domain. This helps in recovering the
metastable state event.
o The synchronizers are used in between cross-clocking domains. This reduces
the metastability by removing the delay that is caused by the data element
that are coming and taking time to get removed from the surface of metal.
 o Use of faster flip-flops that allow the transaction to be more faster and it
removes the delay time between the one component to another component.
It uses a narrower metastable window that makes the delay happen but faster
flip-flops help in making the process faster and reduce the time delay as well.

127. Meelay and Moorey

Main differences between the mealy and Moore state machine:

Moore Machine Model Mealy Machine Model

The Moore model contains the machines that have an entry The Mealy model only uses Input Actions, a
action, and the output depends only on the machine's state. the output depends on the state and t
previous inputs provided during the program

The Moore model is used to design the hardware systems. The Mealy model is used to design bo
hardware and software systems.

The output of the Moore machine depends only on the state The output of the Mealy machine is t
because the program is written in the state only. The output combination of both input and the state.
of the Mealy machine depends on the state as well as on the
input also.

When we make signal changes, the state variables also have The Moore machine doesn't have glitch
some delay. and its output is dependent only on stat
not on the input signal level.

128. 4-bit Johnson counter using D-Flip Flop

129. What is bus cycle and bus clock
130. PROM and EEPROM
131. Inter delay and Intra delay?
132. Where counters used
133. Basic structure of ROM
134. How many flip flops required
135. What is procedural block
136. How to control race around condition
137. Write code for repeat and forever in sv.
138. What is FIFO
139. Modports
140. Interface
The interface constructs in SystemVerilog are a named bundle of nets of
variables that helps in encapsulating communication between multiple design
blocks. An interface can be instantiated in a design and can be connected using a
single name instead of having all

the port names and connections. In addition to connectivity, functionality can

also be abstracted in an interface as it supports defining functions that can be
called by instantiating design for communication. Interfaces also support
procedural ( always/initial blocks) and continuous assignments which are useful
for verification in terms of adding protocol checks and assertions.

Following is a simple example on how an interface can be defined.

interface simple_bus; // Define the interface

logic req, gnt;

logic [7:0] addr, data;

logic [1:0] mode;

logic start, rdy;

endinterface: simple_bus

141. Program block

142. Clocking block
143. Parallel block
144. Fork join block
145. Shallow copy and deep copy?
 There are 2 types of copy. Show copy or deep copy

For example:

class B;
int
endclass

program main;
initial
begin
B b1;
B b2;
b1 = new();
b1.i = 123;
b2 = b1; // b1 and b2 point to the same memory. The properties did not get copied.
$display( b2.i );
end
endprogram
RESULTS:

123

A shallow copy of an object copies all of the member field values.

program main;
initial
begin
B b1;
B b2;
b1 = new();
b1.i = 123;
b2 = new b1; // shallow copy of b1
b2.i = 321;
$display( b1.i );
$display( b2.i );
end
endprogram

RESULTS:

123
321

If the value of b1 change, it will also change the value of b1. It's because it's pointing to the same memory.

To avoid this, we need to use the deep copy.

Deep Copy

A deep copy copies all fields, and makes copies of dynamically allocated memory pointed to by the fields. To
make a deep copy, you must write a copy constructor and overload the assignment operator, otherwise the
copy will point to the original, with disasterous consequences.

EXAMPLE:
class A;
int i;
endclass

class B;
A a;

task copy(A a);

this.a = new a;
endtask

endclass

program main;
initial
begin
B b1;
B b2;
b1 = new();
b1.a = new();
b1.a.i = 123;
b2 = new b1;
b2.copy(b1.a);
$display( b1.a.i );
$display( b2.a.i );
b1.a.i = 321;
$display( b1.a.i );
$display( b2.a.i );

end
endprogram

RESULTS:

123
123
321
123

146. Polymorphism

Polymorphism allows an entity to take a variety of representations. Polymorphism means the ability to
request that the same Operations be performed by a wide range of different types of things. Effectively, this
means that you can ask many different objects to perform the same action. Override polymorphism is an
override of existing code. Subclasses of existing classes are given a "replacement method" for methods in the
superclass. Superclass objects may also use the replacement methods when dealing with objects of the
subtype. The replacement method that a subclass provides has exactly the same signature as the original
method in the superclass.
EXAMPLE: with virtual
class A ;
virtual task disp ();
$display(" This is class A ");
endtask
endclass

class EA extends A ;
task disp ();
$display(" This is Extended class A ");
endtask
endclass

program main ;
EA my_ea;
A my_a;

initial
begin
my_a = new();
my_a.disp();

my_ea = new();
my_a = my_ea;
my_a.disp();
end
endprogram

RESULTS

This is class A
This is Extended class A

147. Virtual interface

An interface encapsulate a group of inter-related wires, along with their directions (via
modports) and synchronization details (via clocking block). The major usage of interface is
to simplify the connection between modules.
But Interface can't be instantiated inside program block, class (or similar non-module entity
in SystemVerilog). But they needed to be driven from verification environment like class. To
solve this issue virtual interface concept was introduced in SV.
Virtual interface is a data type (that implies it can be instantiated in a class) which hold
reference to an interface (that implies the class can drive the interface using the virtual
interface). It provides a mechanism for separating abstract models and test programs from
the actual signals that make up the design. Another big advantage of virtual interface is that
class can dynamically connect to different physical interfaces in run time.

148. Coverage’s
149. Phases in UVM
150. Ethernet explain
151. Difference between combinational and sequential circuit?
152. SV architecture and explain
153. Clocking block

1) What if design engineer and verification engineer do the same mistake in Test bench BFM(Bus Functional
Model) and RTL(DUT)? How can you able to detect errors?

Answer: 1. Code reviews & protocol checkers

2. IP gets verified in multiple environments .. like block level test bench, out of box testbench
(connecting DUT back to back) , full fledged testbench using proven BFM, SoC level testbench using processor
and all that etc... this all environments SHOULD be executed by diferent persons and so you should be able to
catch that bug in one of this testbench ...
3. customer will catch the problem ( worst case )

2) If you got a failure from the customer, how do you debug this? How do you prevent it to happen again?

Answer: 1. First, try to reproduce the problem in your own environment. Try to get customer's vector, so you
can inject the same vector to create the problem in house.
2. If you confirm the problem and fix them, you should put the new assertion or test to catch the
problem again. Add this new test in the future test plan, so the problem will not happen again.