17ES74

FPGA lab 13 tasks

BY 17ES74
1. Design a VGA controller that will display a 50 by 50 pixels square flying on the
screen at a speed of 10 pixels per second. Attach the VHDL code and output results.

VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity vga_controller is
port(clk50_in : in std_logic;
red_out : out std_logic;
green_out : out std_logic;
blue_out : out std_logic;
hs_out : out std_logic;
vs_out : out std_logic);
end vga_controller;
Architecture Behavioral of vga_controller is
signal clk25 : std_logic; -- the 25Mhz clock
signal clk10 : std_logic; -- the 10Mhz clock
signal horizontal_counter : integer range 0 to 800;
signal vertical_counter : integer range 0 to 525;
signal counter: integer range 0 to 800;
begin
-- generate a 25Mhz clock
process (clk50_in)
begin
if clk50_in'event and clk50_in='1' then
clk25<=not clk25;
end if;
end process;
process (clk50_in)
variable p : integer range 1 to 2500000;
begin
if clk50_in'event and clk50_in='1' then
p:=p+1;
if (p=2500000) then
clk10<=not clk10;
end if;
end if;
end process;
process (clk25)
begin
17ES74

if clk25'event and clk25 = '1' then

if (horizontal_counter >= counter ) --
and (horizontal_counter < counter+50 ) --
and (vertical_counter >= 250 ) --
and (vertical_counter < 300 ) --
then
red_out <= '1';
green_out <= '0';
blue_out <= '0';
else
red_out <= '0';
green_out <= '0';
blue_out <= '0';
end if;
if (horizontal_counter > 0 )
and (horizontal_counter < 96 ) -- 96+1
then
hs_out <= '0';
else
hs_out <= '1';
end if;
if (vertical_counter > 0 )
and (vertical_counter < 3 ) -- 2+1
then
vs_out <= '0';
else
vs_out <= '1';
end if;
horizontal_counter <= horizontal_counter+1;
if (horizontal_counter=800) then
vertical_counter <= vertical_counter+1;
horizontal_counter <= 0;
end if;
if (vertical_counter=525) then
vertical_counter <= 0;
end if;
end if;
end process;
process (clk10)
begin
if (clk10'event and clk10='1') then
counter<=counter+10;
end if;
end process;
end behavioral;