EC8095 Unit 2

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ww
w.E
asy
E ngi
nee
rin
g.n
et
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ww
w.E
asy 
DeMorgan’s law
NAND
E Inverted OR
ngi
AB = A + B

NOR Inverted AND nee A+B=AB
rin
g.n
et
A
B F
C
D
TM
TECHNICAL PUBLICATIONS - An up thrust for knowledge

gA  3 3
A 2 33
A Y
A Y
gA  6 3
A A 4 B 4
y  AB  C gB  6 3
B Y gC  5 3
C C
ww A 2 C
Y
73
w.E B 2
asy
y  AB  CD
EA
ngi A 4 B 4
gA  6 3
gB  6 3
B
C
D
Y
nee
C D
Y
gC  6 3
gD 6 3
A
rin
C
12 3
B D
g.n
et
gA  5 3
B 6
y  A (B  C)  DE D gB  8 3
E
A Y
C 6 A 3 gC  8 3
B
D
C gD  8 3
D 6 E 6 gE  8 3
Y 10 3
E 2 A 2
D B 2 C 2
TM

A
Y
Reset
1 2
ww A 4/3
w.E Reset 4
asy
E ngi
nee gu
rin
gd
g.n
et
2 2 1
A Y A Y A Y
1/2 1 1/2
(a) HI-skew inverter (b) Unskewed (c) Unskewed

inverter inverter
(Equal rise resistance) (Equal fall resistance)
TM

n P
1 2
1.414
B 2
Y
A Y
gu = 1.15 A
A 2
gd = 0.81
ww gavg = 0.98
B gu = 4/3
gd = 4/3
Y
w.E gavg = 4/3 1 1 gu = 2

gd = 1
gavg = 3/2
asy
(a) Inverter
E (b) NAND
ngi
(c) NOR
nee
rin
F  ( A  B) (C  D)
30 g.n
500
 et
500
30
5 5
2 
6 3
5 29
4 
6 6
F 1/ 2
TM

5
500 
6
A 20 20 A
B 20 20 B 63
ww
C 10 10 C 16
D w.E 10 10 D
asy
E ngi
nee
rin
g.n
et
TM

VDD
QP
Vo
QN
V1
ww
w.E QN QP
asy QN QP
E ngi
nee VDD
VDD rin
g.n Y = ABCD
Y
A QN1
et
B QN2
A B C D
QN1 QN2 QN3 QN4
C QN3
D QN4
Pseudo nMOS NOR operation Pseudo nMOS NAND operation

Y = ( A + B + C + D) Y = ABCD
TM

ww
w.E
asy
E ngi
nee
Pass transistor
rin Vx
Vin
g.n
Cx
CLK
et
Vin
Cx
Cx
Cx
Cx
TM

Pass transistor
Vx
Vin = VOH
ID
Cx
CLK
Vx
Vmax VDD  VT 0 ,n     F| Vmax  |2  F|)
ww Vx
Vx
w.E Vmax
Vmax = VDD – VT,n
asy
E 0
ngi t
Vx
nee
rin
Pass transistor
g.n
Vin = 0
ID
Vx
Cx
et
CLK
Vx
Vx
Vmax = VDD – VT
Vmax
t
0
Vx
TM

ww
w.E
asy
E ngi
nee
rin
g.n
et
CLK
CLK VDD
Vx
Vin Vout
Cx Cy
CLK
TM

VDD
QP
ww QN
Vo
w.E V1
asy QN
E
QP
QP
ngi
QN
nee VDD
rin
VDD
g.n
Y
A QN1
et
Y = ABCD
B QN2
A B C D
QN1 QN2 QN3 QN4
C QN3
D QN4
Pseudo nMOS NOR operation Pseudo nMOS NAND operation

Y = ( A + B + C + D) Y = ABCD
TM

ww
w.E V DD
asy
V SS
E ngi Z
nee Inputs N-Logic

circuit
rin
CLK
g.n
et
TM

VDD VDD
Vout1 Vout2
ww st
1 stage
nMOS
nd
2 stage
w.E logic
1
nMOS logic
asy
E ngi
nee
rin

Pre -
charge Evaluation
g.n
et
Vout1
Correct
Vout2 Erroneous state
TM

ww
w.E
asy
E ngi N1
nee N2
Inputs n - logic n - logic

rin
g.n
Clock et
Clock
N1 Td1
Erroneous state
N2 Td2
TM

ww
w.E
asy
E ngi A. B. C. D
nee
VDD
rin
g.n
A B C D
Y = (A  B  C  D)
et
A
TM

D (A + BC)
VDD
B C
ww A
w.E Y = (A + BC) D
asy D
E ngi B
A
nee
C
rin
g.n
et
TM

2  1
A Y
Y
1 A 1
ww
w.E
asy
E ngi
nee
rin
g.n
et
TM

VDD
ww
w.E– CLK
asy
CLK
Z
E ngi
a
nee
b rin
c g.n
d et
e
TM

ww
w.E VDD VDD
asy
a
E ngi
Z
b
nee
rin
c
g.n
d
et
e
CLK
Dynamic gate Inverter
TM

VDD
ww Weak
p - device
w.E Z
asy Inputs n - logic block
E CLK
ngi
nee
rin
g.n
et
VDD
Inputs n - logic block
CLK
TM

ww
w.E
asy
E ngi
nee
rin
g.n
et
V DD  I DC
V DD
I DC
TM

ww Pstatic I static  V DD
I static
w.E
asy m 2
E ngi
nee
P Total static 
n
I static  V DD
rin
1
g.n
et
CL
V DD
fp V in Pd
Pdynamic C V DD 2 fp
TM

K 3 t rf
Psc (V DD  V t )
12 tp
tp
t rf
ww
w.E
Ptotal asy
Pstatic  Pdynamic  Psc
E ngi
nee
rin
g.n
et
Pavg Pswitching  Pshort  circuit  Pleakage
(C L )
Vdd
TM

ww
w.E
asy
E ngi
nee
rin
g.n
et
TM

ww
w.E
asy
E ngi
nee
rin
g.n
et
TM

VDD
ww
w.E
asy
E ngi
nee
rin
VDD VDD
g.n
Vo1
Vi2
et
Vo2
Vi1
TM

VOH
V01
Vth
V02
ww VOL t
w.E
asy C
E nMOS
ngi C
A B
neeA B
pMOS
rin C
g.n
et
–s –s –s
a b a b a b
s s s
Vdd
TM

2
Pav * t p  (C L VDD ) 2
(EDP)  PDP * t p  Pav * t p2
ww
w.E
asy
E ngi
PSC
K
12
(VDD  Vt )
3 t rf
tp
nee
rin
g.n
1
2
PHL PLH C load

et
 PHL V50 %
V50 %
 PLH V 50 %
V 50%
C load   V HL C load (V OH  V 50 % )
 PHL 
I avg, LH I avg, HL
C load   V LH C load (V 50 %  V OL )
 PLH 
I avg, LH I avg, LH
TM

ww B
w.E!A
asy F=AB
E A 0 0
ngi
1 1
B 0 1 0 1
nee
F 0 1 1 0
rin
g.n
et
TM

ww
w.E
asy
E ngi
nee
rin
g.n
et
TM

EC8095 Unit 2

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EC8095 Unit 2

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Downloaded From: www.EasyEngineering.

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

(a) HI-skew inverter (b) Unskewed (c) Unskewed

TECHNICAL PUBLICATIONS - An up thrust for knowledge

w.E gavg = 4/3 1 1 gu = 2

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

Pseudo nMOS NOR operation Pseudo nMOS NAND operation

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

Pseudo nMOS NOR operation Pseudo nMOS NAND operation

TECHNICAL PUBLICATIONS - An up thrust for knowledge

nee Inputs N-Logic

TECHNICAL PUBLICATIONS - An up thrust for knowledge

Vout2 Erroneous state

TECHNICAL PUBLICATIONS - An up thrust for knowledge

Inputs n - logic n - logic

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

Dynamic gate Inverter

TECHNICAL PUBLICATIONS - An up thrust for knowledge

asy Inputs n - logic block

Inputs n - logic block

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

(EDP)  PDP * t p  Pav * t p2

PHL PLH C load

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

TECHNICAL PUBLICATIONS - An up thrust for knowledge

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