CPE31 Introduction to HDL

Laboratory No.2
Verilog Model Components

TECHNOLOGICAL INSTITUTE OF THE PHILIPPINES-

MANILA
Name: ROBLES, CLINT AGUSTIN M. Name of the Faculty: ENGR. AIMEE G. ACOBA
Course Code /Section: CPE316 -CPE31S1 Date Performed: 12/10/2020

Data and Result:

A. Run the additional logic gate operation to learn the software in Verilog HDL. Simulate
the operation of Logic Gates using Verilog.

Logic Gates Logic Symbol Boolean Expression Logic gate primitive code
module NOT_gate(a,x);
1. NOT Gate input a;
Q = A’ output x;
not(a,x);
endmodule
module OR_gate(x,a,b);
2. OR gate input a,b;
output y;
Q = A+B or(x,a,b);
endmodule

module NAND_gate(x,a,b);
3. NAND gate input a,b;
output x;
Q = (A.B)’ nand(x,a,b);
endmodule

module NOR_gate(x,a,b);
4. NOR gate input a,b;
output x;
Q =(A+B)’ nor(x,a,b);
endmodule

module XOR_gate(x,a,b);
5. XOR gate input a,b;
output x;
Q = A⊕B xor(x,a,b);
endmodule

module XNOR_gate(x,a,b);
6. XNOR gate input a,b;
output x;
Q =(A⊕B)’ xnor(x,a,b);
endmodule
B. Create appropriate Test Bench for each Verilog code.
Note: To verify if the result is correct, get the truth table of each logic gate.

Logic Gates Logic gate primitive code Testbench Module

module NOT_gate(y,x1); module TestBench;
1. NOT Gate input x1; reg x1;
output y; wire y;
not(y,x1); initial
endmodule begin
$display ("Time x y");
x1=0;;
#1 x1=1;
#1 x1=0;
#1;
end

NOT_gate U1(x1, y);

initial
$monitor("Time=%0d x1=%b y=%b", $time,x1,y);
endmodule
module OR_gate(y,x1,x2); module TestBench;
2. OR gate input x1,x2; reg x1,x2;
output y; wire y;
or(y,x1,x2); initial
endmodule begin
$display ("Time x1 x2 y");
x1=0; x2=0;
#1 x1=1;
#1 x2=1;
#1 x1=0;
#1;
end
OR_gate U1(x1, x2, y);
initial
$monitor("%0d %b %b %b", $time,x1,x2,y);
endmodule
module NAND_gate(y,x1,x2); module TestBench;
3. NAND gate input x1,x2; reg x1,x2;
output y; wire y;
nand(y,x1,x2); initial
endmodule begin
$display ("Time x1 x2 y");
x1=0; x2=0;
#1 x1=1;
#1 x2=1;
#1 x1=0;
#1;
end
NAND_gate U1(x1, x2, y);
initial
$monitor("%0d %b %b %b", $time,x1,x2,y);
endmodule
 module NOR_gate(y,x1,x2); module TestBench;
4. NOR gate input x1,x2; reg x1,x2;
output y; wire y;
nor(y,x1,x2); initial
endmodule begin
$display ("Time x1 x2 y");
x1=0; x2=0;
#1 x1=1;
#1 x2=1;
#1 x1=0;
#1;
end
NOR_gate U1(x1, x2, y);
initial
$monitor("%0d %b %b %b", $time,x1,x2,y);
endmodule
module XOR_gate(y,x1,x2); module TestBench;
5. XOR gate input x1,x2; reg x1,x2;
output y; wire y;
xor(y,x1,x2); initial
endmodule begin
$display ("Time x1 x2 y");
x1=0; x2=0;
#1 x1=1;
#1 x2=1;
#1 x1=0;
#1;
end
XOR_gate U1(x1, x2, y);
initial
$monitor("%0d %b %b %b", $time,x1,x2,y);
endmodule
module XNOR_gate(y,x1,x2); module TestBench;
6. XNOR gate input x1,x2; reg x1,x2;
output y; wire y;
xnor(y,x1,x2); initial
endmodule begin
$display ("Time x1 x2 y");
x1=0; x2=0;
#1 x1=1;
#1 x2=1;
#1 x1=0;
#1;
end
XNOR_gate U1(x1, x2, y);
initial
$monitor("%0d %b %b %b", $time,x1,x2,y);
endmodule
C. Transpose the given Verilog
code into Logic Gates circuit
diagram using Logisim Software.
Print Screen the result
Logic Gates Truth Table Truth table using Logisim

1. NOT Gate

2. OR gate

3. NAND gate

4. NOR gate

5. XOR gate

6. XNOR gate