A B C D E

1 1

LCFC Confidential
GS44B/GS54B/GS44C/GS54C MB Schematics Document
2 KBL-U22/U42 with DDR4 + Nvidia N16S-GTR/N17S-G1 2

2019-02
https://vinafix.com
REV:0.1

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 1 of 60
A B C D E
 5 4 3 2 1

LCFC confidential

NV N16x/N17x
Package: FCBGA595 Memory Bus DDR4 SO-DIMM+MDx4
PCI-Express 1.2V DDR4 Page 17/18
D D
4x Gen3
VRAM: 256*32
GDDR5*2: 2GB x1

USB3.0 x1
USB3.0 Conn
HDMI (DDI 1)
HDMI Conn.

eDP x2
eDP Conn x1

Intel MCP
SATA x1 x1
SATA HDD
KBL-R-U22 /U42 15W USB2.0 x1 USB3.0 Conn
C C

NGFF PCI-Express
SSD 4x Gen3
USB2.0 Conn
BGA-1356
NGFF PCIe x1 42mm*24mm

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USB2.0 x1
WLAN&BT

SPI SPI ROM (16MB)

W25Q128JVSIQ
Page 07

SPK Conn.
Page 30
HD Audio x1
Realtek
HP&Mic RTS5199
B Combo Conn. USB2.0 x1 B

Page 30 Page 43

I2C Touch Pad

Page 45
Page 3~16

SD Conn. LPC

IO Board EC GPIO
ITE IT8586E-LQFP128 HALL Sensor
Page 44

Int.KBD
Page 45
Thermal Sensor
F75303M Page 39

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 2 of 61

5 4 3 2 1
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH ON ON ON ON

Power Plane
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
+3VALW +5VS

+5VALW +1.2V +3VS S4 (Suspend to Disk) LOW LOW LOW ON OFF OFF OFF
1 +VCCIO 1
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
V20B+ +3VALW_PCH +2.5V_DDR +VCCSTG
+VCCSA
+1.8VALW +VCCST +VCC_GT
+1.05VALW +CPU_CORE
State +0.6VS
HSIO PORT Function BOM Structure BTO Item
1 USB3.0 Conn @ Un-stuff
2 USB3.0 Conn 14@ For 14" part
3 NC 15@ For 15" part
USB3.0 4 NC YOGA@ For YOGA530 part
S0 O O O O 5 NC 530@ For 530S part
6 NC
1 USB3.0 Conn
S3 O O O X 2 NC
3 USB3.0 Conn CD@ For C cost down
4 USB2.0 conn
S3
2
Battery only O O O X USB2.0 5 Card reader EMC@ For EMC part 2

6 Touch Screen EMC_15@ For EMC 15" part

7 EMC_NS@
S5 S4 Camera For EMC un-stuff part
AC Only O O X X 8 NC EMC_PX@ For EMC PX part
9 NC EMC_PXNS@ For EMC PX nu-stuff part
10
S5 S4 Bluetooth
Battery only O X X X 5~8 DGPU

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X4
S5 S4 ME@ For ME part
9 WLAN
AC & Battery X X X X PCIE 10 NC
don't exist
11 SATA HDD
12 NC OPT@ For NV GPU part
SMBUS Control Table 13~16 OPTN16@ For NV N16S-GTR GPU part
PCIE/SATA SSD
X4 OPTN17@ For NV N17S-G1 GPU part
SOURCE BATT Charger DGPU IT8586E Memory PCH PMIC SODIMM Thermal WLAN
Down Sensor WiMAX

3 3
EC_SMB_CK1 IT8586E
V V X V X X X X X X
EC_SMB_DA1 +3VL_EC +3VL_EC

EC_SMB_CK2 IT8586E
X X V V X V X X V X
EC_SMB_DA2 +3VS +3VG_AON +3VS +3VALW_PCH TS@ For touch screen part
TP@ For TOuch Pad Part
EC_SMB_CK3 IT8586E UMA@
X X X V X X V X X X For UMA part
EC_SMB_DA3 +3VL_EC +3VL_EC

PCH_SMB_CLK PCH
X X X X X V X V X V
PCH_SMB_DATA +3VALW_PCH +3VALW_PCH +3VS +3VS

EC SMBus1 address EC SMBus2 address EC SMBus3 address PCH SM Bus address

Device Address Device Address Device Address Device Address Vinafix.com
Smart Battery need to update Thermal Sensor(NCT7718W) 1001_100xb PMIC need to update DDR4 SODIMM need to update
4 4
Charger 0001 0010 b PCH need to update Wlan Reserved
DGPU need to update

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 3 of 61
A B C D E
 5 4 3 2 1

SKL_ULT ?
UC1A

CPU_HDMI_TXN2 E55 C47 CPU_EDP_TX0-

34 CPU_HDMI_TXN2 CPU_HDMI_TXP2 DDI1_TXN[0] EDP_TXN[0] CPU_EDP_TX0+ CPU_EDP_TX0- 33
HDMI D2 F55 C46
34 CPU_HDMI_TXP2 CPU_HDMI_TXN1 E58 DDI1_TXP[0] EDP_TXP[0] D46 CPU_EDP_TX1- CPU_EDP_TX0+ 33
34 CPU_HDMI_TXN1 CPU_HDMI_TXP1 DDI1_TXN[1] EDP_TXN[1] CPU_EDP_TX1+ CPU_EDP_TX1- 33
HDMI D1 F58 C45
34 CPU_HDMI_TXP1 CPU_HDMI_TXN0 DDI1_TXP[1] EDP_TXP[1] CPU_EDP_TX1+ 33
F53 A45
34 CPU_HDMI_TXN0 CPU_HDMI_TXP0 G53 DDI1_TXN[2] EDP_TXN[2] B45
HDMI D0 34 CPU_HDMI_TXP0 CPU_HDMI_CLKN F56 DDI1_TXP[2] EDP_TXP[2] A47
34 CPU_HDMI_CLKN CPU_HDMI_CLKP G56 DDI1_TXN[3] EDP_TXN[3] B47
HDMI CLK 34 CPU_HDMI_CLKP DDI1_TXP[3] EDP_TXP[3]
D CPU_EDP_AUX# D
C50 E45
D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 CPU_EDP_AUX CPU_EDP_AUX# 33
C52 DDI2_TXP[0] EDP_AUXP CPU_EDP_AUX 33
D52 DDI2_TXN[1] B52
+3VS DDI2_TXP[1] EDP_DISP_UTIL
A50
RPC27 B50 DDI2_TXN[2] G50
1 4 PCH_HDMI_DDC_CLK D51 DDI2_TXP[2] DDI1_AUXN F50
2 3 PCH_HDMI_DDC_DATA C51 DDI2_TXN[3] DDI1_AUXP E48
DDI2_TXP[3] DDI2_AUXN F48
2.2K_0404_4P2R_5% DDI2_AUXP G46
DISPLAY SIDEBANDS DDI3_AUXN F46 +3VS
PCH_HDMI_DDC_CLK L13 DDI3_AUXP
34 PCH_HDMI_DDC_CLK GPP_E18/DDPB_CTRLCLK
PCH_HDMI_DDC_DATA L12 L9 CPU_HDMI_HPD
34 PCH_HDMI_DDC_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 CPU_HDMI_HPD 34
@
N7 GPP_E14/DDPC_HPD1 L6 GPP_E15 RC432 1 2 0_0201_5% GPP_E15 RC1601 1 @ 2 10K_0201_5%
GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 EC_SCI# 44
N8 N9
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 CPU_EDP_HPD CPU_EDP_HPD RC13 1 2 100K_0201_5%
GPP_E17/EDP_HPD CPU_EDP_HPD 33
N11
+VCCIO N12 GPP_E22/DDPD_CTRLCLK R12 PCH_ENBKL
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN PCH_ENBKL 33,44
R11 PCH_EDP_PWM
EDP_COMP EDP_BKLTCTL PCH_EDP_PWM 33
RC4 2 1 24.9_0402_1% E52 U13 PCH_ENVDD
EDP_RCOMP EDP_VDDEN PCH_ENVDD 33
1 OF 20
SKYLAKE-U_BGA1356
+VCCIO&EDP_COMP : REV = 1 ?
Trace Width: 20mil @
Isolation Spacing: 25mil
Max length: 100mil

DDP*_CTRLDATA strapping sampled on the rising edge of PWROK

Port Strap Enable Disable

Pull up to 3.3 V
Port 1 DDPB_CTRLDATA with 2.2Kohm NC
C C
Pull up to 3.3 V
Port 2 DDPC_CTRLDATA with 2.2Kohm NC

+VCCST_CPU
+VCCSTG
1

RC1625
1

49.9_0402_1% SKL_ULT ?
UC1D
RC19 @
1K_0402_5%
CATERR# D63

https://vinafix.com
2

H_PECI A54 CATERR#

44 H_PECI
2

RC20 1 2 499 +-1% 0402 H_PROCHOT#_R C65 PECI

44,55 H_PROCHOT# PROCHOT# JTAG
H_THRMTRIP# C63
A65 THERMTRIP# B61 XDP_TCK
SKTOCC# PROC_TCK D60 XDP_TDI
CPU MISC
1

PAD @ TC11 1 XDP_BPM0# C55 PROC_TDI A61 XDP_TDO

RC143 PAD @ TC12 1 XDP_BPM1# D55 BPM#[0] PROC_TDO C60 XDP_TMS
PAD @ TC13 1 XDP_BPM2# B54 BPM#[1] PROC_TMS B59 XDP_TRST#
1K_0201_5% BPM#[2] PROC_TRST#
PAD @ TC14 1 XDP_BPM3# C56
BPM#[3] B56 PCH_JTAG_TCK
1
2

1 GPP_E3 A6 PCH_JTAG_TCK D59 PCH_JTAG_TDI TC29 PAD @

PAD @ TC162
A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 PCH_JTAG_TDO
+VCCST_CPU BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 PCH_JTAG_TMS
AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 PCH_JTAG_TRST#
GPP_B4/CPU_GP3 PCH_TRST# A59 JTAGX
RC155 1 2 49.9_0402_1% PROC_OPI_RCOMP AT16 JTAGX
RC156 1 2 49.9_0402_1% PCH_OPI_RCOMP AU16 PROC_POPIRCOMP
U23E@ RC157 1 2 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
U23E@ RC170 1 2 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP

SKYLAKE-U_BGA1356 1 OF 20
B B
REV = 1 ?
@

@
XDP_TCK RC3097 1 2 0_0201_5% JTAGX RC1551 1 2 51_0402_5%
@
XDP_TDO RC3101 1 2 0_0201_5% PCH_JTAG_TDO RC1543 1 2 51_0402_5%
+VCCSTG
@
XDP_TDI RC3098 1 2 0_0201_5% PCH_JTAG_TDI
@
XDP_TMS RC3099 1 2 0_0201_5% PCH_JTAG_TMS
@
XDP_TRST# RC3100 1 2 0_0201_5% PCH_JTAG_TRST#

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDI,EDP)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 4 of 60
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1B

AU53
17 DDRA_DQ[0..15] DDRA_DQ0 AL71 DDR0_CKN[0] AT53 DDRA_CLK0# 17
DDRA_DQ1 DDR0_DQ[0] DDR0_CKP[0] DDRA_CLK0 17
AL68 AU55
DDRA_DQ2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55
DDRA_DQ3 AN69 DDR0_DQ[2] DDR0_CKP[1]
DDRA_DQ4 AL70 DDR0_DQ[3] BA56
DDRA_DQ5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDRA_CKE0 17
D DDRA_DQ6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 D
DDRA_DQ7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56
DDRA_DQ8 AR70 DDR0_DQ[7] DDR0_CKE[3]
DDRA_DQ9 AR68 DDR0_DQ[8] AU45
DDRA_DQ10 DDR0_DQ[9] DDR0_CS#[0] DDRA_CS0# 17
AU71 AU43
DDRA_DQ11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45
DDRA_DQ12 DDR0_DQ[11] DDR0_ODT[0] DDRA_ODT0 17
AR71 AT43
DDRA_DQ13 AR69 DDR0_DQ[12] DDR0_ODT[1]
DDRA_DQ14 AU70 DDR0_DQ[13] BA51
DDRA_DQ15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDRA_MA5 17
17 DDRA_DQ[32..47] DDRA_DQ32 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDRA_MA9 17
BB65 BA52
DDRA_DQ33 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDRA_MA6 17
AW65 AY52
DDRA_DQ34 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDRA_MA8 17
DDRA_DQ35 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDRA_MA7 17
AY63 AY55
DDRA_DQ36 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDRA_BG0 17
DDRA_DQ37 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDRA_MA12 17
AY65 BA54
DDRA_DQ38 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDRA_MA11 17
BA63 BA55
DDRA_DQ39 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDRA_ACT# 17
BB63 AY54
DDRA_DQ40 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDRA_BG1 17
BA61
DDRA_DQ41 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46
DDRA_DQ42 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDRA_MA13 17
BB59 AU48
DDRA_DQ43 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDRA_MA15_CAS# 17
AW59 AT46
DDRA_DQ44 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDRA_MA14_WE# 17
BB61 AU50
DDRA_DQ45 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDRA_MA16_RAS# 17
AY61 AU52
DDRA_DQ46 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDRA_BS0# 17
18 DDRB_DQ[0..15] DDRA_DQ47 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDRA_MA2 17
AY59 AT48
DDRB_DQ0 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDRA_BS1# 17
AY39 AT50
DDRB_DQ1 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDRA_MA10 17
AW39 BB50
DDRB_DQ2 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDRA_MA1 17
AY37 AY50 DDRA_DQS#[0..1]
DDRB_DQ3 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDRA_MA0 17
17 DDRA_DQS#[0..1]
DDRB_DQ4 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDRA_MA3 17
BB39 BB52 DDRA_DQS[0..1]
DDRB_DQ5 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDRA_MA4 17
BA39 17 DDRA_DQS[0..1]
C DDRB_DQ6 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDRA_DQS#0 C
DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] DDRA_DQS#[4..5]
DDRB_DQ7 BB37 AM69 DDRA_DQS0 17 DDRA_DQS#[4..5]
DDRB_DQ8 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDRA_DQS#1
DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] DDRA_DQS[4..5]
DDRB_DQ9 AW35 AT70 DDRA_DQS1 17 DDRA_DQS[4..5]
DDRB_DQ10 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDRA_DQS#4
DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] DDRB_DQS#[0..1]
DDRB_DQ11 AW33 AY64 DDRA_DQS4 18 DDRB_DQS#[0..1]
DDRB_DQ12 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDRA_DQS#5
DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] DDRB_DQS[0..1]
DDRB_DQ13 BA35 BA60 DDRA_DQS5 18 DDRB_DQS[0..1]
DDRB_DQ14 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDRB_DQS#0
DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] DDRB_DQS#[4..5]
DDRB_DQ15 BB33 AY38 DDRB_DQS0 18 DDRB_DQS#[4..5]
18 DDRB_DQ[32..47] DDRB_DQ32 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] DDRB_DQS#1
AY31 AY34 DDRB_DQS[4..5]
DDRB_DQ33 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDRB_DQS1 18 DDRB_DQS[4..5]
DDRB_DQ34 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDRB_DQS#4
DDRB_DQ35 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDRB_DQS4
DDRB_DQ36 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDRB_DQS#5
DDRB_DQ37 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDRB_DQS5
DDRB_DQ38 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5]
DDRB_DQ39 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50
DDRB_DQ40 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# DDRA_ALERT# 17
AY27 AT52
DDRB_DQ41 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDRA_PAR 17
AW27 SMVREF

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DDRB_DQ42 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67
DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA DDR_SA_VREFCA 17 WIDTH:20MIL
DDRB_DQ43 AW25 AY68
DDRB_DQ44 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ BA67 DDR_SB_VREFCA
SPACING: 20MIL
DDR CH - A
DDRB_DQ45 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ DDR_SB_VREFCA 18
BA27
DDRB_DQ46 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CNTL
DDRB_DQ47 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL
DDR0_DQ[63]/DDR1_DQ[47]
1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@
B B

+3VALW

RC30
100K_0402_5%
2

CPU_DRAMPG_CNTL 55
+1.2V
RC3
1K_0402_5%
1

C
1 2 2 QC18
B
E
3

MMBT3904WH_SOT323-3

DDR_VTT_CNTL
2

RC29
10K_0402_5%
@
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 5 of 60
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1C
17 DDRA_DQ[16..31]
DDRA_DQ16 AF65 AN45
DDRA_DQ17 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDRB_CLK0# 18
DDRA_DQ18 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDRB_CLK1# 18
DDRA_DQ19 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDRB_CLK0 18
DDRA_DQ20 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDRB_CLK1 18
D DDRA_DQ21 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 D
DDRA_DQ22 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDRB_CKE0 18
DDRA_DQ23 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDRB_CKE1 18
DDRA_DQ24 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDRA_DQ25 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDRA_DQ26 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
DDRA_DQ27 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDRB_CS0# 18
DDRA_DQ28 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDRB_CS1# 18
DDRA_DQ29 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDRB_ODT0 18
DDRA_DQ30 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDRB_ODT1 18
DDRA_DQ31 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48
17 DDRA_DQ[48..63] DDRA_DQ48 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDRB_MA5 18
DDRA_DQ49 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDRB_MA9 18
DDRA_DQ50 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDRB_MA6 18
DDRA_DQ51 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDRB_MA8 18
DDRA_DQ52 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDRB_MA7 18
DDRA_DQ53 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDRB_BG0 18
DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDRB_MA12 18
DDRA_DQ54 AT65 AN48 DDRA_DQS#[2..3]
DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDRB_MA11 18
DDRA_DQ55 AU65 AN53 DDRA_DQS#[2..3] 17
DDRA_DQ56 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDRB_ACT# 18
DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDRB_BG1 18 DDRA_DQS[2..3]
DDRA_DQ57 AU61 DDRA_DQS[2..3] 17
DDRA_DQ58 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43
DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDRB_MA13 18 DDRA_DQS#[6..7]
DDRA_DQ59 AN60 AY43 DDRA_DQS#[6..7] 17
DDRA_DQ60 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDRB_MA15_CAS# 18
DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDRB_MA14_WE# 18 DDRA_DQS[6..7]
DDRA_DQ61 AP61 AW44 DDRA_DQS[6..7] 17
DDRA_DQ62 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDRB_MA16_RAS# 18
18 DDRB_DQ[16..31] DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDRB_BS0# 18 DDRB_DQS#[2..3]
DDRA_DQ63 AU60 AY47 DDRB_DQS#[2..3] 18
DDRB_DQ16 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDRB_MA2 18
DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDRB_BS1# 18 DDRB_DQS[2..3]
DDRB_DQ17 AT40 AW46 DDRB_DQS[2..3] 18
DDRB_DQ18 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDRB_MA10 18
DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDRB_MA1 18 DDRB_DQS#[6..7]
DDRB_DQ19 AU37 BA46 DDRB_DQS#[6..7] 18
DDRB_DQ20 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDRB_MA0 18
DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] DDRB_MA3 18 DDRB_DQS[6..7]
C DDRB_DQ21 AP40 BA47 DDRB_DQS[6..7] 18 C
DDRB_DQ22 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDRB_MA4 18
DDRB_DQ23 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDRA_DQS#2
DDRB_DQ24 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDRA_DQS2
DDRB_DQ25 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDRA_DQS#3
DDRB_DQ26 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDRA_DQS3
DDRB_DQ27 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDRA_DQS#6
DDRB_DQ28 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDRA_DQS6
DDRB_DQ29 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDRA_DQS#7
DDRB_DQ30 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDRA_DQS7
DDRB_DQ31 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDRB_DQS#2
18 DDRB_DQ[48..63] DDRB_DQ48 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDRB_DQS2
DDRB_DQ49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDRB_DQS#3
DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3]

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DDRB_DQ50 AT25 AR32 DDRB_DQS3
DDRB_DQ51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDRB_DQS#6
DDRB_DQ52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDRB_DQS6
DDRB_DQ53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDRB_DQS#7
DDRB_DQ54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDRB_DQS7
DDRB_DQ55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDRB_DQ56 AT22 DDR1_DQ[55] AN43
DDRB_DQ57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43 DDRB_ALERT# 18
DDRB_DQ58 AU21 DDR1_DQ[57] DDR1_PAR AT13 CPU_DRAMRST#_R DDRB_PAR 18
DDRB_DQ59 AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP_0 RC24 1 2 121_0402_1%
DDRB_DQ60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP_1 RC25 1 2 80.6_0402_1%
DDRB_DQ61 AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP_2 RC26 1 2 100_0402_1%
DDRB_DQ62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDRB_DQ63 AN21 DDR1_DQ[62] DDR CH - B according PDG P105: RCOMP[0] value for SDP is 200+/-
DDR1_DQ[63] 1% ohm, and for DDP is 121+/- 1% ohm

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
B @ B

+1.2V
1

RC22
470_0402_5%
2

2 @ 1 0_0402_5% CPU_DRAMRST#_R
RC23
17,18 CPU_DRAMRST#
1
CC1
0.01U_0201_25V6-K
EMC_NS@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 6 of 60
5 4 3 2 1
 5 4 3 2 1

SPI_CLK RC703 1 2 15_0402_5% SPI_CLK_R

44 SPI_CLK SPI_CLK_R 32
+3VALW_PCH
SPI_SO RC701 1 2 15_0402_5% SPI_SO_R
44 SPI_SO SPI_SO_R 32

2
+3VALW_PCH +3VS +3VS
SPI_SI RC702 1 2 15_0402_5% SPI_SI_R RC3088
44 SPI_SI SPI_SI_R 32 ?
100K_0201_5% SKL_ULT
@ UC1E
SPI_CS0# RC704 1 2 @ 0_0402_5% SPI_CS0#_R
44 SPI_CS0#

4
3

4
3
SPI - FLASH
SMBUS, SMLINK
SPI_CLK_R AV2 R7 PCH_SMB_CLK RPC24
SPI0_CLK GPP_C0/SMBCLK RPC1

2
D SPI_SO_R PCH_SMB_DATA D
AW3 R8 DIMM, NGFF 2.2K_0404_4P2R_5%

G
SPI_SI_R AV3 SPI0_MISO GPP_C1/SMBDATA R10 SMB_ALERT# 2.2K_0404_4P2R_5%
SPI_WP#_R AW2 SPI0_MOSI GPP_C2/SMBALERT#

1
2

1
2
SPI_HOLD#_R AU4 SPI0_IO2 R9 SML0_CLK
SPI_CS0#_R AU3 SPI0_IO3 GPP_C3/SML0CLK W2 SML0_DATA PCH_SMB_CLK QC2A 6 1

S
SPI0_CS0# GPP_C4/SML0DATA SML0_ALERT# SMB_CLK_S3 18,40
AU2 W1

D
SPI_CS2#_R AU1 SPI0_CS1# GPP_C5/SML0ALERT# 2N7002KDWH_SOT363-6
32 SPI_CS2#_R SPI0_CS2#

5
W3 PCH_SML1_CLK

G
RC1154 1 @ 2 100K_0201_5% SPI_CLK_R GPP_C6/SML1CLK V3 PCH_SML1_DAT
SPI - TOUCH GPP_C7/SML1DATA SML1_ALERT#
GPU, EC, Thermal Sensor
AM7
M2 GPP_B23/SML1ALERT#/PCHHOT#
1@ 8 BOARD_ID8 M3 GPP_D1/SPI1_CLK PCH_SMB_DATA 3 4
QC2B

S
CC717 GPP_D2/SPI1_MISO SMB_DATA_S3 18,40
J4

D
12P_0201_25V8-J V1 GPP_D3/SPI1_MOSI 2N7002KDWH_SOT363-6
V2 GPP_D21/SPI1_IO2
2 GPP_D22/SPI1_IO3
M1 LPC AY13 LPC_AD0 RE4418 1 2 @ 0_0402_5%
8 BOARD_ID4 GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 BA13 LPC_AD1 1 2 LPC_AD0_EC 44
RE4424 @ 0_0402_5%
GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1_EC 44
BB13 RE4419 1 2 @ 0_0402_5%
C LINK GPP_A3/LAD2/ESPI_IO2 AY12 LPC_AD3 1 2 LPC_AD2_EC 44
RE4420 @ 0_0402_5%
GPP_A4/LAD3/ESPI_IO3 LPC_AD3_EC 44
G3 BA12
CL_CLK GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# 44
G2 BA11
G1 CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET#
CL_RST#
AW9 CLK_PCI_EC_R RC173 2 1 22_0402_5%
GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_EC 44
KBRST# AW13 AY9
44 KBRST# GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 PM_CLKRUN#
AW11
SERIRQ AY11 GPP_A8/CLKRUN#
44 SERIRQ GPP_A6/SERIRQ

RC3122 1 TPM1@ 2 SKYLAKE-U_BGA1356 1 OF 20

32 TPM_SPI_IRQ#
0_0402_5% REV = 1
?
@ LPC_AD3_EC CE4432 1 2 27P_0402_50V8J EMC_NS@
LPC R/C close to PCH
LPC_AD2_EC CE4428 1 2 27P_0402_50V8J EMC_NS@

LPC_AD1_EC CE4429 1 2 27P_0402_50V8J EMC_NS@

C +3V_SPI LPC_AD0_EC C
+3VALW CE4430 1 2 27P_0402_50V8J EMC_NS@
RC3102 @ 0_0402_5% check CLKRUN# / SUS_STAT# signal if need to connect +3VS
CLK_PCI_EC CE4431 1 2 27P_0402_50V8J EMC_NS@
1 2

D2201 2 1 RB520CM-30T2R_VMN2M2
@ PM_CLKRUN# RC11 1 2 8.2K_0402_5%
+3V_SPI
1. If support DS3, connect to +3VS and don't support EC mirror code; RP3402
2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code. SERIRQ 1 4
* KBRST# 2 3
+3VALW_PCH
10K_0404_4P2R_5%

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SMB_ALERT# 2.2K_0402_5% 2 1 RC1562
KBRST# CC1255 1 2 1000P_0201_50V7-K
RPC29
EMC_NS@ SML0_CLK 1 4
+3V_SPI SML0_DATA 2 3

2.2K_0404_4P2R_5%
1

RC60 RC61
1K_0402_5% 1K_0402_5% SML0_ALERT# RC1564 2 @ 1 2.2K_0402_5%
2

This signal has a weak internal pull-down.

SPI_WP#_R RC54 1 2 15_0402_5% SPI_WP# +3VS 0 = LPC Is selected for EC. (Default)
+3VALW_PCH
1 = eSPI Is selected for EC.
SPI_HOLD#_R RC55 1 2 15_0402_5% SPI_HOLD# Notes:
1. The internal pull-down is disabled after RSMRST#
de-asserts.
4
3

Check with BIOS, SPI is Dual mode or quad mode

2. This signal is in the primary wel
RPC30

2
B B
Rising edge of RSMRST#

G
2.2K_0404_4P2R_5% +3VALW_PCH
1
2

+3V_SPI PCH_SML1_CLK QC10A 6 1 SML1_ALERT# RC1569 1 @ 2 150K_0402_5% +3VS

S
EC_SMB_CK2 26,39,44 44 SML1_ALERT#
D

UC3
2N7002KDWH_SOT363-6 RC1655 1 2 150K_0402_5%

5
SPI_CS0# 1 8

G
/CS VCC @
SPI_SO 2 7 SPI_HOLD# 1
DO (IO1) IO3 CC8 To enable Direct Connect Interface (DCI), a 150K pull up resistor will need to be
SPI_WP# 3 6 SPI_CLK 0.1u_0201_10V6K PCH_SML1_DAT QC10B 3 4 added to PCHHOT# pin. This pin must be low during the rising edge of RSMRST#.

S
IO2 CLK EC_SMB_DA2 26,39,44 (Refer to WW52_MOW)
D

4 5 SPI_SI 2 2N7002KDWH_SOT363-6
GND DI (IO0)
@

W25Q64JVSSIQ_SO8

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A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (MISC,JTAG,SPI,LPC,SMB)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 7 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS
@OPT&GC6 Only for NV GPU SKU
+3VS

RC1559 2 OPT@ 1 10K_0402_5% PXS_PWREN_R 1K_0201_5% 2 OPT@ 1 RC7

PXS_PWREN 23 @ FB_GC6_EN_R
RC1629 1 2 10K_0402_5%
PXS_RST#_R FB_GC6_EN_R 23,26
RC1641 1 @ 2 10K_0402_5% RC804 1 @ 2 0_0402_5%
PXS_RST# 26 GPU_EVENT#
RC1630 1 GC6@ 2 10K_0201_5%
Reserve for GPU sequence GPU_EVENT# 26
RC1557 1 OPT@ 2 10K_0402_5% PXS_RST#_R RC1637 1 @ 2 10K_0402_5% FB_GC6_EN_R

CC1259 1 2 0.01U_0201_10V6K PXS_RST# RC1638 1 @ 2 10K_0201_5% GPU_EVENT#

OPT@
D D
DGPU_PWROK
DGPU_PWROK 23,57

@UMA SKU SKL_ULT ?

2 10K_0201_5% DGPU_PWROK UC1F
RC1558 1 UMA@
LPSS ISH

AN8 P2 BOARD_ID0
AP7 GPP_B15/GSPI0_CS# GPP_D9 P3 BOARD_ID1
AP8 GPP_B16/GSPI0_CLK GPP_D10 P4 BOARD_ID2
RC1561 1 @ 2 2.2K_0402_5% GPP_B18 AR7 GPP_B17/GSPI0_MISO GPP_D11 P1 BOARD_ID3
+3VS +3VS GPP_B18/GSPI0_MOSI GPP_D12
AM5 M4
RPC28 AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3
1 4 PCH_I2C_SCL0 AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
2 3 PCH_I2C_SDA0 RC1563 1 @ 2 2.2K_0402_5% GPP_B22 AN5 GPP_B21/GSPI1_MISO N1
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
2.2K_0404_4P2R_5% UART_RX_DEBUG AB1 GPP_D8/ISH_I2C1_SCL
40 UART_RX_DEBUG UART_TX_DEBUG AB2 GPP_C8/UART0_RXD AD11
40 UART_TX_DEBUG GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA
W4 AD12
AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_C11/UART0_CTS#
PXS_PWREN_R AD1 U1
PXS_RST#_R AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2
DGPU_PWROK AD3 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3 PCH_WLAN_OFF#
FB_GC6_EN_R GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# PCH_BT_OFF# PCH_WLAN_OFF# 40
AD4 U4
2 RC1658 1 PCH_TP_INT# GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# PCH_BT_OFF# 40
AC1 PCH_TS_IRQ @
10K_0402_5% PCH_I2C_SDA0 U7 GPP_C12/UART1_RXD/ISH_UART1_RXD PCH_TS_RST# 2 RC3114 1
RC831 1 @ 2 0_0402_5% AC2
45 TP_I2C_SDA0 PCH_I2C_SCL0 U6 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD GPU_EVENT#
Touch PAD RC3103 1 @ 2 0_0402_5% AC3
45 TP_I2C_SCL0 GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# PCH_TP_INT# 10K_0402_5%
AB4
U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS# PCH_TP_INT# 45
U9 GPP_C18/I2C1_SDA AY8
C C
GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8 BOARD_ID6
AH9 GPP_A19/ISH_GP1 BB7 BOARD_ID5
AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7 AOAC_ON#
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7 AOAC_ON# 40
AH11 GPP_A22/ISH_GP4 AW7
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13
GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6
AF11
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
+3VALW +3VS +3VS
SKYLAKE-U_BGA1356 1 OF 20
RC1600 1 @ 2 1K_0402_5% REV = 1 ?
@
HDA_SDOUT

15@
RC47 1 @ 2 1K_0402_5%

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@
OPT@

OPTN17@
*

RC814 17@
2

2
@

2
@

2
@
HDA_SDO This signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash Descriptor.

RC807

RC808

RC809

RC810

RC811

RC805

RC812

RC3062
1 = Disable Flash Descriptor Security(override). This strap
should only be asserted high during external pull-up in RC42&RC43&RC45 due to nolink CIS,
manufacturing/debug environments ONLY.

1
cant choose the Component,so choose one instead the location UC1G SKL_ULT ? BOARD_ID0
SD00000LH8J, S RES 1/20W 33 +-5% 0201 BOARD_ID1

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%
AUDIO BOARD_ID2
changed the VALUE and LCFC PN for BOM BOARD_ID3
RC43 2 1 33_0201_5% HDA_SYNC BA22 BOARD_ID4
30 HDA_SYNC_AUDIO HDA_BCLK HDA_SYNC/I2S0_SFRM 7 BOARD_ID4 BOARD_ID5
RC42 2 1 33_0201_5% AY22
30 HDA_BITCLK_AUDIO HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK BOARD_ID6
SDIO/SDXC
HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD BOARD_ID7
30 HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11 BOARD_ID8
HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD 7 BOARD_ID8
For EMI 1 AW22 AB13
HDA_SDIN0 For EMI PAD @ HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0
HDA_BCLK TC808 J5 AB12
1 AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
1 I2S1_SFRM GPP_G3/SD_DATA2
CC7 AW20 W11
10P_0201_50V8F CC4220 CC4220 for EMC demand,due to nolink CIS, I2S1_TXD GPP_G4/SD_DATA3 W10
EMC_NS@ 56P_50V_J_NPO_0201
cant choose the Component,so choose one instead the location AK7 GPP_G5/SD_CD# W8

UMAorN16@
B 2 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK B
2 or change x5r&x7r if suit,sutff AK6 W7

14or15@
EMC@ SE00001AF00, S CER CAP 56P 50V J NPO 0201 GPP_F0/I2S2_SCLK GPP_G7/SD_WP

UMA@
AK9

14or17@
Close to PCH GPP_F2/I2S2_TXD

@
AK10 BA9 @
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL @

2
@
H5 AB7 SD_RCOMP
GPP_D19/DMIC_CLK0 SD_RCOMP

RC826

10K_0201_5% RC818

RC819

RC820

RC821

RC822

RC823

RC824

RC3064
RC45 2 1 33_0201_5% HDA_SDOUT D7
30 HDA_SDOUT_AUDIO GPP_D20/DMIC_DATA0
RC3104 1 @ 2 0_0402_5%
44 ME_FLASH

1
D8 AF13

10K_0201_5% 1

1
BOARD_ID7 C8 GPP_D17/DMIC_CLK1 GPP_F23 RC49
GPP_D18/DMIC_DATA1 200_0402_1%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%
PCH_BEEP AW5
30 PCH_BEEP GPP_B14/SPKR

2
+3VS
SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
RC14 1 @ 2 2.2K_0402_5% PCH_BEEP @
RC3113 PCH_TS_IRQ
2 1@
10K_0402_5%
+1.8VALW
Default When
Pin Name Strap Description Configuration +3VALW_PCH
Value Sampled
2

Internal PD RC834
0 = Disable “Top Swap” HDA18@ 4.7K_0402_5%
2

SPKR / Top Swap 0 Rising edge

GPP_B14 Override
mode. (Default) * of PCH_PWROK RC3108
1

1 = Enable “Top Swap” HDA18@

10K_0402_5%
mode. HDA_SDOUT
Internal PD
1

GSPI0_MOSI 0 = Disable “No Reboot” Rising edge Q4609 D

/GPP_B18 No Reboot 0 of PCH_PWROK ME_FLASH# 2
mode. (Default)
1 = Enable “No Reboot”
* G
1

A mode Q4610 D HDA18@ S L2N7002KWT1G_SOT323-3 A

3

ME_FLASH 2
GSPI1_MOSIBoot BIOS Internal PD Rising edge G
/GPP_B22 Strap Bit 0 = SPI (Default) 0 of PCH_PWROK
BBS 1 = LPC * HDA18@ S L2N7002KWT1G_SOT323-3
3

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (LPSS,ISH,AUDIO,SDIO)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 8 of 60
5 4 3 2 1
 5 4 3 2 1

20 PCIE_CRX_GTX_N[5..8]

20 PCIE_CRX_GTX_P[5..8]

20 PCIE_CTX_C_GRX_N[5..8]

20 PCIE_CTX_C_GRX_P[5..8]

SKL_ULT
?
UC1H
D D

SSIC / USB3
PCIE/USB3/SATA
H8 USB30_RX_N1
USB3_1_RXN USB30_RX_P1 USB30_RX_N1 43
G8
PCIE_CRX_GTX_N5 H13
PCIE1_RXN/USB3_5_RXN
USB3_1_RXP
USB3_1_TXN
C13 USB30_TX_N1 USB30_RX_P1
USB30_TX_N1
43
43
USB3.0
PCIE_CRX_GTX_P5 G13 D13 USB30_TX_P1
PCIE_CTX_C_GRX_N5 PCIE_CTX_GRX_N5 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB30_TX_P1 43
0.22U_0201_6.3V6-K OPT@ 1 2 CC16 B17
PCIE_CTX_C_GRX_P5 0.22U_0201_6.3V6-K OPT@ 1 2 CC14 PCIE_CTX_GRX_P5 A17 PCIE1_TXN/USB3_5_TXN J6 USB30_RX_N2
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB30_RX_P2 USB30_RX_N2 41
H6
PCIE_CRX_GTX_N6 USB3_2_RXP/SSIC_1_RXP USB30_TX_N2 USB30_RX_P2 41
G11 B13
PCIE_CRX_GTX_P6 F11 PCIE2_RXN/USB3_6_RXN
PCIE2_RXP/USB3_6_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
A13 USB30_TX_P2 USB30_TX_N2
USB30_TX_P2
41
41
USB3.0
PCIE_CTX_C_GRX_N6 0.22U_0201_6.3V6-K OPT@ 1 2 CC15 PCIE_CTX_GRX_N6 D16
PCIE_CTX_C_GRX_P6 0.22U_0201_6.3V6-K OPT@ 1 2 CC17 PCIE_CTX_GRX_P6 C16 PCIE2_TXN/USB3_6_TXN J10
DGPU PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
H10
PCIE_CRX_GTX_N7 H16 B15
PCIE_CRX_GTX_P7 G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15
PCIE_CTX_C_GRX_N7 0.22U_0201_6.3V6-K OPT@ 1 2 CC18 PCIE_CTX_GRX_N7 D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
PCIE_CTX_C_GRX_P7 0.22U_0201_6.3V6-K OPT@ 1 2 CC19 PCIE_CTX_GRX_P7 C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
PCIE_CRX_GTX_N8 G15 USB3_4_RXP C15
PCIE_CRX_GTX_P8 F15 PCIE4_RXN USB3_4_TXN D15
PCIE_CTX_C_GRX_N8 0.22U_0201_6.3V6-K OPT@ 1 2 CC20 PCIE_CTX_GRX_N8 B19 PCIE4_RXP USB3_4_TXP
PCIE_CTX_C_GRX_P8 0.22U_0201_6.3V6-K OPT@ 1 2 CC21 PCIE_CTX_GRX_P8 A19 PCIE4_TXN AB9 USB20_N1
PCIE4_TXP USB2N_1 USB20_N1 41
PCIE_PRX_DTX_N9 F16 USB2P_1
AB10 USB20_P1
USB20_P1 41 USB3.0
40 PCIE_PRX_DTX_N9 PCIE_PRX_DTX_P9 PCIE5_RXN
E16 AD6
40 PCIE_PRX_DTX_P9 PCIE_PTX_DRX_N9 PCIE5_RXP USB2N_2
CC1264 1 2 0.1u_0201_10V6K C19 AD7
40 PCIE_PTX_C_DRX_N9 PCIE5_TXN USB2P_2
WLAN 40 PCIE_PTX_C_DRX_P9
CC1263 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_P9 D19
PCIE5_TXP AH3 USB20_N3
USB2N_3 USB20_N3 43
G18
F18 PCIE6_RXN USB2P_3
AJ3 USB20_P3
USB20_P3 43 USB3.0
D20 PCIE6_RXP AD9 USB20_N4
PCIE6_TXN USB2N_4 USB20_N4 43
C20
PCIE6_TXP USB2P_4
AD10 USB20_P4
USB20_P4 43 USB2.0
SATA_PRX_DTX_N0 F20 AJ1 USB20_N5
PCIE7_RXN/SATA0_RXN USB2N_5 USB20_N5 30
38 SATA_PRX_DTX_N0
38 SATA_PRX_DTX_P0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
E20
B21 PCIE7_RXP/SATA0_RXP USB2P_5
AJ2 USB20_P5
USB20_P5 30 Card reader
C
HDD 38 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 A21 PCIE7_TXN/SATA0_TXN
PCIE7_TXP/SATA0_TXP
USB2

USB2N_6
AF6 USB20_N6
USB20_N6 33
C

38 SATA_PTX_DRX_P0
G21 USB2P_6
AF7 USB20_P6
USB20_P6 33 Touch Screen
F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N10
PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_P10 USB20_N10 40
D21 AH2
C21 PCIE8_TXN/SATA1A_TXN
PCIE8_TXP/SATA1A_TXP
USB2P_7 USB20_P10 40 BT
AF8 USB20_N7
PCIE_PRX_DTX_N13 USB2N_8 USB20_P7 USB20_N7 33
E22 AF9
37 PCIE_PRX_DTX_N13 PCIE_PRX_DTX_P13 E23 PCIE9_RXN
PCIE9_RXP
USB2P_8 USB20_P7 33 Camera
37 PCIE_PRX_DTX_P13 PCIE_PTX_DRX_N13 B23 AG1
37 PCIE_PTX_DRX_N13 PCIE_PTX_DRX_P13 A23 PCIE9_TXN USB2N_9 AG2
PCIE9_TXP USB2P_9

Vinafix.com
37 PCIE_PTX_DRX_P13
PCIE_PRX_DTX_N14 F25 AH7
37 PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 E25 PCIE10_RXN USB2N_10 AH8 +3VALW_PCH
37 PCIE_PRX_DTX_P14 PCIE_PTX_DRX_N14 D23 PCIE10_RXP USB2P_10

https://vinafix.com
37 PCIE_PTX_DRX_N14 PCIE_PTX_DRX_P14 C23 PCIE10_TXN AB6 USB2_COMP RC118 2 1 113_0402_1% USBRBIAS RPC17
37 PCIE_PTX_DRX_P14 PCIE10_TXP USB2_COMP AG3 USB2_ID RC1626 1 @ 2 0_0402_5% Width 20Mil 1 8 USB_OC0#
RC119 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC1627 1 2 1K_0402_5% Space 15Mil 2 7 USB_OC1#
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE Length 500Mil 3 6 USB_OC3#
PCIE_RCOMPP A9 USB_OC0# 4 5 USB_OC2#
GPP_E9/USB2_OC0# USB_OC0# 43
SSD PCIE_RCOMPN and PCIE_RCOMPP
Trace Width: 12-15mil
PAD @ TC20
PAD @ TC19
1 XDP_PRDY#
1 XDP_PREQ#
D56
D61 PROC_PRDY# GPP_E10/USB2_OC1#
C9
D9
USB_OC1#
USB_OC2# USB_OC1# 41
10K_0804_8P4R_5%
Differential between RCOMPP/RCOMPN PROC_PREQ# GPP_E11/USB2_OC2# USB_OC3# USB_OC2# 43
RC1541 1 TPM@ 2 PIRQA# BB11 B9
32 TPM_SPI_IRQ# GPP_A7/PIRQA# GPP_E12/USB2_OC3#
0_0402_5% @
PCIE_PRX_DTX_N15 E28 J1 GPP_E4 RC1628 1 2 0_0201_5%
37 PCIE_PRX_DTX_N15 PCIE_PRX_DTX_P15 E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 EC_SMI# 44 2016/05/03: Implement as Power Button
37 PCIE_PRX_DTX_P15 PCIE_PTX_DRX_N15 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 function for Windows RedStone support
D24 J3
37 PCIE_PTX_DRX_N15 PCIE_PTX_DRX_P15 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 PCH_SATA_DEVSLP 37
C24
37 PCIE_PTX_DRX_P15 PCIE_PRX_DTX_N16 E30 PCIE11_TXP/SATA1B_TXP H2
37 PCIE_PRX_DTX_N16 SATA0GP
PCIE_PRX_DTX_P16 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 SSD_1_PCIE_DET#
37 PCIE_PRX_DTX_P16 PCIE_PTX_DRX_N16 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 SSD_PCIE_DET#
A25 G4
37 PCIE_PTX_DRX_N16 PCIE_PTX_DRX_P16 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 SSD_PCIE_DET# 37
B25
37 PCIE_PTX_DRX_P16 PCIE12_TXP/SATA2_TXP H1
GPP_E8/SATALED#

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
B B
@

+3VS
+3VS
RC3115 1 2 10K_0402_5% SSD_PCIE_DET#

RC3116 1 2 10K_0402_5% PIRQA#

GPP_E4 RC1617 2 @ 1 10K_0201_5%
RC3117 1 2 10K_0402_5% SATA0GP

RC3118 1 @ 2 10K_0402_5% SSD_1_PCIE_DET#

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCIE,SATA,USB3,USB2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 9 of 60
5 4 3 2 1
 5 4 3 2 1

UC1I
SKL_ULT ?

CSI-2

A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
D CSI2_DP3 CSI2_CLKP3 D

C31 E13 CSI2_COMP RC73 1 2 100_0402_1%

D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 EMMC_RCOMP RC50 1 2 200_0402_1%
EMMC_RCOMP
SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

@DIS For NV GPU SKU UC1J SKL_ULT ?

C CLOCK SIGNALS C

CLK_PCIE_GPU# D42
20 CLK_PCIE_GPU# CLK_PCIE_GPU C42 CLKOUT_PCIE_N0
PCIE CLK0 DGPU 20 CLK_PCIE_GPU GPU_CLKREQ# CLKOUT_PCIE_P0
AR10
20 GPU_CLKREQ# GPP_B5/SRCCLKREQ0#
B42
A42 CLKOUT_PCIE_N1 F43 SUSCLK RC95 1 @ 2 1K_0402_5%
+3VS AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
RPC4 CLK_PCIE_WLAN# D41 BA17 SUSCLK
1 4 GPU_CLKREQ# 40 CLK_PCIE_WLAN# CLK_PCIE_WLAN C41 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK 40
2 3 SSD_CLKREQ# WLAN 40 CLK_PCIE_WLAN WLAN_CLKREQ# AT8 CLKOUT_PCIE_P2 E37 XTAL24_U22_IN
40 WLAN_CLKREQ# GPP_B7/SRCCLKREQ2# XTAL24_IN

https://vinafix.com
E35 XTAL24_U22_OUT +VCCCLK5
10K_0404_4P2R_5% D40 XTAL24_OUT
RC3123 1 2 WLAN_CLKREQ# C40 CLKOUT_PCIE_N3 E42 DIFFCLK_BIASREF RC72 1 2 2.7K_0402_1%
AT10 CLKOUT_PCIE_P3 XCLK_BIASREF
10K_0402_5% GPP_B8/SRCCLKREQ3# AM18 RTC_X1
CLK_PCIE_SSD# B40 RTCX1 AM20 RTC_X2
37 CLK_PCIE_SSD# CLK_PCIE_SSD A40 CLKOUT_PCIE_N4 RTCX2
SSD-1 37 CLK_PCIE_SSD SSD_CLKREQ# AU8 CLKOUT_PCIE_P4 AN18 SRTC_RST#
37 SSD_CLKREQ# GPP_B9/SRCCLKREQ4# SRTCRST# AM16 RTC_RST#
E40 RTCRST#
E38 CLKOUT_PCIE_N5
AU7 CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#

1U_0402_6.3V6K
1 OF 20 1
SKYLAKE-U_BGA1356

CC3
REV = 1 ? VCCRTC
@
B U22_NF@ 2 B
RC3035 2 1 0_0402_5% SRTC_RST#
RC33 1 2 20K_0402_1%
RC34 1 2 20K_0402_1% RTC_RST# RC1624 1 @ 2 0_0402_5%
EC_RTC_RST# 44
L1 U22_EMC_NS@

1U_0402_6.3V6K
XTAL24_U22_IN_R 1 2 XTAL24_U22_IN 1

1
1 2

CC6
JCMOS3
XTAL24_U22_OUT_R 4 3 XTAL24_U22_OUT 2 JCMOS2
4 3 @
@

1
EXC24CH900U_4P Place Bottom
SM070004400
U22_NF@
RC3034 1 2 0_0402_5%

note:U22_NF@ represent the i3-7020U 2.3G/2C/3M

RC3030 U22_NF@
2 1
RTC_X1
1M_0201_5%
YC3
24MHZ_8PF_7R24080003 RC32 2 1 10M_0402_5% RTC_X2

XTAL24_U22_OUT_R 1 3 XTAL24_U22_IN_R YC1

CC1324 1 1 3 CC1325 1 2
GND1 GND2 1
15P_50V_J_NPO_0201 15P_50V_J_NPO_0201
U22_NF@ U22_NF@ U22_NF@ 1 32.768KHZ_9PF_X1A0001410002 1
2 4
2 2 CC4 CC5
7P_50V_D_NPO_0402 7P_50V_D_NPO_0402
KBL U22 Use 2 2
A A

the R,C Change value and Footprint,and YC3 Must be changed:

RC3030: SD04310048J, S RES 1/20W 1M +-5% 0201,
changed RC3030 LCFC PN for BOM
Changed YC3 CC1324 CC1325 source for BOM according the owner recommodation:
YC3:SJ10000S500&SJ10000TG00 CC1324&CC1325:SE00001AD00
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CSI2,EMMC,CLOCK)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 10 of 60
5 4 3 2 1
 5 4 3 2 1

2
CC1322 ?
SKL_ULT
0.1U_0402_25V6 UC1K
EMC_NS@
1 SYSTEM POWER MANAGEMENT
AT11
@ GPP_B12/SLP_S0# AP15 PM_SLP_S3#_R RC96 @1 2 0_0402_5%
1 2 0_0201_5% PLT_RST#_R AN10 GPD4/SLP_S3# BA16 PM_SLP_S4#_R 2 0_0402_5% PM_SLP_S3# 44
RC84 RC97 @1
32 PLT_RST# SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 PM_SLP_S4# 44
@
D RC85 1 2 0_0402_5% PCH_RSMRST#_R AY17 SYS_RESET# GPD10/SLP_S5# D
44 EC_RSMRST# RSMRST# AN15 PM_SLP_SUS#_R 1
1 CPU_PROCPWRGD A68 SLP_SUS# AW15 TC211 @ PAD
@ PAD TC21
VCCST_PWRGD_R RC93 1 2 60.4_0402_1% VCCST_PWRGD B65 PROCPWRGD SLP_LAN# BB17
VCCST_PWRGD GPD9/SLP_WLAN# AN16
RC139 @1 2 0_0201_5% SYS_PWROK_R B6 GPD6/SLP_A#
44 SYS_PWROK 2 0_0402_5% PCH_PWROK_R BA20 SYS_PWROK BA15 PBTN_OUT#_R 2 0_0402_5%
RC126 @1 RC87 @1
44 PCH_PWROK PCH_DPWROK_R BB20 PCH_PWROK GPD3/PWRBTN# AY15 AC_PRESENT_R PBTN_OUT# 44
DSW_PWROK GPD1/ACPRESENT AU13 BATLOW#
SUSWARN#_R AR13 GPD0/BATLOW#
RC1189 1 @ 2 10K_0402_5% SUSACK#AP11 GPP_A13/SUSWARN#/SUSPWRDNACK VCCRTC
GPP_A15/SUSACK# AU11
+3VALW PCIE_WAKE# BB15 GPP_A11/PME# AP16 INTVRMEN RC41 2 1 330K_0402_5%
40 PCIE_WAKE# PCH_LAN_WAKE# AM15 WAKE# INTRUDER#
U4404
AW17 GPD2/LAN_WAKE# AM10
1 5 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE#
PLT_RST# NC VCC AT15 AM11
2 GPD7/RSVD GPP_B2/VRALERT#
3 A 4
GND Y PLT_RST#_B 26,37,40,44
SKYLAKE-U_BGA1356 1 OF 20
SN74LVC1G17DCKR_SC70-5
REV = 1 ?
@ @
RC3107
PLT_RST# 1 2 PLT_RST#_B
RC88 @1 2 0_0402_5% AC_PRESENT_R
44 AC_PRESENT
1/16W_22_1%_0402

V0.2 add PLT_RST# buffer

C +VCCST_CPU C

+3VALW

1
RC137
RC74 1 2 10K_0402_5% AC_PRESENT_R 1K_0201_5%
RC75 2 1 10K_0201_5% BATLOW#

2
RC1599 @1 2 0_0402_5% VCCST_PWRGD_R
RC76 2 1 1K_0402_5% PCIE_WAKE# 44 EC_VCCST_PWRGD
RC90 10K_0201_5%

https://vinafix.com
2 1 PCH_LAN_WAKE# 2
Follow CRB change to 1kohm CC140
1000P_0201_50V7-K
+3VALW_PCH 1
PCH_DPWROK_R RC182 @1 2 0_0402_5% EC_RSMRST#

RC78 1 @ 2 10K_0402_5% SUSWARN#_R

+3VS

RC80 10K_0201_5%
2 1 SYS_RESET#

2200P_0402_50V7K 2@ 1 CC1105 +3V_PWRGD_R

B B
EMC_NS@
1000P_0201_50V7-K 1 2 CC1254 PCH_RSMRST#_R

0.01U_0201_10V6K 1 2 CC104 PCH_PWROK

1000P_0201_50V7-K 1 2 CC103 PCH_DPWROK_R D5101

0_0402_5%
EMC_NS@ +3V_PWRGD_R EC_RSMRST#
54 +3VALW_PG RC11221 @ 2 1 2

47P_0201_25V8-J 1 2 CC101 @ SYS_PWROK 1 2

RC1123 @1 2 0_0402_5%
54,55 ALW_PWRGD
RB521CM-30T2R_VMN2M-2
0.01U_0201_10V6K 1 2 CC1260 EC_RSMRST#

Add to fix Reset&PWRGD test fail issue

RC3119 1 2 10K_0402_5% PCH_RSMRST#_R

RC3120 1 2 10K_0402_5% PCH_PWROK

RC3121 1 2 10K_0402_5% SYS_PWROK

A A

330P_0402_50V7K 1 2 CC1294

100K_0201_5% 1 2 RC92 PLT_RST#_R

Security Classification LC Future Center Secret Data Title
100K_0402_1% 2 @ 1 RC94 PCH_DPWROK_R
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (SYSTEM PWR MANAGEMENT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 11 of 60
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE ? +CPU_CORE +CPU_CORE +VCC_GT +VCC_GT

SKL_ULT SKL_ULT ?
UC1L +VCCCORE_GT2 +VCC_GT UC1M
CPU POWER 1 OF 4
VCORE_VCC_SEN RC77 1 2 100_0402_1% VCCGT_VCC_SEN RC83 1 2 100_0402_1% CPU POWER 2 OF 4
A30 G32 N70
A34 VCC_A30 VCC_G32 G33 A48 VCCGT_N70 N71
A39 VCC_A34 VCC_G33 G35 VCORE_VSS_SEN RC82 1 2 100_0402_1% VCCGT_VSS_SEN RC98 1 2 100_0402_1% A53 VCCGT_A48 VCCGT_N71 R63
A44 VCC_A39 VCC_G35 G37 A58 VCCGT_A53 VCCGT_R63 R64
AK33 VCC_A44 VCC_G37 G38 A62 VCCGT_A58 VCCGT_R64 R65
AK35 VCC_AK33 VCC_G38 G40 A66 VCCGT_A62 VCCGT_R65 R66
AK37 VCC_AK35 VCC_G40 G42 AA63 VCCGT_A66 VCCGT_R66 R67
AK38 VCC_AK37 VCC_G42 J30 AA64 VCCGT_AA63 VCCGT_R67 R68
AK40 VCC_AK38 VCC_J30 J33 AA66 VCCGT_AA64 VCCGT_R68 R69
AL33 VCC_AK40 VCC_J33 J37 AA67 VCCGT_AA66 VCCGT_R69 R70
AL37 VCC_AL33 VCC_J37 J40 AA69 VCCGT_AA67 VCCGT_R70 R71
AL40 VCC_AL37 VCC_J40 K33 AA70 VCCGT_AA69 VCCGT_R71 T62
AM32 VCC_AL40 VCC_K33 K35 +VCCST_CPU AA71 VCCGT_AA70 VCCGT_T62 U65
D
VCC_AM32 VCC_K35 SVID VCCGT_AA71 VCCGT_U65
D
AM3 3 K37 AC6 4 U68
AM35 VCC_AM33 VCC_K37 K38 AC65 VCCGT_AC64 VCCGT_U68 U71
AM37 VCC_AM35 VCC_K38 K40 AC66 VCCGT_AC65 VCCGT_U71 W63
AM38 VCC_AM37 VCC_K40 K42 AC67 VCCGT_AC66 VCCGT_W63 W64
G30 VCC_AM38 VCC_K42 K43 AC68 VCCGT_AC67 VCCGT_W64 W65
VCC_G30 VCC_K43 AC69 VCCGT_AC68 VCCGT_W65 W66
1 VCCGT_AC69 VCCGT_W66
1 K32 E32 VCORE_VCC_SEN CC42 AC70 W67
@ TC90 RSVD_K32 VCC_SENSE E33 VCORE_VSS_SEN VCORE_VCC_SEN 58 0.1u_0201_10V6K AC71 VCCGT_AC70 VCCGT_W67 W68
VSS_SENSE VCORE_VSS_SEN 58 VCCGT_AC71 VCCGT_W68

1
56_0402_5%
AK32 J43 W69

100_0402_1%

100_0402_1%
@
RSVD_AK32 B63 CPU_SVID_ALERT#_R 2 J45 VCCGT_J43 VCCGT_W69 W70

RC131

RC132
RC1544
AB62 VIDALERT# A63 CPU_SVID_CLK_R J46 VCCGT_J45 VCCGT_W70 W71
P62 VCCOPC_AB62 VIDSCK D64 CPU_SVID_DAT_R J48 VCCGT_J46 VCCGT_W71 Y62
V62 VCCOPC_P62 VIDSOUT J50 VCCGT_J48 VCCGT_Y62 +VCCCORE_GT1

2
VCCOPC_V62 G20 J52 VCCGT_J50
VCCSTG_G20 +VCCSTG VCCGT_J52
H63 @ J53 AK42
VCC_OPC_1P8_H63 J55 VCCGT_J53 VCCGTX_AK42 AK43
G61 J56 VCCGT_J55 VCCGTX_AK43 AK45
VCC_OPC_1P8_G61 RC133 1 2 220_0402_1% CPU_SVID_ALERT#_R J58 VCCGT_J56 VCCGTX_AK45 AK46
58 VR_SVID_ALRT# VCCGT_J58 VCCGTX_AK46
AC63 J60 AK48
AE63 VCCOPC_SENSE +VCCCOREG2_GT K48 VCCGT_J60 VCCGTX_AK48 AK50
VSSOPC_SENSE K50 VCCGT_K48 VCCGTX_AK50 AK52
RC134 @1 2 0_0402_5% CPU_SVID_CLK_R VCCGT_K50 VCCGTX_AK52
AE62 58 VR_SVID_CLK K52 AK53
AG62 VCCEOPIO_AE62 K53 VCCGT_K52 VCCGTX_AK53 AK55
VCCEOPIO_AG62 K55 VCCGT_K53 VCCGTX_AK55 AK56
RC1545 @1 2 0_0402_5% CPU_SVID_DAT_R VCCGT_K55 VCCGTX_AK56
AL63 58 VR_SVID_DAT K56 AK58
AJ62 VCCEOPIO_SENSE K58 VCCGT_K56 VCCGTX_AK58 AK60
VSSEOPIO_SENSE K60 VCCGT_K58 VCCGTX_AK60 AK70
1, Alert# Route Between CLK and Data L62 VCCGT_K60 VCCGTX_AK70 AL43
SKYLAKE-U_BGA1356 1 OF 20 L63 VCCGT_L62 VCCGTX_AL43 AL46
REV = 1 ? L64 VCCGT_L63 VCCGTX_AL46 AL50
@ L65 VCCGT_L64 VCCGTX_AL50 AL53
L66 VCCGT_L65 VCCGTX_AL53 AL56
L67 VCCGT_L66 VCCGTX_AL56 AL60
L68 VCCGT_L67 VCCGTX_AL60 AM48
L69 VCCGT_L68 VCCGTX_AM48 AM50
L70 VCCGT_L69 VCCGTX_AM50 AM52
L71 VCCGT_L70 VCCGTX_AM52 AM53
M62 VCCGT_L71 VCCGTX_AM53 AM56
N63 VCCGT_M62 VCCGTX_AM56 AM58
C
N64 VCCGT_N63 VCCGTX_AM58 AU58 C

N66 VCCGT_N64 VCCGTX_AU58 AU63

Vinafix.com
N67 VCCGT_N66 VCCGTX_AU63 BB57
N69 VCCGT_N67 VCCGTX_BB57 BB66
VCCGT_N69 VCCGTX_BB66
VCCGT_VCC_SEN J70 AK62
58 VCCGT_VCC_SEN VCCGT_VSS_SEN J69 VCCGT_SENSE VCCGTX_SENSE AL61
58 VCCGT_VSS_SEN VSSGT_SENSE VSSGTX_SENSE

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

https://vinafix.com

B B
+VCCCORE_GT2
+VCCCORE_GT2
+CPU_CORE

RC1068 1 U42_F@ 2 0.0002_0805

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 1 1
CC1326

CC1327

CC1328

CC1329

+VCC_GT
@2 2 2 @2
RC1069 1 U22_NF@
2 0.0002_0805 @

07/04 add location based on Layout condition

+VCCCORE_GT1
+CPU_CORE

+VCCCORE_GT1
RC1070 1 U42_F@ 2 0.0002_0805

+VCC_GT +VCCCOREG2_GT
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 1
RC3029 1 2 0_0402_5%
CC1330

CC1331

CC1332

U22_NF@

2 2 2

U42_F@ U42_F@U42_F@

07/04 add location based on Layout condition

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/12/14 Deciphered Date 2017/12/13 MCP (CPU PWR1)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 12 of 60
5 4 3 2 1
 5 4 3 2 1

+VCCIO
?
+1.2V UC1N SKL_ULT

CPU POWER 3 OF 4

2800mA AU23 AK28 3100mA

AU28 VDDQ_AU23 VCCIO_AK28 AK30
AU35 VDDQ_AU28 VCCIO_AK30 AL30
AU42 VDDQ_AU35 VCCIO_AL30 AL42
BB23 VDDQ_AU42 VCCIO_AL42 AM28
BB32 VDDQ_BB23 VCCIO_AM28 AM30 +VCCSA
BB41 VDDQ_BB32 VCCIO_AM30 AM42
BB47 VDDQ_BB41 VCCIO_AM42
D VDDQ_BB47 D
BB51 AK23 5100mA
VDDQ_BB51 VCCSA_AK23 AK25
VCCSA_AK25 G23
AM40 VCCSA_G23 G25
+VDDQ_CPU_CLK VDDQC VCCSA_G25 G27
A18 VCCSA_G27 G28
+VCCST_CPU VCCST VCCSA_G28 J22
A22 VCCSA_J22 J23
+VCCSTG VCCSTG_A22 VCCSA_J23 J27
AL23 VCCSA_J27 K23
+VCCSFR_OC VCCPLL_OC VCCSA_K23 K25
K20 VCCSA_K25 K27
130mA K21 VCCPLL_K20 VCCSA_K27 K28
+VCCPLL_CPU VCCPLL_K21 VCCSA_K28 K30
VCCSA_K30
AM23 VCCIO_SENSE 1 TC136 @
VCCIO_SENSE AM22 VSSIO_SENSE 1 TC137 @
VSSIO_SENSE
H21 VCCSA_VSS_SEN
VSSSA_SENSE H20 VCCSA_VCC_SEN VCCSA_VSS_SEN 58
VCCSA_SENSE VCCSA_VCC_SEN 58

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

+VCCSA

+VCCSTG +VCCST_CPU
+VDDQ_CPU_CLK
120mA
@ @
RC14971 2 0_0402_5% RC103 1 2 0_0402_5% VCCSA_VCC_SEN RC101 1 2 100_0402_1%
+1.2V +VCCIO
1U_0201_6.3V6-M

1U_0402_6.3V6K
1
10U_0402_6.3V6M

1U_0402_6.3V6K
1 1 RC1604 1 @ 2 0_0402_5%
CC1229

+VCCST_CPU
CC1228

CC86
VCCSA_VSS_SEN RC102 1 2 100_0402_1%
1

CC87
C @ C
2
2 2 Reserved for VCCST/VCCSTG/VCCPLL
power optimized 2

+1.0VALW +VCCST_CPU
+VCCSFR_OC +1.2V 1x22uF, 11x10uF, 4x1uF
@ +VCCPLL_CPU
RC104 1 2 0_0402_5% RC1605 1 @ 2 0_0402_5%
1U_0201_6.3V6-M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
22U_0603_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
CC1366
1 @ 120mA Reserved for VCCST/VCCSTG/VCCPLL power optimized 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1
CC85

RC105 1 2 0_0402_5%

CC1321

CC4232

CC1323

CC4233

CC4234

CC4235
+VCCST_CPU

CC4236

CC4237
CC4231

CC4212

CC4213

CC4214

CC1315

CC1316

CC1317

CC1318

CC1319

CC1320
0.1u_0201_10V6K

1U_0402_6.3V6K
2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CC1249

CC84
2 2

44 EC_VCCIO_EN
RC128 1
@
2 0_0402_5% VCCIO_EN
2 2

https://vinafix.com +VCCIO
@ @
@ @

3.1A 2x10uF, 4x1uF

1
CC77
0.01U_0201_6.3V7-K

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
@ 1 1 1 1 1 1 1 1 1 1
2

CC1301

CC1302

CC1303

CC1304

CC1305

CC1306

CC1368

CC1367

CC4222

CC4227
2 2 2 2 2 2 2 2 2 2
@
B B
@ @ @ @

@
RC142 1 2 0_0402_5% VCCST_EN
44 EC_VCCST_EN

1
CC81
0.01U_0201_6.3V7-K
@
2

+VCCIO
+1.0VALW
10U_0402_6.3V6M
10U_0402_6.3V6M

22U_0402_4V6-M
22U_0402_4V6-M

1 1
1 1
CC1250

C1102
CC71

CC72

@
@
2 2
2 2 UC4
1 14
2 IN1_1 OUT1_2 13
IN1_2 OUT1_1
VCCIO_EN 3 12 CC1293 1 2 1000P_0201_50V7-K
46 VCCIO_EN EN1 CT1
+5VALW
4 11
VBIAS GND
VCCST_EN 5 10 CC1292 1 2 1000P_0201_50V7-K
A EN2 CT2 A
+VCCST_CPU
+1.0VALW
6 9
IN2_1 OUT2_2
10U_0402_6.3V6M

7 8
IN2_2 OUT2_1
1
10U_0402_6.3V6M

15
CC80

Thermal Pad @
1
CC79

G2898KD1U_TDFN14P_2X3 2

2
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CPU PWR2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 13 of 60
5 4 3 2 1
 5 4 3 2 1

+1.0VALW RC1503 1 2 0_0603_5% +VCCAMPHY

@
RC1504 1 2 0_0402_5%
+1.0VALW +VCCAPLL_1P0

+VCCHDA

D D
@
RC1586 1 2 0_0402_5%
+3VALW_PCH

+1.8VALW RC3109 1 HDA18@2 0_0402_5%

RC1620 1 @ 2 0_0402_5% VCCMPHYON_1P0_L1

+1.0VALW

1U_0402_6.3V6K
1

CC144
2

+3VALW_PCH

0.696A
+1.0VALW

1U_0402_6.3V6K
Near AB19
1

1U_0402_6.3V6K

1U_0402_6.3V6K
CC141
1 1

CC156

CC174
22mA 2.574A @ @ +3VALW_PCH
+1.0VALW +1.0VALW ?

1U_0402_6.3V6K
1 1

22U_0603_6.3V6-M
SKL_ULT
2 UC1O

CC158
2 2

CC153
+1.0VALW
1.5A @
CPU POWER 4 OF 4

1U_0402_6.3V6K
+VCCDSW_1P0 2 2 AB19 1

1U_0201_6.3V6-M
VCCPRIM_1P0_AB19
1U_0201_6.3V6-M

CC176
1 AB20 AK15 20mA Near Y15
22U_0402_4V6-M

VCCPRIM_1P0_AB20 VCCPGPPA +3VALW_PCH

CC145
1 1 P18 AG15 4mA @

1U_0402_6.3V6K
VCCPRIM_1P0_P18 VCCPGPPB
CC159

CC147

Near AF18 Y16 6mA 1

VCCPGPPC 2

CC175
@ AF18 Y15 8mA
2 AF19 VCCPRIM_CORE_AF18 VCCPGPPD T16 6mA @
2 2 VCCPRIM_CORE_AF19 VCCPGPPE +1.8VALW
C V20 AF16 161mA C

1U_0402_6.3V6K
VCCPRIM_CORE_V20 VCCPGPPF +1.8VALW 2
V21 AD15 61mA 1
VCCPRIM_CORE_V21 VCCPGPPG

CC142
PCH Internal VRM +3VALW_PCH
AL1 V19

0.1u_0201_10V6K

1U_0402_6.3V6K
DCPDSW_1P0 VCCPRIM_3P3_V19
Near N15 1 1

CC143
2

CC149
K17 T1
VCCMPHYON_1P0_L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1 +1.0VALW
+VCCAMPHY
88mA L1
VCCMPHYAON_1P0_L1
1U_0201_6.3V6-M

AA1 6mA
22U_0402_4V6-M

N15 VCCATS_1P8 2 2
1 1 VCCMPHYGT_1P0_N15
CC151

N16 AK17 1mA

C1096

@ N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3

P15 VCCMPHYGT_1P0_N17 AK19 1mA
2 2 VCCMPHYGT_1P0_P15 VCCRTC_AK19 VCCRTC
Near K15 P16 BB14

0.1u_0201_10V6K

1U_0402_6.3V6K
VCCMPHYGT_1P0_P16 VCCRTC_BB14
1 1

CC146

CC1242
K15 BB10 VCCRTCEXT
L15 VCCAMPHYPLL_1P0_K15 DCPRTC
VCCAMPHYPLL_1P0_L15

0.1u_0201_10V6K
A14 35mA

https://vinafix.com
VCCCLK1 +1.0VALW 2 2
22mA V15 @ 1
+VCCAPLL_1P0 VCCAPLL_1P0 K19 29mA RC1587 1 2 0_0402_5%

CC55
VCCCLK2 +1.0VALW
0.1u_0201_10V6K

1U_0402_6.3V6K

1 1 AB17

1U_0402_6.3V6K

22U_0402_4V6-M
+1.0VALW VCCPRIM_1P0_AB17
CC154

Y18 L21 24mA 1 1

C1097

VCCPRIM_1P0_Y18 VCCCLK3 +1.0VALW 2

CC56

C1098
+VCCHDA
0.118A AD17 N20 33mA @
2 2 +3VALW VCCDSW_3P3_AD17 VCCCLK4 +VCCCLK4
0.1u_0201_10V6K

1 AD18
AJ17 VCCDSW_3P3_AD18 L19 4mA 2 2
CC165

VCCDSW_3P3_AJ17 VCCCLK5 +VCCCLK5

68mA AJ19 A10 10mA
2 VCCHDA VCCCLK6 +1.0VALW

1U_0402_6.3V6K
11mA AJ16 AN11 1
+3VALW_PCH VCCSPI GPP_B0/CORE_VID0 AN13

CC169
0.642A AF20 GPP_B1/CORE_VID1
+1.0VALW VCCSRAM_1P0_AF20
AF21
VCCSRAM_1P0_AF21 2
1U_0402_6.3V6K

1 Near AF20 T19

VCCSRAM_1P0_T19
CC57

T20
VCCSRAM_1P0_T20
CD@ 75mA AJ21 RC1587,RC1588,RC1589 Change to 0402 for placement Bourne 20170630
2 +3VALW_PCH VCCPRIM_3P3_AJ21
1U_0402_6.3V6K

1 AK20
+1.0VALW VCCPRIM_1P0_AK20
CC171

@
33mA N18 RC1588 1 2 0_0402_5%
B +1.0VALW VCCAPLLEBB +VCCCLK4 +1.0VALW B
CD@
2

22U_0603_6.3V6-M
1
1U_0402_6.3V6K

SKYLAKE-U_BGA1356 1 OF 20
1

C1099
REV = 1 @
CC148

?
@
2
2

Near A18 @
RC1589 1 2 0_0402_5%
+VCCCLK5 +1.0VALW

22U_0402_4V6-M
1

C1100
@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCH PWR)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 14 of 60
5 4 3 2 1
 5 4 3 2 1

SKL_ULT
UC1Q ?
SKL_ULT
UC1P ?
D GND 2 OF 3 D
GND 1 OF 3
AT63 BA49
A5 AL65 AT68 VSS_AT63 VSS_BA49 BA53
A67 VSS_A5 VSS_AL65 AL66 AT71 VSS_AT68 VSS_BA53 BA57
A70 VSS_A67 VSS_AL66 AM13 AU10 VSS_AT71 VSS_BA57 BA6
AA2 VSS_A70 VSS_AM13 AM21 AU15 VSS_AU10 VSS_BA6 BA62

Vinafix.com
AA4 VSS_AA2 VSS_AM21 AM25 AU20 VSS_AU15 VSS_BA62 BA66
AA65 VSS_AA4 VSS_AM25 AM27 AU32 VSS_AU20 VSS_BA66 BA71
AA68 VSS_AA65 VSS_AM27 AM43 AU38 VSS_AU32 VSS_BA71 BB18
AB15 VSS_AA68 VSS_AM43 AM45 AV1 VSS_AU38 VSS_BB18 BB26
AB16 VSS_AB15 VSS_AM45 AM46 AV68 VSS_AV1 VSS_BB26 BB30
AB18 VSS_AB16 VSS_AM46 AM55 AV69 VSS_AV68 VSS_BB30 BB34
AB21 VSS_AB18 VSS_AM55 AM60 AV70 VSS_AV69 VSS_BB34 BB38
VSS_AB21 VSS_AM60 VSS_AV70 VSS_BB38 SKL_ULT ?
AB8 AM61 AV71 BB43 UC1R
AD13 VSS_AB8 VSS_AM61 AM68 AW10 VSS_AV71 VSS_BB43 BB55
AD16 VSS_AD13 VSS_AM68 AM71 AW12 VSS_AW10 VSS_BB55 BB6 GND 3 OF 3
AD19 VSS_AD16 VSS_AM71 AM8 AW14 VSS_AW12 VSS_BB6 BB60 F8 L18
AD20 VSS_AD19 VSS_AM8 AN20 AW16 VSS_AW14 VSS_BB60 BB64 G10 VSS_F8 VSS_L18 L2
AD21 VSS_AD20 VSS_AN20 AN23 AW18 VSS_AW16 VSS_BB64 BB67 G22 VSS_G10 VSS_L2 L20
AD62 VSS_AD21 VSS_AN23 AN28 AW21 VSS_AW18 VSS_BB67 BB70 G43 VSS_G22 VSS_L20 L4
AD8 VSS_AD62 VSS_AN28 AN30 AW23 VSS_AW21 VSS_BB70 C1 G45 VSS_G43 VSS_L4 L8
AE64 VSS_AD8 VSS_AN30 AN32 AW26 VSS_AW23 VSS_C1 C25 G48 VSS_G45 VSS_L8 N10
AE65 VSS_AE64 VSS_AN32 AN33 AW28 VSS_AW26 VSS_C25 C5 G5 VSS_G48 VSS_N10 N13
AE66 VSS_AE65 VSS_AN33 AN35 AW30 VSS_AW28 VSS_C5 D10 G52 VSS_G5 VSS_N13 N19
AE67 VSS_AE66 VSS_AN35 AN37 AW32 VSS_AW30 VSS_D10 D11 G55 VSS_G52 VSS_N19 N21
AE68 VSS_AE67 VSS_AN37 AN38 AW34 VSS_AW32 VSS_D11 D14 G58 VSS_G55 VSS_N21 N6
AE69 VSS_AE68 VSS_AN38 AN40 AW36 VSS_AW34 VSS_D14 D18 G6 VSS_G58 VSS_N6 N65
AF1 VSS_AE69 VSS_AN40 AN42 AW38 VSS_AW36 VSS_D18 D22 G60 VSS_G6 VSS_N65 N68
AF10 VSS_AF1 VSS_AN42 AN58 AW41 VSS_AW38 VSS_D22 D25 G63 VSS_G60 VSS_N68 P17
AF15 VSS_AF10 VSS_AN58 AN63 AW43 VSS_AW41 VSS_D25 D26 G66 VSS_G63 VSS_P17 P19
AF17 VSS_AF15 VSS_AN63 AP10 AW45 VSS_AW43 VSS_D26 D30 H15 VSS_G66 VSS_P19 P20
C AF2 VSS_AF17 VSS_AP10 AP18 AW47 VSS_AW45 VSS_D30 D34 H18 VSS_H15 VSS_P20 P21 C
AF4 VSS_AF2 VSS_AP18 AP20 AW49 VSS_AW47 VSS_D34 D39 H71 VSS_H18 VSS_P21 R13
AF63 VSS_AF4 VSS_AP20 AP23 AW51 VSS_AW49 VSS_D39 D44 J11 VSS_H71 VSS_R13 R6
AG16 VSS_AF63 VSS_AP23 AP28 AW53 VSS_AW51 VSS_D44 D45 J13 VSS_J11 VSS_R6 T15
AG17 VSS_AG16 VSS_AP28 AP32 AW55 VSS_AW53 VSS_D45 D47 J25 VSS_J13 VSS_T15 T17
AG18 VSS_AG17 VSS_AP32 AP35 AW57 VSS_AW55 VSS_D47 D48 J28 VSS_J25 VSS_T17 T18
AG19 VSS_AG18 VSS_AP35 AP38 AW6 VSS_AW57 VSS_D48 D53 J32 VSS_J28 VSS_T18 T2
AG20 VSS_AG19 VSS_AP38 AP42 AW60 VSS_AW6 VSS_D53 D58 J35 VSS_J32 VSS_T2 T21
AG21 VSS_AG20 VSS_AP42 AP58 AW62 VSS_AW60 VSS_D58 D6 J38 VSS_J35 VSS_T21 T4
AG71 VSS_AG21 VSS_AP58 AP63 AW64 VSS_AW62 VSS_D6 D62 J42 VSS_J38 VSS_T4 U10
AH13 VSS_AG71 VSS_AP63 AP68 AW66 VSS_AW64 VSS_D62 D66 J8 VSS_J42 VSS_U10 U63
AH6 VSS_AH13 VSS_AP68 AP70 AW8 VSS_AW66 VSS_D66 D69 K16 VSS_J8 VSS_U63 U64
AH63 VSS_AH6 VSS_AP70 AR11 AY66 VSS_AW8 VSS_D69 E11 K18 VSS_K16 VSS_U64 U66
VSS_AH63 VSS_AR11 VSS_AY66 VSS_E11 VSS_K18 VSS_U66

https://vinafix.com
AH64 AR15 B10 E15 K22 U67
AH67 VSS_AH64 VSS_AR15 AR16 B14 VSS_B10 VSS_E15 E18 K61 VSS_K22 VSS_U67 U69
AJ15 VSS_AH67 VSS_AR16 AR20 B18 VSS_B14 VSS_E18 E21 K63 VSS_K61 VSS_U69 U70
AJ18 VSS_AJ15 VSS_AR20 AR23 B22 VSS_B18 VSS_E21 E46 K64 VSS_K63 VSS_U70 V16
AJ20 VSS_AJ18 VSS_AR23 AR28 B30 VSS_B22 VSS_E46 E50 K65 VSS_K64 VSS_V16 V17
AJ4 VSS_AJ20 VSS_AR28 AR35 B34 VSS_B30 VSS_E50 E53 K66 VSS_K65 VSS_V17 V18
AK11 VSS_AJ4 VSS_AR35 AR42 B39 VSS_B34 VSS_E53 E56 K67 VSS_K66 VSS_V18 W13
AK16 VSS_AK11 VSS_AR42 AR43 B44 VSS_B39 VSS_E56 E6 K68 VSS_K67 VSS_W13 W6
AK18 VSS_AK16 VSS_AR43 AR45 B48 VSS_B44 VSS_E6 E65 K70 VSS_K68 VSS_W6 W9
AK21 VSS_AK18 VSS_AR45 AR46 B53 VSS_B48 VSS_E65 E71 K71 VSS_K70 VSS_W9 Y17
AK22 VSS_AK21 VSS_AR46 AR48 B58 VSS_B53 VSS_E71 F1 L11 VSS_K71 VSS_Y17 Y19
AK27 VSS_AK22 VSS_AR48 AR5 B62 VSS_B58 VSS_F1 F13 L16 VSS_L11 VSS_Y19 Y20
AK63 VSS_AK27 VSS_AR5 AR50 B66 VSS_B62 VSS_F13 F2 L17 VSS_L16 VSS_Y20 Y21
AK68 VSS_AK63 VSS_AR50 AR52 B71 VSS_B66 VSS_F2 F22 VSS_L17 VSS_Y21
AK69 VSS_AK68 VSS_AR52 AR53 BA1 VSS_B71 VSS_F22 F23
AK8 VSS_AK69 VSS_AR53 AR55 BA10 VSS_BA1 VSS_F23 F27
AL2 VSS_AK8 VSS_AR55 AR58 BA14 VSS_BA10 VSS_F27 F28
AL28 VSS_AL2 VSS_AR58 AR63 BA18 VSS_BA14 VSS_F28 F32 1 OF 20
SKYLAKE-U_BGA1356
AL32 VSS_AL28 VSS_AR63 AR8 BA2 VSS_BA18 VSS_F32 F33 REV = 1
B VSS_AL32 VSS_AR8 VSS_BA2 VSS_F33 ? B
AL35 AT2 BA23 F35 @
AL38 VSS_AL35 VSS_AT2 AT20 BA28 VSS_BA23 VSS_F35 F37
AL4 VSS_AL38 VSS_AT20 AT23 BA32 VSS_BA28 VSS_F37 F38
AL45 VSS_AL4 VSS_AT23 AT28 BA36 VSS_BA32 VSS_F38 F4
AL48 VSS_AL45 VSS_AT28 AT35 F68 VSS_BA36 VSS_F4 F40
AL52 VSS_AL48 VSS_AT35 AT4 BA45 VSS_F68 VSS_F40 F42
AL55 VSS_AL52 VSS_AT4 AT42 VSS_BA45 VSS_F42 BA41
AL58 VSS_AL55 VSS_AT42 AT56 VSS_BA41
AL64 VSS_AL58 VSS_AT56 AT58
VSS_AL64 VSS_AT58
1 OF 20
SKYLAKE-U_BGA1356
1 OF 20
SKYLAKE-U_BGA1356 REV = 1 ?
REV = 1 ? @
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (VSS)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 15 of 60
5 4 3 2 1
 5 4 3 2 1

?
SKL_ULT
UC1S

RESERVED SIGNALS-1 note: Intel i3-7020U 2.3G/2C(f)/3M is 4 Cores original and ?

changed into 2 cores。i3-7020U 2.3G/2C/3M is 2 cores。 UC1T SKL_ULT

CPU_CFG0 E68 BB68 so (f) is stuff U42@,No(f) is stuff U22. and power use 1 VR,all use U22@
D B67 CFG[0] RSVD_TP_BB68 BB69 SPARE D
PAD @ TC143 1 CPU_CFG2 D65 CFG[1] RSVD_TP_BB69
CFG[2] AW 69 F6
D67 AK13 RSVD_AW 69 RSVD_F6
CPU_CFG4 CFG[3] RSVD_TP_AK13 AW 68 E3 XTAL24_U42_IN
E70 AK12 RSVD_AW 68 RSVD_E3
CFG[4] RSVD_TP_AK12 AU56 C11
C68 RSVD_AU56 RSVD_C11
CFG[5] AW 48 B11
2
D68 BB2 XTAL24_U42_OUT RSVD_AW 48 RSVD_B11
CFG[6] RSVD_BB2 C7 A11

2
RC1618 C67 BA3 RSVD_C7 RSVD_A11
CFG[7] RSVD_BA3 U12 D12
1K_0402_5% RC106 F71 RSVD_U12 RSVD_D12
CFG[8] U11 C12
@ 1K_0402_5% G69 RSVD_U11 RSVD_C12
CFG[9] H11 F52
F70 AU5 RSVD_H11 RSVD_F52
1

G68 CFG[10] TP5 AT5

1 CFG[11] TP6
H70
G71 CFG[12] 1 OF 20
CFG[13] SKYLAKE-U_BGA1356
H69 D5
G70 CFG[14] RSVD_D5 D4 REV = 1 ?
CFG[15] RSVD_D4 @
B2
E63 RSVD_B2 C2
F63 CFG[16] RSVD_C2
CFG[17] B3 RC71 U42_F@
E66 RSVD_B3 A3 2 1
F66 CFG[18] RSVD_A3 1M_0201_5%
CFG[19] AW 1
C CFG_RCOMP E60 RSVD_AW 1 YC2 C
CFG_RCOMP E1 24MHZ_8PF_7R24080003
1 XDP_ITP_PMODE E8 RSVD_E1 E2
PAD @ TC166 ITP_PMODE RSVD_E2 XTAL24_U42_OUT_R 1 3 XTAL24_U42_IN_R
AY2 BA4 1 3
2

AY1 RSVD_AY2 RSVD_BA4 BB4 GND1 GND2

RC162 RSVD_AY1 RSVD_BB4 CC12 U42_F@ CC11
1 1
D1 A4 15P_50V_J_NPO_0201 2 4
15P_50V_J_NPO_0201
49.9_0402_1% RSVD_D1 RSVD_A4
D3 C4 U42_F@ U42_F@
RSVD_D3 RSVD_C4
1

K46
RSVD_K46 TP4
BB5 2 KBL R U42 Use 2 the R,C Change value and Footprint,and YC3 Must be changed:
K45 RC71: SD04310048J, S RES 1/20W 1M +-5% 0201,
RSVD_K45 A69
AL25 RSVD_A69 B69
RSVD_AL25 RSVD_B69 need to check with Intel changed RC71 LCFC PN for BOM
AL27 the R,C Change value and Footprint,and YC2 Must be changed
RSVD_AL27 AY3 RSVD_AY3
RSVD_AY3 need to use 38.4MHz (30ohm) for Cannonlake-u
Changed YC3 CC11 CC12 source for BOM according the owner recommodat
C71 YC3:SJ10000S500&SJ10000TG00 CC11&CC12:SE00001AD00
RSVD_C71

2
B70 D71
RSVD_B70 RSVD_D71 C70 RC107
F60 RSVD_C70
RSVD_F60 0_0201_5%
C54 U42_F@ 1
A52 RSVD_C54 D54 RC241 2 0_0402_5%
@

1
B RSVD_A52 RSVD_D54 B
BA70 AY4 L36
BA68 RSVD_TP_BA70 TP1 BB3
RSVD_TP_BA68 TP2 need to check with Intel XTAL24_U42_IN_R 4 3 XTAL24_U42_IN
@ 4 3
J71 AY71 VSS_AY71 RC1081 2 0_0402_5%
RSVD_J71 VSS_AY71

https://vinafix.com
J68 AR56 XTAL24_U42_OUT_R XTAL24_U42_OUT
RSVD_J68 ZVM# 1 2
1 2
1 F65 AW 71
PAD @ TC169 VSS_F65 RSVD_TP_AW 71 EXC24CH900U_4P
1 G65 AW 70
PAD @ TC170 VSS_G65 RSVD_TP_AW 70 U42_EMC_NS@
F61 AP56 SM070004400
E61 RSVD_F61 MSM# C64 U42_F@ 2
RSVD_E61 PROC_SELECT# RC240 1 0_0402_5%

1 OF 20
SKYLAKE-U_BGA1356 L36 Co-layer w/ RC241,RC240
REV = 1 ?
@

Default
A Pin Name Strap Description Configuration A
Value
Security Classification LC Future Center Secret Data Title
CFG[4] Display Port —1 = eDP Disabled 1 Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CFG,RESERVED)
Presence strap —0 = eDP Enabled * THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 16 of 60
5 4 3 2 1
 5 4 3 2 1

Apply X76 BOM to control DDP Memory Down stuff components! DDRA_DQ[0..63]
DDRA_DQ[0..63] 5,6
DDRA_DQS#[0..7]
DDRA_DQS#[0..7] 5,6
UD2 @
UD1 @ DDRA_DQS[0..7]
DDRA_DQS[0..7] 5,6
DDRA_MA0 P3 G2 DDRA_DQ27
DDRA_MA0 P3 G2 DDRA_DQ6 A0 LDQ0 DDRA_MA[0..13] +0.6VS
A0 LDQ0 DDRA_MA1 P7 F7 DDRA_DQ25 DDRA_MA[0..13] 5
DDRA_MA1 P7 F7 DDRA_DQ3 A1 LDQ1 DDRA_BG1_R R10177 1 2 0_0402_5% DDRA_BG1
A1 LDQ1 DDRA_MA2 R3 H3 DDRA_DQ31 DDRA_BG1 5
DDRA_MA2 R3 H3 DDRA_DQ7 A2 LDQ2 +1.2V
A2 LDQ2 DDRA_MA3 N7 H7 DDRA_DQ24 DDP@

1
DDRA_MA3 N7 H7 DDRA_DQ4 A3 LDQ3
A3 LDQ3 DDRA_MA4 N3 H2 DDRA_DQ30
DDRA_MA4 N3
A4 LDQ4
H2 DDRA_DQ2
Byte 0 DDRA_MA5 P8 A4 LDQ4 H8 DDRA_DQ28 Byte 3 RD1702

1
DDRA_MA5 P8 H8 DDRA_DQ0 A5 LDQ5 0_0402_5%
A5 LDQ5 DDRA_MA6 P2 J3 DDRA_DQ26 2
DDRA_MA6 P2 J3 DDRA_DQ1 A6 LDQ6 R10176 @
A6 LDQ6 DDRA_MA7 R8 J7 DDRA_DQ29
DDRA_MA7 R8 J7 DDRA_DQ5 A7 LDQ7 0_0402_5% CD1702 @
DDRA_MA8 R2 A3 DDRA_DQ19

2
DDRA_MA8 R2 A7 LDQ7 A3 DDRA_DQ11 SDP@
DDRA_MA9 R7 A8 UDQ0 B8 DDRA_DQ20 .01U_0402_16V7-K
DDRA_MA9 R7 A8 UDQ0 B8 DDRA_DQ12 1
DDRA_MA10 M3 A9 UDQ1 C3 DDRA_DQ23

2
A9 UDQ1

1
DDRA_MA10 M3 C3 DDRA_DQ10 A10/AP UDQ2 DDRA_CLK0# RD1704 1 MD@ 2 1/20W_36_1%_0201
A10/AP UDQ2 DDRA_MA11 T2 C7 DDRA_DQ16
D
DDRA_MA11
DDRA_MA12
T2
A11 UDQ3
C7 DDRA_DQ9
DDRA_DQ14 Byte 1 DDRA_MA12 M7 A11 UDQ3 C2 DDRA_DQ18 Byte 2 C23 DDRA_CLK0 RD1705 1 MD@ 2 1/20W_36_1%_0201 D
M7 C2 DDRA_MA13 A12/BC_N UDQ4 DDRA_DQ21 3300P_0402_50V7K
T8 C8

2
DDRA_MA13 T8 A12/BC_N UDQ4 C8 DDRA_DQ8 @
A13 UDQ5 D3 DDRA_DQ22
A13 UDQ5 D3 DDRA_DQ15 +0.6VS
DDRA_MA14_WE# L2 UDQ6 D7 DDRA_DQ17
DDRA_MA14_WE# L2 UDQ6 D7 DDRA_DQ13
5 DDRA_MA14_WE# DDRA_MA15_CAS# M8 WE_N/A14 UDQ7
DDRA_MA15_CAS# M8 WE_N/A14 UDQ7
5 DDRA_MA15_CAS# DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V
DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V
5 DDRA_MA16_RAS# RAS_N/A16 D1 DDRA_CS0# RD1708 1 MD@ 2 1/20W_36_1%_0201
RAS_N/A16 D1 DDRA_CLK0# K8 VDD1 J1 UD1_DDRA_UZQ R10145 1 SDP@ 2 0_0402_5% DDRA_ODT0 RD1709 1 MD@ 2 1/20W_36_1%_0201
DDRA_CLK0# K8 VDD1 J1
5 DDRA_CLK0# DDRA_CLK0 K7 CK_C VDD2 L1
DDRA_CLK0 K7 CK_C VDD2 L1 DDRA_CKE0 RD1710 1 MD@ 2 1/20W_36_1%_0201
5 DDRA_CLK0 CK_T VDD3 R1
CK_T VDD3 R1 RD228 1 DDP@ 2 240_0402_1%
DDRA_CKE0 K2 VDD4 B3
DDRA_CKE0 K2 VDD4 B3
5 DDRA_CKE0 CKE VDD5 G7
CKE VDD5 G7 DDRA_DQS#3 F3 VDD6 B9 UD2_DDRA_UZQ R10147 1 SDP@ 2 0_0402_5%
DDRA_DQS#0 F3 VDD6 B9 DDRA_MA0 RD1711 1 MD@ 2 1/20W_36_1%_0201
DDRA_DQS3 G3 LDQS_C VDD7 J9
DDRA_DQS0 G3 LDQS_C VDD7 J9 DDRA_MA1 RD1714 1 MD@ 2 1/20W_36_1%_0201
DDRA_DQS#2 A7 LDQS_T VDD8 L9
DDRA_DQS#1 A7 LDQS_T VDD8 L9 RD231 1 DDP@ 2 240_0402_1% DDRA_MA2 RD1717 1 MD@ 2 1/20W_36_1%_0201
DDRA_DQS2 B7 UDQS_C VDD9 T9
+1.2V DDRA_DQS1 B7 UDQS_C VDD9 T9 +1.2V DDRA_MA3 RD1718 1 MD@ 2 1/20W_36_1%_0201
UDQS_T VDD10
UDQS_T VDD10
E2 A1 UD3_DDRA_UZQ R10148 1 SDP@ 2 0_0402_5%
RD1712 1 2 0_0402_5% @ DDRA_DM1 E2 A1 RD1713 1 2 0_0402_5% @ DDRA_DM2 NF/UDM_N/UDBI_N VDDQ1 DDRA_MA4 RD1719 1 MD@ 2 1/20W_36_1%_0201
NF/UDM_N/UDBI_N VDDQ1 E7 C1
RD1715 1 2 0_0402_5% @ DDRA_DM0 E7 C1 RD1716 1 2 0_0402_5% @ DDRA_DM3 NF/LDM_N/LDBI_N VDDQ2 DDRA_MA5 RD1720 1 MD@ 2 1/20W_36_1%_0201
NF/LDM_N/LDBI_N VDDQ2 G1 DDRA_MA6
G1 DDRA_BS0# VDDQ3 RD232 1 DDP@ 2 240_0402_1% RD1721 1 MD@ 2 1/20W_36_1%_0201
DDRA_BS0# VDDQ3 N2 F2 DDRA_MA7
N2 F2 DDRA_BS1# BA0 VDDQ4 RD1722 1 MD@ 2 1/20W_36_1%_0201
5 DDRA_BS0# DDRA_BS1# BA0 VDDQ4 N8 J2
N8 J2 BA1 VDDQ5 UD4_DDRA_UZQ
5 DDRA_BS1# BA1 VDDQ5 F8 R10151 1 SDP@ 2 0_0402_5%
F8 DDRA_ACT# VDDQ6
DDRA_ACT# VDDQ6 L3 J8 DDRA_MA8
L3 J8 DDRA_CS0# ACT_N VDDQ7 RD1723 1 MD@ 2 1/20W_36_1%_0201
5 DDRA_ACT# DDRA_CS0# ACT_N VDDQ7 L7 A9 DDRA_MA9
L7 A9 DDRA_ALERT# CS_N VDDQ8 RD233 1 DDP@ 2 240_0402_1% RD1724 1 MD@ 2 1/20W_36_1%_0201
5 DDRA_CS0# DDRA_ALERT# CS_N VDDQ8 P9 D9 DDRA_MA10
P9 D9 ALERT_N VDDQ9 +2.5V_DDR RD1725 1 MD@ 2 1/20W_36_1%_0201
5 DDRA_ALERT# ALERT_N VDDQ9 +2.5V_DDR G9 DDRA_MA11
G9 DDRA_BG0 VDDQ10 RD1726 1 MD@ 2 1/20W_36_1%_0201
DDRA_BG0 VDDQ10 M2
M2 BG0
5 DDRA_BG0 BG0 B1
B1 DDRA_ODT0 VPP1
DDRA_ODT0 VPP1 K3 R9 DDRA_MA12
K3 R9 ODT VPP2 RD1727 1 MD@ 2 1/20W_36_1%_0201

MD@
@
5 DDRA_ODT0 ODT VPP2 DDRA_MA13

MD@

MD@
DDRA_PAR T3 M1 +VREF_CA_MD RD1728 1 MD@ 2 1/20W_36_1%_0201

1U_0402_6.3V6K

1U_0402_6.3V6K
DDRA_PAR T3 M1 +VREF_CA_MD DDRA_MA14_WE# RD1731 1 MD@ 2 1/20W_36_1%_0201

1U_0402_6.3V6K

1U_0402_6.3V6K
5 DDRA_PAR PAR VREFCA
PAR VREFCA 1 1 DDRA_MA15_CAS# RD1732 1 MD@ 2 1/20W_36_1%_0201
1 1 RD1730 1 MD@ 2 10K_0402_5% TEN_UD2 N9 E1
RD1729 1 MD@ 2 10K_0402_5% TEN_UD1 N9 E1 TEN VSS1

.047U_0402_16V7K
TEN VSS1 K1

.047U_0402_16V7K
K1 VSS2 1 1
CPU_DRAMRST# P1 VSS2 N1 MD@1 1 CPU_DRAMRST# P1 N1 MD@ CD1710
CD1706 RESET_N VSS3 T1 2 2 DDRA_MA16_RAS#
6,18 CPU_DRAMRST# RESET_N VSS3 T1 .1U_0402_10V6-K 2 2 .1U_0402_10V6-K RD1733 1 MD@ 2 1/20W_36_1%_0201
F1 VSS4 B2 DDRA_BG0 RD1734 1 MD@ 2 1/20W_36_1%_0201

CD1709

CD1711

CD1712
F1 VSS4 B2 2 @

CD1705

CD1707

CD1708
H1 VSSQ1 VSS5 G8 2 +1.2V DDRA_BG1_R RD1816 1 DDP@ 2 1/20W_36_1%_0201
H1 VSSQ1 VSS5 G8 2 2 @ VSSQ2 VSS6
VSSQ2 VSS6 A2 K9 DDRA_BS0#
A2 K9 VSSQ3 VSS8 RD1735 1 MD@ 2 1/20W_36_1%_0201
VSSQ3 VSS8 D2 DDRA_BS1#
D2 RD1736 1 2 1/20W_36_1%_0201
E3 VSSQ4 T7 1 DDP@ 2 MD@
E3 VSSQ4 T7 1 DDP@ 2 VSSQ5 VSS7 DDRA_ACT#
VSSQ5 VSS7 A8 R10171 0_0402_5% 1 RD1737 1 MD@ 2 1/20W_36_1%_0201
A8 R10170 0_0402_5% VSSQ6

1
VSSQ6 D8 CD1701 DDRA_PAR RD1738 1 MD@ 2 1/20W_36_1%_0201
D8 VSSQ7 DDRA_BG1_R
C VSSQ7 DDRA_BG1_R E8 M9 .1U_0402_10V6-K RD1701 +1.2V C
E8 M9 VSSQ8 BG1
VSSQ8 BG1 C9 1.8K_0402_1%
C9 VSSQ9 UD2_DDRA_UZQ @ 2
VSSQ9 UD1_DDRA_UZQ H9 E9 MD@
H9 E9 VSSQ10 UZQ
VSSQ10 UZQ F9 DDRA_ALERT#
F9 RD1741 1 MD@ 2 49.9_0402_1%

2
LZQ
LZQ

1
1

RD1740 1 RD1703 2 MD@ +VREF_CA_MD

RD1739 5 DDR_SA_VREFCA
MT40A1G16HBA-083E-A_FBGA96 240_0402_1% 2.7_0402_1%
MT40A1G16HBA-083E-A_FBGA96 240_0402_1%
MD@ 1
MD@

1
1

2
CD1704 MD@ The ALERT signal must be routed in the opposite direction to
2

RD1706 CD1703
0.022U_16V_K_X7R_0402 1.8K_0402_1% .1U_0402_10V6-K
2 MD@
the address/command bus.
2 @ For example, the alert signal must first connect to the last

2
1
RD1707 device that the address/command bus is connected to.
24.9_0402_1%
MD@

2
@ +1.2V
UD3 (1uF_0402_6.3V) *16
UD4 @ Place 4 near each DRAM
DDRA_MA0 P3 G2 DDRA_DQ47
DDRA_MA1 P7 A0 LDQ0 F7 DDRA_DQ41 DDRA_MA0 P3 G2 DDRA_DQ63
DDRA_MA2 A1 LDQ1 DDRA_DQ46 DDRA_MA1 A0 LDQ0 DDRA_DQ60

MD_N3T@

MD_N3T@

MD_N3T@
R3 H3 P7 F7

@
MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@
DDRA_MA3 N7 A2 LDQ2 H7 DDRA_DQ45 DDRA_MA2 R3 A1 LDQ1 H3 DDRA_DQ58

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
A3 LDQ3 A2 LDQ2

4.3U_0402_4V6-M

4.3U_0402_4V6-M

4.3U_0402_4V6-M
DDRA_MA4 N3 H2 DDRA_DQ42 DDRA_MA3 N7 H7 DDRA_DQ56 CD1840 CD1841 CD1842
DDRA_MA5 P8 A4 LDQ4 H8 DDRA_DQ40 Byte 5 DDRA_MA4 N3 A3 LDQ3 H2 DDRA_DQ62 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

3
DDRA_MA6 A5 LDQ5 DDRA_DQ43 DDRA_MA5 A4 LDQ4 DDRA_DQ61 Byte 7

MD_3T@

MD_3T@
P2 J3 P8 H8

MD_3T@
DDRA_MA7 R8 A6 LDQ6 J7 DDRA_DQ44 DDRA_MA6 P2 A5 LDQ5 J3 DDRA_DQ59

https://vinafix.com
DDRA_MA8 R2 A7 LDQ7 A3 DDRA_DQ35 DDRA_MA7 R8 A6 LDQ6 J7 DDRA_DQ57

4
A8 UDQ0 A7 LDQ7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DDRA_MA9 R7 B8 DDRA_DQ36 DDRA_MA8 R2 A3 DDRA_DQ50

CD1713

CD1714

CD1715

CD1716

CD1717

CD1718

CD1719

CD1720

CD1721

CD1722

CD1723

CD1724

CD1725

CD1726

CD1727

CD1728
DDRA_MA10 M3 A9 UDQ1 C3 DDRA_DQ39 DDRA_MA9 R7 A8 UDQ0 B8 DDRA_DQ49
DDRA_MA11 T2 A10/AP UDQ2 C7 DDRA_DQ37 DDRA_MA10 M3 A9 UDQ1 C3 DDRA_DQ54
DDRA_MA12 M7 A11 UDQ3 C2 DDRA_DQ34 Byte 4 DDRA_MA11 T2 A10/AP UDQ2 C7 DDRA_DQ48
DDRA_MA13 T8 A12/BC_N UDQ4 C8 DDRA_DQ32 DDRA_MA12 M7 A11 UDQ3 C2 DDRA_DQ51 Byte 6
A13 UDQ5 D3 DDRA_DQ38 DDRA_MA13 T8 A12/BC_N UDQ4 C8 DDRA_DQ53
DDRA_MA14_WE# L2 UDQ6 D7 DDRA_DQ33 A13 UDQ5 D3 DDRA_DQ55
DDRA_MA15_CAS# M8 WE_N/A14 UDQ7 DDRA_MA14_WE# L2 UDQ6 D7 DDRA_DQ52
CAS_N/A15 WE_N/A14 UDQ7 +1.2V (1OuF_0603_6.3V) *5
B DDRA_MA16_RAS# L8 +1.2V DDRA_MA15_CAS# M8 +1.2V B
RAS_N/A16 D1 DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V Place around the DRAMs
DDRA_CLK0# VDD1 RAS_N/A16 (1OuF_0603_6.3V) *3
K8 J1 D1 +2.5V_DDR
DDRA_CLK0 K7 CK_C VDD2 L1 DDRA_CLK0# K8 VDD1 J1
Place around the DRAMs
CK_T VDD3 R1 DDRA_CLK0 K7 CK_C VDD2 L1
DDRA_CKE0 K2 VDD4 B3 CK_T VDD3 R1

MD@

MD@

MD@

MD@

MD@

MD@

MD@

MD@
CKE VDD5 G7 DDRA_CKE0 K2 VDD4 B3

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDRA_DQS#5 F3 VDD6 B9 CKE VDD5 G7
DDRA_DQS5 G3 LDQS_C VDD7 J9 DDRA_DQS#7 F3 VDD6 B9 1 1 1 1 1 1 1 1 1
LDQS_T VDD8 LDQS_C VDD7 1 1
DDRA_DQS#4 A7 L9 DDRA_DQS7 G3 J9 CD1734 CD1735
+1.2V DDRA_DQS4 B7 UDQS_C VDD9 T9 DDRA_DQS#6 A7 LDQS_T VDD8 L9 22P_0402_50V8-J 22P_0402_50V8-J
UDQS_T VDD10 +1.2V DDRA_DQS6 B7 UDQS_C VDD9 T9 @ @
UDQS_T VDD10 2 2 2 2 2 2 2 2 2
RD1742 1 2 0_0402_5% @ DDRA_DM4 E2 A1 2 2

CD1729

CD1730

CD1731

CD1732

CD1733

CD1743

CD1745

CD1746

CD1839
RD1743 1 2 0_0402_5% @ DDRA_DM5 E7 NF/UDM_N/UDBI_N VDDQ1 C1 RD1744 1 2 0_0402_5% @ DDRA_DM6 E2 A1
NF/LDM_N/LDBI_N VDDQ2 G1 RD1745 1 2 0_0402_5% @ DDRA_DM7 E7 NF/UDM_N/UDBI_N VDDQ1 C1
DDRA_BS0# N2 VDDQ3 F2 NF/LDM_N/LDBI_N VDDQ2 G1
DDRA_BS1# N8 BA0 VDDQ4 J2 DDRA_BS0# N2 VDDQ3 F2
BA1 VDDQ5 F8 DDRA_BS1# N8 BA0 VDDQ4 J2
DDRA_ACT# L3 VDDQ6 J8 BA1 VDDQ5 F8
DDRA_CS0# L7 ACT_N VDDQ7 A9 DDRA_ACT# L3 VDDQ6 J8
DDRA_ALERT# CS_N VDDQ8 DDRA_CS0# ACT_N VDDQ7 +0.6VS +2.5V_DDR
P9 D9 L7 A9
ALERT_N VDDQ9 G9 +2.5V_DDR DDRA_ALERT# P9 CS_N VDDQ8 D9
DDRA_BG0 M2 VDDQ10 ALERT_N VDDQ9 G9 +2.5V_DDR
BG0 VDDQ10

4.3U_0402_4V6-M

4.3U_0402_4V6-M
B1 DDRA_BG0 M2 CD1843 CD1844
DDRA_ODT0 K3 VPP1 R9 BG0 B1

3
ODT VPP2 DDRA_ODT0 VPP1
MD@

MD@

K3 R9

MD_3T@

MD_3T@
DDRA_PAR +VREF_CA_MD ODT VPP2

MD@

@
T3 M1
1U_0402_6.3V6K

1U_0402_6.3V6K

PAR VREFCA 1 1
DDRA_PAR T3 M1 +VREF_CA_MD

4
CD1736 CD1737

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 PAR VREFCA
RD1746 1 MD@ 2 10K_0402_5% TEN_UD3 N9 E1 1 1 22P_0402_50V8-J 22P_0402_50V8-J
TEN VSS1
.047U_0402_16V7K

K1 1 1 RD1747 1 MD@ 2 10K_0402_5% TEN_UD4 N9 E1 @ @

VSS2 TEN VSS1 2 2

.047U_0402_16V7K
CPU_DRAMRST# P1 N1 MD@ CD1739 K1
RESET_N VSS3 VSS2 1 1
T1 .1U_0402_10V6-K 2 2 CPU_DRAMRST# P1 N1 MD@ CD1748
F1 VSS4 B2 RESET_N VSS3 T1 .1U_0402_10V6-K 2 2
CD1738

CD1740

CD1741

H1 VSSQ1 VSS5 G8 2 2 @ F1 VSS4 B2

CD1747

CD1742

CD1744
A2 VSSQ2 VSS6 K9 H1 VSSQ1 VSS5 G8 2 2 @
D2 VSSQ3 VSS8 A2 VSSQ2 VSS6 K9
E3 VSSQ4 T7 1 DDP@ 2 D2 VSSQ3 VSS8
A8 VSSQ5 VSS7 R10172 0_0402_5% E3 VSSQ4 T7 1 DDP@ 2 +0.6VS (1uF_0402_6.3V) *8 (1OuF_0603_6.3V) *2 +0.6VS
D8 VSSQ6 A8 VSSQ5 VSS7 R10173 0_0402_5%
E8 VSSQ7 M9 DDRA_BG1_R D8 VSSQ6 Place 2 near each DRAM Place around the DRAMs
C9 VSSQ8 BG1 E8 VSSQ7 M9 DDRA_BG1_R
VSSQ9 UD3_DDRA_UZQ VSSQ8 BG1

MD@
H9 E9 C9

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@
VSSQ10 UZQ F9 H9 VSSQ9 E9 UD4_DDRA_UZQ

10U_0603_6.3V6M

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
LZQ VSSQ10 UZQ F9
LZQ 1 1 1 1 1 1 1 1 1 1 1 1
1

CD1759 CD1760
1

A A
RD1748 22P_0402_50V8-J 22P_0402_50V8-J
MT40A1G16HBA-083E-A_FBGA96 240_0402_1% RD1749 @ @
MD@ 240_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2
MT40A1G16HBA-083E-A_FBGA96

CD1749

CD1750

CD1751

CD1752

CD1753

CD1754

CD1755

CD1756

CD1757

CD1758
MD@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2017/06/24 Deciphered Date 2018/06/23 DDR4 Memory Down

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 17 of 61
5 4 3 2 1
 5 4 3 2 1

+1.2V

DDR4 SO-DIMM DDRB_DQ[0..63]

DDRB_DQ[0..63] 5,6

1
DDRB_DQS#[0..7] RD1801
DDRB_DQS#[0..7] 5,6
+1.2V +1.2V +1.2V +1.2V 240_0402_1%
DDRB_DQS[0..7] JDDR1B
+1.2V +1.2V +1.2V +1.2V @
JDDR1A DDRB_DQS[0..7] 5,6

2
DDRB_MA3 131 132 DDRB_MA2
1 2 6 DDRB_MA3 DDRB_MA1 133 A3 A2 134 DDRB_EVENT# DDRB_MA2 6
DDRB_DQ20 3 VSS_1 VSS_2 4 DDRB_DQ17 6 DDRB_MA1 135 A1 EVENT_n 136
5 DQ5 DQ4 6 DDRB_CLK0 137 VDD_9 VDD_10 138 DDRB_CLK1
DDRB_DQ21 7 VSS_3 VSS_4 8 DDRB_DQ16 6 DDRB_CLK0 DDRB_CLK0# 139 CK0_t CK1_t 140 DDRB_CLK1# DDRB_CLK1 6
9 DQ1 DQ0 10 6 DDRB_CLK0# 141 CK0_c CK1_c 142 DDRB_CLK1# 6
DDRB_DQS#2 11 VSS_5 VSS_6 12 DDRB_PAR 143 VDD_11 VDD_12 144 DDRB_MA0
DDRB_DQS2 13 DQS0_C DM0_n/DBIO_n/NC 14 6 DDRB_PAR Parity A0 DDRB_MA0 6
D 15 DQS0_t VSS_7 16 DDRB_DQ19 D
DDRB_DQ18 17 VSS_8 DQ6 18 DDRB_BS1# 145 146 DDRB_MA10
19 DQ7 VSS_9 20 DDRB_DQ22 6 DDRB_BS1# 147 BA1 A10/AP 148 DDRB_MA10 6
DDRB_DQ23 21 VSS_10 DQ2 22 DDRB_CS0# 149 VDD_13 VDD_14 150 DDRB_BS0#
23 DQ3 VSS_11 24 DDRB_DQ5 6 DDRB_CS0# DDRB_MA14_WE# 151 CS0_n BA0 152 DDRB_MA16_RAS# DDRB_BS0# 6
DDRB_DQ4 25 VSS_12 DQ12 26 6 DDRB_MA14_WE# 153 WE_n/A14 RAS_n/A16 154 DDRB_MA16_RAS# 6
27 DQ13 VSS_13 28 DDRB_DQ1 DDRB_ODT0 155 VDD_15 VDD_16 156 DDRB_MA15_CAS#
DDRB_DQ0 29 VSS_14 DQ8 30 6 DDRB_ODT0 DDRB_CS1# 157 ODT0 CAS_n/A15 158 DDRB_MA13 DDRB_MA15_CAS# 6
31 DQ9 VSS_15 32 DDRB_DQS#0 6 DDRB_CS1# 159 CS1_n A13 160 DDRB_MA13 6
33 VSS_16 DQS1_c 34 DDRB_DQS0 DDRB_ODT1 161 VDD_17 VDD_18 162
35 DM1_n/DBl1_n/NC DQS1_t 36 6 DDRB_ODT1 163 ODT1 C0/CS2_n/NC 164 +VREF_CA_DIMM
DDRB_DQ7 37 VSS_17 VSS_18 38 DDRB_DQ6 165 VDD_19 VREFCA 166 DDRB_SA2

2.2U_0402_6.3V6M
.1U_0402_10V6-K
39 DQ15 DQ14 40 167 C1/CS3_n/NC SA2 168
DDRB_DQ3 41 VSS_19 VSS_20 42 DDRB_DQ2 DDRB_DQ33 169 VSS_53 VSS_54 170 DDRB_DQ32 1 @1

CD1801
43 DQ10 DQ11 44 171 DQ37 DQ36 172
DDRB_DQ8 45 VSS_21 VSS_22 46 DDRB_DQ13 DDRB_DQ37 173 VSS_55 VSS_56 174 DDRB_DQ35
47 DQ21 DQ20 48 175 DQ33 DQ32 176
VSS_23 VSS_24 VSS_57 VSS_58 2 2
DDRB_DQ11 49 50 DDRB_DQ9 DDRB_DQS#4 177 178

CD1802
51 DQ17 DQ16 52 DDRB_DQS4 179 DQS4_c DM4_n/DBl4_n/NC 180
DDRB_DQS#1 53 VSS_25 VSS_26 54 181 DQS4_t VSS_59 182 DDRB_DQ34
DDRB_DQS1 55 DQS2_c DM2_n/DBl2_n/NC 56 DDRB_DQ39 183 VSS_60 DQ39 184
57 DQS2_t VSS_27 58 DDRB_DQ14 185 DQ38 VSS_61 186 DDRB_DQ36
DDRB_DQ10 59 VSS_28 DQ22 60 DDRB_DQ38 187 VSS_62 DQ35 188
61 DQ23 VSS_29 62 DDRB_DQ12 189 DQ34 VSS_63 190 DDRB_DQ41
DDRB_DQ15 63 VSS_30 DQ18 64 DDRB_DQ45 191 VSS_64 DQ45 192
65 DQ19 VSS_31 66 DDRB_DQ24 193 DQ44 VSS_65 194 DDRB_DQ43
DDRB_DQ28 67 VSS_32 DQ28 68 DDRB_DQ44 195 VSS_66 DQ41 196

Vinafix.com
69 DQ29 VSS_33 70 DDRB_DQ25 197 DQ40 VSS_67 198 DDRB_DQS#5
DDRB_DQ29 71 VSS_34 DQ24 72 199 VSS_68 DQS5_c 200 DDRB_DQS5
73 DQ25 VSS_35 74 DDRB_DQS#3 201 DM5_n/DBl5_n/NC DQS5_t 202
+1.2V 75 VSS_36 DQS3_c 76 DDRB_DQS3 DDRB_DQ47 203 VSS_69 VSS_70 204 DDRB_DQ46
77 DM3_n/DBl3_n/NC DQS3_t 78 205 DQ46 DQ47 206
DDRB_DQ26 79 VSS_37 VSS_38 80 DDRB_DQ27 DDRB_DQ40 207 VSS_71 VSS_72 208 DDRB_DQ42
81 DQ30 DQ31 82 209 DQ42 DQ43 210
DDRB_DQ30 83 VSS_39 VSS_40 84 DDRB_DQ31 DDRB_DQ53 211 VSS_73 VSS_74 212 DDRB_DQ48
DQ26 DQ27 DQ52 DQ53
1

85 86 213 214
87 VSS_41 VSS_42 88 DDRB_DQ52 215 VSS_75 VSS_76 216 DDRB_DQ49
RD1802 RD1803 89 CB5/NC CB4/NC 90 217 DQ49 DQ48 218
240_0402_1% 240_0402_1% 91 VSS_43 VSS_44 92 DDRB_DQS#6 219 VSS_77 VSS_78 220
93 CB1/NC CB0/NC 94 DDRB_DQS6 221 DQS6_c DM6_n/DBl6_n/NC 222
2

DDRB_DQS#8 95 VSS_45 VSS_46 96 223 DQS6_t VSS_79 224 DDRB_DQ51

C DDRB_DQS8 97 DQS8_c DM8_n/DBI8_n/NC 98 DDRB_DQ54 225 VSS_80 DQ54 226 C
99 DQS8_t VSS_47 100 227 DQ55 VSS_81 228 DDRB_DQ50
101 VSS_48 CB6/NC 102 DDRB_DQ55 229 VSS_82 DQ50 230
103 CB2/NC VSS_49 104 231 DQ51 VSS_83 232 DDRB_DQ56
105 VSS_50 CB7/NC 106 DDRB_DQ60 233 VSS_84 DQ60 234
107 CB3/NC VSS_51 108 CPU_DRAMRST# 235 DQ61 VSS_85 236 DDRB_DQ57
DDRB_CKE0 109 VSS_52 RESET_n 110 DDRB_CKE1 CPU_DRAMRST# 6,17 DDRB_DQ61 237 VSS_86 DQ57 238

.1U_0402_10V6-K
6 DDRB_CKE0 111 CKE0 CKE1 112 DDRB_CKE1 6 @ 239 DQ56 VSS_87 240 DDRB_DQS#7
VDD_1 VDD_2 1 VSS_88 DQS7_c

CD1803
DDRB_BG1 113 114 DDRB_ACT# 241 242 DDRB_DQS7
6 DDRB_BG1 DDRB_BG0 115 BG1 ACT_n 116 DDRB_ALERT# DDRB_ACT# 6 243 DM7_n/DBl7_n/NC DQS7_t 244
6 DDRB_BG0 117 BG0 ALERT_n 118 DDRB_ALERT# 6 DDRB_DQ59 245 VSS_89 VSS_90 246 DDRB_DQ62
DDRB_MA12 119 VDD_3 VDD_4 120 DDRB_MA11 2 247 DQ62 DQ63 248
6 DDRB_MA12 DDRB_MA9 121 A12 A11 122 DDRB_MA7 DDRB_MA11 6 DDRB_DQ58 249 VSS_91 VSS_92 250 DDRB_DQ63
6 DDRB_MA9 123 A9 A7 124 DDRB_MA7 6 251 DQ58 DQ59 252
DDRB_MA8 125 VDD_5 VDD_6 126 DDRB_MA5 SMB_CLK_S3 253 VSS_93 VSS_94 254 SMB_DATA_S3
6 DDRB_MA8 DDRB_MA6 127 A8 A5 128 DDRB_MA4 DDRB_MA5 6 7,40 SMB_CLK_S3
1 2 +VDD_SPD 255 SCL SDA 256 DDRB_SA0 SMB_DATA_S3 7,40
6 DDRB_MA6 A6 A4 DDRB_MA4 6 +3VS VDDSPD SA0

https://vinafix.com
129 130 257 258

.1U_0402_10V6-K
2.2U_0402_6.3V6M
VDD_7 VDD_8 RD1804 VPP_1 VTT DDRB_SA1 +0.6VS
1 1 259 260
0_5%_0603 VPP_2 SA1

CD1805
@

CD1804
261 262
GND_1 GND_2
ARGOS_D4AR0-26001-1P40 2 2
ME@ ARGOS_D4AR0-26001-1P40
ME@

+1.2V
+2.5V_DDR
1 RD1805 2
0_5%_0603
+VPP
Vinafix.com
@
.1U_0402_10V6-K

1
CD1806

Note:
1

+0.6VS +2.5V_DDR
2 VREF trace width:20 mils at least Layout Note:
RD1806
1K_0402_1% Spacing:20mils to other signal/planes Place near DIMM
Place near DIMM scoket
2

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
B B

@
1 1 @1 1 1 1 1 1
1
RD1807 2 +VREF_CA_DIMM @
5 DDR_SB_VREFCA
2_0402_5% @
.1U_0402_10V6-K

1
2 2 2 2 2 2 2 2
1
1

CD1815

CD1807

CD1808

CD1809

CD1810

CD1811

CD1812

CD1813

CD1814
CD1816
0.022U_16V_K_X7R_0402 RD1808
2 1K_0402_1%
2
1

RD1809 10uF change to 0402 Bourne 20170501

24.9_0402_1%

+1.2V
2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@ @ @ @
CD1817

CD1818

CD1819

CD1820

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CD1821

CD1822

CD1823

CD1824

CD1825

CD1826

CD1827

CD1828

CD1829

CD1830

CD1831

CD1832
Need to confirm SPD address setting
+3VS +3VS +3VS
10uF change to 0402 Bourne 20170501
+1.2V
1

RD1810 RD1811 RD1812

@

0_0402_5% 0_0402_5% 0_0402_5%

@

@ @
@
33P_0402_50V8J

33P_0402_50V8J
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K
2

1 1 1 1 1 1
A DDRB_SA0 DDRB_SA1 DDRB_SA2 A

2 2 2 2 2 2
CD1835

CD1836
CD1833

CD1834

CD1837

CD1838
1

RD1813 RD1814 RD1815

0_0402_5% 0_0402_5% 0_0402_5%
@ @ For EMC
Near JDDRL1
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 DDR4 SO-DIMM

SPD Address = 010 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 18 of 61
5 4 3 2 1
 5 4 3 2 1

N16x GPIO

GPIO I/O ACTIVE Function Description Performance Mode P0 TDP and EDP-Continuous current (GDDR5)
GPIO0 OUT - GPU Core VDD PWM control signal
FBVDDQ Other
Min FBVDD (GPU+Mem) (1.05V)
GPIO1 OUT N/A FB Enable for GC6 2.0 GPU Mem Core Clk NVVDD (1.35V) (1.35V) (6) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W)
D GPIO2 OUT N/A D

N16S-GMR 16 1.6 849 TBD 19 TBD 2 TBD 4.2 TBD 800 TBD 60 TBD
GPIO3 OUT N/A
N16S-GTR 18 1.7 967 26.5 2 4.2 800 60
GPIO4 OUT N/A

GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN

GPIO6 IN - GPU wake signal for GC6 2.0

GPIO7 OUT N/A

GPIO8 I/O - System side PCIe reset Monitor

GPIO9 I/O N/A 2.2K Pull-up

GPIO10 OUT FBVREF_ALTV for GDDR5

GPIO11 OUT - N16x Multi-level Straps

GPIO12 IN AC Power Detect Input (10K pull High)
Physical Logical Logical Logical Logical
GPIO13 OUT - Phase Shedding Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO14 IN N/A
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
C C
GPIO15 IN N/A ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
GPIO16 N/A
STRAP1 +3VGS
GPIO17 IN N/A STRAP2 +3VGS
Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3 +3VGS
GPIO18 IN N/A
STRAP4 +3VGS
GPIO19 IN N/A

https://vinafix.com
GPIO20 N/A

GPIO21 OUT GPU PCIe self-reset control

OVERT OUT Active Low Thermal Catastrophic Over Temperature

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 VGA Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 19 of 61
5 4 3 2 1
 5 4 3 2 1

+3.3V_1.8V_AON +3V_1.8VGS +3.3V_1.8V_AON

2
RV2005 RV2006 RV2007
0_0402_5% @ 10K_0402_5%
@ OPT@ +1.0VGS
0_0402_5%
UV1A ? COMMON INS35853665

1
1/14 PCI_EXPRESS
1
D CV2027 Under Near GPU and PS D
0.1u_0201_10V6K

OPTN17@

OPTN17@

OPTN17@

OPTN17@
@

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6-M
4.7U_0402_6.3V6M

OPTN17@
2

OPT@

OPT@
2

1U_0402_6.3V6K
AA22 PEX_DVDD
PLT_RST_VGA# AC7 PEX_DVDD_1 AB23 1 1 1 1 2 2 1
26 PLT_RST_VGA# PEX_DVDD_2 N16:+1.05VGS(recommend)
OPT@ QV2001 AC24
1 3 CLK_REQ_GPU# AC6 PEX_RST_N PEX_DVDD_3 AD25 +1.0VGS(Used)

CV2011

CV2002

CV2003

CV2012

CV2004
10 GPU_CLKREQ#

CV2001

CV2010
PEX_CLKREQ_N PEX_DVDD_4 AE26 N17:+1.0VGS
PEX_DVDD_5 2 2 2 2 1 1 2
CLK_PCIE_GPU AE8 AE27
10 CLK_PCIE_GPU CLK_PCIE_GPU# PEX_REFCLK PEX_DVDD_6
LSI1012XT1G_SC-89-3 AD8
10 CLK_PCIE_GPU# PEX_REFCLK_N
RV2009 1 @ 2 0_0402_5% PCIE_CRX_GTX_P5 PCIE_CRX_C_GTX_P5 PEX_HVDD +3V_1.8VGS
OPT@ CV2005 1 2 0.22U_0201_6.3V6-K AC9
PCIE_CRX_GTX_N5 OPT@ CV2013 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N5 AB9 PEX_TX0
PEX_TX0_N

2
PCIE_CTX_C_GRX_P5 AG6 2000mA Under GPU Near GPU GPU and PS OPTN17@
RV2008 PCIE_CTX_C_GRX_N5 PEX_RX0 (below 150mils) PEX_HVDD
AG7 AA10 2 1 0_0805_5%
10K_0402_5% PEX_RX0_N PEX_HVDD_1

OPT@

OPT@
AA12

OPTN17@

OPTN17@
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6-M
@ RV2001

CV2018 OPTN17@
PCIE_CRX_GTX_P6 PCIE_CRX_C_GTX_P6 PEX_HVDD_2 +1.0VGS

OPT@

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
OPT@ CV2006 1 2 0.22U_0201_6.3V6-K AB10 AA13

33P_0402_50V8J
OPT@
PCIE_CRX_GTX_N6 OPT@ CV2007 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N6 AC10 PEX_TX1 PEX_HVDD_3 AA16 OPTN16@
1 1 1 1 1 2 2 1 1

OPT_RF@
PEX_TX1_N PEX_HVDD_4 1 1

CV2022
AA18 2 1 0_0805_5%
PCIE_CTX_C_GRX_P6 AF7 PEX_HVDD_5 AA19
PCIE_CTX_C_GRX_N6 AE7 PEX_RX1 PEX_HVDD_6 AA20 RV2002

CV2014

CV2008

CV2015

CV2016

CV2019

CV2020

CV2021
CV2017
PEX_RX1_N PEX_HVDD_7 AA21 2 2 2 2 1 1 2 2
2 2
PCIE_CRX_GTX_P7 OPT@ CV2009 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P7 AD11 PEX_HVDD_8 AB22 PEX_HVDD
PCIE_CRX_GTX_N7 OPT@ CV2023 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N7 AC11 PEX_TX2 PEX_HVDD_9 AC23 N16:+1.05VGS(recommend)
PEX_TX2_N PEX_HVDD_10 AD24 +1.0VGS(Used)
PCIE_CTX_C_GRX_P7 AE9 PEX_HVDD_11 AE25
PEX_RX2 PEX_HVDD_12 N17:+1.8VGS
PCIE_CTX_C_GRX_N7 AF9 AF26
PEX_RX2_N PEX_HVDD_13 AF27 For RF
PCIE_CRX_GTX_P8 OPT@ CV2024 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P8 AC12 PEX_HVDD_14
PCIE_CRX_GTX_N8 OPT@ CV2025 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N8 AB12 PEX_TX3 Change by Bourne 20170412
PEX_TX3_N
PCIE_CTX_C_GRX_P8 AG9
PCIE_CTX_C_GRX_N8 AG10 PEX_RX3
PEX_RX3_N
AB13
AC13 PEX_TX4
PEX_TX4_N
C C
AF10 +3.3V_1.8V_AON
9 PCIE_CRX_GTX_N[5..8] PEX_RX4
AE10
PEX_RX4_N
9 PCIE_CRX_GTX_P[5..8]
AD14 OPTN16@
AC14 PEX_TX5 AA8 PEX_PLL_HVDD RV2003 1 2 0_0402_5%
PEX_PLL_HVDD
9 PCIE_CTX_C_GRX_N[5..8] PEX_TX5_N PEX_PLL_HVDD_1
PEX_PLL_HVDD_2
AA9 +3V_1.8VGS N16:+3.3V_AON
AE12
9 PCIE_CTX_C_GRX_P[5..8] PEX_RX5 N17:+1.8VGS

.1U_0402_10V6-K
AF12 1 OPTN17@
PEX_RX5_N

OPT@
CV2026
RV2004 1 2 0_0402_5%
AC15
AB15 PEX_TX6
PEX_TX6_N 2 Change by Bourne 20170412
AG12
AG13 PEX_RX6
PEX_RX6_N

https://vinafix.com
Under GPU
AB16
AC16 PEX_TX7 (below 150mils)
PEX_TX7_N PEX_DVDD/Q Decouling
AF13
AE13 PEX_RX7
PEX_RX7_N
AD17 MLCC N16 N17 location
AC17 PEX_TX8
PEX_TX8_N
1.0uF 1 1
AE15
AF15 PEX_RX8 Under
PEX_RX8_N 4.7uF 0 1
AC18
PEX_TX9 Near
AB18
PEX_TX9_N
4.7uF 1 2
AG15
AG16 PEX_RX9 10uF 0 2 Midway
PEX_RX9_N

PEX LANES 15 - 4 ARE DEFEATURED

AB19
PEX_TX10
22uF 0 1
AC19
PEX_TX10_N
AF16
B
AE16 PEX_RX10 B
PEX_RX10_N PEX_HVDD/Q Decouling
AD20
AC20 PEX_TX11
PEX_TX11_N
MLCC N16 N17 location
AE18
AF18 PEX_RX11
PEX_RX11_N 1.0uF 1 4 Under
AC21
PEX_TX12 Near
AB21
PEX_TX12_N
4.7uF 1 2
AG18
AG19 PEX_RX12 10uF 1 2 Midway
PEX_RX12_N
AD23
PEX_TX13
22uF 1 1
AE23
PEX_TX13_N
AF19
AE19 PEX_RX13
PEX_RX13_N
AF24
AE24 PEX_TX14
PEX_TX14_N
AE21
AF21 PEX_RX14
PEX_RX14_N PEX_PLL_HVDD/Q Decouling
AG24
AG25 PEX_TX15
PEX_TX15_N
MLCC N16 N17 location
AG21
AG22 PEX_RX15
PEX_RX15_N 0.1uF 1 1 Near
AF25 PEX_TERMP 2.49K_0402_1% 2 OPT@ 1 RV2010
PEX_TERMP

N17S-G1-A1_GB2C-64-595 @
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_PCIE Interface

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 20 of 61
5 4 3 2 1
 5 4 3 2 1

UV1B ? COMMON INS35854731

2/14 FBA
FBA_D0 E18
FBA_D1 F18 FBA_D0
FBA_D2 E16 FBA_D1
27,28 FBA_D[0..63] FBA_D3 FBA_D2
F17
FBA_D4 D20 FBA_D3
27,28 FBA_CMD[31..0] FBA_D5 FBA_D4
D21
FBA_D6 F20 FBA_D5
27,28 FBA_EDC[7..0] FBA_D7 FBA_D6
E21
FBA_D8 E15 FBA_D7
27,28 FBA_DBI[7..0] FBA_D9 D15 FBA_D8
FBA_D10 F15 FBA_D9
D D
FBA_D11 F13 FBA_D10
FBA_D12 C13 FBA_D11
FBA_D13 B13 FBA_D12
FBA_D14 E13 FBA_D13
FBA_D15 D13 FBA_D14
FBA_D16 B15 FBA_D15
FBA_D17 C16 FBA_D16
FBA_D18 A13 FBA_D17
FBA_D19 A15 FBA_D18
FBA_D20 B18 FBA_D19
FBA_D21 A18 FBA_D20
FBA_D22 A19 FBA_D21
FBA_D23 C19 FBA_D22
FBA_D24 B24 FBA_D23 +1.35VGS
FBA_D25 C23 FBA_D24
FBA_D26 A25 FBA_D25
FBA_D27 A24 FBA_D26
FBA_D28 A21 FBA_D27
FBA_D29 B21 FBA_D28

1
FBA_D30 C20 FBA_D29

1
FBA_D31 C21 FBA_D30 RV210
FBA_D32 FBA_D31 10K_0402_1% RV209
R22
FBA_D33 FBA_D32 FBA_CMD0 OPT@ 10K_0402_1%
R24 C27
FBA_D34 T22 FBA_D33 FBA_CMD0 C26 FBA_CMD1 OPT@

2
FBA_D35 R23 FBA_D34 FBA_CMD1 E24 FBA_CMD2

2
FBA_D36 N25 FBA_D35 FBA_CMD2 F24 FBA_CMD3 FBA_CMD14
FBA_D37 N26 FBA_D36 FBA_CMD3 D27 FBA_CMD4
FBA_D38 N23 FBA_D37 FBA_CMD4 D26 FBA_CMD5 FBA_CMD30
FBA_D39 N24 FBA_D38 FBA_CMD5 F25 FBA_CMD6
FBA_D40 V23 FBA_D39 FBA_CMD6 F26 FBA_CMD7
FBA_D41 V22 FBA_D40 FBA_CMD7 F23 FBA_CMD8
FBA_D42 T23 FBA_D41 FBA_CMD8 G22 FBA_CMD9 FBA_CMD13
FBA_D43 U22 FBA_D42 FBA_CMD9 G23 FBA_CMD10
FBA_D44 Y24 FBA_D43 FBA_CMD10 G24 FBA_CMD11 FBA_CMD29
FBA_D45 AA24 FBA_D44 FBA_CMD11 F27 FBA_CMD12
FBA_D46 Y22 FBA_D45 FBA_CMD12 G25 FBA_CMD13
FBA_D47 AA23 FBA_D46 FBA_CMD13 G27 FBA_CMD14

1
C FBA_D48 AD27 FBA_D47 FBA_CMD14 G26 FBA_CMD15 C
FBA_D49 AB25 FBA_D48 FBA_CMD15 M24 FBA_CMD16 RV212 RV211
FBA_D50 AD26 FBA_D49 FBA_CMD16 M23 FBA_CMD17 10K_0402_1% 10K_0402_1%
FBA_D51 AC25 FBA_D50 FBA_CMD17 K24 FBA_CMD18 OPT@ OPT@
FBA_D52 AA27 FBA_D51 FBA_CMD18 K23 FBA_CMD19

2
FBA_D53 AA26 FBA_D52 FBA_CMD19 M27 FBA_CMD20
FBA_D54 W26 FBA_D53 FBA_CMD20 M26 FBA_CMD21
FBA_D55 Y25 FBA_D54 FBA_CMD21 M25 FBA_CMD22
FBA_D56 R26 FBA_D55 FBA_CMD22 K26 FBA_CMD23
FBA_D57 T25 FBA_D56 FBA_CMD23 K22 FBA_CMD24
FBA_D58 N27 FBA_D57 FBA_CMD24 J23 FBA_CMD25
FBA_D59 R27 FBA_D58 FBA_CMD25 J25 FBA_CMD26
FBA_D59 FBA_CMD26 +1.35VGS
FBA_D60 V26 J24 FBA_CMD27
FBA_D61 V27 FBA_D60 FBA_CMD27 K27 FBA_CMD28
FBA_D62 W27 FBA_D61 FBA_CMD28 K25 FBA_CMD29

https://vinafix.com
FBA_D63 W25 FBA_D62 FBA_CMD29 J27 FBA_CMD30
FBA_D63 FBA_CMD30 J26 FBA_CMD31
FBA_CMD31 B19
FBA_DBI0 D19 FBA_CMD32 F22 RV2105 2 @ 1 60.4_0402_1%
FBA_DBI1 D14 FBA_DQM0 FBA_CMD34 J22 RV2106 2 @ 1 60.4_0402_1%
FBA_DBI2 C17 FBA_DQM1 FBA_CMD35
FBA_DBI3 C22 FBA_DQM2
FBA_DBI4 P24 FBA_DQM3
FBA_DBI5 W24 FBA_DQM4
FBA_DBI6 AA25 FBA_DQM5
FBA_DBI7 U25 FBA_DQM6
FBA_DQM7

FBA_EDC0 E19
FBA_EDC1 C15 FBA_DQS_WP0
FBA_EDC2 B16 FBA_DQS_WP1 D24 FBA_CLK0
FBA_EDC3 B22 FBA_DQS_WP2 FBA_CLK0 D25 FBA_CLK0# FBA_CLK0 27
FBA_EDC4 R25 FBA_DQS_WP3 FBA_CLK0_N FBA_CLK1 FBA_CLK0# 27
N22
FBA_EDC5 W23 FBA_DQS_WP4 FBA_CLK1 M22 FBA_CLK1# FBA_CLK1 28
FBA_EDC6 AB26 FBA_DQS_WP5 FBA_CLK1_N FBA_CLK1# 28
FBA_EDC7 T26 FBA_DQS_WP6
FBA_DQS_WP7
B B
F19 D18 FBA_WCLK01
FBA_DQS_RN0 FBA_WCK01 FBA_WCLK01# FBA_WCLK01 27
C14 C18
FBA_DQS_RN1 FBA_WCK01_N FBA_WCLK23 FBA_WCLK01# 27
A16 D17
A22 FBA_DQS_RN2 FBA_WCK23 D16 FBA_WCLK23# FBA_WCLK23 27
FBA_DQS_RN3 FBA_WCK23_N FBA_WCLK45 FBA_WCLK23# 27
P25 T24
W22 FBA_DQS_RN4 FBA_WCK45 U24 FBA_WCLK45# FBA_WCLK45 28
FBA_DQS_RN5 FBA_WCK45_N FBA_WCLK67 FBA_WCLK45# 28 +FB_PLLAVDD PEX_HVDD
AB27 V24
FBA_DQS_RN6 FBA_WCK67 FBA_WCLK67# FBA_WCLK67 28
T27 V25 Place close to BGA
FBA_DQS_RN7 FBA_WCK67_N FBA_WCLK67# 28
200mA
LV2101 PEX_HVDD
Under GPU Near GPU OPT@ N16:+1.05VGS(recommend)
F16 2 1
FB_PLL_AVDD_1 SBK160808T-300Y-N +1.0VGS(Used)
+FB_PLLAVDD

OPT@

22U_0603_6.3V6-M
P22 N17:+1.8VGS
FB_PLL_AVDD_2

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
1
Place close to ball 1 1 1 1

OPT@
CV2101

OPT@ CV2102

OPTN17@ CV2103

OPTN17@ CV2104
H22
FB_REFPLL_AVDD 30ohms (ESR=0.01) 0603 Bead
2

CV2105
2 2 2 2
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

1 1 1
OPT@
CV2106

CV2107

CV2108
OPTN17@

OPTN17@

D23 2 2 2
FB_VREF
FB_PLL/Q Decouling
N17S-G1-A1_GB2C-64-595 @

N17S Add 2x0.1u MLCC N16 N17 location

0.1uF 2 4 Under

22uF 1 1 Near
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_MEM Interface

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 21 of 61
5 4 3 2 1
 5 4 3 2 1

+VGA_CORE
+VGA_CORE
Under GPU 12x4.7uF 5x1uF
+VGA_CORE CV2201 CV2202 CV2203 CV2204 CV2205 CV2206 CV2207 CV2208 CV2209 CV2210 CV2211 CV2212 CV2213 CV2214 CV2215 CV2216 CV2217 CV2218
UV1C ? COMMON INS37185662
UV1G ? COMMON INS35856873

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

33P_0402_50V8J
11/14 NVVDD

OPTN17@
6/14 XVDD
K10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

OPTNS@

OPTN17@

OPTNS@

OPTNS@

OPTN17@
VDD_001

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
K12

OPT@

OPT_RF@
K14 VDD_002
G1 N4 VDD_003
XVDD_1 XVDD_36 K16
G2 N5 VDD_004 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
XVDD_2 XVDD_37 K18
G3 N7 VDD_005
XVDD_3 XVDD_38 L13
G4 P3 VDD_006
XVDD_4 XVDD_39 L15
D G5 P4 VDD_007 D
XVDD_5 XVDD_40 M10
G6 P6 VDD_008
XVDD_6 XVDD_41 M12
G7 R1 VDD_009
XVDD_7 XVDD_42 M16
H3 R2 VDD_010
XVDD_8 XVDD_43 M18
H4 R3 VDD_011
XVDD_9 XVDD_44 N11
H6 R4 VDD_012
XVDD_10 XVDD_45 N13
J1 R5 VDD_013 Near GPU 4x4.7uF 11x10uF 4x22uF
XVDD_11 XVDD_46 N15
J2 R6 VDD_014
XVDD_12 XVDD_47 N17
J3 R7 VDD_015 CV2219CV2220 CV2221 CV2222 CV2223 CV2224 CV2225 CV2226 CV2227 CV2228 CV2229 CV2230 CV2231 CV2232 CV2233 CV2234 CV2235 CV2236 CV2237 CV2238 CV2239 CV2240
XVDD_13 XVDD_48 P14
J4 T1 VDD_016
XVDD_14 XVDD_49 R11
J5 T2 VDD_017

10U_0603_6.3V6M

10U_0603_6.3V6M
XVDD_15 XVDD_50 R13

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

33P_0402_50V8J
J6 T3 VDD_018

OPTN17_NS@

OPTN17_NS@

OPTN17_NS@
XVDD_16 XVDD_51 R15

OPTN17@

OPTN17@

OPTN17_NS@

OPTN17@

OPTN17@

RF_NS@
J7 T4 VDD_019 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2

OPTNS@

OPTNS@

OPTN17@

OPTN17@

OPTN17@

OPTN17@

OPTNS@

OPTN17@

OPTNS@

OPTNS@
XVDD_17 XVDD_52 R17

OPT@

OPT@

OPT@
K1 T5 VDD_020
XVDD_18 XVDD_53 T10
K2 T6 VDD_021
XVDD_19 XVDD_54 T12
K3 T7 VDD_022
XVDD_20 XVDD_55 T16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1
K4 U3 VDD_023
XVDD_21 XVDD_56 T18
K5 U4 VDD_024
XVDD_22 XVDD_57 U13
K6 U6 VDD_025
XVDD_23 XVDD_58 U15
K7 V1 VDD_026
XVDD_24 XVDD_59 +VGA_CORE V10
L3 V2 VDD_027
XVDD_25 XVDD_60 V12 CV88 Use virtual Symbol for diff value
L4 V3 VDD_028
XVDD_26 XVDD_61 V14
M1 V4 VDD_029
XVDD_27 XVDD_62 V16
M2 V5 RV2201 1 @ 2 0_0402_5% VDD_030
XVDD_28 XVDD_63 V18
M3 V6 RV2202 1 2 0_0402_5% VDD_031
M4 XVDD_29 XVDD_64 V7
@ NVVDD/Q Decouling
M5 XVDD_30 XVDD_65 W1
M7 XVDD_31 XVDD_66 W2
N1 XVDD_32 XVDD_67 W3 VDD_SENSE
F2 NVVDD_VCC_SENSE
NVVDD_VSS_SENSE NVVDD_VCC_SENSE 57 MLCC N16 N17 location
XVDD_33 XVDD_68 F1
N2 W4 GND_SENSE NVVDD_VSS_SENSE 57
N3 XVDD_34 XVDD_69
XVDD_35 4.7uF 10 12
trace width: 16mils
differential voltage sensing. Under
differential signal routing. 1.0uF 4 5

N17S-G1-A1_GB2C-64-595
N17S-G1-A1_GB2C-64-595 47uF 1 0

@
C C
@

10uF 0 11
Near
22uF 1 4
4.7uF 5 4
330uF 1 2
+1.35VGS

https://vinafix.com
UV1D ? COMMON INS35857178
12/14 FBVDDQ

B26 +1.35VGS
C25 FBVDDQ_01
E23 FBVDDQ_02 +VGA_CORE
FBVDDQ_03 1x10uF 3x22uF
E26
F14 FBVDDQ_04 Under GPU(below 150mils) 8x10uF 2x10uF Near GPU UV1F ? COMMON INS35856561
F21 FBVDDQ_05 CV2241 CV2242 CV2243 CV2244 CV2245 CV2246 CV2247 CV2248 CV2249 CV2250 CV2251 CV2252 CV2253 CV2254 7/14 VDDS
G13 FBVDDQ_06
FBVDDQ_07

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0603_6.3V6M
G14
FBVDDQ_08
0.1U_0402_25V6

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

OPTN17_NS@
G15 L11

OPTN17@
FBVDDQ_09 1 1 1 2 VDDS_1
OPTN17@

OPTN17@

OPTN17@
G16 1 2 1 1 1 1 1 1 1 1 L17
OPTNS@

OPTN17@

OPTN17@

OPTN17@

OPT@

OPT@
FBVDDQ_10 VDDS_2
OPTNS@

OPT@

G18 M14
OPT@

G19 FBVDDQ_11 P10 VDDS_3

G20 FBVDDQ_12 P12 VDDS_4
FBVDDQ_13 2 2 2 1 VDDS_5
G21 2 1 2 2 2 2 2 2 2 2 P16
L22 FBVDDQ_14 P18 VDDS_6
L24 FBVDDQ_19 T14 VDDS_7
L26 FBVDDQ_20 U11 VDDS_8
M21 FBVDDQ_21 U17 VDDS_9
N21 FBVDDQ_22 VDDS_10
B
R21 FBVDDQ_23 B
FBVDDQ_24 CV32 CV686 Use virtual Symbol for diff value
T21
V21 FBVDDQ_25
W21 FBVDDQ_26
H24 FBVDDQ_27 FBVDD/Q Decouling
H26 FBVDDQ_15
J21 FBVDDQ_16 F4 1 TV2201 @
K21 FBVDDQ_17 MLCC N16 N17 location VDDS_SENSE F3 FB_CLAMP RV2203 1 OPTN16@ 2 10K_0402_5%
FBVDDQ_18 GNDS_SENSE

0.1uF 2 0 N17S-G1-A1_GB2C-64-595

@
1.0uF 2 8
Under
4.7uF 2 0
10uF 0 2
10uF 1 1
Near
22uF 1 3
+1.35VGS

FB_CAL_PD_VDDQ
D22 RV2204 1 OPT@ 2 40.2_0402_1% CALIBRATION PIN GDDR5

FB_CAL_PU_GND
C24 RV2205 1 OPT@ 2 40.2_0402_1% FB_CAL_x_PD_VDDQ 40.2Ohm
A A

FB_CAL_TERM_GND
B25 RV2206 1 OPT@ 2 60.4_0402_1% FB_CAL_x_PU_GND 40.2Ohm
Place near balls
FB_CAL_xTERM_GND 60.4Ohm

Security Classification LC Future Center Secret Data Title

N17S-G1-A1_GB2C-64-595
Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_+VGA_CORE,FBVDDQ
@

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 22 of 61
5 4 3 2 1
 5 4 3 2 1

+3V_1.8VGS
N16 3V3_MAIN(N17 VDD_18) Decouling Discharge
+5VALW +1.35VGS
Under GPU Near GPU MLCC N16 N17 location
@
UV1E ? COMMON INS35858730 +VDD18 RV2301 1 2 0_0402_5%

1
14/14 VDD18
0.1uF 2 2

OPT@

OPT@
Under RV2303

1U_0402_6.3V6K

4.7U_0402_6.3V6M
RV2302

.1U_0402_10V6-K

.1U_0402_10V6-K
G8 1 1 1 1 Change by Bourne 20170412
VDD18_1 47K_0402_5% 470_0603_5%

OPT@

OPT@
CV2301

CV2302
G9
VDD18_2 G10 1.0uF 1 1 OPTNS@ OPTNS@
1V8_AON_1 G12

3 2
1V8_AON_2 2 2 2 2 Near

CV2303

CV2304
D
4.7uF 1 1 FBVDDQ_PWR_EN# 5 QV2301B
G
LBSS138DW1T1G_SOT363-6

6
D
S

4
D FBVDDQ_PWR_EN 2 OPTNS@ D
+3.3V_1.8V_AON QV2301A
G
S LBSS138DW1T1G_SOT363-6

1
N16 3V3_AON(N17 1V8_AON) Decouling OPTNS@
Under GPU Near GPU
VDD_AON RV2304 1 @ 2 0_0402_5%
MLCC N16 N17 location

OPT@

OPT@
1U_0402_6.3V6K

4.7U_0402_6.3V6M
.1U_0402_10V6-K

.1U_0402_10V6-K
N17S-G1-A1_GB2C-64-595 1 1 1 1 0.1uF 1 2 Under +5VALW +3.3V_1.8V_AON

OPT@
@

CV2305

CV2306
OPTN17@

1
2 2 2 2 1.0uF 1 1 RV2306

CV2307

CV2308
Near RV2305
47K_0402_5%
470_0603_5%
4.7uF 1 1 OPTNS@ OPTNS@

3 2
D
PXS_PWREN# 5 QV2302B
G
2N7002KDWH_SOT363-6

6
D
PXS_PWREN 2 QV2302A S OPTNS@
PXE_VDD & 1V8_AON

4
G +3V_1.8VGS
2N7002KDWH_SOT363-6
S OPTNS@

1
PXS_PWREN RV2307 1 @ 2 0_0402_5% PXS_PWR_EN_R 1
8 PXS_PWREN PXS_PWR_EN_R 56
RV2308 CV2309
470_0603_5% 10U_0603_6.3V6M
1 OPTNS@
2
GC6@
RV2309

2
100K_0402_5%
@

1
D
2

2 OPTNS@
G
C QV2303 C

+3VS S L2N7002KWT1G_SOT323-3
DV2301 @ +3.3V_1.8V_AON

3
DGPU_PWROK 1 2
2
2

1 2
RV2310 RV2311
RB521CM-30T2R_VMN2M-2
10K_0402_5% 10K_0402_5%
@ OPT@ RV2316 建虚拟料号,N16=470 ohm,N17=5.11 ohm
1
1

DV2302 +5VALW +1.0VGS

PXS_PWREN 2 RV2313
1 PXE_VDD_EN 2 1 PXE_VDD_EN_R RV109 change to 470ohm 0805 for N16 GPU
1.8VGS_PWR_EN 1 2 0_0402_5%
3 PXE_VDD_EN_R 55
RV27 @
30K_0402_5%

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1

OPT@ 2
LBAT54AWT1G_SOT323-3
RV2314

1
OPT@

1
10K_0402_5% D5102 OPT@ CV2310 RV2316
@ 0.22U_6.3V_K_X5R_0402 RV2317 RV2315 470_0805_5%
1 47K_0402_5% 5.11_0805_1%
1 2 OPT@
2

OPT@ OPTN17@ @

2
1 2

2
RB521CM-30T2R_VMN2M-2

+1.8VG_AON TO +1.8VGS

1
D
+1.0VGS_PWR_EN# 2 QV2304
G AO3402_SOT-23-3
OPTN17@

S
+3VS
+3VALW +3VS

3
1
D
1

PXE_VDD_EN_R 2 QV2305

1
RV2318 +1.0VGS G LBSS139WT1G_SC70-3
B B
82K_0402_1% RV2319 RV2320 OPT@ S

1
@ 10K_0402_5% 10K_0402_5% @ D
@ @ 2 QV2306
1

DV2303
2

PXS_PWREN G LBSS139WT1G_SC70-3
RV2321 1 @ 2 0_0402_5% 2 RV2322
2

2
PEX_PWROK OPTN16@ S
1 NVVDD_EN 1K_0402_5%

3
1.8VGS_PWR_EN NVVDD_EN 57
RV2323 1 @ 2 0_0402_5% 3 @

1
26,56 1.8VGS_PWR_EN D
1

C 2 QV2307
2

RV2325 1 @ 2 0_0402_5% LBAT54AWT1G_SOT323-3

1

.1U_0402_10V6-K
+3V_1.8VGS 2 QV2308 1 G LBSS139WT1G_SC70-3
@
CV2311
RV2324 B S@
.1U_0402_10V6-K

RV2326 1 @ 2 0_0402_5% @

3
100K_0402_1% 1 E
@
CV2312

@
2
2

2 MMBT3904WH_SOT323-3

+5VALW +VGA_CORE

1
Vinafix.com RV2328
47K_0402_5%
OPTNS@
RV2327
10_0603_5%
OPTNS@

3 2
D
NVVDD_EN# 5 QV2309B
DV2304
FB_GC6_EN_R RV2329 1 GC6_EN G LBSS138DW1T1G_SOT363-6
@ 2 0_0402_5% 2

6
8,26 FB_GC6_EN_R D OPTNS@
1 FBVDDQ_PWR_EN S

4
FBVDDQ_PWR_EN 56 NVVDD_EN 2 QV2309A
3
GC6@ G
LBSS138DW1T1G_SOT363-6
S
DGPU_PWROK RV2330 1 OPT@ BAV70W-7-F_SOT323-3

1
2 10K_0402_5% OPTNS@
8,57 DGPU_PWROK

PEX_PWROK @ NGC6@
RV2332 1 2 0_0402_5% RV2333 1 2 0_0402_5%
1

A A
.1U_0402_10V6-K

1 RV2331
OPT@
CV2313

200K_0402_5%
GC6@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_AON/MAIN PWR/SEQUENCE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 23 of 61
5 4 3 2 1
 5 4 3 2 1

UV1H ? COMMON INS35859464

13/14 GND

D D
A2 K11
AB17 GND_001 GND_057 K13
AB20 GND_005 GND_058 K15
AB24 GND_006 GND_059 K17
AC2 GND_007 GND_060 L10
AC22 GND_008 GND_061 L12
AC26 GND_009 GND_062 L14
AC5 GND_010 GND_063 L16
AC8 GND_011 GND_064 L18
AD12 GND_012 GND_065 L5
AD13 GND_013 GND_069 M11
A26 GND_014 GND_070 M13
AD15 GND_002 GND_071 M15
AD16 GND_015 GND_072 M17
AD18 GND_016 GND_073 N10
AD19 GND_017 GND_074 N12
AD21 GND_018 GND_075 N14
AD22 GND_019 GND_076 N16
AE11 GND_020 GND_077 N18
AE14 GND_021 GND_078 P11
AE17 GND_022 GND_079 P13
AE20 GND_023 GND_080 P15
AB11 GND_024 GND_081 P17
AF1 GND_003 GND_082 P23
AF11 GND_025 GND_084 P26
AF14 GND_026 GND_085 R10
AF17 GND_027 GND_087 R12
AF20 GND_028 GND_088 R14
AF23 GND_029 GND_089 R16
AF5 GND_030 GND_090 R18
AF8 GND_031 GND_091 T11
AG2 GND_032 GND_092 T13
AG26 GND_033 GND_093 T15
AB14 GND_034 GND_094 T17
B1 GND_004 GND_095 U10
B11 GND_035 GND_096 U12
B14 GND_036 GND_097 U14
B17 GND_037 GND_098 U16
C C
B20 GND_038 GND_099 U18
B23 GND_039 GND_100 U23
B27 GND_040 GND_102 U26
B5 GND_041 GND_103 V11
B8 GND_042 GND_105 V13
E11 GND_043 GND_106 V15
E14 GND_044 GND_107 V17
E17 GND_045 GND_108 Y2
E2 GND_046 GND_109 Y23
E20 GND_047 GND_110 Y26
E22 GND_048 GND_111 Y5
E25 GND_049 GND_112 AA7
E5 GND_050 GND_F AB7
E8 GND_051 GND_H
GND_052

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H2
GND_053 GND_083
P2
H5 P5
L2 GND_056 GND_086 U2
GND_066 GND_101 U5
GND_104

H23 L23
H25 GND_054 GND_067 L25
GND_055 GND_068

N17S-G1-A1_GB2C-64-595
@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 24 of 61
5 4 3 2 1
 5 4 3 2 1

UV1J ? COMMON INS35860124

PEX_PLLVDD/Q Decouling 4/14 IFPAB

DVI HDMI DP
MLCC N16 N17 location SL/DL

AC4
IFPA_L3_N AC3
1.0uF 1 NA Under TXC/TXC
IFPA_L3
AA6
IFPAB_RSET
1uF 1 NA TXD0/0
IFPA_L2_N
Y3
Near Y4
IFPA_L2
+1.0VGS 4.7uF 1 NA
TXD1/1 AA2
W7 IFPA_L1_N AA3
UV1I ? COMMON INS35860218 IFPAB_PLLVDD IFPA_L1
D 5/14 NC D

TXD2/2 AA1
Under GPU Near GPU IFPA_L0_N AB1
RV2501 2 OPTN16@1 0_0402_5% +PEX_PLLVDD +PEX_PLLVDD AA14 IFPA_L0
AA15 NC_1

1U_0402_6.3V6K

4.7U_0402_6.3V6M
CV2502 OPTN16@

OPTN16@
AB6 NC_2
PEX_SVDD_3V3 NC_3 AA5
AB8 IFPA_AUX_SDA_N

.1U_0402_10V6-K
1 1 NC_4 AA4
CV2501 1 AD10 IFPA_AUX_SCL
OPTN16@

AD7 NC_5
PEX_PLLVDD 1 @ 2 PEX_TSTCLK_OUT AE22 NC_6
N16:+1.0VGS(recommend) 2 2 NC_7 AB4
RV2502 200_0402_1% AE3

CV2503
2 IFPB_L3_N AB5
N17:NC AE4 NC_8 TXC
IFPB_L3
+3.3V_1.8V_AON AF2 NC_9
PEX_TSTCLK_OUT# AF22 NC_10
NC_11 W6 TXD0/3 AB2
AF3 IFP_IOVDD_1 IFPB_L2_N
NC_12 AB3

1
+3.3V_1.8V_AON Differential signal AF4 IFPB_L2
NC_13 Y6
RV2504 AG3 IFP_IOVDD_2
10K_0402_5% D10 NC_14
NC_15 TXD1/4 AD2
@ E10 IFPB_L1_N
NC_16 AD3
F10 IFPB_L1

2
F5 NC_17
MULTI_STRAP_REF0_GND F6 NC_18
OPTN16@ NC_19 TXD2/5 AD1
RV2503 2 1 0_0402_5% PEX_SVDD_3V3 W5 IFPB_L0_N
NC_20 AE1
IFPB_L0
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

1
OPTN16@

OPTN16@

1 1 RV2505
AD5
40.2K_0402_1% IFPB_AUX_SDA_N AD4
OPTN16@ IFPB_AUX_SCL
PEX_SVDD_3V3 N17S-G1-A1_GB2C-64-595
CV2504

CV2505

2
N16:+3.3V_AON(recommend) 2 2

@
N17:NC
Change by Bourne 20170412
IFPAB (DEFEATURED 0N GM108)

Change by Bourne 20170412 Near GPU N17S-G1-A1_GB2C-64-595

@
C
PEX_SVDD/Q Decouling C
UV1K ? COMMON INS35860067
MLCC N16 N17 location 10/14 MISC2

4.7uF 2 NA Near
D12 1
ROM_CS_N TV2501 @
B12 ROM_SI
ROM_SI ROM_SO ROM_SI 29
A12
D1 ROM_SO C12 ROM_SCLK ROM_SO 29
STRAP0
29 STRAP0 STRAP0 ROM_SCLK ROM_SCLK 29
STRAP1 D2
29 STRAP1 STRAP1
STRAP2 E4
29 STRAP2 E3 STRAP2
STRAP3
29 STRAP3 STRAP3
STRAP4 D3

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29 STRAP4 C1 STRAP4
STRAP5
29 STRAP5 STRAP5

D11 RV2506 2 @ 1 10K_0402_5%

BUFRST_N

XS_PLLVDD/Q Decouling
MLCC N16 N17 location
PEX_HVDD
N16:+1.05VGS(recommend) 0.1uF 1 1 Under
+1.0VGS(Used)
N17:+1.8VGS 22uF 1 0 Near
N17S-G1-A1_GB2C-64-595
PEX_HVDD

@
LV2501 Under GPU +3.3V_1.8V_AON
1 2 OPT@ LV2502 1 @ 2 0_0402_5% XS_PLLVDD
UV1L ? COMMON INS35860348
B SBK160808T-300Y-N B
CV2507 @

9/14 XTAL_PLL
.1U_0402_10V6-K

30ohms (ESR=0.05) Bead SP_PLLVDD & VID_PLLVDD/Q Decouling

.1U_0402_10V6-K

2
1
OPT@

XS_PLLVDD
CV2506

L6
SP_PLLVDD M6 XS_PLLVDD RV2507
MLCC N16 N17 location
OPT@

OPT@

GPCPLL_AVDD SP_PLLVDD 10K_0402_5% @

22U_0603_6.3V6-M
4.7U_0402_6.3V6M

2 F11
1 1 2 VID_PLLVDD N6 GPCPLL_AVDD
VID_PLLVDD

1
0.1uF 2 2 Under 150mA
2 2
CV2508

CV2509

10uF 1 0
Near
Under GPU(below 150mils) 10K_0402_5% 2 OPT@ 1 RV2508 XTALSSIN A10 C10 XTALOUT
47uF 1 0 XTAL_SSIN XTAL_OUTBUFF
LV2503 1 @ 2 0_0402_5% SP_PLLVDD
XTAL_IN C11 B10 XTAL_OUT
XTAL_IN XTAL_OUT
.1U_0402_10V6-K

.1U_0402_10V6-K

1 1 N17S-G1-A1_GB2C-64-595
OPT@

OPT@
CV2510

CV2511

OPTN17@

@
RV25101 2 0_0402_5% VID_PLLVDD

1
OPT@
2 2 RV2509
RV2511 1 OPT@ 2 10M_0402_5% XTAL_OUT 10K_0402_5%

2
2
R4712
51_0402_1%
YV1
OPT@
OPTN17@

1
Change by Bourne 20170412 XTAL_IN 1 4
1
LV2504 2 0_0402_5% GPCPLL_AVDD OSC1 GND2
2 3 XTAL_OUT_R
GND1 OSC2
.1U_0402_10V6-K

OPT@

12P_0402_50V8-J

12P_0402_50V8-J
1

OPT@
GPCPLL_AVDD/Q Decouling 1 1
CV2514
OPTN17@

27MHZ_10PF_7V27000050
OPT@
2
CV2512

CV2513
A MLCC N16 N17 location 2 2 A

0.1uF NA 1 Under

4.7uF NA 1
Near
22uF NA 1
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_STRAP/DP/HDMI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 25 of 61
5 4 3 2 1
 5 4 3 2 1

+3.3V_1.8V_AON +3.3V_1.8V_AON
UV1M ? COMMON INS35861009
8/14 MISC1 GPU Address 0x9E

2
2
RV2602
RV2601
2.2K_0402_5% QV2601A

2
2.2K_0402_5% OPT@
OPT@
D9 VGA_SMB_CK2

G1
I2CS_SCL D8 VGA_SMB_DA2 OPT@ PJT7838_SOT363-6

1
1
OVERT# A6 I2CS_SDA VGA_SMB_CK2 1 6
AE2 OVERT A9 I2CC_SCL S1 D1 EC_SMB_CK2 7,39,44
TS_VREF I2CC_SCL B9 I2CC_SDA
I2CC_SDA Internal Thermal Sensor
2 @ 1 0_0402_5%
D E12 D

.1U_0402_10V6-K
1 THERMDN C9 I2CB_SCL RV2603

@
F12 I2CB_SCL C8 I2CB_SDA

5
THERMDP I2CB_SDA QV2601B OPT@

CV2601

G2
2 PJT7838_SOT363-6
VGA_SMB_DA2 4 3
S2 D2 EC_SMB_DA2 7,39,44

C6 NVVDD_PWM_VID
GPIO0 FB_GC6_EN NVVDD_PWM_VID 57 RV2604 2 @ 1 0_0402_5%
B2 PU AT EC SIDE, +3VS AND 4.7K
GPIO1 D6 GPU_EVENT#_R
GPIO2 C7 NVVDDS_PWM 1
GPIO3 1.8VGS_PWR_EN_R TV2601
PLT_RST_VGA# @ F9
RV174 1 2 56_0402_5% GPIO4 A3
1 GPIO5 A4 PSI_VGA
CV218 GPIO6 B6 PSI_VGA 57
220P_0201_25V7-K GPIO7 MEM_VDD_CTL
E9
@ GPIO8 VGA_ALERT#
F8
2

2 GPIO9 C5 GPIO10_FBVREF_ALTV +3.3V_1.8V_AON +3VALW +3VS

GPIO10 GPIO10_FBVREF_ALTV 27
E7
GPIO11 D7 VGA_AC_DET_R 2 1
VGA_AC_DET 44

2
OVERT# 3 1 GPIO12 DV2601 OPT@ RV2609
WRST# 44 B4
GPIO13 RB751V-40_SOD323-2 10K_0402_5%
B3
GPIO14 GC6N17@

2
1 C3 RV2610
CV221 GPIO15 SYS_PEX_RST_MON#_GPU
QV24 D5 RV2606 1 2 0_0402_5% SYS_PEX_RST_MON# RV2613 10K_0402_5%
0.01U_0201_10V6K GPIO16 D4 FB_GC6_EN_R
OPTN16@ 10K_0402_5% GC6N17@

1
@ LSI1012XT1G_SC-89-3 GPIO17 FB_GC6_EN_R 8,23
2 C2 @
@ GPIO18 F7

1
GPIO19 E6

3
GPIO20 GPU_PEX_RST_HOLD#_GPU GPU_PEX_RST_HOLD# GC6N17@ QV2602B
C4 RV2607 1 2 0_0402_5%
GPIO21 VGA_CRT_DATA

D2
A7 OPTN16@
GPIO22 VGA_CRT_CLK 5 PJT7838_SOT363-6
B7 G2
GPIO23

S2
6
N17S-G1-A1_GB2C-64-595
QV2602A

4
@

D1
FB_GC6_EN 2 PJT7838_SOT363-6
C G1 C
@

S1
MEM_VDD_CTL RV1397 1 2 0_0402_5% SYS_PEX_RST_MON#

2
RV2614 GC6N17@

1
10K_0402_5%
GC6@

1
UV1N ? COMMON INS35861249
3/14 JTAG +3.3V_1.8V_AON GC6N16@
RV2615 1 2 0_0402_5%
2.2K_0404_4P2R_5%
1 AE5 VGA_CRT_DATA 2 3
TV2602 JTAG_TCK VGA_CRT_CLK
1 AE6 1 4
TV2603 1 AF6 JTAG_TDI @
TV2604 JTAG_TDO RPV4
1 AD6

https://vinafix.com
2 TV2605 JTAG_TMS 2.2K_0404_4P2R_5%
10K_0402_5% OPT@ 1 RV2611 AG4
10K_0402_5% 2 OPT@ 1 RV2612 TESTMODE AD9 JTAG_TRST_N I2CB_SCL 2 3
NVJTAG_SEL I2CB_SDA 1 4 +3.3V_1.8V_AON +3.3V_1.8V_AON
@ RPV3

.1U_0402_10V6-K
2.2K_0404_4P2R_5%

2
1

@
I2CC_SCL

CV2604
2 3
I2CC_SDA 1 4 RV2616
10K_0402_5%
@
RPV2 GC6@ 2

2
MEM_VDD_CTL RV224 1 @ 2 10K_0402_5%
+3.3V_1.8V_AON

N17S-G1-A1_GB2C-64-595 GPU_EVENT#_R 3 1 GPU_EVENT#

GPU_EVENT# 8
@

1.8VGS_PWR_EN_R RV18 2 OPT@ 1 1K_0402_1%

GC6@
QV2604
OVERT# RV20 1 OPT@ 2 10K_0402_5% LSI1012XT1G_SC-89-3

VGA_ALERT# RV2619 1 @ 2 0_0402_5%

RV23 1 OPT@ 2 10K_0402_5%
B B
VGA_AC_DET_R RV26 1 OPT@ 2 100K_0402_5%

PSI_VGA RV29 1 @ 2 10K_0402_5%

GPU_PEX_RST_HOLD# RV31 1 OPT@ 2 10K_0402_5% +3VS

+3VS

2
RV2921
10K_0402_5%
OPT@

2
RV2922
+3VS 10K_0402_5%
+3.3V_1.8V_AON OPT@ 1.8VGS_PWR_EN

1
1.8VGS_PWR_EN 23,56
+3.3V_1.8V_AON
2

RV2617

1
2

3
0_0402_5%
RV2618 RV2622 QV2704B

D2
@ 5
10K_0402_5% 10K_0402_5% PJT7838_SOT363-6
1

OPTN16@ OPT@ G2
OPT@

S2
1

1
+1.8VGARST

6
.1U_0402_10V6-K

4
OPT@
CV2605

QV2704A

D1
1.8VGS_PWR_EN_R 2 PJT7838_SOT363-6
G1
2 OPT@

S1
DV2602
5

UV2602 GPU_PEX_RST_HOLD# 2

1
PLT_RST#_B 1 1
P

11,37,40,44 PLT_RST#_B B SYS_PEX_RST_MON# PLT_RST_VGA# 20

4 3
2 Y
8 PXS_RST# A
G

LBAT54AWT1G_SOT323-3
MC74VHC1G09DFT2G_SC70-5 OPTN16@
3

OPT@ OPTNS@
1

RV2631 1 2 0_0402_5%
1

1.8VGS_PWR_EN_R RV2923 1 2 0_0402_5% 1.8VGS_PWR_EN

RV2620
RV2621 OPTN17@
A 100K_0402_5% 100K_0402_5% A
OPT@ OPT@
2
2

RC1557 has PD

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GPIO/JTAG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 26 of 61
5 4 3 2 1
 5 4 3 2 1

Lower 32 bits
MF=0 No Mirror
21,28 FBA_D[0..63]
+1.35VGS
21,28 FBA_CMD[31..0]
UM5
21,28 FBA_EDC[7..0]
MF=0 MF=1 MF=1 MF=0 Close to VRAM
21,28 FBA_DBI[7..0]
A4 FBA_D0 CV741 CV743 CV742 CV623 CV621 CV622 CV625
FBA_EDC0 C2 DQ24 DQ0 A2 FBA_D1

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
FBA_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D2
D D
FBA_EDC2 EDC1 EDC2 DQ26 DQ2 FBA_D3 1 1 1 1 1 1 1

OPT_NS@
R13 B2 BYTE0

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
EDC2 EDC1 DQ27 DQ3

OPT@
FBA_EDC3 R2 E4 FBA_D4
EDC3 EDC0 DQ28 DQ4 E2 FBA_D5
DQ29 DQ5 F4 FBA_D6
DQ30 DQ6 2 2 2 2 2 2 2
FBA_DBI0 D2 F2 FBA_D7
FBA_DBI1 D13 DBI0# DBI3# DQ31 DQ7 A11 FBA_D8
FBA_DBI2 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D9
OPT@ FBA_DBI3 P2 DBI2# DBI1# DQ17 DQ9 B11 FBA_D10
FBA_CLK0 RV193 1 2 40.2_0402_1% DBI3# DBI0# DQ18 DQ10
21 FBA_CLK0 B13 FBA_D11
FBA_CLK0 DQ19 DQ11 FBA_D12
BYTE1
FBA_CLK0# J12 E11
RV194 1 OPT@ 2 40.2_0402_1% FBA_CLK0# J11 CK DQ20 DQ12 E13 FBA_D13
21 FBA_CLK0#
FBA_CMD14 J3 CK# DQ21 DQ13 F11 FBA_D14 CV744 CV745 CV746 CV627 CV628 CV630 CV629
1 CKE# DQ22 DQ14 F13 FBA_D15

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CV228 DQ23 DQ15 FBA_D16

1U_0402_6.3V6K
U11
0.01U_0201_10V6K FBA_CMD2 DQ8 DQ16 FBA_D17 1 1 1 1 1 1 1
H11 U13

OPT_NS@

OPT@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
OPT@ FBA_CMD4 BA0/A2 BA2/A4 DQ9 DQ17 FBA_D18

OPT_NS@
2 K10 T11
FBA_CMD3 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBA_D19
FBA_CMD1 BA2/A4 BA0/A2 DQ11 DQ19 FBA_D20
BYTE2
H10 N11 2 2 2 2 2 2 2
BA3/A3 BA1/A5 DQ12 DQ20 N13 FBA_D21
DQ13 DQ21 M11 FBA_D22
FBA_CMD6 K4 DQ14 DQ22 M13 FBA_D23
FBA_CMD11 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBA_D24
FBA_CMD10 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBA_D25
FBA_CMD7 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA_D26
FBA_CMD9 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA_D27
A12/RFU/NC DQ3 DQ27 N4 FBA_D28 Around VRAM
DQ4 DQ28 FBA_D29
BYTE3
A5 N2
U5 VPP/NC1 DQ5 DQ29 M4 FBA_D30
VPP/NC2 DQ6 DQ30 M2 FBA_D31 CV747 CV748 CV750 CV749 CV751 CV752 CV753
DQ7 DQ31
+1.35VGS

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
RV182 1 OPT@ 2 1K_1%_0201 J1
RV183 1 OPT@ 2 1K_1%_0201 FBA_SEN0 J10 MF 1 1
SEN 1 1 1 1 1

OPT@

OPT@

OPT@

OPT@

OPT@
RV185 1 2 121_0402_1% OPT@ J13 B1
ZQ VDDQ1

OPT_NS@

OPT_NS@
D1
VDDQ2 F1
VDDQ3 2 2
FBA_CMD8 J4 M1 2 2 2 2 2
FBA_CMD12 G3 ABI# VDDQ4 P1
C FBA_CMD0 G12 RAS# CAS# VDDQ5 T1 C
FBA_CMD15 L3 CS# WE# VDDQ6 G2
FBA_CMD5 L12 CAS# RAS# VDDQ7 L2
WE# CS# VDDQ8 B3
VDDQ9 D3
VDDQ10 F3
FBA_WCLK01# D5 VDDQ11 H3
21 FBA_WCLK01# FBA_WCLK01 WCK01# WCK23# VDDQ12
D4 K3
21 FBA_WCLK01 WCK01 WCK23 VDDQ13 M3
FBA_WCLK23# P5 VDDQ14 P3
21 FBA_WCLK23# FBA_WCLK23 WCK23# WCK01# VDDQ15
P4 T3
21 FBA_WCLK23 WCK23 WCK01 VDDQ16 E5
VDDQ17 N5
A10 VDDQ18 E10
FBA_VREFC VREFD1 VDDQ19
U10 N10

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+1.35VGS FBA_VREFC J14 VREFD2 VDDQ20 B12
VREFC VDDQ21 D12
CV224 1 VDDQ22 F12
820P_0402_25V7 VDDQ23 H12
VDDQ24
1

FBA_CMD13 J2 K12 +1.35VGS

RV192 OPT@ 2 RESET# VDDQ25 M12
549_0402_1% VDDQ26 P12
OPT@ VDDQ27 T12
VDDQ28 G13
1 2

FBA_VREFC H1 VDDQ29 L13 CV2606 CV2607 CV2608 CV2609

K1 VSS1 VDDQ30 B14

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
B5 VSS2 VDDQ31 D14 CV2622

4.3U_0402_4V6-M
RV191 VSS3 VDDQ32 1 1 1 1

OPT_N3T@

OPT_N3T@

OPT_N3T@

OPT_N3T@
G5 F14

3
1.33K_0402_1% VSS4 VDDQ33

OPT_3T@
L5 M14
OPT@ VSS5 VDDQ34
T5 P14
2

B10 VSS6 VDDQ35 T14

4
VSS7 VDDQ36 2 2 2 2
D10
G10 VSS8
L10 VSS9 A1
P10 VSS10 VSSQ1 C1
T10 VSS11 VSSQ2 E1
H14 VSS12 VSSQ3 N1
K14 VSS13 VSSQ4 R1
B B
VSS14 VSSQ5 U1
VSSQ6 H2
+1.35VGS G1 VSSQ7 K2
L1 VDD1 VSSQ8 A3
VDD2 VSSQ9 +1.35VGS
G4 C3
FBA_VREFC L4 VDD3 VSSQ10 E3
RV190 C5 VDD4 VSSQ11 N3
R5 VDD5 VSSQ12 R3
931_0402_1% C10 VDD6 VSSQ13 U3
2 1 VDD7 VSSQ14 CV2610 CV2611 CV2612 CV2613
R10 C4
VDD8 VSSQ15

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
D11 R4 CV2623

4.3U_0402_4V6-M
OPT@ G11 VDD9 VSSQ16 F5 1 1 1 1

OPT_N3T@

OPT_N3T@

OPT_N3T@

OPT_N3T@
VDD10 VSSQ17

3
OPT_3T@
L11 M5
P11 VDD11 VSSQ18 F10
1

D QV26
G14 VDD12 VSSQ19 M10
2

4
26 GPIO10_FBVREF_ALTV LBSS139WT1G_SC70-3 L14 VDD13 VSSQ20 C11 2 2 2 2
G VDD14 VSSQ21 R11
OPT@
1

S VSSQ22 A12
3

RV208 VSSQ23 C12

100K_0402_5% VSSQ24 E12
OPT@ VSSQ25 N12
VSSQ26 R12
2

170-BALL VSSQ27 U12

VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13
VSSQ30 A14
VSSQ31 C14
VSSQ32 E14
VSSQ33 N14
VSSQ34 R14
VSSQ35 U14
VSSQ36
@ H5GQ1H24AFR-T2L_BGA170

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GDDR5_Rank0_[31:0]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
teknisi
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 27 of 61
5 4 3 2 1
 5 4 3 2 1

upper 32 bits

21,27 FBA_D[0..63] MF=0 No Mirror

21,27 FBA_CMD[31..0]
UM14
21,27 FBA_EDC[7..0]
MF=0 MF=1 MF=1 MF=0
D 21,27 FBA_DBI[7..0] D
A4 FBA_D32
FBA_EDC4 C2 DQ24 DQ0 A2 FBA_D33
FBA_EDC5 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D34
FBA_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D35
FBA_EDC7 EDC2 EDC1 DQ27 DQ3 FBA_D36
BYTE4
R2 E4
EDC3 EDC0 DQ28 DQ4 E2 FBA_D37
DQ29 DQ5 F4 FBA_D38
FBA_DBI4 D2 DQ30 DQ6 F2 FBA_D39
FBA_DBI5 D13 DBI0# DBI3# DQ31 DQ7 A11 FBA_D40
FBA_DBI6 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D41
FBA_DBI7 P2 DBI2# DBI1# DQ17 DQ9 B11 FBA_D42
DBI3# DBI0# DQ18 DQ10 B13 FBA_D43
FBA_CLK1 DQ19 DQ11 FBA_D44
BYTE5 +1.35VGS
J12 E11
FBA_CLK1# J11 CK DQ20 DQ12 E13 FBA_D45 Close to VRAM
FBA_CMD30 J3 CK# DQ21 DQ13 F11 FBA_D46
FBA_CLK1 OPT@ CKE# DQ22 DQ14 FBA_D47
RV195 1 2 40.2_0402_1% F13 CV654 CV729 CV650 CV651 CV653 CV652 CV730
21 FBA_CLK1 DQ23 DQ15 FBA_D48
U11
FBA_CLK1# RV196 1 OPT@ 2 40.2_0402_1% FBA_CMD18 H11 DQ8 DQ16 U13 FBA_D49

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
21 FBA_CLK1# FBA_CMD20 BA0/A2 BA2/A4 DQ9 DQ17 FBA_D50

10U_0603_6.3V6M
K10 T11
1 BA1/A5 BA3/A3 DQ10 DQ18 1 1 1 1 1 1 1

OPT_NS@

OPT_NS@
FBA_CMD19 K11 T13 FBA_D51

OPT@

OPT@

OPT_NS@

OPT_NS@

OPT_NS@
CV649 FBA_CMD17 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBA_D52
0.01U_0201_10V6K BA3/A3 BA1/A5 DQ12 DQ20 FBA_D53
BYTE6
N13
OPT@ DQ13 DQ21 M11 FBA_D54
2 DQ14 DQ22 2 2 2 2 2 2 2
FBA_CMD22 K4 M13 FBA_D55
FBA_CMD27 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBA_D56
FBA_CMD26 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBA_D57
FBA_CMD23 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA_D58
FBA_CMD25 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA_D59
A12/RFU/NC DQ3 DQ27 N4 FBA_D60
DQ4 DQ28 FBA_D61
BYTE7
A5 N2 CV731 CV732 CV733 CV638 CV639 CV641 CV640
U5 VPP/NC1 DQ5 DQ29 M4 FBA_D62
VPP/NC2 DQ6 DQ30

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
M2 FBA_D63
DQ7 DQ31
1 1 1 1 1 1 1

OPT_NS@
+1.35VGS

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
RV197 1 OPT@ 2 1K_1%_0201 J1

OPT@
RV198 1 OPT@ 2 1K_1%_0201 FBA_SEN1 J10 MF
RV201 1 2 121_0402_1% OPT@ J13 SEN B1
ZQ VDDQ1 D1 2 2 2 2 2 2 2
C VDDQ2 F1 C
FBA_CMD24 J4 VDDQ3 M1
FBA_CMD28 G3 ABI# VDDQ4 P1
FBA_CMD16 G12 RAS# CAS# VDDQ5 T1
FBA_CMD31 L3 CS# WE# VDDQ6 G2
FBA_CMD21 L12 CAS# RAS# VDDQ7 L2
WE# CS# VDDQ8 B3
VDDQ9 D3 Around VRAM
VDDQ10 F3
FBA_WCLK45# D5 VDDQ11 H3 CV734 CV735 CV736 CV737 CV738 CV739 CV740
21 FBA_WCLK45# FBA_WCLK45 WCK01# WCK23# VDDQ12
D4 K3
21 FBA_WCLK45 WCK01 WCK23 VDDQ13

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
M3
FBA_WCLK67# P5 VDDQ14 P3 1 1 1 1 1 1 1

OPT@

OPT@

OPT@

OPT@
21 FBA_WCLK67# FBA_WCLK67 P4 WCK23# WCK01# VDDQ15 T3

OPT_NS@

OPT_NS@

OPT_NS@
21 FBA_WCLK67 WCK23 WCK01 VDDQ16 E5

https://vinafix.com
VDDQ17 N5
FBA_VREFC VDDQ18 2 2 2 2 2 2 2
A10 E10
U10 VREFD1 VDDQ19 N10
FBA_VREFC J14 VREFD2 VDDQ20 B12
VREFC VDDQ21 D12
1 VDDQ22
CV665 F12
820P_0402_25V7 VDDQ23 H12
FBA_CMD29 J2 VDDQ24 K12
OPT@ 2 RESET# VDDQ25 M12
VDDQ26 P12
VDDQ27 T12
VDDQ28 G13
H1 VDDQ29 L13
K1 VSS1 VDDQ30 B14
B5 VSS2 VDDQ31 D14
G5 VSS3 VDDQ32 F14
L5 VSS4 VDDQ33 M14
VSS5 VDDQ34 +1.35VGS
T5 P14
B10 VSS6 VDDQ35 T14
D10 VSS7 VDDQ36
G10 VSS8
L10 VSS9 A1
VSS10 VSSQ1 CV2618 CV2619 CV2620 CV2621
B P10 C1 CV2625 B
VSS11 VSSQ2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
T10 E1

4.3U_0402_4V6-M
H14 VSS12 VSSQ3 N1 1 1 1 1

OPT_N3T@

OPT_N3T@

OPT_NS@

OPT_N3T@

OPT_3T@
VSS13 VSSQ4

3
K14 R1
VSS14 VSSQ5 U1
VSSQ6 H2

4
+1.35VGS G1 VSSQ7 K2 2 2 2 2
L1 VDD1 VSSQ8 A3
G4 VDD2 VSSQ9 C3
L4 VDD3 VSSQ10 E3
C5 VDD4 VSSQ11 N3
R5 VDD5 VSSQ12 R3
C10 VDD6 VSSQ13 U3
R10 VDD7 VSSQ14 C4
D11 VDD8 VSSQ15 R4
G11 VDD9 VSSQ16 F5
L11 VDD10 VSSQ17 M5
P11 VDD11 VSSQ18 F10 +1.35VGS
G14 VDD12 VSSQ19 M10
L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 R11
VSSQ22 A12
VSSQ23 C12 CV2614 CV2615 CV2616 CV2617 CV2624
VSSQ24 E12

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VSSQ25 N12

4.3U_0402_4V6-M
OPT_NS@
VSSQ26 1 1 1 1

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
R12

3
170-BALL VSSQ27 U12
VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13

4
VSSQ30 2 2 2 2
A14
VSSQ31 C14
VSSQ32 E14
VSSQ33 N14
VSSQ34 R14
VSSQ35 U14
VSSQ36
@
H5GQ1H24AFR-T2L_BGA170
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_GDDR5_Rank0_[64:32]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 28 of 61
5 4 3 2 1
 5 4 3 2 1

+3.3V_1.8V_AON
X76
GPU FB Memory (GDDR5) RAMCFG[4:0] STRAP2 STRAP1 STRAP0

2
RV2901 RV2902 RV2903 Samsung 8Gb K4G80325FB-HC28 0(0x0000) L L L
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
8Gb Micron 8Gb MT51J256M32HF-70:A 1(0x0001) L L H

1
D D

25 STRAP0 STRAP0
25 STRAP1 STRAP1 Hynix 8Gb H5GC8H24MJR-R0C 2(0x0010) L H L
25 STRAP2 STRAP2

2
RV2904 RV2905 RV2906
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
1

1
+3.3V_1.8V_AON
STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE

L L L 0 0 0 0
2

2
RV2907 RV2908 RV2909
100K_0402_5% 100K_0402_5% 100K_0402_5% 1: SMB_ALT_ADDR ENABLE
@ @ @
C 0: SMB_ALT_ADDR DISABLE C
1

1: DEVID_SEL REBRAND
25 STRAP3 STRAP3
25 STRAP4 STRAP4 0: DEVID_SEL ORIGNAL
25 STRAP5 STRAP5

1: PCIE_CFG LOW POWER

2

0: PCIE_CFG HIGH POWER

RV2910 RV2911 RV2912
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @ 1: VGA_DEVICE ENABLE
1

0: VGA_DEVICE DISABLE

Strap5 is NC pin on N16 https://vinafix.com

DEVID_SEL
0 (Default)
B B
1

+3V_1.8VGS +3.3V_1.8V_AON PCIE_CFG

ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0] 1:ENABLE 0:DISABLE 0 (Default)
2
2

RV2914
RV2913
0_0402_5%
0_0402_5% 0000 SOR0/1/2/3 DISABLE 1
OPTN17@ N17S-G1 H H M
OPTN16@
1
1

N16S-GTR SMBUS_ALT_ADDR
2

RV2915 RV2916 RV2917 0 0x9E (Default)

100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
1 0x9C (Multi-GPU usage)
1

25 ROM_SI
ROM_SI
ROM_SO
VGA_DEVICE
25 ROM_SO ROM_SCLK
25 ROM_SCLK 0 3D Device (Class Code 302h)
2

RV2918 RV2919 RV2920 1 VGA Device (Default)

100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 GPU_MISC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 29 of 61
5 4 3 2 1
 5 4 3 2 1

RA3025 1 2 1K_0402_5% CA423 1 2 0.1U_6.3V_K_X5R_0402

DA3002

44 EC_BEEP 3

1 RA3023 1 2 1K_0402_5% CA3017 1 2 0.1U_6.3V_K_X5R_0402 BEEP

D D
2
8 PCH_BEEP

10K_0402_5%
2
BAT54CW_SOT323-3

RA3024
@

1
RA3026 1 2 0_0402_5%
@

Vinafix.com

C C

+5VS
+3VS J1
1
2 1
BEEP 3 2
4 3
5 4
+3VL 5
36 NOVO_BTN# 6
7 6
44 EC_MUTE# 7
8
9 8
9 USB20_N5 10 9
9 USB20_P5 10
11

https://vinafix.com
12 11
33 DMIC_CLK 12
33 DMIC_DATA 13
DVDD_IO 14 13
+3VALW
CPU HDA BUS power 15 14
8 HDA_BITCLK_AUDIO 15
16
1 2 0_5%_0603 8 HDA_SDOUT_AUDIO 17 16
RA27 @
8 HDA_SDIN0 17
18
8 HDA_SYNC_AUDIO 18
19
DVDD_IO DVDD_IO 19
+1.8VALW 20
+1.8VS 20
21
RA726 22 GND1
1mA GND2
1 2
2

1/2W_0.01_+-1%_0603_50PPM/C RA3027 HIGHS_FC5AF201-1151H

HDA18@ @ 0_0402_5% ME@
1

Change Symbol to SP01001IF00 amy 0706

B B

HDA_BITCLK_AUDIO 20Pin CONN

1
CA3018
33P_0402_50V8J
EMC_NS@ 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 IO board

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 30 of 61
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Title
<Title>

Size Document Number Rev

A GS44B/GS54B 0.1

Date: Wednesday, May 29, 2019 Sheet 31 of 61

5 4 3 2 1
 5 4 3 2 1

+3VALW +3V_TPM

R2101
1 2
0.01_0603_1%
TPM@

C2101

C2103

C2104
1 2 1 1

0.1U_6.3V_K_X5R_0201

C2102
10U_0603_6.3V6M

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
@ +3V_TPM

TPM@ TPM@ @
2 1 2 2
D D

+3VALW

2
R2102
@ 10K_0402_5% R2103 R2104
TPM@ 10K_0402_5% @ 10K_0402_5%

22
U2101

1
1

VDD3

VDD2

NCI/VDD1
1

1
TPM@
R2110 2 1 0_0402_5% TPM_IRQ# 18
9 TPM_SPI_IRQ# PIRQ# 3
NCI1 4 R10178 1 @ 2 0_0402_5%
R2105 1 TPM@ 2 33_0402_5% TPM_MOSI 21 NCI2 5
7 SPI_SI_R TPM_MISOI MOSI NCI3
R2106 1 TPM@ 2 33_0402_5% 24 10
7 SPI_SO_R MISO NCI4 11
NCI5 12
NCI6 13
R2107 2 TPM@ 1 0_0402_5% TPM_CS2# 20 NCI7 14
7 SPI_CS2#_R CS# VDD/NCI8 15
R2108 1 TPM@ 2 33_0402_5% TPM_CLK 19 NCI9 16
7 SPI_CLK_R SCLK GND/NCI10 25
17 NCI11 26
11,32 PLT_RST# RST# NCI12 27
6 NCI13 28
GPIO NCI14 31
TPM_PP 7 NCI15
PP

29 R2111 1 @ 2 0_0402_5%
NC1 PLT_RST# 11,32

1
30
NC2

GND1

GND2

GND3

GND4

GND5
R2112
0_0402_5%
C @ C
SLB9670VQ2.0FW7.61_VQFN32_5X5

23

32

33
2

9
TPM@

https://vinafix.com
TABLE

Pin TCG Infineon ST Micro Nuvoton NATIONZ

No
PTP Spec (v38) SLB9670VQ2.0 FW 7.61 ST33HTPH2E32AHB4 NPCT750LABYX Z32H330TC

1 VDD NC/VDD NC VSB VDD

2 GND GND GND NC GND
B
3 GPIO NC NC NC NC B
4 GPIO NC NC PP/GPIO6 NC
5 NC NC NC NC NC
6 VNC/GPIO GPIO GPIO GPIO3 NC
7 GPIO/VDD PP PP NC PP
8 VDD VDD NC VHIO VDD

9 GND GND NC NC GND

10 VNC NC NC NC NC
11 NC NC NC NC NC
12 NC NC NC NC NC
13 VNC/GPIO NC NC GPIO4 NC
14 VDD NC/VDD NC NC VDD
15 NC NC NC NC NC
16 GND NC/GND NC GND GND

17 SPI_RST# RST# SPI_RST# PLTRST# SPI_RST#

18 SPI_PIRQ# PIRQ# SPI_PIRQ# PIRQ#/GPIO2 SPI_PIRQ#
19 SPI_CLK SCLK SPI_CLK SCLK SPI_CLK
20 SPI_CS# CS# SPI_CS# SCS#/GPIO5 SPI_CS#
21 MOSI MOSI MOSI MOSI/GPIO7 MOSI
22 VDD VDD VPS VHIO VDD
23 GND GND NC GND GND
24 MISO MISO MISO MISO MISO

A A
25 NC NC NC NC NC
26 NC NC NC NC NC
27 NC NC NC NC NC
28 NC NC NC NC NC
29 VNC/GPIO NC NC SDA/GPIO0 NC
30 VNC/GPIO NC NC SCL/GPIO1 NC
31 VNC NC NC NC NC
32 GND GND NC NC GND Security Classification LC Future Center Secret Data Title
TPM
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 32 of 61
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT CMOS Camera

+3VS +LCDVDD_CON +3VS_EDP
+LCDVDD +3VS
F3806 W=40mils

0.047U_0402_16V7K
U3301 1 2
D R120 W=60mils D
5 1 1 2 1

.1U_0402_10V6-K
IN OUT C3304 2

10U_0603_6.3V6M
0_5%_0603 1 1A_32V_ERBRD1R00X @
1 2

C3303

C3305
GND @

33P_0402_50V8J
.1U_0402_10V6-K
C3306

4.7U_0603_6.3V6K
@
.1U_0402_10V6-K PCH_ENVDD 4 3 2
EN OCB 1 1 1 1

@
@ 2
2

C3307

C3308

C3309
SY6288C20AAC_SOT23-5
2 2 2 EMI request

U3301 EN PIN VIH MIN 1.35V

For RF +LEDVDD CPU_EDP_TX0+ C3319 1 2 0.1U_0402_25V6 EDP_TX0+
PCH_ENVDD V20B+ 4 CPU_EDP_TX0+
4 PCH_ENVDD
F3301 CPU_EDP_TX0- C3320 1 2 0.1U_0402_25V6 EDP_TX0-
4 CPU_EDP_TX0-
1

1 2
R1
100K_0402_5% @ 3A_32V_ERBRD3R00X CPU_EDP_TX1+ C3321 1 2 0.1U_0402_25V6 EDP_TX1+
4 CPU_EDP_TX1+

0.1U_0402_25V7-K
+3VS

4.7U_0805_25V6-K
CPU_EDP_TX1- C3322 1 2 0.1U_0402_25V6 EDP_TX1-
2

4 CPU_EDP_TX1-

1
1

C3312
C3311
2
R3312 CPU_EDP_AUX# C3355 1 2 0.1U_0402_25V6 EDP_AUX#

2
PCH_ENBKL 2 4 CPU_EDP_AUX#
1 @ 2 0_0402_5% 4.7K_0402_5% @
4,44 PCH_ENBKL CPU_EDP_AUX EDP_AUX
R3311 @ C3356 1 2 0.1U_0402_25V6
4 CPU_EDP_AUX

1
@
BKOFF# R3313 1 2 0_0402_5% DISPOFF#
44 BKOFF#
EMI Request
C +3VS JEDP1 C

+LEDVDD 1
2 1
2
2

3
R3314 4 3
1K_0402_5% 5 4
5
@ Camera R3308 1
@
2 0_0402_5%
EDP_TX0+
EDP_TX0-
6
7 6
@
1

R3316 1 2 0_0402_5% INVT_PWM 8 7

4 PCH_EDP_PWM EDP_TX1+ 8
9
9
1

L3301 @ EDP_TX1- 10
USB20_N7 1 2 USB20_N7_R 11 10
R3317 9 USB20_N7 1 2 EDP_AUX 11
12
100K_0402_5% EDP_AUX# 12

https://vinafix.com
13
USB20_P7 4 3 USB20_P7_R 14 13
9 USB20_P7
2

4 3 DISPOFF# 15 14
EXC24CH900U_4P INVT_PWM 16 15
CPU_EDP_HPD 17 16
4 CPU_EDP_HPD 17
+LCDVDD_CON 18
@ 18
R3309 1 2 0_0402_5% 19
20 19
21 20
DMIC_CLK 22 21
30 DMIC_CLK DMIC_DATA 22
23
30 DMIC_DATA 23
+3VS_EDP 24
25 24
26 25
27 26
EMI request USB20_P7_R 28 27
USB20_N7_R 29 28 ME@
30 29
DISPOFF# INVT_PWM 30
DMIC_DATA DMIC_CLK 31
32 G1
G2
B 1 1 DRAPH_FC5AF301-3181H B
1 1
@ C10192 @ C3323 @ @ W/O Touch panel
C3324 C3325
100P_0402_50V8J 100P_0402_50V8J 470P_0402_50V7K 470P_0402_50V7K
2 2
2 2

+3VS

Touch Screen R101791 TS@ 2 0_0402_5%

R24 1 TS@ 2 0_0402_5% +5VS +3VS_TS

USB20_P6_CONN
EMC_NS@ USB20_N6_CONN R26 1 TS1@ 2 0_0402_5%
EXC24CH900U_4P JTS1
1
2

USB20_P6 4 3 USB20_P6_CONN +3VS_TS C25 1

9 USB20_P6 4 3 1
AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2

0.1u_0201_10V6K R28 2 TS@ 1 0_0402_5% TS_RS 2

EMC_NS@

D5104

EMC_NS@

D5105
2

44 EC_TS_ON 2
TS@ 3
3
1

USB20_N6 1 2 USB20_N6_CONN D2 2 USB20_N6_CONN 4

9 USB20_N6 1 2 USB20_P6_CONN 4
5
1

L15 6 5
6
1

7
GND1 8
1

GND2
A A
2

R23 1 TS@ 2 0_0402_5% HIGHS_WS83061-S0171-HF

AZ5725-01F.R7GR_DFN1006P2X2 ME@
2

EMC_NS@
change symbol to SP021412291 by amy 0620
For ESD
For EMI
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 eDP/CAMERA.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 33 of 61
5 4 3 2 1
 5 4 3 2 1

+3VS

+3VS

2
G
CPU_HDMI_TXP2 C3401 1 2 .1U_0402_10V6-K HDMI_TX2_DP_C
4 CPU_HDMI_TXP2 CPU_HDMI_TXN2 HDMI_TX2_DN_C
C3402 1 2 .1U_0402_10V6-K
4 CPU_HDMI_TXN2

2
PCH_HDMI_DDC_DATA 1 6 DDPB_DATA_U

S
4 PCH_HDMI_DDC_DATA

D
CPU_HDMI_TXP1 C3403 1 2 .1U_0402_10V6-K HDMI_TX1_DP_C R3407
4 CPU_HDMI_TXP1 Q3401A

2
CPU_HDMI_TXN1 C3404 1 2 .1U_0402_10V6-K HDMI_TX1_DN_C Q3402

G
4 CPU_HDMI_TXN1 1M_0402_5%
2N7002KDWH_SOT363-6

1
CPU_HDMI_TXP0 C3405 1 2 .1U_0402_10V6-K HDMI_TX0_DP_C
4 CPU_HDMI_TXP0 CPU_HDMI_TXN0 HDMI_TX0_DN_C CPU_HDMI_HPD HDMI_DET
C3406 1 2 .1U_0402_10V6-K 3 1

5
4 CPU_HDMI_TXN0 4 CPU_HDMI_HPD

D
L2N7002KWT1G_SOT323-3

2
D CPU_HDMI_CLKP HDMI_CLK_DP_C D
C3407 1 2 .1U_0402_10V6-K
4 CPU_HDMI_CLKP CPU_HDMI_CLKN HDMI_CLK_DN_C
C3408 1 2 .1U_0402_10V6-K PCH_HDMI_DDC_CLK DDPB_CLK_U HDMI* HPD Cost Reduced Level Shifter Design
4 CPU_HDMI_CLKN 4 3 R3410

S
4 PCH_HDMI_DDC_CLK

D
20K_0402_5%
Q3401B

1
2N7002KDWH_SOT363-6
+5VS_HDMI

2
1
HDMI_TX0_DP_CON 1 2 HDMI_TX0_DN_CON RP3401
R10180 270_0402_1% EMC_HDMI_NCMC@ 2.2K_0404_4P2R_5%
HDMI_TX1_DP_CON 1 2 HDMI_TX1_DN_CON +5VS_HDMI
R10181 270_0402_1% EMC_HDMI_NCMC@ JHDMI1

3
4
HDMI_TX2_DP_CON 1 2 HDMI_TX2_DN_CON
R10182 270_0402_1% EMC_HDMI_NCMC@ 18 15 DDPB_CLK_U
HDMI_CLK_DP_CON 1 2 HDMI_CLK_DN_CON +5V_Power SCL 16 DDPB_DATA_U
R10183 270_0402_1% EMC_HDMI_NCMC@ SDA
HDMI_TX0_DP_CON 7
HDMI_TX0_DN_CON 9 TMDS_Data0+ 13
HDMI_TX1_DP_CON 4 TMDS_Data0- CEC 17
For EMC request HDMI_TX1_DN_CON TMDS_Data1+ DDC/CEC_Ground HDMI_DET
6 19
HDMI_TX2_DP_CON 1 TMDS_Data1- Hot_Plug_Detect
HDMI_TX2_DN_CON 3 TMDS_Data2+
TMDS_Data2-
8 14
5 TMDS_Data0_Shield Utility
2 TMDS_Data1_Shield
TMDS_Data2_Shield
20
11 GND1 21
HDMI_CLK_DP_C R3418 1 @ 2 0_0402_5% HDMI_CLK_DP_CON 10 TMDS_Clock_Shield GND2 22
Need to change about 470Ohm 5%-575412 Page115 Rev0.8 HDMI_CLK_DN_C R3419 1 @ 2 0_0402_5% HDMI_CLK_DN_CON 12 TMDS_Clock+ GND3 23
TMDS_Clock- GND4
HDMI_TX0_DP_C R3401 1 2 470_0402_5%
C HDMI_TX0_DN_C C
R3402 1 2 470_0402_5%
ALLTO_C128AF-K1935-L
HDMI_TX1_DP_C R3403 1 2 470_0402_5% ME@
HDMI_TX1_DN_C R3404 1 2 470_0402_5% change symbol to SP011703273 by amy 0622

HDMI_TX2_DP_C R3405 1 2 470_0402_5%

HDMI_TX2_DN_C

HDMI_CLK_DP_C
R3406 1 2 470_0402_5% Vinafix.com
R3408 1 2 470_0402_5%

HDMI_CLK_DN_C R3409 1 2 470_0402_5%

https://vinafix.com
1

D R3412 1 @ 2 0_0402_5%
+3VS 2
G Q3403
L2N7002KWT1G_SOT323-3 EXC24CH900U_4P
S HDMI_TX0_DP_C 4 3 HDMI_TX0_DP_CON
3

4 3
1 2 EMC_HDMI_CMC@
HDMI_TX0_DN_C 1 2 HDMI_TX0_DN_CON
R3411 1 2
100K_0402_5% L3401
@
R3413 1 @ 2 0_0402_5%

R3414 1 @ 2 0_0402_5%

F1 use 1.1A
EXC24CH900U_4P
+5VS_HDMI_F +5VS_HDMI HDMI_TX1_DP_C 4 3 HDMI_TX1_DP_CON
+5VS 4 3
EMC_HDMI_CMC@
B F3401 HDMI_TX1_DN_C HDMI_TX1_DN_CON B
1 2
1 2 1 2
L3402
1.1A_8V_1206L110THYR note: one sku stuff EMC_HDMI_NCMC@ to verify the res
R3415 1 @ 2 0_0402_5% instead of CMC,Other sku stuff EMC_HDMI_CMC@
1
C3409
1 3 .1U_0402_10V6-K
D

Q3404 2
LP2301ALT1G_SOT23-3
G

1 2 0_0402_5%
2

R3416 @

46 SUSP EXC24CH900U_4P
HDMI_TX2_DP_C 4 3 HDMI_TX2_DP_CON
4 3
D3401
HDMI_CLK_DP_CON HDMI_CLK_DP_CON EMC_HDMI_CMC@
1 1 10 9 HDMI_TX2_DN_C HDMI_TX2_DN_CON
1 2
1 2
HDMI_CLK_DN_CON 2 2 9 8 HDMI_CLK_DN_CON
L3403
HDMI_TX0_DP_CON 4 4 7 7 HDMI_TX0_DP_CON
R3417 1 @ 2 0_0402_5%
HDMI_TX0_DN_CON 5 5 6 6 HDMI_TX0_DN_CON

3 3

8
D3402
HDMI_DET 1 1 10 9 HDMI_DET
AZ1045-04F_DFN2510P10E-10-9 For EMC
DDPB_CLK_U 2 2 9 8 DDPB_CLK_U
EMC_NS@ EXC24CH900U_4P
HDMI_CLK_DP_C 4 3 HDMI_CLK_DP_CON
DDPB_DATA_U 4 4 7 7 DDPB_DATA_U 4 3
D3403 EMC_HDMI_CMC@
+5VS_HDMI 5 5 6 6 +5VS_HDMI
HDMI_TX1_DN_CON 1 1 10 9 HDMI_TX1_DN_CON HDMI_CLK_DN_C 1 2 HDMI_CLK_DN_CON
1 2
3 3 HDMI_TX1_DP_CON HDMI_TX1_DP_CON L3404
A 2 2 9 8 A
8 HDMI_TX2_DN_CON HDMI_TX2_DN_CON
4 4 7 7 For EMC
HDMI_TX2_DP_CON 5 5 6 6 HDMI_TX2_DP_CON
AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ 3 3

Security Classification LC Future Center Secret Data Title

AZ1045-04F_DFN2510P10E-10-9
EMC_NS@ Issued Date 2015/08/20 Deciphered Date 2016/08/20 HDMI_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 34 of 61
5 4 3 2 1
 A B C D E F G H

1.1.8VGS_PWR_EN_R pull high RV18----P26

2.ON/OFFBTN# add diode D25-----P36
3.del

1 1

2 2

https://vinafix.com
3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 35 of 61
A B C D E F G H
 5 4 3 2 1

ON/OFF switch
+3VL +3VALW
D D

2
R3606 R3608
100K_0402_5% 100K_0402_5%
@
R3607 1 2

1
200_0402_1% +3VL

2
NOVO# D3615 2 R3611
44 NOVO#
100K_0402_5%
1 NOVO_BTN#
NOVO_BTN# 30
R3612

1
ON/OFF 3 @
ON/OFFBTN# 1 2 ON/OFF
45 ON/OFFBTN# ON/OFF 44
BAT54CW_SOT323-3

J5 1 2 @ 0_0402_5%
1
@
SHORT PADS C9
0.1U_0402_25V6
J6 1 2 @ @2

SHORT PADS

ON/OFFBTN#

AZ5123-01F.R7GR_DFN1006P2X2

1
D25

1
C C

2
EMC@

2
https://vinafix.com

B B

LID switch

+3VL

U3601
R3602 1 @ 2 0_0402_5% +VCC_LID 2
VCC
2
@ C3601 3 R3603 1 @ 2 0_0402_5% LID_SW#
OUTPUT LID_SW# 44
.01U_0402_16V7-K
1 1
GND 2
AH9247-W-7_SC59-3 C3602
100P_0402_50V8J
1
EMC_NS@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 HALL Sensor

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 36 of 61
5 4 3 2 1
 5 4 3 2 1

+3VS_SSD
+3VS
@
R3701 1 2 0_5%_0603 Min 3A

0.1U_0402_10V7K
4.7U_0603_6.3V6K
1 1 1 1

10U_0603_6.3V6M

10U_0603_6.3V6M
@

D D
2 2 2 2

C3701

C3702

C3703

C3704
@ @
@
+3VS_SSD

JSSD1

1 2
3 GND_1 3.3V_1 4

0.1U_0402_10V7K
5 GND_2 3.3V_2 6 1 1

10U_0603_6.3V6M
9 PCIE_PRX_DTX_N13 PERN3 N/C_2
7 8
9 PCIE_PRX_DTX_P13 9 PERP3 N/C_3 10
0.22U_0402_10V6K 1 2 C3705 PCIE_PTX_C_DRX_N13 11 GND_3 DAS/DSS# 12
9 PCIE_PTX_DRX_N13 1 2 C3706 PCIE_PTX_C_DRX_P13 13 PETN3 3.3V_3 14 2 2
0.22U_0402_10V6K

C10175

C10176
9 PCIE_PTX_DRX_P13 PETP3 3.3V_4
15 16
17 GND_4 3.3V_5 18
9 PCIE_PRX_DTX_N14 19 PERN2 3.3V_6 20
9 PCIE_PRX_DTX_P14 PERP2 N/C_4 @
21 22
0.22U_0402_10V6K 1 2 C3707 PCIE_PTX_C_DRX_N14 23 GND_5 N/C_5 24
9 PCIE_PTX_DRX_N14 PETN2 N/C_6

1
0.22U_0402_10V6K 1 2 C3708 PCIE_PTX_C_DRX_P14 25 26
9 PCIE_PTX_DRX_P14 PETP2 N/C_7
27 28 R3702
29 GND_6 N/C_8 30
9 PCIE_PRX_DTX_N15 PERN1 N/C_9 10K_0402_5%
31 32
9 PCIE_PRX_DTX_P15 33 PERP1 N/C_10 34 @

2
0.22U_0402_10V6K 1 2 C3709 PCIE_PTX_C_DRX_N15 35 GND_7 N/C_11 36
9 PCIE_PTX_DRX_N15 PCIE_PTX_C_DRX_P15 PETN1 N/C_12
0.22U_0402_10V6K 1 2 C3710 37 38 R3703 1 2 0_0402_5% @
9 PCIE_PTX_DRX_P15 PETP1 DEVSLP PCH_SATA_DEVSLP 9
39 40
41 GND_8 N/C_13 42
9 PCIE_PRX_DTX_P16 43 PERN0/SATA-B+ N/C_14 44
9 PCIE_PRX_DTX_N16 45 PERP0/SATA-B- N/C_15 46
0.22U_0402_10V6K 1 2 C3711 PCIE_PTX_C_DRX_N16 47 GND_9 N/C_16 48
9 PCIE_PTX_DRX_N16 PCIE_PTX_C_DRX_P16 PETN0/SATA-A- N/C_17 PLT_RST#_B
0.22U_0402_10V6K 1 2 C3712 49 50
9 PCIE_PTX_DRX_P16 PETP0/SATA-A+ PERST# SSD_CLKREQ_Q# PLT_RST#_B 11,26,40,44
C 51 52 R3704 1 2 0_0402_5% @ SSD_CLKREQ# 10 C
53 GND_10 CLKREQ# 54 1
10 CLK_PCIE_SSD# REFCLKN PEWAKE# TP3701
55 56
10 CLK_PCIE_SSD REFCLKP N/C_18
57 58
+3VS_SSD GND_11 N/C_19
59 NC NC 60
61 NC NC 62
63 NC NC 64 +3VS_SSD

1
65 NC NC 66
R3706 67 68
100K_0402_5% @ SSD_DET 69 N/C_1 SUSCLK 70
71 PEDET 3.3V_7 72

0.1U_0402_10V7K
73 GND_12 3.3V_8 74
1 1

10U_0603_6.3V6M
2
75 GND_13 3.3V_9
@ GND_14
R3705 1 2 0_0402_5%
9 SSD_PCIE_DET#
77 76

https://vinafix.com
PEG1 PEG2 2 2

C10177

C10178
1

D Q3701 ARGOS_NASM0-S6701-TS40
2 ME@ @
G
SSD_DET#
L2N7002KWT1G_SOT323-3 S
@ 0--SATA Change Symbol to SP070013X00 amy 0614
3

1--PCIE

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 NGFF_SSD_1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 37 of 61
5 4 3 2 1
 5 4 3 2 1

D D

JHDD1

10 11
SATA_PTX_DRX_P0 C66 1 2 0.01U_16V_K_X7R_0402 SATA_PTX_C_DRX_P0 9 10 GND1
9 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PTX_C_DRX_N0 9
9 SATA_PTX_DRX_N0 C67 1 2 0.01U_16V_K_X7R_0402 8 12
7 8 GND2
SATA_PRX_DTX_N0 C68 1 2 0.01U_16V_K_X7R_0402 SATA_PRX_C_DTX_N0 6 7
9 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 0.01U_16V_K_X7R_0402 SATA_PRX_C_DTX_P0 5 6
9 SATA_PRX_DTX_P0 4 5
3 4
2 3
1 2
+5VS_HDD 1
HIGHS_FC5AF101-2931H
ME@

change symbol to SP01001WV00 by amy 0620

C C

+5VS_HDD +5VS

@
R3801 1 2 0_5%_0603

1 1 1 1 1 1 1
C3805 C3811 C3806 C3808 C3809
33P_0402_50V8J 33P_0402_50V8J .1U_0402_10V6-K 10U_0805_10V6K 10U_0805_10V6K C10183 C10184

https://vinafix.com
RF_NS@ RF_NS@ @ 22U_10V_M_X5R_0603 22U_10V_M_X5R_0603
2 2 2 2 2 2 2
@ @

For EMC

B B

Vinafix.com

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 SATA HDD CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 38 of 61
5 4 3 2 1
 5 4 3 2 1

SMSC thermal sensor Near GPU&VRAM REMOTE2+

Near CPU core
1
placed near DIMM

1
C3901 C
REMOTE1+
2 Q3901
1 100P_0402_50V8J
@ B MMBT3904WH_SOT323-3

1
C10157 C 2 @E
REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: 2 Q3902

3
100P_0402_50V8J @ B MMBT3904WH_SOT323-3 REMOTE2-
Trace width/space:10/10 mil 2 @ E

3
Trace length:<8" REMOTE1-

D +3VALW D
+3VALW
+3VS
Near CPU
+3VS

1
1 R3903
R2403 1 @ 2 10K_0402_5% SEN_THERM_N C2401 R3904
SEN_ALERT_N 13.7K_0402_1%
R2404 1 @ 2 10K_0402_5% 13.7K_0402_1%
@ 0.1U_0402_10V7K
2

2
NTC_V1

2
NTC_V2

1
R3905
U3901 R3906
100K_0402_1%_NCP15WF104F03RC
100K_0402_1%_NCP15WF104F03RC
OPT@
1 10 EC_SMB_CK2

2
1 EC_SMB_CK2 7,26,44

2
@ VCC SCL
C2403 REMOTE1+ 2 9 EC_SMB_DA2
2200P_0402_50V7K DP1 SDA EC_SMB_DA2 7,26,44
2 REMOTE1- 3 8 SEN_ALERT_N
DN1 ALERT#
REMOTE2+ 4 7 SEN_THERM_N
DP2 THERM#
1
@ REMOTE2- 5 6
C2405 DN2 GND
2200P_0402_50V7K
2
F75303M_MSOP10 @

C C
+3VALW

1
R3908
13.7K_0402_1%

2
44 NTC_V3

1
https://vinafix.com
R3907
100K_0402_1%_NCP15WF104F03RC

HW thermal sensor

2
+5VS +5VS_FAN1

+5VLP +5VLP R3915 1 2 0_0402_5% @

+5VLP
1
C3907 1
C3908 @
10U_0805_10V6K
2

.1U_0402_10V6-K
C3904 0.1U_0402_10V7K

1 R3909 R3910 2
@ @ 2
21.5K_0402_1% 21.5K_0402_1%
@ @
1

2
B
U3902 @ FAN Conn B
1 8 TMSNS1 R3911 1 @ 2 0_0402_5% NTC_V1
VCC TMSNS1 NTC_V1 44
2 7 PHYST1 1
R3912 @ 2 10K_0402_5% +5VS_FAN1
GND RHYST1
JFAN1
3 6 TMSNS2 R3913 1 @ 2 0_0402_5%NTC_V2
54 EC_ON_R OT1 TMSNS2 NTC_V2 44 44 EC_FAN_PWM1 1
2 1
4 5 PHYST2 1
R3914 @ 2 10K_0402_5% 44 EC_FAN_SPEED1 2
OT2 RHYST2 3
4 3
G718TM1U_SOT23-8 4
5
over temperature threshold: 6 GND1
GND2
RSET=3*RTMH
92+/-30C HIGHS_WS33040-S0351-HF
Hysteresis temperature threshold. ME@
RHYST=(RSET*RTML)/(3*RTML-RSET) Change Symbol to SP021410082 amy 0614
56+/-30C

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 Thermal sensor/FAN CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 39 of 61
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX) +3VS +3V_WLAN

@
R10187 1 2 0_5%_0603

+3VALW

R2236
1 2
1 0.01_0603_1% 1
@

1
R2234 C10188
1 2 100U_1206_6.3V6M

2
0.01_0603_1%
@
@
1

C2212
0.01U_0402_25V7K
2@
+3VALW
Q36
LP2301ALT1G_SOT23-3
AOAC@

D
3 1

0.1u_0201_10V6K
1 1
C2083

C2082
2
0.1u_0201_10V6K @
@
2 2
R4677
AOAC_ON# 1 2
8 AOAC_ON#
100K_0402_5%
AOAC@ 1
C2081
0.1u_0201_10V6K +3V_WLAN
AOAC_ON# R1266 2 AOAC@ +3V_WLAN
1 2
100K_0402_5%
AOAC@ 1 2 10K_0402_5% PCH_WLAN_OFF#
RC832
RC833 1 2 10K_0402_5% PCH_BT_OFF#

0.01U_0402_25V7K
2 1 1 1 2

10U_0603_6.3V6M
.1U_0402_10V6-K
C10181

C10179
2 2 2

C10180
JWLAN1
@ +3VS
1 2 @ @
USB20_P10 3 GND1 3.3VAUX1 4
9 USB20_P10 USB20_N10 USB_D+ 3.3VAUX2
5 6 1
9 USB20_N10 7 USB_D- LED1# 8 T4001
GND2 PCM_CLK/I2S_SCK

1
9 10
11 SDIO_CLK PCM_SYNC/I2S_WS 12 R258
13 SDIO_CMD PCM_IN/I2S_SD_IN 14 1/20W_49.9K_1%_0201
15 SDIO_DATA0 PCM_OUT/I2S_SD_OUT 16 1

https://vinafix.com
17 SDIO_DATA1 LED#2 18 T4002

2
19 SDIO_DATA2 GND11 20
21 SDIO_DATA3 UART_WAKE# 22 UART_RX_DEBUG_R R10184 1 @ 2 0_0402_5%
23 SDIO_WAKE# UART_RXD UART_RX_DEBUG 8
SDIO_RESET# +3VS

1
KEY E
25 PIN24~PIN31 NC PIN 24 R259
27 26 1/20W_49.9K_1%_0201
29 28
31 30

2
33 32 UART_TX_DEBUG_R R10185 1 @ 2 0_0402_5%
GND3 UART_TXD UART_TX_DEBUG 8
35 34
9 PCIE_PTX_C_DRX_P9 37 PETP0 UART_CTS 36
+3VS +3V_WLAN 9 PCIE_PTX_C_DRX_N9 PETN0 UART_RTS EC_TX_RSVD
39 38 R4006 1 @ 2 0_0402_5%
41 GND4 VENDOR_DEFINED1 40 EC_RX_RSVD R4007 1 @ 2 0_0402_5%
WLAN 9 PCIE_PRX_DTX_P9
2

43 PERP0 VENDOR_DEFINED2 42
9 PCIE_PRX_DTX_N9 PERN0 VENDOR_DEFINED3
2

R4066 45 44
G

47 GND5 COEX3 46 EC_RX 44

@ 10K_0402_5%
Q4008 10 CLK_PCIE_WLAN REFCLKP0 COEX2
@ 49 48
3 10 CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R 3
51 50 R4010 1 @ 2 0_0402_5%
SUSCLK 10
1

3 1 WLAN_CLKREQ_Q# 53 GND6 SUSCLK 52 PLT_RST#_B

10 WLAN_CLKREQ# CLKREQ0# PERST0# PLT_RST#_B 11,26,37,44
S

R4012 1 2 0_0402_5% PCIE_WAKE#_WLAN 55 54 BT_OFF# R4013 1 2 1K_0402_5%

11 PCIE_WAKE# 57 PEWAKE0# W_DISABLE2# 56 WLAN_OFF# PCH_BT_OFF# 8
L2N7002KWT1G_SOT323-3 @ R4014 1 @ 2 0_0402_5%
GND7 W_DISABLE1# PCH_WLAN_OFF# 8
R10186 1 @ 2 0_0402_5%
R4011 1 @ 2 0_0402_5%
59 58 SMB_DATA_S3_R 1 2 0_0402_5%
R4008 @
RSRVD/PETP1 I2C_DATA SMB_CLK_S3_R SMB_DATA_S3 7,18
61 60 R4696 1 @ 2 0_0402_5%
63 RSRVD/PETN1 I2C_CLK 62 1 2 0_0402_5% SMB_CLK_S3 7,18
R4017 @
GND8 ALERT# EC_TX 44
65 64
67 RSRVD/PERP1 RSRVD 66
69 RERVD/PERN1 UIM_SWP/PERST1# 68
GND9 UIM_POWER_SNK/CLKREQ1#

1
71 70
73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72 R4018
75 RSRVD/REFCLKN1 3.3VAUX3 74 100K_0402_5%
GND10 3.3VAUX4
77 76

2
GND15 GND14

+3V_WLAN
ARGOS_NASE0-S6701-TS40
ME@

0.01U_0402_25V7K
1 1 1

10U_0603_6.3V6M
.1U_0402_10V6-K
C10162

C10163

2 2 2
C10158

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2016/12/14 Deciphered Date 2017/12/13 NGFF_WLAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 40 of 61
A B C D E
 5 4 3 2 1

+5VALW +USB_VCCA
+USB_VCCA
RIGHT SIDE USB3.0 PORT x1 5
U4401
IN OUT
1
1
C4401 2
1U_0402_6.3V6K GND
4 3 USB_OC1#
2 43,44 USB_ON# ENB OCB USB_OC1# 9
SY6288D20AAC_SOT23-5 1

150U_B2_6.3VM_R35M
C10165

2
+
Low Active 2A C4102
1U_0402_10V6K

1
2
@

D D

R4109 1 @ 2 0_0402_5%

EXC24CH900U_4P
USB20_N1 4 3 USB20_N1_R
9 USB20_N1 4 3

USB20_P1 1 2 USB20_P1_R
9 USB20_P1 1
L4101
2
EMC@
C4102 close to USB Conn
+USB_VCCA
R4111 1 @ 2 0_0402_5%
JUSB2

USB30_TX_R_P2 9
1 StdA_SSTX+
USB30_TX_R_N2 8 VBUS
USB20_P1_R 3 StdA_SSTX-
UARTA_P80_EN 7 D+
USB20_N1_R 2 GND_DRAIN 10
USB30_RX_R_P2 6 D- GND_2 11
4 StdA_SSRX+ GND_3 12
R4313 1 @ 2 0_0402_5% USB30_RX_R_N2 GND_1 GND_4
5 13
StdA_SSRX- GND_5

1
R538
L4307 EMC_NS@ R537

2 Debug@
USB30_TX_P2 2 .1U_0402_10V6-K USB30_TX_C_P2 ALLTO_C19043-10905-L

100K_0402_5%
C4105 1 1 2 USB30_TX_R_P2 0_0402_5%
9 USB30_TX_P2 1 2 ME@
@ Change Symbol to DC23300M800 amy 1017

1
USB30_TX_N2 C4106 1 2 .1U_0402_10V6-K USB30_TX_C_N2 4 3 USB30_TX_R_N2
9 USB30_TX_N2 4 3
EXC24CH900U_4P

C C
R4311 1 @ 2 0_0402_5%

+USB_VCCA
EMC@ D4102 USB20_P1_R
USB30_RX_R_N2 10 1 USB30_RX_R_N2
NC1 Line-1

1
R4310 1 @ 2 0_0402_5% USB20_N1_R
USB30_RX_R_P2 9 2 USB30_RX_R_P2

AZ5725-01F.R7GR_DFN1006P2X2
NC2 Line-2

1
D4101
USB30_TX_R_N2 7 4 USB30_TX_R_N2

2
L4308 EMC_NS@ NC3 Line-3
USB30_RX_P2 USB30_RX_R_P2

AZ5423-01F.R7GR_DFN1006P2E2

D4103

AZ5423-01F.R7GR_DFN1006P2E2

D4104
1 2 EMC_NS@

2
9 USB30_RX_P2 1 2 USB30_TX_R_P2 6 5 USB30_TX_R_P2

https://vinafix.com
NC4 Line-4

2
USB30_RX_N2 USB30_RX_R_N2 3
4 3 GND1
9 USB30_RX_N2

2
4 3
EMC 8

1
EXC24CH900U_4P GND2
AZ1143-04F-R7G_DFN2510P10E10

1
R4309 1 @ 2 0_0402_5%

EMC@

EMC@
B
For USB Debug Function B

USBDEBUG Kernel debug

Set input Set input

Set output Low ENABLE

UARTA_P80_EN POST 80
Set input DISABLE

Set output Low ENABLE

OE# S FUNCTION
H X DISABLE

L L D(+/-) to 1D(+/-)

L H D(+/-) to 2D(+/-)

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 USB3 PORT_LEFT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 41 of 61
5 4 3 2 1
 5 4 3 2 1

D D

C C

B
https://vinafix.com B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 42 of 61
5 4 3 2 1
 A B C D E

Right SIDE USB3.0 PORT

R4112 1 @ 2 0_0402_5%

+5VALW +USB_VCCB
U4301
5 1 L4102 EMC_NS@
IN OUT USB30_TX_P1 C4311 1 2 .1U_0402_10V6-KUSB30_TX_C_P1 1 2 USB30_TX_R_P1
1 9 USB30_TX_P1 1 2
C4301 2
1U_0402_6.3V6K GND
4 3 USB_OC0# USB30_TX_N1 C4312 1 2 .1U_0402_10V6-KUSB30_TX_C_N1 4 3 USB30_TX_R_N1
2 41,44 USB_ON# ENB OCB USB_OC0# 9 9 USB30_TX_N1 4 3 +USB_VCCB
SY6288D20AAC_SOT23-5 EXC24CH900U_4P
1 1

R4113 1 @ 2 0_0402_5%
Low Active 2A

1
C10168
R4114 1 @ 2 0_0402_5% +

150U_B2_6.3VM_R35M

2
C4304
L4103 EMC_NS@ 2
1U_0402_10V6K

1
USB30_RX_P1 1 2 USB30_RX_R_P1
9 USB30_RX_P1 1 2 @

USB30_RX_N1 4 3 USB30_RX_R_N1
9 USB30_RX_N1 4 3
R4314 1 @ 2 0_0402_5%
EXC24CH900U_4P
EXC24CH900U_4P R4115 1 @ 2 0_0402_5%
USB20_N3 4 3 USB20_N3_R
9 USB20_N3 4 3

USB20_P3 1 2 USB20_P3_R
9 USB20_P3 1 2
L4306 EMC@

R4312 1 @ 2 0_0402_5% C4304 close to USB Conn

+USB_VCCB
USB20_P3_R
+USB_VCCB
USB20_N3_R JUSB1
2 2
USB30_TX_R_P1 9
EMC@ StdA_SSTX+

1
1
D4310 USB30_TX_R_N1 VBUS

D4311
AZ5423-01F.R7GR_DFN1006P2E2

D4308
AZ5423-01F.R7GR_DFN1006P2E2

AZ5725-01F.R7GR_DFN1006P2X2
USB30_RX_R_N1 USB30_RX_R_N1 8

1
10 1 USB20_P3_R StdA_SSTX-
NC1 Line-1 3
7 D+
USB30_RX_R_P1 9 2 USB30_RX_R_P1 GND_DRAIN
NC2 Line-2 D4309 USB20_N3_R 2 10
USB30_RX_R_P1 6 D- GND_2 11
USB30_TX_R_N1 7 4 USB30_TX_R_N1 StdA_SSRX+ GND_3

2
NC3 Line-3 EMC_NS@ 4 12
USB30_RX_R_N1 5 GND_1 GND_4 13
USB30_TX_R_P1 6 5 USB30_TX_R_P1

2
StdA_SSRX- GND_5
NC4 Line-4

EMC@

EMC@
3
GND1 ALLTO_C19043-10905-L
8 ME@
GND2
EMC

https://vinafix.com
AZ1143-04F-R7G_DFN2510P10E10
Change Symbol to SP011703284 amy 0614
D4308 and D4311 (SC400006510):due to CIS source cant use,so need
change to SC400008800, S DIO_ESD AZ5423-01F.R7GR DFN1006P2E

USB20_N4_R

USB2.0 PORT x1 USB20_P4_R

2
R4691 1 2 0_0402_5% Close to Connector
+USB2_VCCA D48
@ AZC199-02S.R7G_SOT23-3
EMC@
3 EMC@ 3
EXC24CH900U_4P
USB20_P4 4 3 USB20_P4_R 1 1
9 USB20_P4 4 3 C4995 C4996
470P_0402_50V7K 1U_0603_25V6M
USB20_N4 1 2 USB20_N4_R @
9 USB20_N4 1 2 2 2
@ JUSB3
L4309

1
1
USB20_N4_R 2 VBUS
USB20_P4_R 3 D-
R4690 1 2 0_0402_5% 4 D+ 5
GND GND1 6
GND2 7
@
GND3 8
GND4 FOR ESD
ALLTO_C107G1-10803-L
ME@

+5VALW +USB2_VCCA +USB2_VCCA

U4402 change symbol to SP011807041 amy 0710
5 1
IN OUT
1
C10169 2 +USB2_VCCA
1U_0402_6.3V6K GND
USB_ON# 4 3 USB_OC2#
2 ENB OCB USB_OC2# 9
1

1
SY6288D20AAC_SOT23-5 C10172
2

AZ5725-01F.R7GR_DFN1006P2X2
+

1
C10174
Low Active 2A 1U_0402_10V6K
1

2 D5103
150U_B2_6.3VM_R35M

@
EMC_NS@

2
2
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 USB3 Port_Right & USB2.0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 43 of 61
A B C D E
 5 4 3 2 1

+3VS

+3VL_EC +3VL_EC
1 @
CE4410+3VS RE4401 1 2 0_5%_0603
+3VL
1

1
.1U_0402_10V6-K
RE4404 RE4460 +3VL_EC
2 +3VL_EC_R
100K_0402_5% 100K_0402_5%
UMA@ OPTN16@ EC_PCHHOT# 1 2 SML1_ALERT# +3VL_EC 1 @ 2 0_5%_0603
@ SML1_ALERT# 7 LE4401
2

2
EC_ID1 EC_ID0 0_0402_5% RE279 +3VS
All capacitors close to EC 1 1

.1U_0402_10V6-K

.1U_0402_10V6-K
1

1
Close EC Close EC +3VL_EC

CE4408

CE4409
RE4406 RE4461 @ @ @
100K_0402_5% 100K_0402_5% CE4401 1 1 1 1 1 1

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
2 2

CE4402

CE4403

CE4404

CE4405

CE4406

CE4407
OPT@ OPTN17@ 1 2 VCOREVCC

2
+3VL_EC_R EC_FAN_SPEED1 RE4411 2 1 10K_0402_5%
2

R4615

0_5%_0603
D 2 2 2 2 2 2 D
.1U_0402_10V6-K 1 @ 2 0_5%_0603 EC_AGND EC_FAN_PWM1
LE4402 RE4413 1 @ 2 10K_0402_5%
RE4408 1 @ 2 0_0402_5% LPC_FRAME# RE4414 1 2 10K_0402_5%

1
@
@
CPU_VR_READY RE4423 1 2 10K_0402_5%
EC_AGND
minimum trace width 12 mil EC_TP_ON RE4415 1 @ 2 10K_0402_5%

114
121
127
12

11

26
50
92

74
3
UE4401
ENBKL RE4425 1 @ 2 100K_0402_5%

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

VSTBY(PLL)

AVCC
VBAT

VCORE
Vinafix.com
26 WRST# KBRST#_EC
RE4416 1 @ 2 0_0402_5% 4 24
7 KBRST# SERIRQ_EC KBRST#/GPB6 PWM0/GPA0 PWR_LED#
RE4417 1 @ 2 0_0402_5% 5 25 For PMIC
+3VL_EC 7 SERIRQ SERIRQ/GPM6 PWM1/GPA1 PWR_LED# 45
RE4421 1 @ 2 0_0402_5% LPC_FRAME#_EC 6 28 BATT_LOW_LED#
+3VALW +3VL_EC
7 LPC_FRAME# LPC_AD3_EC 7 LFRAME#/GPM5 PWM2/GPA2 29 BATT_CHG_LED# BATT_LOW_LED# 45
@ BATT_CHG_LED# 45
7 LPC_AD3_EC LPC_AD2_EC LAD3/GPM3 PWM3/GPA3 EC_FAN_PWM1
1
DE4401 2 8 PWM 30 EC_FAN_PWM1 39
7 LPC_AD2_EC LPC_AD1_EC LAD2/GPM2 PWM4/GPA4
9 31

1
7 LPC_AD1_EC LPC_AD0_EC 10 LAD1/GPM1 PWM5/GPA5 32 EC_BEEP
RB751V-40_SOD323-2
7 LPC_AD0_EC CLK_PCI_EC LAD0/GPM0 PWM6/SSCK/GPA6 EC_VCCST_EN EC_BEEP 30 RE4427 RE4428
13 LPC 34 @
1 2 7 CLK_PCI_EC 14 LPCCLK/GPM4 PWM7/RIG1#/GPA7 120 EC_VCCST_EN 13 0_0402_5% 0_0402_5%
WRST#
EC_SMI# WRST# TMRI0/GPC4 @
100K_0402_5% RE4422 15 124 SUSP#
1U_0402_6.3V6K

9 EC_SMI# EC_RX ECSMI#/GPD4 TMRI1/GPC6 SUSP# 46,54

16 RPE4401

2
1 40 EC_RX PWUREQ#/BBO/SMCLK2ALT/GPC7
EC_TX 17 66 NTC_V1 EC_SMB_DA3 1 4
CE4411

40 EC_TX LPCPD#/GPE6 ADC0/GPI0 NTC_V1 39

PLT_RST#_B 22 67 NTC_V2 EC_SMB_CK3 2 3
11,26,37,40 PLT_RST#_B LPCRST#/GPD2 ADC1/GPI1 NTC_V2 39
EC_SCI# 23 68 BATT_TEMP
2 4 EC_SCI# EC_RTCRST#_ON ECSCI#/GPD3 ADC2/GPI2 NTC_V3 BATT_TEMP 52,53
126 ADC 69 NTC_V3 39 2.2K_0404_4P2R_5%
GA20/GPB5 ADC3/GPI3 70 CPU_VR_READY
IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72 RE4426 2
ADP_I
@ 1 0_0402_5%
CPU_VR_READY 58
ADP_I 53
ADC6/DSR1#/GPI6 PSYS 53,58

45 KSI[0..7]
KSI[0..7] KSI0 58
KSI0/STB#
LQFP-128L ADC7/CTS1#/GPI7
73 SYS_PWROK
SYS_PWROK 11
+3VL_EC
KSI1 59 78 EC_TS_ON
KSI1/AFD# DAC2/TACH0B/GPJ2 EC_TS_ON 33
KSO[0..17] KSI2 60 79 EC_TP_ON
45 KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 H_PROCHOT#_EC EC_TP_ON 45
C KSI3 61 DAC 80 C
KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 ENBKL R4401 2 @ 1 0_0402_5% EC_ON RE4430 2 1 100K_0402_5%
KSI4 DAC5/RIG0#/GPJ5 PCH_ENBKL 4,33
KSI5 63
KSI6 64 KSI5 85 EC_ON_GPIORE4429 2 @ 1 0_0402_5% EC_ON RE4458 2 @ 1 100K_0402_5%
65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 PBTN_OUT# EC_ON 54,55
KSI7
KSI7 PS2DAT0/TMB1/GPF1 EC_SMB_CK3 PBTN_OUT# 11
KSO0 36 87 SUSP# RE4432 1 2 100K_0402_5%
37 KSO0/PD0 GPF2 88 EC_SMB_DA3 EC_SMB_CK3 55
KSO1 Int. K/B PS2
KSO1/PD1 GPF3 EC_SMB_DA3 55
KSO2 38 89 SYSON RE4433 1 2 100K_0402_5%
KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90
KSO4 40 KSO3/PD3 PS2DAT2/GPF5 EC_VCCST_EN RE4434 1 @ 2 100K_0402_5%
KSO5 41 KSO4/PD4 96 CAPS_LED#
+3VS KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3 CAPS_LED# 45
2.2K_0404_4P2R_5% KSO6 42 97 PCH_PWR_EN EC_VCCIO_EN RE4435 1 @ 2 100K_0402_5%
EC_SMB_CK2 KSO6/PD6 GPH4/ID4 EC_VCCST_PWRGD PCH_PWR_EN 55
2 3 KSO7 43 98 R4402 1
EC_SMB_DA2 KSO7/PD7 GPH5/ID5 PCH_PWROK EC_VCCST_PWRGD 11 EC_VCCST_PWRGD OD output ENBKL 2 100K_0402_5%
1 4 KSO8 44 99
KSO8/ACK# GPH6/ID6 PCH_PWROK 11
KSO9 45
RPE4403 KSO10 46 KSO9/BUSY 101 EC_SPI_CS0# RE4446 2 @ 1 0_0402_5% SPI_CS0#

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KSO11 51 KSO10/PE NC1 102 EC_SPI_SI RE4448 2 @ 1 0_0402_5% SPI_SI SPI_CS0# 7
+3VL_EC 52 KSO11/ERR# NC2 103 EC_SPI_SO 2 1 0_0402_5% SPI_SO SPI_SI 7 Add to fix Reset&PWRGD test fail issue
KSO12 SPI Flash ROM RE4450 @
KSO12/SLCT NC3 EC_SPI_CLK SPI_CLK SPI_SO 7 VDDQ_PGOOD
RPE4402 KSO13 53 105 RE4452 2 @ 1 0_0402_5% CE4412 1 2 .01U_0402_16V7-K
2 3 EC_SMB_DA1 KSO14 54 KSO13 NC4 SPI_CLK 7
1 4 EC_SMB_CK1 KSO15 55 KSO14 PM_SLP_S4# CE4413 1 2 1000P_0402_50V7K EMC_NS@
KSO16 56 KSO15 108 ACIN#
2.2K_0404_4P2R_5% KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW#
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# 36 PM_SLP_S3# CE4414 1 2 1000P_0402_50V7K EMC_NS@

36 ON/OFF ON/OFF 110 82 SYSON CE4415 1 2 1000P_0402_50V7K EMC_NS@

EC_ON RE4436 2 @ 1 0_0402_5% 111 PWRSW# EGAD/GPE1 83 VDDQ_PGOOD
XLP_OUT SM Bus EGCS#/GPE2 VDDQ_PGOOD 55
EC_SMB_CK1 115 84 EC_VPP_PWREN NOVO# CE4416 1 2 .01U_0402_16V7-K
52,53 EC_SMB_CK1 EC_SMB_DA1 SMCLK1/GPC1 EGCLK/GPE3 EC_VPP_PWREN 55
Charger & Battery 116
52,53 EC_SMB_DA1 H_PECI 2 43_0402_5% PECI_EC SMDAT1/GPC2 EC_MUTE#
4 H_PECI RE44371 117 GPIO 77
EC_MUTE# 30
EC_ID1 118 SMCLK2/PECI/GPF6 GPJ1 100 GPG2 PECI_EC CE4417 2 1 47P_0402_50V8J EMC_NS@
EC_SMB_CK2 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 106 BKOFF#
7,26,39 EC_SMB_CK2 EC_SMB_DA2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 ME_FLASH BKOFF# 33 BATT_TEMP CE4418
GPU SENSOR Thermal 95 104 1 2 100P_0402_50V8J EMC_NS@
7,26,39 EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 ME_FLASH 8
107 SYSON
DTR1#/SBUSY/GPG1/ID7 119 EC_RSMRST#_R RE4459 1 SYSON 55
21K_0402_5% EC_RSMRST#
+3VL ACIN# CE4419 1 2 100P_0402_50V8J EMC_NS@
CRX0/GPC0 EC_VCCIO_EN EC_RSMRST# 11
123
1 2 0_0402_5% 112 CTX0/TMA0/GPB2 18 PM_SLP_S3# EC_VCCIO_EN 13
RE4438 @
VSTBY0 RI1#/GPD0 PM_SLP_S4# PM_SLP_S3# 11 CE4420
RE4439 1 2 0_0402_5% @ 125 21 PM_SLP_S4# 11 ON/OFF 1 2 @ 1U_0402_6.3V6K
B 58 EC_VR_ON GPE4 RI2#/GPD1 B
WAKE UP 76 NOVO# NOVO# 36
+5VALW TACH2/GPJ0 48 EC_FAN_SPEED1
TACH1A/TMA1/GPD7 EC_FAN_SPEED1 39 PLT_RST#_B CE4421 2 1 220P_0402_50V7K EMC_NS@
47
USB_ON# 33 TACH0A/GPD6 19
USB_ON# 41,43 USB_ON# EC_PCHHOT# GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 NUM_LED# 45
RE4440 2 1 100K_0402_5% 35 GPIO 20
RTS1#/GPE5 L80LLAT/GPE7
EC_ID0 93
CLKRUN#/GPH0/ID0 For ESD
+3VL
EMC Request
RE4442 1 @ 2 10K_0402_5% BKOFF# VGA_AC_DET 2
26 VGA_AC_DET AC_PRESENT CK32KE/GPJ7
128 Clock EMC_NS@ EMC_NS@
11 AC_PRESENT CK32K/GPJ6
RE4443 2 1 100K_0402_5% LID_SW# CLK_PCI_EC RE61 1 2 10_0402_5% CE23 1 2 10P_0402_50V8J

RE4445
1 2 10K_0402_5% BKOFF#
AVSS
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

RE4447 1 @ 2 0_0402_5% H_PROCHOT# 4,55

53,58 VR_HOT#
IT8586E-AX_LQFP128_14X14

1
113
122
27
49
91

75
1

RE4451 2
100_0402_5% CE4423
47P_0402_50V8J
1

2
EC_AGND EMC_NS@

1
QE4402 D
H_PROCHOT#_EC 2
G
+3VL
S L2N7002KWT1G_SOT323-3

3
+3VL_EC
2

RE4456 1 2 10K_0402_5% GPG2 RE4453

EC_RTC_RST# 10
100K_0402_5%
1

RE4457 1 @ 2 10K_0402_5% GPG2 QE4401 D

EC_RTCRST#_ON 2
1

ACIN# RE4454 1 @ 2 0_0402_5%

G
1

A A

RE4455 S L2N7002KWT1G_SOT323-3
1

D QE4403
3

when mirror, GPG2 pull high 2

10K_0402_5%
ACIN 53
when no mirror, GPG2 pull low @ G
2

S
L2N7002KWT1G_SOT323-3
3

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 EC_ITE8586

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 44 of 61
5 4 3 2 1
 5 4 3 2 1

KSI[0..7]
KSI[0..7] 44
KSO[0..17]
KSO[0..17] 44

K/B Connector
JKB1
R84 1 @ 2 0_0402_5% PWR_CAPS_LED 32 33
+3VALW CAPS_LED# CAPS_LED#_R 32 GND1
R275 1 2200_0402_1% 31 34
44 CAPS_LED# 30 31 GND2
KSO15
KSO10 29 30
KSO11 28 29
KSO14 27 28
KSO13 26 27
KSO12 25 26
KSO3 24 25
D
KSO6 23 24 D
KSO8 22 23
KSO7 21 22 TP_I2C_SCL0
KSO4
KSO2
20
19
21
20
TP/B Connector +3VS TP_PWR
TP_I2C_SDA0

19

3
KSI0 18
17 18 1 @ 2 0_5%_0603
KSO1 R4509 DT4501
KSO5 16 17
KSI3 15 16 EMC_NS@
KSI2 14 15
14 1
KSO0 13 C4509
KSI5 12 13 .1U_0402_10V6-K
KSI4 11 12
KSO9 10 11 2
KSI6 9 10
KSI7 8 9
KSI1 7 8 AZC199-02S.R7G_SOT23-3

1
KSO16 R281 1 @ 2 0_0402_5% KSO16_R 6 7
KSO17_R 6 For EMC
KSO17 R280 1 @ 2 0_0402_5% 5
R101741 NUM_LED#_R 5
44 NUM_LED# 15@ 2 200_0402_1% 4
PWR_LED# R101751 2 200_0402_1% 3 4
ON/OFFBTN# 2 3
36 ON/OFFBTN# 2
1
1

HIGHS_FC8AR321-3160-1H
ME@
100P_0402_50V8J 1 2 C4503 PWR_CAPS_LED
Change Symbol to SP011807040 amy 0709
EMC_NS@

100P_0402_50V8J 1 2 C4504 CAPS_LED#

EMC_NS@

100P_0201_25V8J 1 2 C118 NUM_LED#_R

EMC_15_NS@

JTP1
R4510 1 2 0_0402_5% @EC_TP_ON_R 1
44 EC_TP_ON 2 0_0402_5% @TP_INT# 1
R4511 1 2
8 PCH_TP_INT# 3 2
TP_I2C_SDA0 4 3
8 TP_I2C_SDA0 TP_I2C_SCL0 4
5
8 TP_I2C_SCL0 6 5
TP_PWR 6
1 1 7
C4510 C4511 8 GND1
100P_0402_50V8J GND2
100P_0402_50V8J
CAPS_LED# NUM_LED#_R PWR_LED# 2 2 EMC_NS@ HIGHS_FC5AF061-2931H
C
EMC_NS@ C
ME@

Change Symbol to SP01001WX00 Bourne 0629

1

D4501 D23 D46

1

AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2

EMC_NS@ EMC_15_NS@ EMC_NS@
2

2
2

For EMC

https://vinafix.com

PWM
BATT_LOW_LED# LED1 1 2 R4514 1 2 470_0402_5%
44 BATT_LOW_LED# +3VALW
B B
L-C192JFCT-LCFC_SUPER_AMBER
1
1

D4504
AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@
2
2

GPIO
BATT_CHG_LED# LED2 1 2 R4516 1 2 1.5K_0402_5%
44 BATT_CHG_LED# +5VALW
L-C192WDT-LCFC_WHITE
1
1

D4506
AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@
2
2

LED Stute LED Behavior

White_on(battery：21%~100%)
System on
Amber_on(battery：0%~20%)

Standby White_on(battery：21%~100%)
PWR_LED# LED3 1 2 R4672 1 2 470_0402_5%
+3VALW
Power Button
44 PWR_LED# LID closed Amber_Blink_3S(battery：0%~20%)
L-C192WDT-LCFC_WHITE OFF
System off
1

D16
1

Battery only OFF

AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@ Charging Amber_on(battery：1%~90%)
Charging
White_on(battery：91%~100%)
2
2

PWR_LED Change to M/B (310->320) 08/17

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 KB/TP_CONN.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 45 of 61
5 4 3 2 1
 A B C D E

+5VLP
+3VALW +3VALW_PCH
PJ8
1 2
1 2

1
0.1U_0402_10V7K
R4605
JUMP_43X39 100K_0402_5%
1
1 @ 1
1 1

C4622
C4621 C4624

2
22U_0603_6.3V6-M .01U_0402_16V7-K
@ EMC@ 2
2 2
@ SUSP
34 SUSP

1
Q4602 D
2
44,54 SUSP# G

S L2N7002KWT1G_SOT323-3

3
Reserve for VCCSGT discharge

2 2

+5VALW +VCCSTG
+1.8VALW +1.8VS

1
R4624
@ R4625 200_0402_5%
R10188 1 2 0_5%_0603
100K_0402_5% @
@

2
Q4601 0.6A
0.1U_0402_10V7K

@3 1 LP2301ALT1G_SOT23-3

1
Q4607 D

https://vinafix.com
1
0.1U_0402_10V7K

VCCIO_EN# 2
2
C4609

1 G
R10189
G

C4610
2

0.1U_0402_10V7K

0.1U_0402_10V7K

1
10K_0402_5% Q4608 D @ S L2N7002KWT1G_SOT323-3
2

3
@ 2
2 13 VCCIO_EN
1 1
1

G
C4611

C4612

@
SUSP R4603 1 2 0_0402_5%
S L2N7002KWT1G_SOT323-3
@

3
@ 2 2
@
1

R4604 @ @
1
@ 470K_0402_5%
C4613
0.1U_0402_10V7K
2

2
@

3 3

+0.6VS +2.5V_DDR
For DisCharge
1

R4607 R4608
47_0603_5% 200_0402_5%
@ @
2

2
1

D Q4603 D Q4604
2 SUSP 2 SUSP
G G

S L2N7002KWT1G_SOT323-3 S L2N7002KWT1G_SOT323-3
3

@ @

4 4

08/29: Need double check enable signal and the resistance

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20

DC V TO VS INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 46 of 61
A B C D E
 5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN

V V
A2 A4 B5
3 +3V_PCH

V
PU301 PU904

V
B+
+3VALW
BATT BATT V 1
DPWROK_EC
V
MODE

V V V
B1
4
PCH_RSMRST#
EC 14
PM_DRAM_PWRGD
5 PBTN_OUT#

V
EC_ON PM_SLP_S3# PCH 15
PM_SLP_S4# H_CPUPWRGD CPU

V V
A3 B4 PM_SLP_S5#
PM_SLP_SUS# 6

V
CPU_PLTRST# 16
12
PCH_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF V
NOVO

NVDD_PWR_EN

https://vinafix.com
(DIS)
Vb
+VGA_CORE

V
11 VR_REDY SYSON 7 +1.35V
PU801
PU501

V
DGPU_PWROK
DGPU_PWR_EN
10 Va (DIS)

V
PU901 VR_ON +1.5VS_VGA

V
Q31
V

PU601

V
+CPU_CORE
+5VS

B B

V
Q32 +1.05VSP_VGA

V
SUSP#,SUSP 9 +3VS PU702

V
VGA

V
PU602
+1.5VS +3VS_VGA

V
Q27

V
PU502
+0.675V
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Power sequence block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GS44B/GS54B
Date: Wednesday, May 29, 2019 Sheet 47 of 61
5 4 3 2 1
 5 4 3 2 1

Hole
PCB Fedical Mark PAD MD Shielding
H2
HOLEA
D
FD4901 FD4902 FD4903 FD4904 FD4905 FD4906 D

SH1 SH2 SH3 SH4 SH5 SH6

1

SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64

SPRING_FINGER_6.2X1.64

1
PAD_C10P0D8P0

1
1

1
H3 H4 H5 H6 H7 H8
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
C
PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 C

H9 H10 Vinafix.com
HOLEA HOLEA

H17 H18
1

HOLEA HOLEA SODIMM Shielding

PAD_C7P0D4P0 PAD_C7P0D4P0
1

1
H11
HOLEA
H12
HOLEA
H13
HOLEA
PAD_O2P5X3P0D2P5X3P0N
https://vinafix.com
PAD_O2P5X3P0D2P5X3P0N SH10
SH11
SHIELDING_SUL-35A2M_9P2X3P3_1P
SHIELDING_SUL-35A2M_9P2X3P3_1P
SH12
SH13

SHIELDING_SUL-35A2M_9P2X3P3_1P
SH14
SHIELDING_SUL-35A2M_9P2X3P3_1P
SHIELDING_SUL-35A2M_9P2X3P3_1P
1

B B

PAD_C7P0D2P8 PAD_C7P0D2P8 PAD_C7P0D2P8

1
1

1
1

1
1

1
H14

1
HOLEA
1

PAD_C7P0D2P4

H15 H16
HOLEA HOLEA
1

A A
PAD_CT7P0B10P0D4P0 PAD_CT7P0B10P0D4P0

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS441/FS540
Date: Wednesday, May 29, 2019 Sheet 49 of 61
5 4 3 2 1
 5 4 3 2 1

V20B+
+5VS
Richtek
+5VALW/8A
LV5083AGQUF
Adaptor 65W
D D
+1.05VGS/2.1A

Converter +3VS

FOR SYSTEM +1.0VALW/6A

+3VALW/ 6A
EN PGOOD

+1.8VALW/1A

TI Richtek +1.35V/8A Silergy +2.5V/1A

BQ24780SRUYR LV5095B LV5028AGQV

Battery Charger Switch Mode SYS PMIC
EN
C C

Switch Mode FOR VRAM PGOOD

+1.2V/6A

UPI +0.6VS/2A

SMBus UP1666QQKF +VGA_CORE/30A

https://vinafix.com
EN Switch Mode
PGOOD
FOR GPU VDDC

Battery IA Core/42A
Richtek
polymer RT3602ACGQW VCCGT/18A

3S1P/2S2P Switch Mode VCCSA/4A

EN FOR CPU Core
PGOOD
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-Power Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
Date: Wednesday, May 29, 2019 Sheet 50 of 61
5 4 3 2 1
 5 4 3 2 1

PJ102 @ PJ101 @
JUMP_43X79 JUMP_43X79
1 2 1 2
1 2 1 2 VIN
3.25A HCB2012KF-121T50_0805
JDCIN1 PF5101 PL5101
1 ADPIN 1 2 APDIN_F 1 2
1 2
GND1 EMC@
3 7A_24VDC_F1206HI7000V024TM
GND2

1000P_0201_50V7-K
470P_0201_50V7-K
4
GND3 @

1000P_0201_50V7-K

470P_0201_50V7-K
5 HCB2012KF-121T50_0805
GND4

EMC@

EMC@
PC5101

PC5102
6 PL5102
GND5

2
EMC@

EMC@
PC5103

PC5104
D 7 1 2 D
GND6
EMC_NS@
HIGHS_PJSS0026-8B01H

1
ME@

change symbol to DC021508142 by amy 0704

+3VL

1
PR5101
1.5K_0402_1%

VCCRTC 2
1

PR5102
C C
45.3K_0402_1%
RTC_VCC
2

1
JRTC1
3 2 PR5103 1 1
2 1
PD5101 1K_0603_5% 3 2
GND1
2

BAT54CW_SOT323-3 4
PC5105 GND2
1U_0402_6.3V6K
1

https://vinafix.com
HIGHS_WS33020-S0351-HF
@ ME@
change symbol to SP021510283 by amy 0620

RTC_VCC 20MIL
+3VL 20MIL
VCCRTC 20MIL

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-DCIN / RTC charger

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
Date: Wednesday, May 29, 2019 Sheet 51 of 61
5 4 3 2 1
 5 4 3 2 1

SUYIN_125022HB008M202ZL VBAT EMC@

D JBATT1
10A HCB2012KF-121T50_0805
BATT+ D
1 PL5201
1 2 1 2
9 2 3 EC_SMCA PR5201 1 2 100_0402_1%
10 GND1
GND2
3
4
4 EC_SMDA 1 2
EC_SMB_CK1 44,53
EC_SMB_DA1 44,53
1 2 2S1P polymer battery
5 PR5202 100_0402_1%
5 6 PL5202
voltage level: +5.5V ~
6 7
7
HCB2012KF-121T50_0805 8.8 V

3
8 EMC@
8

1
PC5201 PC5202
ME@ 1000P_0201_50V7-K 0.01U_0201_25V6-K
EMC@ EMC@

2
PD5201
AZC199-02S.R7G_SOT23-3
EMC_NS@

1 PR5203
1 2
+3VALW
100K_0402_1%

PR5204
C 1 2 C
BATT_TEMP 44,53
10K_0402_5%
1
1

PD5202
AZ5215-01F_DFN1006P2E2
EMC_NS@
2
2

https://vinafix.com

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
Date: Wednesday, May 29, 2019 Sheet 52 of 61
5 4 3 2 1
 5 4 3 2 1

VIN
PQ5301 PQ5302
AONS32314_DFN8-5 AON7408L_DFN8-5 N2
N1 PR5301
1 1 PJ5301 @ 0.01_1206_1%
2 2 JUMP_43X118 V20B+
5 3 3 5 1 2 1 4
1 2
2 3
D D

220P_0402_50V7K

470P_0402_50V7K

680P_0402_50V7K
470P_0201_50V7-K

4700P_0402_50V7-K

6800P_0402_25V7-K
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.022U_0402_25V7K

0.01U_0201_25V6-K
4

EMC_NS@

EMC_NS@
PC5301
2 2

1
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
PC5303

PC5304

PC5305

PC5306

PC5307

PC5308

PC5309

PC5310
1

PC5302
PR5302

2
4.7_0603_5% 1 1

5
0.1U_0201_25V6-K

2
PQ5303
PC5311
AON6324_DFN8-5
1 2
PR5303 @
BQ24780_BATDRV 1 2 BQ24780_BATDRV_R 4

2
09/09 NC MEC part
PC5312 PC5313 0_0603_5%
0.1U_0201_25V6-K 0.1U_0201_25V6-K

3
2
1
2
PR5304
499K_0402_1% PC5314
0.01U_0201_25V6-K

1
VIN BATT+

2
BAT54CW_SOT323-3
PD5301
2

3
V20B+

4.02K_0603_1%
VIN

1
1

1
4.02K_0603_1%

10U_0805_25V6K

10U_0805_25V6K
0.1U_0201_25V6-K
ACN

EMC_NS@
ACP
PR5305

PR5306

1
PC5318

PC5315

PC5319
10_1206_5%
2
1

PR5308
BQ24780_VDD
2

2
2

5
C PR5307 0.47U_25V_K_X5R_0603 PU5301 C
7.15K_0402_1% 44.2K_0402_1%

ACN
ACP
PC5317
1 2 PC5316

1
PR5309 2 1 780_VCC 28 24 1 2

2
VCC REGN PQ5304
1 2 ACDET 6 2.2U_10V_K_X5R_0603 4
PC5320 ACDET PR5310 PC5321 AON7380_DFN8-5
0.01U_0402_25V7K 25 BST_CHG 1 2 2 1
BTST PR5311
2.2_0603_5% 0.047U_0603_16V7K PL5301 0.01_1206_1% 6A

3
2
1
3
CMSRC HIDRV
26 DH_CHG 2.2UH_PCMB063T-2R2MS_8A_20% BATT+
@ 1 2 CHG 1 4

5
PR53122 1 20K_0402_1% 4
ACDRV

1
@ 2 3
PR5313 2 1100K_0402_1% 27 LX_CHG PR5314

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
BQ24780_VDD PHASE
@ 2.2_0805_5%

https://vinafix.com

1
PR5315 1 2 0_0402_5% ACIN_R 5 PQ5305

PC5322

PC5323

PC5324

PC5325
44 ACIN ACOK EMC_NS@
@ 4

2
PR5316 1 2 0_0402_5% EC_SMB_DA1_R 11 AON7380_DFN8-5

2
44,52 EC_SMB_DA1 SDA 23 DL_CHG

470P_0201_25V7K
LODRV

1
@

2
PR5317 1 2 0_0402_5% EC_SMB_CK1_R 12 22 PC5327

PC5326

3
2
1
44,52 EC_SMB_CK1 SCL GND 1000P_0402_50V7K

2
@ BQ24780SRUYR_QFN28_4X4 EMC_NS@

1
PR5318 1 2 0_0402_5% ADP_I_R 7 29 @

0.1U_0201_25V6-K

0.1U_0201_25V6-K
44 ADP_I IADP PAD

2
IDCHG 8 18 BQ24780_BATDRV

PC5328

PC5329
IDCHG BATDRV
9 PR5319 10_0603_5%

1
44,58 PSYS PMON 17 2 1
BATSRC
20K_0402_1%
100P_0201_25V8J

100P_0201_25V8J

100P_0201_25V8J
2

PR5341 @ 20 SRP_R 2 1 SRP

0.1U_0201_25V6-K
SRP
2

1 2 0_0402_5% 10 PR5320 10_0603_5%

PR5321

PC5332

44,58 VR_HOT#
PC5330

PROCHOT#

2
PC5331

PC5333
1

13
1

CMPIN
@
1

1
BATPRES#
TB_STAT#
14
CMPOUT 19 SRN_R 2 1 SRN
B
ILIM 21 SRN PR5322 10_0603_5% B
ILIM
2

16

15
PR5323
0_0402_5% @
09/19 PR331 change from 147K to 133K
PR5324 PR5325
1

1 2 ILIM_R 1 2 TB_STAT#
+3VALW BATT_TEMP 44,52
30K_0402_1%
133K_0402_1% +5VS
EMC demand
0.01U_0201_25V6-K

1
2

PC5334

PR5326
100K_0402_1%
1

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
EMC_NS@

EMC_NS@

EMC_NS@
EMC_NS@

EMC_NS@

EMC_NS@
1

1
PC6166

PC6167

PC6168

PC6169

PC6170

PC6171
V20B+

2
ACDECT setting 17.2V
Charge current limit HW=7A
DC discharge limit =26A

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
Discharge current limit HW=9A during Turbo boost

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
1

1
PC6180

PC6181

PC6172

PC6173

PC6174

PC6175

PC6176

PC6177

PC6178

PC6179
2

2
A A

Vinafix.com
Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
Date: Wednesday, May 29, 2019 Sheet 53 of 61
5 4 3 2 1
 5 4 3 2 1

EC_ON pull high reserve at EC，

no need USM enable=1.57V USM 3VALW:
TDC=6A
ME require, so PC5500/PC5501 reverve +5VLP OCP=8A
for EE noise debug-sky 0814 OVP=120%
1
PJ5401
2 +3VALW_VIN Fsw=500KHz
V20B+ 1 2
5VALW:

0.1U_0402_25V6

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
JUMP_43X79
TDC=8A

EMC@
2 2

1
@

PC5401

PC5500

PC5501

25
D
100K_0402_1%
PR5401
PU5401 10_0603_5%
PR5403
0.1U_0603_25V7K
PC5405 OCP=10A D

VDDSW
2@

2
1 1 1 3 +3VALW_BS 1 2 1 2
11
VIN1
BOOT1
PL5401
OVP=120% PJ5403

@
PR5402
@
0_0402_5%
LX1_1
1
2
+3VALW_LX 1 2 Fsw=500KHz
+3VALW_P 1
1 2
2
+3VALW

150U_B2_6.3VM_R35M
PR5404 1 2EC_ON_R 1 2 +3VALW_EN +3VALW_EN 10 LX1_2 35 1.5UH_PCMB063T-1R5MS_10A_20%

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
0.1U_0402_25V6
44,55 EC_ON EN1 LX1_3 JUMP_43X79

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
@
1

1
6 +3VALW_P 1 1 1 1
0_0402_5% @

PC5404
1 1

PC6161

PC6162

PC6163

PC6164
1 2 +5VALW_EN +3VALW_PG 9 VOUT1 +

PC5408

PC5409
39 EC_ON_R 11 +3VALW_PG PGOOD1

PC6165
@ 2 2 2 2
PR5405 0_0402_5% PC5411 2 2 2
4
1 2 7 VBYP3 +3VALW
VCC1
+3VLP
+3VALW PJ5407 @
PJ5402 1U_0402_6.3V6K 5
100mA 2 1
1 2 +5VALW_VIN LDO3 2 1 +3VL
V20B+

10U_0805_25V6K

10U_0805_25V6K
1 2 PC5412 1 2 4.7U_0603_6.3V6K
10_0603_5% JUMP_43X39 @ @

PC5414

PC5415
1 1

0.1U_0402_25V6
JUMP_43X79

EMC@
PR5406

PC5413
@ 14 22 +5VALW_BS 1 2 PC5416 1 2 0.1U_0603_25V7K
VIN2 BOOT2

2
PL5402 PJ5913
2

2 2 23
100K_0402_5%

100K_0402_5%

LX2_1
2

24 +5VALW_LX 1 2 +5VALW_P 1 2
PR5407

@
LX2_2 36 1 2 +5VALW
PR5408

LX2_3

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
+5VALW_EN 15 1.5UH_PCMB063T-1R5MS_10A_20%

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
EN2 JUMP_43X79

LV5083AGQUF_UQFN36_5X4
19 +5VALW_P 1 1 1 1

0.1U_0402_25V6
1

VOUT2 1 1

@
@

PC5418

PC5419

PC5420

PC5421
1

PC5450

PC5451
1

PC5417
ALW_PWRGD 16
+3VALW_PG

ALW_PWRGD

11,55 ALW_PWRGD PGOOD2 2 2 2 2

2 2

2
21
PC5422 VBYP5 +5VALW
1 2 18
VCC2
+5VLP
C 20
100mA PC5423 1 2 4.7U_0603_6.3V6K C
1U_0402_6.3V6K LDO5
@ @
+3VALW

22UC_6.3VC_MC_X5RC_0603
33

1U_0402_6.3V6K
VINSW1
1 PJ5404

+3VALW_LX

+5VALW_LX
PC5424
@
29 +3VS_SW 1 2 +3VS

PC5425
VOUTSW1 1 2

2
2

1U_0402_6.3V6K
JUMP_43X79

1
31 3VS_SS 1 2

PC5499
SS1
@ @ @

1
PR5409 1 2 +3VS_EN 30 PC5426

2
44,46 SUSP# ENSW1 2200P_0402_25V7-K PR5410 PR5411
0_0402_5% 2.2_0805_5% 2.2_0805_5%
PJ5406
PC5427 2 1 1U_0402_6.3V6K

https://vinafix.com
EMC_NS@ EMC_NS@
34 28 +5VS_SW 1 2 +5VS

1+3VALW_SN 2

1+5VALW_SN 2
VINSW2 VOUTSW2 1 2
+5VALW
22UC_6.3VC_MC_X5RC_0603

@
1
1U_0402_6.3V6K

1U_0402_6.3V6K
1

1
26 5VS_SS 1 2 JUMP_43X79
PC5428

PC5430

PC5431
SS2
@ @ @

PGND_2

PGND_1

AGND_2

AGND_3

AGND_1
SUSP# PR5412 1 2 +5VS_EN 27 PC5429
2

2
2 ENSW2 2200P_0402_25V7-K
0_0402_5%
PC5432 2 1 1U_0402_6.3V6K PC5433 PC5434
1000P_0402_50V7K 1000P_0402_50V7K

13

12

17

32

2
@ @ EMC_NS@ EMC_NS@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR_3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
Date: Wednesday, May 29, 2019 Sheet 54 of 61
5 4 3 2 1
 5 4 3 2 1

D D
@
PR521 1 2 0_0402_5%
EC_ON 44,54

PMIC_VCC 1 2 0_0402_5%
PR522 @ ALW_PWRGD 11,54
+5VALW
+5VLP PR502 @
1 2
10_0603_5%
@ PR520
VDDQ_EN

PMIC_EN
PR501 1 2 0_0402_5% 1 2
44 SYSON 10_0603_5%
@ PC500
PR503 1 2 0_0402_5% VTT_EN 1 2
5 CPU_DRAMPG_CNTL PR505
@ VDDQ_P 1 2 2.2U_0603_6.3V6K
PR507 1 2 0_0402_5% +1.8VALW_L_EN

VSYS_PMIC
10_0402_5%

1
@
1 2 0_0402_5% +1.05VALW_EN PC502
PR506 +3VALW
44 PCH_PWR_EN 0.1U_0201_25V6-K

2
@
PR508 1 2 0_0402_5% +2.5V_DDR_EN
44 EC_VPP_PWREN

28

27

41
PU500

100K_0402_5%
VSYS

VCC

PMIC_EN

GND
0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
@

1
+2.5V_DDR_EN 29 25 PMIC_SMB_DAT1 PR510 1 2 0_0402_5%

PC504

PC506

PC505

PC503

PC508

PR513
R_0402
EN_LDO1 SDA EC_SMB_DA3 44
@
+1.8VALW_L_EN 1 26 PMIC_SMB_CLK1 PR511 1 2 0_0402_5%
EC_SMB_CK3 44

1
EN_LDO2 SCL
+1.05VALW_EN 11 24 PMIC_ALERT# PR512 2 1 0_0402_5%
@ @ @ @ @ @ H_PROCHOT# 4,44

2
EN_V1P0A OT
+1.0VGS_B_EN 16 22 +1.05VALW_PG 1 PAD @ PTC501
EN_V1P8A PG_V1P0A
C VDDQ_PGOOD 44 C
VDDQ_EN 31 21 +1.0VGS_B_PG 1 PAD @ PTC502
EN_VDDQ PG_V1P8A
VTT_EN VDDQ_PGOOD

22UC_6.3VC_MC_X5RC_0603
@ 36 23
PR525 1 2 0_0402_5% +1.0VGS_B_EN EN_VTT PG_VDDQ PL500
23 PXE_VDD_EN_R PJ504
+5VALW PJ501 LX_1P05
1UH_PCMB063T-1R0MS_12A_20%
+1.05VALW_FB
12 1 2 1 2
6A PCH and to N16 GPU PMIC load switch

0.1U_0402_25V6
1 2 +1.05VALW_B_VIN 7 LX_V1P0A1 13 1 2
+1.0VALW

UMA@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1M_0402_5%
1 2 VIN_V1P0A1 LX_V1P0A2

1
8 14 if need to change to R33 choke

PC537
1 VIN_V1P0A2 LX_V1P0A3 1 1 1 1 1 1 JUMP_43X118

1
@
15

PR519

PC509

PC511

PC512

PC513

PC514

PC515

PC516
JUMP_43X118 LX_V1P0A4
PC510 @

2
@ 10 +1.05VALW_FB
0.1u_0201_10V6K

2
2 VO_V1P0A 2 2 2 2 2 2
PJ509 EMC_NS@

2
+1.0VGS_B_VIN PL502 PJ505
1 2 17 @ @
+5VALW 1 2 19 LX_V1P8A1 18 LX_1P0 1 2 +1.0VGS_FB 1 2
1 VIN_V1P8A LX_V1P8A2 1 2 +1.0VGS N17 GPU/ setting to 1.0V, 2.1A

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PC534 1UH_PH041H-1R0MS_3.8A_20%
09/08 reserve one pull down JUMP_43X79 22UC_6.3VC_MC_X5RC_0603 20 +1.0VGS_FB
1 1
@ OPT@
VO_V1P8A OPT@ JUMP_43X79
N16 GPU/ setting to 1.05V, 2.1A

PC535

PC536
2 @
PC529 33 UG_VDDQ
+1.2V_P UGATE_VDDQ PC518 2 2
1 210U_0603_10V6K 38 PR1031 @
VIN_VTT 32 BST_VDDQ 1 2 2 1
BS_VDDQ

OPT@

OPT@
PJ508 @ 0.1U_50V_M_X7R_0603
2 1 39 0_0603_5%

LX_1P05
+0.6VS 2 1 VTT

LX_1P0
34 LX_VDDQ
1 LX_VDDQ
PC519
1A JUMP_43X39 40
22UC_6.3VC_MC_X5RC_0603
VSNS_VTT LGATE_VDDQ
35 LG_VDDQ

1
PR515 @ 2 37 +1.2V_P
1 2 30 VSNS_VDDQ PR1029 PR1030
33K_0402_1% CS_VDDQ 4.7_0603_5% 4.7_0603_5%

PJ502 PJ503
1A EMC_NS@ EMC_OPTNS@ 14" N17S-G1 1.8VGS 0.3A
@ @

2
2 1 +2.5V_DDR_VIN 5 6 +2.5V_P 2 1
+3VALW 2 1
PC521
VIN_LDO1 LDO1 2 1 +2.5V_DDR 15" N17P-G0 1.8VGS 1.6A

1
1 2
JUMP_43X39 1 2 PC520 JUMP_43X39 PC1109 PC1110
B B
1200P_0402_50V7-K 1200P_0402_50V7-K
1A

2
22UC_6.3VC_MC_X5RC_0603 PJ511
10U_0603_10V6K @ EMC_NS@ EMC_OPTNS@
3 +1.8VALW_L_P 2 1
4 LDO2 2 1 +1.8VALW
VIN_LDO2 2

22UC_6.3VC_MC_X5RC_0603
FB_LDO2 JUMP_43X39

2
110K_0402_1%
1

PR516

PC522
PJ510 @ LV5075BGQV_VQFN40_5X5
2 1 +1.8VALW_L_VIN V20B+

+1.8VALW_L_FB
+3VALW 2 1 2

1
JUMP_43X39 1
PC523 PJ507
VDDQ_P 2 1

https://vinafix.com
10U_0603_10V6K 2 1
2

0.1U_0201_25V6-K
5
JUMP_43X118

10U_0805_25V6K

10U_0805_25V6K
PC524
@

1
PC525

PC526
2
PQ500

2
UG_VDDQ

EMC_NS@
PR517 4
75K_0402_1% AON7408L_DFN8-5

+1.2V

1
6A

3
2
1
0.47UH_PCMB053T-R47MS_13A_20%
PJ506
PL501
LX_VDDQ 1 2 +1.2V_P 1 2
1 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
JUMP_43X118

2
1 1 1 1 1
PQ501 4.7_0603_5% @

PC527

PC528

PC530

PC517
PC1113
PR518
AON7380_DFN8-5
2 2 2 2 2
EMC_NS@

1
LG_VDDQ 4

1
A A
PC533
1200P_0402_50V7-K

3
2
1

2
EMC_NS@
@

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR PMIC-DDR4/1.0ALW/1.8ALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
Date: Wednesday, May 29, 2019 Sheet 55 of 61
5 4 3 2 1
 A B C D

V20B+
PJ3601@
1.5A PC3603
2 1
2 1 0.1U_50V_M_X7R_0603

10U_0805_25V6K

10U_0805_25V6K
PR3601
+1.35V_BST 1 2+1.35V_BST_R 1 2

1
JUMP_43X79

PC3601

PC3602
10_0603_5%
OPT@ OPT@ 08/09 PL3601 from 053Tto 063T- SKY
OPT@ +1.35VGS

2
PD3601
PU3601

18
1 2

5
PL3601
0.68UH_PCMB063T-R68MS_16A_20% PJ3602 8A

VBOOT
AGND
RB751V-40_SOD323-2 +1.35V_VIN 12 3 +1.35V_LX 1 2 +1.35V_P 2 1
OPTNS@ OPT@ OPT@ VIN4 SW_1 2 1

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
OPT@ JUMP_43X118
1 2 +1.35V_EN 16 4
23 FBVDDQ_PWR_EN EN4 SW_2 1 1 1 1 1 1 @

PC3611

PC3606

PC3607

PC3612

PC3608

PC3613
PR706

1
1
100K_0402_5% 1 2 PC3604 PC3605 OPTNS@ 1

OPT@ 0.022U_0402_25V7K 15 +1.35V_FB 1 2 PR3603

25 FB 2.2_0603_5% 2 2 2 2 2 2
OPT@ NC_3

1
0.1U_0402_25V6 EMC_OPTNS@

OPTNS@
OPT@

OPT@
23 PR3606

2
NC_2

OPTNS@
22

+1.35V_SN
1K_0402_1%
NC_1

OPT@

OPT@
OPT@

1
6
+5VALW

2
PGND_1

1
7 PR3607
2 1 24 PGND_2 PC3619 +1.35V_FB_1 42.2K_0402_1%
GC6@ VCC_SW 8 1000P_0402_50V7K
Vout=1.35V±5%
OPT@

2
PGND_3

1
PC3616 OPT@ 1U_0402_6.3V6K EMC_OPTNS@ PC3620 Vset=1.36V±2%
9 560P_0402_50V7-K 09/08 change PR3607 from 41.2K to 21K
1.8VGS_PWR_EN 1 PR3610 2 MAIN_PWR_EN 19 PGND_4
OPT@ 09/19 change PR3609 from 21K to 42.2K
OCP>12A

2
23,26 1.8VGS_PWR_EN EN2 10
2.2K_0402_5% +3.3V_1.8V_AON PGND_5
PR3605 0_0402_5% Vref=0.6V
1 2 1 2 VIN1_3.3V_1.8V 21 11 +1.35V_FB
@ VIN2 PGND_6 +3V_1.8VGS OVP=(1.25~1.35)*Vref

1
PC3614 OPT@ 0.047U_0402_25V7K
1 2 20
PC3615 1U_0402_6.3V6K VOUT2 PR3609
UVP=(0.7~0.8)*Vref
PXS_PWR_EN_R

1U_0402_6.3V6K
OPTNS@ 28 31.6K_0402_1%
23 PXS_PWR_EN_R EN3 OPT@
Fsw=700Khz

2
1

OPT@
PC3618
1 2
1 26 +3.3V_1.8V_AON
LSW1 RDS=36~50mohm,Io=0.5A
PC3621 VIN3_1 VOUT3_1
OPT@ 0.1U_0402_25V6 03/11 change PR3609 from 32.4K to 31.6K
LSW2 RDS=18~25mohm,Io=1A

2
+3.3V_1.8V_AON_IN 2 27
VIN3_2 VOUT3_2
LSW3 RDS=5~7mohm,Io=3.5A

1
29 PC3623
VIN3_3
1U_0402_6.3V6K

TH_ALT

PGOOD
OPT@

2
VCC
+3.3V_1.8V_AON_IN

+3VS

14

17

13
PR3613

2
2 1
PC3622
0_0402_5% +3V_1.8VGS 1U_0402_6.3V6K

+1.35V_VCC
1
+3.3V_1.8V_AON

1
+1.8V_VGA
OPTN16@ PR3615 OPTNS@ PR3611 PR3612
2 2

PR3614 2 1 100K_0402_1% 100K_0402_1%

2 1 OPTNS@ OPTNS@
0_0402_5%

2
0_0402_5%
NGC6@
OPTN17@

1
09/08 change RV1394 to PR3615 PC3629
1U_0402_6.3V6K

2
OPT@
09/08 change RV1395 to PR3613
09/08 change RV1396 to PR3614

https://vinafix.com
+1.8VALW +1.8V_VGA

PJ9
2 1
2 1

JUMP_43X39
@
+1.8VS

PJ10
2 1
2 1

JUMP_43X39
@

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-VGA-PMIC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
Date: Wednesday, May 29, 2019 Sheet 56 of 61
A B C D
 5 4 3 2 1

PWM-VID Specification
N17 Config N16 Config B
RT8816 PSI UP1666 PSI Phase Configuration
Vmin(V) 0.3 0.6
1.6V~5.5V 1.6~5.5V 2Phase CCM
Vmax(V) 1.3 1.2
1.08~1.35V 1~1.4V 2Phase DEM
Vboot(V) 0.8 0.9
0.7~0.88V 0.4V~0.8V 1Phase CCM
Vstep(mV) 6.25 6.25
0~0.4V 0~0.2V 1Phase DEM
N(level) 160 96
Fpwm(KHz) 675 1.125 V20B+
D Tdmin(nS) 9.26 9.26 +VGA_CORE_VIN D
PJ5701
T(uS) <100 <100 1 2
1 2
+5VALW

EMC_OPTNS@
JUMP_43X79

0.1U_0201_25V6-K

10U_0805_25V6K

10U_0805_25V6K
@

1
PC801

1
PC802

PC803
1

2
5
PR801
PU801
2_0603_5% PQ801
OPT@ AON6380_DFN8-5
OPT@ OPT@

2
NVVDD_PVCC 18
PVCC NVVDD_HG1
OPT@
2 4
UGATE1

1
PC804 PR805
+3.3V_1.8V_AON PC805
1U_0402_6.3V6K 2.2_0603_5%
1 NVVDD_BS11 2 1 2
OPT@

3
2
1
BOOT1
1

21 OPT@
PR806 GND 0.22U_0603_25V7K
5.1K_0402_1% OPT@
PL801 +VGA_CORE
OPT@ PHASE1
20 NVVDD_PH1 1 2 30A

2200P_0402_50V7K 1/8W_1_5%_0805
2

1
@ 0.22UH_PCMB063T-R22MS_23A_20%

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PR802 1 2 0_0402_5% NVVDD_PSI_R 4

PR803

EMC_OPT@

330U_D2_2V_Y

330U_D2_2V_Y
26 PSI_VGA PSI OPT@ 1 1
1 1 1 1 1 1

PC806

PC807

PC809

PC810

PC811

PC812

PC808

PC813
PR804 OPT@ PR807 OPTNS@ PQ802 + +
1 2 1 2 AON6324_DFN8-5
+3VS

2
1K_0402_1% 5.1K_0402_1% 19 NVVDD_LG1 4
LGATE1 OPT@ 2 2 2 2 2 2 2 2
13 1
8,23 DGPU_PWROK PGOOD

OPT@

OPT@
PC814
PR808

EMC_OPT@
OPT@ NVVDD_EN_R
1 2 3 OPT@ OPT@
23 NVVDD_EN

3
2
1
EN 2

OPTNS@

OPTNS@
OPT@

OPT@
1/16W_37.4K_1%_0402 V20B+
1

C PC815 C
OPT@ 0.1U_0402_10V7K +VGA_CORE_VIN PJ5702
1
PD801 2 OPT@
2

1 2
RB751V-40_SOD323-2 1 2

EMC_OPTNS@

10U_0805_25V6K

10U_0805_25V6K
0.1U_0201_25V6-K
PR809 1 2 0_0402_5% NVVDD_VID_R 5 14 NVVDD_HG2 JUMP_43X79
26 NVVDD_PWM_VID VID UGATE2

1
PC830

PC833

PC831
@
1

@ PR810 PQ803
PC817
PC816 2.2_0603_5%

2
0.1U_0402_10V7K 15 NVVDD_BS21 2 1 2 4 AON6380_DFN8-5
2

BOOT2
OPTNS@ OPT@
OPT@ 0.22U_0603_25V7K +VGA_CORE
OPT@ OPT@
OPT@ PL802

3
2
1
09/08 change 1U to 0.1uh
16 NVVDD_PH2 1 2
2 1 NVVDD_VREF 8 PHASE2

2200P_0402_50V7K 1/8W_1_5%_0805

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
VREF

1
0.22UH_PCMB063T-R22MS_23A_20%

PR811
PC818

EMC_OPT@

330U_D2_2V_Y
OPT@ 1 1 1
1

PC821

PC820
0.1U_0402_25V7-K

OPTNS@

PC819
PR812 +
OPT@ 20.5K_0402_1%

2
2 2
OPTNS@ NVVDD_LG2 2
17 PQ804

https://vinafix.com
1
2

LGATE2 AON6324_DFN8-5

OPT@

OPT@
4

PC824

EMC_OPT@
OPT@

1
NVVDD_REFIN 7
REFIN PR5921 2 PR814
2

30K_0402_5% 100_0402_1%
1

PR833 UPI_OPT@ 1 2

3
2
1
PR813

2
82.5K_0402_1% OPT@
16.5K_0402_1%
PR816
UPI_OPT@
OPTNS@ PR815
1

6.19K_0402_1%
2

1 2 1 2 NVVDD_VIDBUF 6 @
1

PC825 REFADJ 10 NVVDD_FBRTN PR817 1 2 0_0402_5%

OPTNS@ FBRTN NVVDD_VSS_SENSE 22
0.01U_0402_25V7K 4.32K_0402_1%
1

B B
OPTNS@ OPTNS@
2

1
PR818 PC826 PC827 VR Remote Sense - Tie to GPU sense points
309_0402_1% 4700P_0402_25V7-K 11 NVVDD_FB 1000P_0402_25V7-K
FB
OPTNS@ OPTNS@ OPTNS@
2

2
PR819
2

Vinafix.com
2 1NVVDD_FS 9 12 NVVDD_SS PR824 1 2 0_0402_5%
FS/OC COMP NVVDD_VCC_SENSE 22
V20B+ 475K_0402_1%
PR825
PR820 RT_OPT@ 100_0402_1%
2 1 1 2 +VGA_CORE

2.2_0603_5% OPT@
RT_OPT@
UP1666QQKF_WQFN20_3X3
PR821 set OC and PC837 set external SS for RT8816
1

UPI_OPTNS@

PC849 OPTNS@
1000P_0402_25V7-K
1

RT_OPTNS@

RT_OPT@

1U_0402_25V6-K PR832
1000P_0402_25V7-K
2

1
PC836

PR834 51K_0402_1%
110K_0402_1%

RT_OPT@
2

PC837

PR821

100K_0402_1% UPI_OPT@
UPI_OPT@
2

PR827
Vboot=0.8V
2

@
2
2

1 2 NVVDD_FBRTN PC834
1000P_0402_25V7-K
Ripple=±20mV
0_0402_5%
UPI_OPT@ TDC=28.5A Iccmax=55A OCP>75A
PR820,PR819,PC849 set TON for RT8816
1
2

PR826
TDC=30A Iccmax=60.1A OCP>80A
0_0402_5%
RT_OPT@ PR833,PR834 set FS/OC for UP1666 Vref=2V
PR833=82.5,PR834=100k, OCP=85A change by 0705-sky
1

FUVP:Vfb=0.2V
SUVP:Vcomp=3V
PR832,PC834,PR836 set COMP for UP1666 OVP:Vfb=2V
Fsw=320KHz
A
PR816,PR812,PR815,PR813,PR818,PC826 BOM structure control for N16 or N17 A

Component Value N17 N16

R1(KΩ) PR816 6.19 20
R2(KΩ) PR812 20.5 20
R3(KΩ) PR815 4.32 2 UPI_OPT@ : for UP1666 Security Classification LC Future Center Secret Data Title
R4(KΩ) PR813 16.5 18
RT_OPT@ : for RT8816A Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-VGA_CORE
R5(KΩ) PR818 0.309 0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
C(nF) PC826 4.7 2.7 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
Date: Wednesday, May 29, 2019 Sheet 57 of 60
5 4 3 2 1
 5 4 3 2 1

+VCCST_CPU
+5VALW +5VALW V20B+
+VCCST_CPU

8.2_0603_5%
1

2
PR5802
PC5801 2.2_0603_5%
1U_0402_6.3V6K PR5801

1
75_0402_1%

100_0402_1%
45.3_0402_1%

2.2_0402_1%
PR5803

PR5804

PR5805

PR5806
1

1
2.2U_0603_10V7K

4.7U_0603_6.3V6K
@ +VCCST_CPU 2 2

PC5803
D D

VR_PVCC
2

1K_0402_1%
PC5802
@

1
44,53 PSYS

PR5808
VR_VCC
PR5809 PR5807
PU5801 bom need change to RT3602AH( SA00009B600 )--sky-0704

VR_VRMP
1
1 1

1K_0402_1%
10_0402_1% PC5804 54.9_0402_1% @
VR_SVID_DAT_1

PR5810
2 1 0.1U_0402_25V7-K

2
VR_SVID_DAT 12
PR5811 @

2
0_0402_5% @
VR_SVID_ALRT#_1 1 2

2
VR_SVID_ALRT# 12
PR5812 @ RT3602AHGQW_WQFN52_6X6

18

13

12
49.9_0402_1% PU5801
VR_SVID_CLK_1 2 1 20K_0402_1%

PVCC

VCC

VIN
VR_SVID_CLK 12 1 PR5813 2 50 42
PSYS VR_READY CPU_VR_READY 44
VREF 1 2 VR_EN 41
44 EC_VR_ON EN 35
0_0402_5% @ VR_HOT VR_HOT# 44,53
PR5814 VR_SVID_DAT_1 36
VDIO 26 GT_BST 1 2 1 2 499_0402_1%
VR_SVID_ALRT#_1 BOOT_AUXI
3.83K_0402_1%

19.1K_0402_1%

37 2.2_0603_5% PR5818
ALERT
1

6.81K_0402_1%

PR5815 PC5805 1 2
VR_SVID_CLK_1 GT_PH_R 59
PR5816

PR5817

PR5821

38 25 0.22U_0603_16V7K
VCLK UGATE_AUXI GT_UG 59
649_0402_1% 2.2K_0402_3%_TSM0B222H3953RE
PR5819 PH5801
24 1 2 1 2
2

PHASE_AUXI GT_PH 59 +VCC_GT_R 59

SET1 2
SET1 23 1 2
LGATE_AUXI GT_LG 59
1.21K_0402_1%

2.2K_0402_1%
1

SET2 5 PR5822
SET2
PR5820

1/16W_69.8_1%_0402 4.12K_0402_1%
1

33 GT_CSP 1 2
ISENP_AUXI
PR5823

SET3 6 PC5806 0.47U_0402_25V6K

SET3
3.16K_0402_1%

32
2

ISENN_AUXI
1

1
VREF
PR5824

0.22U_0603_16V7K
2
1

1/16W_15_+-1%_0402

PC5807
SA_BST
PR5825

14 1 2 0.1U_0402_25V6

2
BOOT_SA
1

PC5808
46 PR5826 2.2_0603_5%
2

VREF06/PSET
1
PR5827

0.47U_0402_25V6K 3.9_0402_1%

422_0402_1%

2
PR5828

1/16W_37.4K_1%_0402 15 1 PR5829 2
2

UGATE_SA SA_UG 59 SA_PH_R 59

1

GT_Imon
63.4_0402_1%

1 2 34
IMON_AUXI
PR5830

C PR5832 PR5831 C
2

1
1 2 16 PH5802
10_0402_5% 2.2K_0402_1%
2

PHASE_SA SA_PH 59 1 PR5833 2 1 2

31.6K_0402_1%
PR5835 +VCCSA_R 59
2 PR5834 PH5803
2

2 Vcore_Imon
PC5809

1 2 1 2 1 1 17
IMON_MAIN LGATE_SA SA_LG 59
1/16W_48.7K_1%_0402 3.92K_0402_1% 100_0402_1%
1
100K_0402_1%_NCP15WF104F03RC
1 2 SA_Imon 43
1 PR5836 2 sky 0908: change PH5802 from
PR5837
57.6K_0402_1%
IMON_SA
ISENP_SA
44 SA_CSP 2
PC5810
1
0.47U_0402_25V6K
SL200003K00 to SD000004O8J
45
ISENN_SA

1
330P_0402_50V7K 82P_0402_50V9-G 51 0.1U_0402_25V6
12,58 VCORE_VCC_SEN VSEN_MAIN

0.22U_0603_16V7K
PC5812 PC5813 2.2_0603_5% PC5811
1 2 1 2 22 Vcore_BST1 1 PR5839 2

2
BOOT_MAIN

PC5815
https://vinafix.com
1 2 1 2 Vcore_COMP 4
12,58 VCORE_VCC_SEN COMP_MAIN

2
PR5840 PR5841 21
UGATE_MAIN Vcore_UG1 59
2

10K_0402_1% 52.3K_0402_1% 1/16W_348_1%_0402

PC5814@ 2 1 2 1 Vcore_FB 3

1
FB_MAIN 20 PR5843
1000P_0402_50V7K @ PC5816 PR5842 @
1

PHASE_MAIN Vcore_PH1 58,59 1 2

470P_0402_50V7K 16.9K_0402_1%
52 Vcore_PH1_R 59
12 VCORE_VSS_SEN RGND_MAIN 19
LGATE_MAIN Vcore_LG1 59 1 2
+CPU_CORE1 59
PC5817 0.47U_0402_25V6K
270P_50V_K_X7R_0402 @
PC5818 68P_0402_50V8J 31 10 1 2
12,58 VCCGT_VCC_SEN VSEN_AUXI ISEN1P_MAIN
PC5819 PR5845
1 2 1 2 7 180K_0402_1%
ISEN1N_MAIN

1
1 2 1 2 GT_COMP 30 0.1U_0402_25V6 1/16W_348_1%_0402
12,58 VCCGT_VCC_SEN COMP_AUXI U42@
10K_0402_1% PR5848 PC5820 1 PR5849 2
Vcore_PH2_R 59
2

PC5821 PR5847 39

2
2 1 2 1 1/16W_23.2K_1%_0402 GT_FB 28 DRVEN DRVEN 59
1000P_0402_50V7K
@ FB_AUXI U42@
@ PC5822 PR5850 @ 40 1 2 PR5920 1 2 0_0402_5%
1

PWM_MAIN Vcore_PWM 59 +CPU_CORE2 59

470P_0402_50V7K 16.9K_0402_1% PC5823 0.47U_0402_25V6K U42@
29
12 VCCGT_VSS_SEN RGND_AUXI 9 1 2
PC5824 68P_0402_50V8J
220P_0402_50V7K PC5825 ISEN2P_MAIN PR5851 0_0402_5%
U22@
1 2 1 2 8
B ISEN2N_MAIN B
1 2

1
1 2 1 2 SA_COMP 47 +5VALW VREF 0.1U_0402_25V6
13 VCCSA_VCC_SEN COMP_SA 10K_0402_1%
10K_0402_1% U22@ 110K_0402_1% PC5826
11 TSEN_CORE PR5919 2 PR5856 1 2 1 2 1
PR5854 PR5855 U42@

2
TSEN_MAIN
2

PC5827 2 1 2 1 1/16W 48.7K +-1% 0402 SA_FB 49 15.8K_0402_1%

1000P_0402_50V7K PC5828 @ PR5859 @ FB_SA PR5857 PR5858
@ VREF
470P_0402_50V7K 16.9K_0402_1% 49.9_0402_1%
1

48 PR5861 PR5862
110K_0402_1% PH5804
13 VCCSA_VSS_SEN RGND_SA 27 TSEN_GT 2 PR5860 1 2 1 2 1 2 1
TSEN_AUXI 15.4K_0402_1%
GND

1/16W_464_1%_0402@ 100K_0402_1%_NCP15WF104F03RC

2
PH5805 @
2 1
53

PR5864
100K_0402_1%_NCP15WF104F03RC 16.9K_0402_1%

1
Place close to MOSFET

1
PR5869
16.9K_0402_1%
PR5861 PR5862 PR5869
@

2
U42 464 15.4K 16.9K

301 21K 13.7K

U22

2 1 1M_0402_1% 1 2 PR5917 Vcore_Imon

58,59 Vcore_PH1
PC5829 10P_0402_50V8J

2 1 1M_0402_1% 1 2 PR5918
59 Vcore_PH2
PC5830 10P_0402_50V8J
U42@ U42@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-CPU-CORE-1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
A2 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
Date: Wednesday, May 29, 2019 Sheet 58 of 61
5 4 3 2 1
 5 4 3 2 1

PJ5901
V20B+
GT_VIN 1 2
1 2

10U_0805_25V6K

10U_0805_25V6K
JUMP_43X79

0.1U_0201_25V6-K
1 1

1
@ Vboot=0V Loadline=3.1mΩ

EMC@
PC5901

PC5902

PC5903
PQ5901 Ripple=+30mV/-10mV(0A~0.5A)

2
2 2
AON6380_DFN8-5
+VCC_GT Ripple=±10mV(0.5A~TDC)
4
58 GT_UG Ripple=±15mV(TDC~Iccmax)
0.15UH_PCME063T-R15MS0R907_37A_20% TDC=18A Iccmax=31A OCP=37A
PL5901
GT_PH 1 2
OVP=VID+370mV~VID+430mV

3
2
1
58 GT_PH
D
18A Max Overshoot:70mv/10us D

2200P_0402_50V7K 1/8W_1_5%_0805
1
PQ5908 @ @ UVP=VID-370mV~VID-225mV

2
EMC@
PR5901
AON6324_DFN8-5
PJ5902 PJ5912 Fsw=550Khz
JUMPER JUMPER

1
4

2
58 GT_LG
1 +VCC_GT_R 58

EMC@
PC5926
3
2
1
2
GT_PH_R 58

V20B+

33U_D2_25VM_R40M
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
5
1

0.1U_0201_25V6-K
PQ5902 1 1 1 1

PC5988
AON6380_DFN8-5 +

PC5927

PC5929

PC5930

PC5978

PC5979
EMC@

2
4 2 2 2 2 2
58 Vcore_UG1
U22 :21A
@ U42: 48A
+CPU_CORE

3
2
1
0.15UH_PCME063T-R15MS0R907_37A_20%
PL5902
1 2
58 Vcore_PH1
Vboot=0V Loadline=1.8mΩ

2200P_0402_50V7K 1/8W_1_5%_0805
1
PQ5903 @ @ Ripple=+30mV/-10mV(0A~0.5A)

2
EMC@
PR5902
AON6324_DFN8-5
C PJ5905 PJ5906 Ripple=±10mV(0.5A~TDC) C
JUMPER JUMPER

1
4
Ripple=±15mV(TDC~Iccmax)

2
58 Vcore_LG1
+CPU_CORE1 58
1 TDC=21A/48A Iccmax=32A/70A

EMC@
PC5956
OCP=37A / 74A

3
2
1
2 Vcore_PH1_R 58
Max Overshoot:70mv/10us
OVP=VID+370mV~VID+430mV
UVP=VID-370mV~VID-225mV
V20B+ Fsw=550Khz

10U_0805_25V6K

10U_0805_25V6K
+5VALW

https://vinafix.com
0.22U_0603_16V7K

0.1U_0201_25V6-K
PC5957 1 1

1
1 2 1 2

PC5958

PC5959

PC5960
PR5903
2.2_0603_5% U42@ PQ5904 U42@

2
2

2 2
U42@ AON6380_DFN8-5
PR5904
U42@ 2.2_0603_5% U42@
PU5901 4 @ @
4 Vcore_BST2
+CPU_CORE
1

Vcore_VCC 8 BOOT
VCC 3 Vcore_UG2 0.15UH_PCME063T-R15MS0R907_37A_20%
2 Vcore_PWM_D UGATE
1U_0402_10V6K

PR5905 1 @ 5 PL5903
3
2
1
58 Vcore_PWM 0_0402_5% PWM 2 Vcore_PH2 1 2
PHASE
1

Vcore_EN
PC5961

2200P_0402_50V7K 1/8W_1_5%_0805
1 2 1
58 DRVEN EN
5

1
10_0402_5% 7 Vcore_LG2 @ @
U42@ LGATE U42@

2
U42@
PR5907
U42@ PR5906 6 PQ5905
2

GND1 9 Vcore_PH2 58
AON6324_DFN8-5 PJ5907 PJ5908
GND2
JUMPER JUMPER

1
RT9610CGQW_WDFN8_2X2 U42@

2
4
U42@ 1 +CPU_CORE2 58

U42@
PC5964
3
2
1

B 2 B
Vcore_PH2_R 58

ME require, so PC5500/PC5501 reverve

for EE noise debug-sky 0814 PJ5903
SA_VIN 1
10U_0805_25V6K

2
1 2 V20B+
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
5

@
0.1U_0201_25V6-K

2 2 1 Vboot=0V Loadline=10.3Ω
1

JUMP_43X79
PC5976

PC5977
EMC@
PC5965

PC5967

@ Ripple=+30mV/-10mV(0A~0.5A)
2

PQ5906 1 1 2
4
Ripple=±10mV(0.5A~TDC)
AON7408L_DFN8-5 Ripple=±15mV(TDC~Iccmax)
TDC=4A Iccmax=4.5A OCP=7A
+VCCSA
3
2
1

Max Overshoot:70mv/10us
58 SA_UG
0.47UH_PCMB042T-R47MS_7A_20% OVP=VID+370mV~VID+430mV
1 2
58 SA_PH
PL5904 UVP=VID-370mV~VID-225mV
2200P_0402_50V7K 1/8W_1_5%_0805

58 SA_LG
5

@ @ Fsw=550Khz
4A
2

2
EMC_NS@
PR5908

PQ5907
AON7380_DFN8-5 PJ5910 PJ5911
JUMPER JUMPER
1

1
2

4
+VCCSA_R 58
1
A A
EMC_NS@
PC5975
3
2
1

2 SA_PH_R 58

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/10 Deciphered Date 2018/07/10 PWR-CPU-CORE-2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
A2 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 140S-WHL
Date: Wednesday, May 29, 2019 Sheet 59 of 61
5 4 3 2 1
 A
B
C
D

+VCC_GT

+VCC_GT

2
1
1
+

2
1
2 3
PC6125

+VCCSA
22UC_6.3VC_MC_X5RC_0603 PC6110 PC6077

@
10U_0603_6.3V6M 220U_D2_2VM_R6M
+CPU_CORE

2
1
2
1
2
1
2
1
+

PC6126 PC6111 PC6032

N3T@
22UC_6.3VC_MC_X5RC_0603 10U_0603_6.3V6M 2 1 10U_0603_6.3V6M PC6001

2
1
+
330U_D2_2V_Y

5
5

2
1
2
1
PC6078 PC6055

2
1
PC6112 330U_D2_2V_Y 1U_0402_6.3V6K PC6033

+CPU_CORE
PC6127 10U_0603_6.3V6M 10U_0603_6.3V6M
2
1
+

22UC_6.3VC_MC_X5RC_0603

2
1
2
1
U42@ PC6002

+CPU_CORE

2
1

@
PC6113 PC6034 330U_D2_2V_Y
PC6128 10U_0603_6.3V6M 10U_0603_6.3V6M
22UC_6.3VC_MC_X5RC_0603

@
@

2
1
2
1
1
+

2
1
2 3

PC6114 PC6035
PC6129 10U_0603_6.3V6M 10U_0603_6.3V6M PC6003
22UC_6.3VC_MC_X5RC_0603 220U_D2_2VM_R6M

2
1
PC6036

2
1
10U_0603_6.3V6M
PC6079 2 1
22UC_6.3VC_MC_X5RC_0603

N3T@

2
1
PC6058

@
2
1
2
1
PC6115 1U_0402_6.3V6K
PC6130 10U_0603_6.3V6M PC6080 2 1 @
2
1

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

N3T@

2
1
PC6059 PC6037

2
1
2
1

PC6116 1U_0402_6.3V6K 10U_0603_6.3V6M

10U_0603_6.3V6M PC6081 PC6004
2
1

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

@
2
1
PC6038

2
1
2
1

PC6117 10U_0603_6.3V6M
10U_0603_6.3V6M PC6082 2 1 PC6005
2
1

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

N3T@

2
1
PC6061 PC6039 2 1

2
1
@

PC6118 1U_0402_6.3V6K 10U_0603_6.3V6M

2
1
10U_0603_6.3V6M PC6083 2 1 PC6006
PC6131 22UC_6.3VC_MC_X5RC_0603 1U_0402_6.3V6K
10U_0603_6.3V6M PC6062

N3T@
2
1

1U_0402_6.3V6K

+VCCSA

2
1
2
1
PC6007

@
PC6132 PC6119 22UC_6.3VC_MC_X5RC_0603
10U_0603_6.3V6M 10U_0603_6.3V6M
2
1

2
1
2
1
2
1
PC6008
PC6133 PC6120 PC6084 2 1 22UC_6.3VC_MC_X5RC_0603
10U_0603_6.3V6M 10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603

N3T@
PC6063

@
2
1
2
1
2
1
1U_0402_6.3V6K

@
PC6134 PC6121 PC6085 2 1
10U_0603_6.3V6M 10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603
2
1

PC6064

2
1
2
1
2
1
2
1

1U_0402_6.3V6K PC6009
PC6135 PC6122 PC6086 2 1 PC6043 22UC_6.3VC_MC_X5RC_0603

4
4

10U_0603_6.3V6M 10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603 10U_0603_6.3V6M

N3T@
2
1

PC6065

2
1
2
1
2
1
2
1

@
1U_0402_6.3V6K PC6010
PC6136 PC6123 PC6087 PC6044 22UC_6.3VC_MC_X5RC_0603
10U_0603_6.3V6M 10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603 10U_0603_6.3V6M
2
1

@
@

2
1
2
1
2
1

PC6011
PC6124 PC6088 PC6045 22UC_6.3VC_MC_X5RC_0603

2
1
10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603 10U_0603_6.3V6M
2
1

PC6137
2
1

10U_0603_6.3V6M PC6012
PC6046 22UC_6.3VC_MC_X5RC_0603

@
2
1
10U_0603_6.3V6M
@
2
1

PC6138
10U_0603_6.3V6M U42@ PC6013
2
1

22UC_6.3VC_MC_X5RC_0603

2
1
2
1 PC6047
PC6139 PC6100 10U_0603_6.3V6M
10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603
2
1

@
U42@

2
1
2
1
2
1

PC6048
PC6140 PC6101 10U_0603_6.3V6M PC6014
10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
@

2
1
2
1
2
1

@
PC6141 PC6102 PC6015
10U_0603_6.3V6M 22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
2
1
2
1

2
1

PC6103 PC6016
22UC_6.3VC_MC_X5RC_0603 PC6049 22UC_6.3VC_MC_X5RC_0603
10U_0603_6.3V6M
2
1
2
1

2
1

PC6104 PC6017
22UC_6.3VC_MC_X5RC_0603 PC6050 22UC_6.3VC_MC_X5RC_0603
10U_0603_6.3V6M
2
1
2
1

2 1
PC6105 PC6018
22UC_6.3VC_MC_X5RC_0603 4 3 22UC_6.3VC_MC_X5RC_0603
3T@

2 1 4.3U_0402_4V6-M
PC6155

@
PC6146
1U_0402_6.3V6K

+VCCSA
2 1
2
1

2 1
2 1 PC6019
PC6142 4 3 22UC_6.3VC_MC_X5RC_0603
3T@

1U_0402_6.3V6K
PC6093 4.3U_0402_4V6-M
2
1

1U_0402_6.3V6K
PC6156 PC6020
+VCC_GT

3
3

2 1 2 1 22UC_6.3VC_MC_X5RC_0603
2
1

PC6143 PC6150 2 1
1U_0402_6.3V6K 1U_0402_6.3V6K PC6021
2 1 4 3 22UC_6.3VC_MC_X5RC_0603
3T@

2 1
4.3U_0402_4V6-M

@
2
1

PC6144
1U_0402_6.3V6K PC6149 PC6157 PC6022
1U_0402_6.3V6K 22UC_6.3VC_MC_X5RC_0603
2 1
2 1

@
PC6145
1U_0402_6.3V6K 2 1 4 3
3T@

2 1
4.3U_0402_4V6-M
2
1

4 3

@
PC6151 4.3U_0402_4V6-M PC6158 PC6023
1U_0402_6.3V6K 22UC_6.3VC_MC_X5RC_0603
PC6159
@
@
2
1

2 1
PC6024
PC6152 22UC_6.3VC_MC_X5RC_0603
1U_0402_6.3V6K
@
2
1

PC6025
22UC_6.3VC_MC_X5RC_0603
2 1
2
1

@
4 3 PC6026
4.3U_0402_4V6-M 22UC_6.3VC_MC_X5RC_0603
@
2
1

PC6160
PC6027
22UC_6.3VC_MC_X5RC_0603

Issued Date
Security Classification
+2PCS_1U_0402_6V= sky_07_09
VCCGT: 1PCS_330U_D2_2V+1PCS_220U_D2_2V

+2PCS_1U_0402_6V=07-09 sky
VCCSA:5PCS_22U_0603_6V+6PCS_10U_0603_6V
+10PCS_22U_0603_6V+9PCS_9U_0603_6V

2
2

2018/07/10
https://vinafix.com
Vinafix.com

Deciphered Date
LC Future Center Secret Data
sky modify_20180925
sky modify_20180709
Vender modify_20180705

layout change PC6024/PC6025

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
2018/07/10

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
PC6003 @ and stuff 6 pcs 22U/0603

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
+16PCS_1U_0201_6V=

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
to PC6036/PC6046

Date:
change 10U/0402 to 10U/0603, 1U/0201 to 1U/0402

Custom
Title
CPU_CORE: 2PCS_330U_D2_2V+1PCS_220U_D2_2V

Size Document Number

+13PCS_22U_0603_6V+18PCS_10U_0402_6V

1
1

Wednesday, May 29, 2019

Sheet
140S-WHL
PWR-CPU Decoupling Cap

60
of
61
Rev
0.3
A
B
C
D