Design Entry CIS-Allegro To Xpedition Design Translation Guide

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TABLE OF CONTENTS
1 INTRODUCTION .................................................................................................................................................4
1.1 VERSIONS SUPPORTED ....................................................................................................................................................................... 5
2 SOFTWARE REQUIREMENTS ...............................................................................................................................5
3 PRE-TRANSLATION STEPS (CUSTOMER SITE) .......................................................................................................5
3.1 INSTALL THE TRANSLATORS AND COPY SKILL SCRIPTS ............................................................................................................................... 5
3.2 INSTALL THE TRANSLATORS ................................................................................................................................................................. 5
3.3 COPY SKILL SCRIPTS .......................................................................................................................................................................... 5
3.4 PREPARE SOURCE DESIGN .................................................................................................................................................................. 6
3.5 RUN SKILL SCRIPT TO EXTRACT ALLEGRO DATA....................................................................................................................................... 6
3.6 SET UP USER LAYER MAPPING ............................................................................................................................................................ 7
3.7 RUN PRE-TRANSLATION CHECK SCRIPT ................................................................................................................................................... 7
3.8 SEND EXTRACTED DATA TO TRANSLATOR OPERATOR ............................................................................................................................... 8
4 TRANSLATE ALLEGRO PCB TO XPEDITION LAYOUT ..............................................................................................8
4.1 RUN ALLEGRO TO XPEDITION LAYOUT TRANSLATOR ................................................................................................................................ 8
4.2 CREATE A CENTRAL LIBRARY ............................................................................................................................................................... 9
4.3 LOAD CELLS AND PADSTACKS INTO THE CENTRAL LIBRARY. ..................................................................................................................... 10
4.4 OPEN THE TRANSLATED DESIGN AND FORWARD ANNOTATE ................................................................................................................... 12
4.5 UPDATE PLANE CLASSES .................................................................................................................................................................. 16
4.6 [OPTIONAL] CONSTRAINTS UPDATE .................................................................................................................................................... 16
5 TRANSLATE ORCAD SCHEMATIC TO XPEDITION DESIGNER ........................................................... 18
5.1 CREATE NEW PROJECT..................................................................................................................................................................... 18
5.2 IMPORT ORCAD SCHEMATIC ............................................................................................................................................................ 19
5.3 IMPORT SCHEMATIC – CONFIGURATION .CNV FILE ................................................................................................................................. 20
5.4 IMPORT SCHEMATIC – TRANSLATION .................................................................................................................................................. 23
6 SCHEMATIC POST-TRANSLATION STEPS .............................................................................................. 25
6.1 RUN XPEDITION DESIGNER DIAGNOSTICS ............................................................................................................................................ 25
6.2 SCHEMATIC VERIFICATION ................................................................................................................................................................ 25
7 SYNCHRONIZE XPEDITION SCHEMATIC AND LAYOUT...................................................................... 26
7.1 PACKAGE XPEDITION DESIGNER ......................................................................................................................................................... 26
7.2 RESOLVE PACKAGER ERRORS............................................................................................................................................................. 27
7.3 SYNCHRONIZE XPEDITION DESIGNER/XPEDITION LAYOUT/CONSTRAINT MANAGER ..................................................................................... 27
7.4 COPY LAYOUT PROJECT FILES INTO DESIGNER PROJECT............................................................................................................................ 28
7.5 CHECK DESIGN STATUS ..................................................................................................................................................................... 30
7.6 FORWARD ANNOTATION .................................................................................................................................................................. 30
8 VALIDATE AND CLEAN UP ................................................................................................................................. 33
8.1 REVIEW OPEN NETLINES IN HAZARD EXPLORER .................................................................................................................................... 33
8.2 [OPTIONAL] CLOSE TINY OPEN NETS .................................................................................................................................................. 33
9 APPENDIX A – SCHEMATIC TRANSLATOR’S CONFIGURATION ............................................................................ 34
OrCAD/Allegro to Xpedition Design Translation 3

1 Introduction
This document describes the process of translating a Design Entry CIS/Allegro design to Xpedition Designer
Layout integrated project. This is a new process using a new translator first released in VX.2.10. In this
release both the new and old translators are supported. In future releases the old translator will be removed.
The diagram below provides an overview of the steps.
Basic Allegro PCB to Xpedition process is published in the product documentation and available on Mentor
Support Center.
Oftentimes after translation the design needs to be synchronized with an existing company Central Library,
which itself may have been translated previously. Mentor Graphics refers to this as “retargeting” a design
to a different library. Before beginning the design translation process you should determine whether the
design is to be retargeted, and if so, identify the library to target after translation. One good way to determine
if a design can be retargeted to an existing library is to compare the part numbers in the design to the library.
If the library has the needed part numbers, retargeting may be appropriate. If the library has a low percentage
of the parts used in the design, then retargeting is not a good idea. The design parts would have to be added
to the library before retargeting.
If retargeting, there are certain steps you can take during translation to make the retargeting work better.
These steps will be mentioned throughout the document. In summary, these steps are:
• Configure the schematic translator to map the correct property to Part Number. (section 5.3.3)
• Reference the target library using the UseTranslatedCentLib option (Appendix)

1.1 Versions Supported
Design Entry CIS (also called OrCAD Capture): version 17.2 is the highest version that can be
translated.
Allegro PCB Editor: versions from 16.6 to 17.2 can be translated.
2 Software Requirements
The following are requirements and recommendations as to the software that needs to be loaded on the
computer to complete the conversion process. Other software may be required outside the recommended
software below.
• Microsoft Access ODBC 64-BIT Driver

o https://www.microsoft.com/en-us/download/details.aspx?id=13255
• Xpedition Enterprise VX.2.10
o Xpedition Designer
o Xpedition Layout
o Constraint Manager
o Library Manager (100 license is used in this process)
• Allegro 16.X/17.X or Allegro 15.7 w/ Allegro PCB Design XL and Constraint Manager
installed (to run Skill extraction scripts)
3 Pre-translation steps (Customer Site)

3.1 Install the Translators and Copy Skill Scripts
Before translating a Cadence design, some design preparation must be done in the Allegro
environment. The design preparation may be done on one machine and the actual translation on
another machine. To get the Skill scripts needed for design preparation, one must install the “Allegro
to Xpedition” translator. This includes the Skill scripts, so it must be installed even if the translator
will not actually be run on the same machine as the Cadence design preparation.
Follow the instructions below to install the translators, copy Skill scripts to the correct area to run them
in the Cadence environment, and set environment variables used by the translator.
3.2 Install the Translators

The Allegro to Xpedition Layout translator is included in the standard Xpedition Layout installation.
The translator is free of charge but does require a Support Center login.
3.3 Copy Skill Scripts

3.3.1 Copy the skill files (*.il) from the Xpedition install directory to the $HOME\pcbenv
directory. This location stores scripts executed from the Cadence tools.
3.3.2 If one loads the product to the default path (C:\MentorGraphics), the skill scripts will be
found in the following location:
C:\MentorGraphics\EEVX.2.10\SDD_HOME\translators\skill_scripts
3.4 Prepare Source Design

The following steps must be executed in the Cadence environment in order to prepare the design for
translation.
3.4.1 Ensure Source Schematic and Layout are Synchronized

Before translation, the schematic and layout must be fully synchronized by forward- and back-
annotating. The differences between schematic and layout, such as Ref Designator or Part
Number change, swapped pins and connectivity change, should be fixed.
3.4.2 Clean OrCAD Design Cache

In order to achieve better Central Library data quality, one must run the OrCAD “cleanup
cache” command to clean the design prior the translation. This pre-translation step will avoid
redundant items in the Central Library and will help to minimize errors during the part creation
process. The cleanup command removes nonexistent parts from the cache which are otherwise
processed by the OrCAD translator.
3.4.3 Run DB Doctor in Allegro PCB

Run Tools ► Database Check (also known as DB Doctor) in Allegro PCB Editor to check for
database problems.
3.5 Run Skill Script to Extract Allegro Data

The Allegro translator does not read Allegro data directly. Rather, it reads data created by running a
Skill script in Allegro. Execute the script as described below.
NOTE: Spaces in the path or Allegro board file name will cause the SKILL extraction to fail. Remove
any spaces before running the script.
3.5.1 Open the layout (.brd) in Allegro PCB Editor (if not already open).
3.5.2 Enter skill load “all2layout.il” in the command window.
3.5.3 Enter all2layout in the command window.
3.5.4 Select OK to the Allegro to Xpedition Translator with the default settings to generate the
skill extraction.
3.5.1 Review .<brd file location directory>\aexoutput\devices\create_devices.log. The log

summarizes information about device translation errors (the text files in .\device directory are
used to create PDB in the translated Xpedition Layout).
• [If necessary] Remove geometries that cause the create_devices command to fail.

If the create_devices command fails during the extraction process, the geometries that cause
the problem must be removed from the design. One common case is one-pin components that
are no-connects. Such items must be removed.
To remove a geometry, use the script shown below. In this example, the device with reference
designator “LB1M1” is removed.
skill axlDeleteObject(axlDBFindByName(`refdes "LB1M1"))
After deleting geometries, save the PCB database. Re-run the skill code as in step 3.5 above
3.5.2 Review .<brd file name>_MGC\LogFiles\interfacelog.txt log file. The log summarizes the
extraction errors related to layout translation.
3.6 Set Up User Layer Mapping

This section will discuss the option to translate user layer data. Graphical data such as formats and drill
tables can be translated into Xpedition user layers. This requires the creation of the aexuserlayers.txt file.
The graphics/text not built into a cell, but existing at the board level, can now be translated on user draft
layer with aexuserlayers.txt.
3.6.1 Create a text file called aexuserlayers.txt.
3.6.2 Edit the aexuserlayer.txt file and add the full path of the Allegro layer name.
3.6.3 Place the file in the folder at the same level as the design.brd file. This is required for proper
skill extraction.
3.7 Run pre-translation check script

The check script will check the design and alert you to possible problems with the design that will
adversely affect translation. NOTE: spaces in the path or Allegro board file name will cause the
SKILL extraction to fail. Remove any spaces before running the script.
▪ Open the layout (.brd) in Allegro PCB Editor.
3.7.1 Enter skill load “transcheck.il” in the command window.
3.7.2 Enter transcheck in the command window.
3.7.3 Review the translatorcheck.log. It is located at the same location where the .brd file was
located.

3.8 Send Extracted Data to Translator Operator
Often somebody executes the steps above to extract the data needed from the Cadence environment,
and then sends the data to another person to run the translation. In this case, send everything described
below.
• “aexoutput” directory created by the Skill script
4 Translate Allegro PCB to Xpedition Layout

In this step, the files created by the Skill script are translated into an Xpedition Layout design.
4.1 Run Allegro to Xpedition Layout Translator

4.1.1 Invoke the MGC Command window from Start► All Programs► Xpedition Enterprise
X-ENTP VX.2.10 (64-bit) ►MGC EBS CMD VX.2.10
4.1.2 Enter “all2layout” and select the Enter key.
4.1.3 Navigate to the aexoutput folder created by the skill script as the Skill Output directory.

4.1.4 Navigate to the Layout output directory where the Xpedition Layout database should be
written. You must enter a folder name that exist.
4.1.5 Select the Translate button.
4.1.6 The translator will say it is Finished when the translator has completed successfully.
4.1.7 Close the translator dialog window by selecting the Cancel button.
4.2 Create a Central Library

In this section we will create a Central Library that we will add the Cells and Padstacks to from
Xpedition Layout.
4.2.1 Invoke the Library Manager from Start► All Programs► Xpedition Enterprise X-
ENTP VX.2.10 (64-bit) ►Library Manager VX.2.10
4.2.2 Select File► New

4.2.3 Navigate to the Folder where you want the Central Library to reside.
4.2.4 Select the OK button.
4.2.5 Select the Cell folder in the Library Navigator tree and expand it.
4.2.6 Add a Cell Partition. In this case Design was used.
4.3 Load Cells and Padstacks into the Central Library.

In this section we will use Library Services to load the cells and padstacks into the Central Library.
4.3.1 Use Tools ► Library Services.

4.3.2 Select the Cells Tab.
4.3.3 Select the Library Database option for Import From.
4.3.4 Select the navigator icon next to the Import From window.
4.3.5

4.3.6 Set the selection type to be PCB file (*.pcb)
4.3.7 Navigate to and select the translated design.pcb file.
4.3.8 Select the Open button.
4.3.9 Select the double Arrow icon to move the cells over into the Cells to import window.
4.3.10 Select the Apply button.
4.3.11 Select the Close button to exit Library Services.
4.3.12 Close the Central Library.
4.4 Open the Translated Design and Forward Annotate

At this point, the Xpedition Layout design has a keyin netlist and is not integrated with the translated
Xpedition Designer schematic. In this step the Xpedition Layout design will be opened, and forward
annotated to verify that the design data is correct.
4.4.1 Open the translated .pcb file in Xpedition Layout.
4.4.2 Set the Xpedition Layout licenses that are desired and OK the product license dialog.
4.4.3 Select OK.

4.4.4 Select OK.
4.4.5 Select Setup ► Project Integration.
4.4.6 Select the Edit Project File icon (it is the magnifier glass and pencil icon next to the Project
file and Design window.)
4.4.7 .Select the Netlist tab. Notice that the design has a keyin netlist that was created by the
translator.
4.4.8 Check Use Constraint Manager for constraint entry switch.

4.4.9 Select the OK button in the ‘Xpedition Layout’ pop-up window.
4.4.10 Click OK in the next pop-up
4.4.11 Run Forward Annotation with the following options

• Select Only extract missing library data
• Select Allow Alpha-only reference designators.
• Turn off all Trace Removal Options.
4.4.12 Select the green light next to No connectivity changes to be forward annotated. This will
initiate forward annotation from the netlist.
4.4.13 Close the Project Integration dialog.
4.4.14 There should be a message stating that Forward Annotation completed successfully or with
warnings.
4.4.15 Using View ► Display Control, review the pad and trace layers.
4.4.16 Open Setup ► Constraint Manager and review the constraints. It is important to know
what constraints are defined before synchronizing with the translated schematic in order to
recognize if any constraints are lost when forward annotating from the schematic.
4.4.17 File ► Save the design.

4.5 Update Plane Classes
The translator only creates a single ‘(Default)’ Plane Class. It does not read specific settings on each
plane shape to create additional plane classes. If additional plane classes are needed to accurately
reflect the plane settings in Allegro, add those plane classes in Layout dialog Planes ► Plane Classes
and Parameters ► New Plane Class. Then, assign the plane class to specific plane shape in the
layout.
4.6 [optional] Constraints Update

Once the layout has been migrated to Constraint Manager, you can bring over some additional constraint
information, mainly high-speed design related. Following additional constraints can be added in the
Constraint Manager if used in the Allegro PCB
• Back Drill
• Constraint Class
• Differential Pairs
o Updates the differential pair names to match Allegro
o Creates differential pairs that were defined as xnets in Allegro
o Adds additional constraints
• Match Group
• Pin Pairs
4.6.1 The steps to update the constraints

Launch a MGC BSD CMD window from the start menu and run the aexcmupdate program. When
the program dialog appears browse for the .pcb file of the newly upgraded design.
• The design must not be opened in Layout when this process is run.
• Options on the dialog will enable if that type of data is detected in the import file (in example
none of the high-speed constraints were migrated, so the options disabled)

5 Translate OrCAD Schematic to Xpedition Designer
In this section, the OrCAD schematic is translated to Xpedition Designer.
5.1 Create New Project

Create a new Xpedition Designer-Xpedition Layout project from default Xpedition Layout template,
by selecting the Central Library, project location and name.
5.1.1 Open Xpedition Designer and create a new Xpedition project.
5.1.2 Navigate to the Location where the Xpedition Designer data will be stored.
5.1.3 Provide the design Name.
5.1.4 Browse and select the Central Library created in the Allegro design translation process, see
section 4.1.5. The Central Library contain design-specific padstacks and cells at this point of
time.
5.1.5 Select the Create button.
By default, the wizard creates empty schematic called “Schematic1” attached to “Board1”.
5.1.6 Delete “Schematic1” from the Xpedition Designer project prior to translation in order to
avoid complication if the default OrCAD schematic is also named “Schematic1”. As a result,
the translator, in certain cases, may interpret the design hierarchy inaccurately.

5.2 Import OrCAD Schematic
5.2.1 In Xpedition Designer, select File ► Import ► OrCAD.
The Schematic tab is used to specify OrCAD schematics (*.dsn) for translation. The Libraries
tab is used to specify OrCAD libraries (*.olb) for translation. The Settings tab is used to specify
attribute mappings and some other translation options, such as scaling or options related to
PDB creation.

5.2.2 Under Schematics to translate, select Add. Browse and select the OrCAD .dsn file to be
translated.
5.2.3 Select Translate attributes. This controls whether attributes mapped in [COMPONENT
ATTRIBUTES] section of the configuration file are translated to Xpedition Designer.
5.2.4 Unselect Translate symbols only (without the schematic).
5.2.5 Select Create Design Library.
5.2.6 Unselect Create generic symbols.
5.2.7 Select Use default color scheme. This option applies the ‘automatic’ color to graphical
objects, which allows the colors to be controlled by the scheme selected in Xpedition
Designer. If the option is not selected, the translator will try to retain the OrCAD schematic
colors.
5.3 Import schematic – configuration .cnv file

5.3.1 Select the Settings tab and specify required options.
Review all selections for each settings tab. Each selection corresponds to a keyword in the
orcad_dx.cnv configuration file. These settings control mapping of OrCAD syntax to
Designer. For more information on specific mappings, refer to the document “Designer
Symbol and Schematic Translator User’s Guide” in the product documentation.
5.3.2 Browse and select the mapping file.

The default location is the .cnv file in the Xpedition install tree. If the file has been customized,
navigate to where the edited file resides. Note that there are two .cnv files in the install, one
for the netlist flow (orcad.cnv) and another one for the integrated flow (orcad_dx.cnv). It is
important to use the orcad_dx.cnv file.

If the settings are to be modified it is best to select the Save As button and save the file in a
location outside of the product install area. Data entered in the dialog is automatically saved
to the current file, so it is important to do Save As before modifying mapping information
5.3.3 [COMPONENT ATTRIBUTES] section: Part Number

Careful attention should be paid to how the Part Number property is created during schematic
translation. Some trial and error may be required to get this correct. The goal should be to get
the schematic part numbers to match the partlist/BOM for the original design. These part
numbers should match the part numbers in the layout if they match in the original design. If
the design is being retargeted to an existing library, the part numbers should match that library.
The translator by default utilizes the Orcad “Source Package” attribute to assign the Part
Number on parts in the Xpedition Designer schematic and Central Library. This approach
usually leads to generic Part Number assignment. For example, two capacitors having different
cell and other physical instance properties may share an identical Part Number if both parts
have the same “Source Package” value. There is an option in the configuration file that allows
assigning the required Orcad attribute into the Xpedition Layout Part Number.
The option UpdateMappedDevicesin the [CONVERSION] section works in conjunction with

the Part Number mapping in [COMPONENT ATTRIBUTES] section. The Part Number in
this example is built from the Orcad schematic instance data.
Example:

[CONVERSION]
UpdateMappedDevices=1
[COMPONENT ATTRIBUTES]
PNID=Part Number
This configuration will convert PNID into Part Number in the Xpedition Designer schematic
and design-specific Central Library. NOTE: generic Part Numbers based on the “Source
Package” attribute are created in the library in addition to the custom part numbers created
from “PNID”.
5.3.4 [COMPONENT ATTRIBUTES] section: property removal

Some Orcad properties are flow-specific and may be filtered out in the translation. Such
properties should be mapped to a null value in the configuration file. In the example below,
the properties “Source Path” and “Source Library” are removed.
5.3.5 [COMPONENT ATTRIBUTES] section: property rename

Map additional Orcad properties as necessary. Wherever possible, use standard Designer
property names as defined in the Property Definition Editor in Library Manager. It may be
difficult to determine in advance the names of all properties used in the Concept schematic.
For this reason, it may be necessary to translate the schematic twice. In the first translation,
the property mappings are not configured. Then a list of properties can be reported from the

translated schematic, and these properties can be mapped in the configuration file for a second
translation.
5.3.6 [GLOBAL SCALING] section.

The Orcad translator is able to scale schematics as they are translated. This is helpful in
situations where the translated schematics must match a company standard, for example to
achieve 0.2 inch pin spacing on symbols in order to match the corporate library symbol
standard.
The scale is defined by two integer values: Multiplier and Divisor. Scaling can specify only
one or both.
Example 1.
[GLOBAL SCALING]
Multiplier=3
Divisor=2
The translator will use scale 3/2 = 1.5. This will make the design 50% larger.
Example 2.
[GLOBAL SCALING]
Multiplier=3
Divisor=2
The translator will use scale 1/2 = 0.5. This will make the design 50% smaller.
5.3.7 Other translation options.

There are many other important translation options available in the configuration .cnv file,
particularly in the CONVERSION section. Each option has a small description in the GUI, so
the user can better understand the functionality.
More detailed description of the options, with the examples, are given in the Appendix A.
5.4 Import schematic – Translation

5.4.1 Return to the Schematic tab and select Translate. The translation summary is shown in the
end of the process.

Review the warnings and errors in the log file saved in Xpedition Designer project directory.
5.4.2 The schematic translation process is now complete. The Central Library has been updated
with design-specific symbols and parts (PDB).
As pointed in section 5.3.3 , the translator creates the generic parts driven by ‘Source Package’
property (see in red) and the parts driven by the custom Part Number mapping, in example this
was PNID property. The generic parts can be deleted from the Central Library after translation,
if necessary.

6 Schematic post-translation steps
This step achieves several goals:
• Correct database inconsistencies using Xpedition Designer Diagnostics
• Use schematic verification checks to find different types of issues
6.1 Run Xpedition Designer Diagnostics

After a translation, it is recommended to run Xpedition Designer Diagnostics. Xpedition Designer
Diagnostics helps to find and correct database inconsistencies stemming from unexpected events
during the translation process.
6.1.1 Open the translated schematic in Xpedition Designer.
6.1.2 Run Tools ► Diagnostics. Scan the results window for errors. It is typical to see errors
such as below.
Click on the blue text Click here to fix all errors.
6.2 Schematic verification

There are two types of checks in the Designer, graphics rule check (GRC) and design rule checks
(DRC).
• Graphics rule checker can find the graphical issues such as overlapping or off grid objects.
• The schematic DRC are grouped by different issues types, one of them is ‘Migration’,
‘Connectivity’ and others. It’s advices to use following checks at minimum for the translated
designs: drc-107, drc-108, drc-123, drc-127, drc-128, drc-504. In general case, this is custom
setup which can be saved in the .ini file, and reused for every translated schematic.
• See more details about available rule checks in the Designer product documentation.

7 Synchronize Xpedition Schematic and Layout
In this section, the schematic and layout are synchronized. The first step is to package the schematic data.
After packaging, the schematic is forward annotated to Xpedition Layout.
7.1 Package Xpedition Designer

This step will assign PDB part numbers (from the library) to the symbols and check for any errors in
the schematic.
7.1.1 In Xpedition Designer, select Tools ► Package.
7.1.2 Enable Allow Alpha-Only Reference Designators.
7.1.3 Select Rebuild Local library data; Preserve locally built data.
7.1.4 Select OK to package.
A successful schematic package will end with the following in the output window:

7.1.5 Verify in the Output window that the Packager finished successfully.
7.2 Resolve Packager Errors

Sometimes Packager will not complete successfully. The following is only guidance and is not a
complete list of packager errors and solutions. Please refer to Support Center for more information on
errors not described here.
7.2.1 Missing Part Number
• There is no Part Number: <###> in the Parts DataBase for symbols with Part Name:
(null) and Part Label: (null). Please add the Part Number to the PDB either directly or
by having the project file point to a PDB that contains it.
This error means either the Part Number defined on the symbol does not exist in the Central
Library or the Part Name and/or Part Label on the schematic symbol do not match the Part
Name or Part Label defined in the PDB for that Part Number. To remedy the problem, do one
of the following:
• Replace the device on the schematic using Component Replace.
• Edit the properties on the schematic symbol to match the Part definition.
• Edit the part definition to match the schematic symbol properties.
• Delete the symbol/device from the schematic and then Place Device again.
If the Part Numbers in question are known to exist in the Central Library and Name/Label
match, then the PDB partitions that contain the Part Numbers may not be available to the
Packager. To fix this, correct the search path scheme in xDM Library Tools.
7.2.2 Schematic Cell Name does not match the PDB Cell Name
Allegro translator may generate slightly different cell name than those specified on schematic
instances in OrCAD Capture. E.g. CON-PIN against CON-PIN_CN1. Xpedition Designer will
notify the mismatch in Package. In order to fix the issue, edit Cell Name value or remove whole
Cell Name property from instance since it is specified in design-specific library
7.3 Synchronize Xpedition Designer/Xpedition Layout/Constraint Manager

With the schematic successfully packaged, constraints need to be synched between the translated
schematic and the translated PCB before the first forward annotation can occur. During this process,

the program reconciles any differences between net names and stack-up information found in
Xpedition Designer and in Xpedition Layout.
7.3.1 Invoke Start ► All Programs ► Xpedition Enterprise X-ENTP VX.2.10 ► Translators
► Utilities ► Synch Migrated Designs VX.2.10.
7.3.2 For Migrated Design Project File, browse to the integrated-flow schematic .prj file created
in section 5.
7.3.3 For Migrated Design PCB, browse to the Xpedition Layout .pcb file created during the
board translation, see section 4
7.3.4 Enable Import PCB Constraints to Schematic.
7.3.5 Press OK to execute the program.
7.3.6 Review message that appears. If there are errors, review main log file.
<_EXP folder location>\PCB\LogFiles\SyncMigratedDesigns.txt
Also, review constraints migration log files.

<Designer .prj location>\PCB_Constraints_Export.txt
<Designer .prj location>\SCH_Constraints_Import.txt
7.4 Copy layout project files into Designer project

With the schematic successfully packaged and the constraints now in synch, the PCB project files
can be copied in the Designer project. The PCB file should be then re-linked with Designer .prj file.
7.4.1 In an Explorer window, browse to the translated Xpedition Layout folder.
7.4.2 Copy the PCB folder from the translated Xpedition Layout parent folder into the Xpedition
Designer Schematic project folder.
7.4.3 Browse to the .pcb file in the PCB folder, right button click, and choose Open to open in
Xpedition Layout.
Since the PCB was copied to a new location, the reference to the project file has been lost. A
message will appear.
Click Yes and browse to the Xpedition Designer project file.
7.4.4 Click OK in the following pop-up
7.4.5 Click Yes in the following pop-up. The Project Integration interface is opened.
7.5 Check design status
7.5.1 Prior to running Forward Annotation, it is advised to check the Design Status in Xpedition
Layout for any open connections. Any new open connections after forward annotation give
are evidence of mismatches between schematic and layout data that should be investigated.
7.5.2 Select Output ► Design Status.
In this example there are no open connections in the layout prior to Forward Annotation
7.6 Forward Annotation

7.6.1 In Project Integration GUI, set the Library Extraction Option to Delete local data; then
rebuild all local library data. Note: if cells were modified in the library for any reason, the
updated cells will be placed on the board during forward annotation with this option selected.
7.6.2 Select Allow Alpha-only reference Designators.
7.6.3 Unselect all Trace removal options.

7.6.4 Select the amber light next to Forward Annotation Required, connectivity changed. This
will begin forward annotation.
7.6.5 Verify that forward annotation has finished successfully. If warnings or errors are indicated
review the log file.
• One typical FA error is related to Partition Search Paths setup for the cells. If FA error says
about “No cell library search paths found”, then open Library Manager (see following
picture) and update search path for the cells, then redo FA.

7.6.6 Close the Project Integration dialog window.
7.6.7 Select File ► File Viewer.
7.6.8 Select the ForwardAnnotation.txt file and review the results. Look at the bottom of the file
for errors or net changes.
7.6.9 File ►Save and exit Xpedition Layout

8 Validate and Clean Up
Now that the design is synchronized, review the project for correctness and completeness in the following
areas:
• Open Netlines
• [optional] review ‘broken traces’ reported in FA log file
• [optional] use a command to ‘close tiny opens’
8.1 Review Open Netlines in Hazard Explorer

Use Hazard Explorer dialog to identify any broken connection, and other issues. In many cases, the
open netlines are related to the discipency between schematic and layout, caused by the translation or
incomplete synchronization in Orcad\Allegro design.
In example below, the broken routing is related to swapped pins not being FA to PCB layout in
Orcad/Allegro design.
8.1.1 From within Xpedition Layout, open Analysis ► Hazard Explorer.
8.1.2 Select Open Netlines tab in the navigator to get the status from the layout. Then you can
cross-probe the issue from the Explorer to layout.
8.2 [optional] Close Tiny Open Nets

Occasionally some of the opens reported in Hazard Explorer ► Open Netlines are caused by cell
replacement, where trace ends do not exactly match the pad center or by Allegro layout connectivity
model differences. Such open netlines are very small. Xpedition Layout has a command called “cto”
(close tiny opens) that automatically closes most tiny opens.
8.2.1 Before executing this command, turn all layers ON and then in Route Mode, select all
(CTRL+A).
8.2.2 Enter “cto” in the Keyin Command box.
This concludes the translation process.

9 Appendix A – Schematic translator’s configuration
Option in .cnv Expected Notes/Examples A use case
value
PartNameCase keep It applies to Central Library ‘Part Number’ The given options control the character
upper and ‘Part Number’ property instantiated on case of the converted objects in the
lower symbols in the schematic. Central Library and schematic. It helps
to harmonize the names in accordance
E.g. with the predefined library
specification, in case this information is
[CONVERSION] not consistent in the source Orcad
PartNameCase=lower library. For example, the symbol or cell
names in the source library could be in
The Part Number although being defined upper and low case, i.e. a mix that is
‘pn-xxxx-xxxx’ in the source Orcad library is not a desired state in the new Central
translated ‘PN-XXXX-XXXX’ in the Central Library.
Library. The property is updated on symbols
in the schematic accordingly By the default all options are set ‘keep’
SymbolNameCase keep It applies Central Library symbol name and means all character case is kept as
upper symbols instantiated in the schematic specified in the source Orcad library.
lower
E.g.
[CONVERSION]
SymbolNameCase=upper
A symbol called ‘res_v’ in the source Orcad

library is translated ‘RES_V’ in the Central
Library. The PDB reference and names in the
schematic are updated accordingly.
PinNumberCase keep It applies part (PDB) pin numbers in the
upper Central Library and symbols pin numbers in
lower the schematics
E.g.
[CONVERSION]
PinNumberCase=upper
A translated part in the Central Library has a

reference to the cell pins in upper case ‘A1’,
‘A10’, ‘AB22’ and so on. Note, this may not
necessarily match actual cell pin number
character.
CellNameCase keep It applies a cell name referenced in the
upper Central Library part. It does not change the
lower actual cell name in the library which is
translated in a separate step by PCB
translator.
CreateLibraryPartitions 1 1 – the partition names for parts and symbols The given options specify how the
0 are taken as cached within .dsn schematic parts can be grouped by partitions in
file (there are the paths cached to specific the Central Library. More transparent
Orcad .olb files) partition structure is helpful for those
customers using Central Library flow
0 – the partition names are taken from .dsn without Databook or EDM
file name

PartitionName a name of the The name of the partition is given explicitly.
required The parts and symbols are translated in the
partition in partition of the name as specified.
the Central
Library E.g.
[CONVERSION]
PartitionName=Project-AAAB
- All parts and symbols in the design-

specific Central Library are added in the
partitions called ‘Project-AAAB’. In
case of schematic translation, schematic
instances are updated with that Partition
name, in order to make it consistent
with the Central Library.
- Note, this translation option overrides
CreateLibraryPartitions setup if any
exist in the .cnv file
This option could be helpful for the design

translation to group all design-specific parts
in a single Central Library partition. Note, it
could an issue then to retarget such design
with the Reference library
GenerateSymPinNumb 1 1 - Adds the pin numbers to a symbol pin, in This option was used in case the PDB
ers 0 addition to PDB pin number. in the Central Library were created by
auxiliary automation (Advanced
0 – no pin number to a symbol pin is added Library Editor). There should be no
need to use this option in current
release
MoveSymbolProperties 1 1 – translates symbol properties as specified This could be helpful for the Orcad
ToParts 0 in .olb file (and cached in .dsn) to PDB customers which do not use CIS flow.
properties in Central Library In this case, all properties are defined
within .olb, cached in .dsn file so can
0 – no symbol properties translated in PDB be migrated to Central Library in the
schematic translation context.
In case of CIS flow customers, the

Databook configuration in Xpedition
flow should fix the issue.
UpdatePropertyDefiniti 1 E.g. The Orcad library and design properties
onFile 0 can be translated into Central Library
[COMPONENT ATTRIBUTES] properties. If the property need to be
MFG_PN= edited in the Designer schematic, it
MFG2_PN=Manufacturer 2 should be listed in the Central Library
property .prp file. In order to simplify
and the setup process for the translated
data, the translator can add the property
[CONVERSION] in the .prp automatically.
UpdatePropertyDefinitionFile =1
Property ‘Manufacturer 2’ is added in the

Central Library .prp file.

CollectInstanceCells 1 1 – add instance cell found in the schematic In case of CIS flow, specific cell
0 into Central Library PDB /Top Cell assignment per Orcad schematic part is
a database driven. So, the cached
0 – cell is assigned in the PDB from the library in .dsn schematic does not have
cached in .dsn file library data. Note, it could information about cell. This option
be a discipency between CIS and .olb library helps to build accurate PDB in the
cell assignment. design-specific Central Library, despite
related .olb files do not contain
information about cell, or there is a
discipency between the .olb library
(default cell) and actual cell assignment
(CIS database driven).
Mappings in The Ref Des prefixes drive the component This is used to set up a system property
[PART TYPE] section type assignment. In the default .cnv file all ‘Type’ in the Central Library for each
standard component types are listed. part.
- In case the prefix is not mapped in It has a limited use in the Xpedition
[PART TYPE], then the default Type flow. For example, in Constraint
‘IC’ is used Manger it is used as information during
applying constraint template on a net. It
E.g. helps to determine a part during pin
matching between constraint template
[PART TYPE] and target net.
C=Capacitor
D=Diode
In example, for every part having Ref Des

prefix ‘C’, the part ‘Type’ is set ‘Capacitor’.

Property mappings in Custom - By default, all properties found in .dsn These mappings work either to remove
[COMPONENT mappings schematic file or library .olb file are property and related value in translation
ATTRIBUTES] translated into Designer schematic and or rename the property in the Central
Central Library properties as-is. The Library. The mappings in this section
illegal characters replacement apply apply to a part property and symbol
automatically, in order the object names property simultaneously.
be conformal with Xpedition flow
requirements. The property can be - Part properties in the Central
added in the configured Central Library Library are not required if
.prp file (use Databook or EDM Library is used
UpdatePropertyDefinitionFile=1), and to instantiate symbol and relevant
also added in the PDB property in the data in the schematic. In this
Central Library (use scenario, the properties are
MoveSymbolPropertiesToParts=1) usually removed in translation,
because the data are stored and
- If the property has to be renamed, then managed in the database outside
the format is <Property A>=<Property Central Library.
B> NOTE: some Central Library
where on the left side is the source Orcad system properties may be helpful
flow property name, and on the right is the for the mapping to describe the
Central Library property name. part better. Those are Part Name,
Part Label and Description.
- If the property is removed, then the
format <Property A>= - The property Part Number is
where on the left side is the source Orcad identified automatically based on
flow property name, and on the right is null. the Orcad .olb Source Package
data, cached in .dsn. In case of
E.g. Orcad CIS driven flow, actual Part
[COMPONENT ATTRIBUTES] Number (as stored in the database
MFG_PN= and used in BOM) can be
MFG2_PN=Manufacturer 2 different from Source Package. In
Partid=Part Name that case, a custom mapping is
PNID=Part Number required. Ask the customer to
confirm which property to map.
In the example, the properties MFG_PN is
removed and MFG2_PN is renamed to be a - In case of CIS flow, all schematic
custom property ‘Manufacture 2’ in the properties are added instantly. The
Central Library. translator does not add instance
The CIS property ‘Partid’ is mapped with the property into design-specific
Central Library system property Part Name. Central Library as PDB property
The CIS property ‘PNID’ is mapped with the (one exception is a cell
Central Library system property Part assignment, see
Number. CollectInstanceCells option). It is
more convenient for CIS
customers to create Databook
configuration, in order to update
properties in the translated
schematic from the external
database, than from Central
Library

UseTranslatedCentLib Path to the Translator sets symbol and partition names The option is usually used ‘to retarget’
reference on converted designs and libraries to match design.
Central those used in the Referenced library. Oftentimes after translation the design
Library .lmc needs to be synchronized with an
file E.g. existing (reference) company Central
Library, which itself may have been
[CONVERSION] translated previously. Mentor Graphics
UseTranslatedCentLib=C:\Libraries\Compan refers to this as “retargeting” a design
y_X_reflib.lmc. from the design-specific library to a
It is assumed it is a master ECAD library, different library.
with the read-only access.
Using this option the translator can
Project library is located resolve following major issues:
D:\Translation\Project_libraries\Project-
AAAB.lmc. It is configured in the Designer - Symbol partition name change in
project for the Orcad schematic ‘Project- the Reference (company) library,
AAAB’ translation. for instance, from ‘A\res.1’ to
‘.B\res.1’ where the ‘res1’ is a
The translator will use symbol name
Company_X_reflib.lmc library structure to A symbol partition in the Reference
update Project-AAAB.lmc library structure library can be changed from ‘A’ to ‘B’.
and related schematic. This will facilitate the This creates the discipency between
retargeting of this particular design with the local schematic data which were related
company library after translation. against different library structure (e.g.
partition A), and a new library structure
(in e.g. partition ‘B’).
Similarly, the symbol location can be
changed from one partition to another,
which is the same issue because the
library symbol in now stored in a
different partition.
- No connect pins
The translator add no connect pins to
the design-specific parts as defined in
the Reference library.
CISConfigFile Path to .dbc CIS configuration file .dbc. It is a sort of These two options are used to translate
file Databook .dbc file in Xpedition flow CIS flow driven libraries. NOTE: this
CISDatabaseFile Path to mdb CIS database in MS Access .mdb format is not used for design translation.
file
The configuration .dbc and the database
in .mdb format are supplemental for
.olb libraries translation in this case.
ValidateCells 1 E.g. The cells and parts translation is done

0 separately, so it may create the
[CONVERSION] discipency between the part pins (as
ValidateCells=1 specified in PDB) and actual cell pins.
PinNumberCase=lower This option checks how the pin number
in the part correspond with the cell’s
The cell in the Central Library has all pins in pin numbers stored in the Central
upper case,e.g A1, A10, etc. At the same Library. If the pins do not match, the
time, the PinNumberCase option enables all translator reports the warning and skip
referenced pin numbers in the part are a cell assignment in PDB.
translated in low case. This may create the

discipency between part and cell pin
numbers.
As a part of the validation, the translator

identifies the discipency and report the error
‘Cell cannot be assigned to a part’. The cell
assignment for the related part is not done.
Note, that validation works not just for the
use case ‘A1’ vs. ‘a1’. Any difference in the
pin numbers between the part and available
Central Library cells, is identified.
SmartLibraryMerge 1 E.g. design translation This option is used to minimize the

0 number of duplicated symbols in the
[CONVERSION] Central Library. Usually such
SmartLibraryMerge=1 duplication is caused by the duplication
CreateLibraryPartitions=1 in the source design by using
inconsistent libraries (duplicated data
- Symbol ‘res_v.1’ in the schematic was in the libraries, obsolete data, copied
instantiated from the Orcad library data from the reference designs, etc.).
‘RESISTOR.olb’. Other related use case when there is a
- The translation is done in the Central need to translate few designs in the
Library with pre-populated symbols, Xpedition flow, but keep a single
where symbol ‘res_v.1’ is located in the Central Library for these few translated
partition ‘DISCRETE’. designs (the translation can be done in
a sequence, one design by one in the
The translator will not translate symbol same library). This option helps to
res_v.1 into partition ‘RESISTOR’ in merge the data by avoiding duplicated
assumption the pin names are identical symbols.
between res_v from .dsn and Central Library
symbol res_v.1 in the partition ‘DISCRETE’.
The related symbols in the translated
schematic will be updated with the Partition
‘DISCRETE’.
In the end, one symbol DISCRETE\res_v.1
is retained in the library, not two.
Mappings in The mappings between configured .olb and This is used for Orcad library
[LIBRARY Central Library partition is entered translation only. It can be helpful for
PARTITIONS] those customers not using
Databook/EDM flow, to adjust the
structure of the translated Central
Library

Design Entry CIS-Allegro To Xpedition Design Translation Guide

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OrCAD/Allegro to Xpedition Design Translation 3

The diagram below provides an overview of the steps.

OrCAD/Allegro to Xpedition Design Translation 4

• Microsoft Access ODBC 64-BIT Driver

3 Pre-translation steps (Customer Site)

3.2 Install the Translators

3.3 Copy Skill Scripts

3.4 Prepare Source Design

3.4.1 Ensure Source Schematic and Layout are Synchronized

3.4.2 Clean OrCAD Design Cache

3.4.3 Run DB Doctor in Allegro PCB

3.5 Run Skill Script to Extract Allegro Data

3.5.2 Enter skill load “all2layout.il” in the command window.

3.5.3 Enter all2layout in the command window.

3.5.1 Review .<brd file location directory>\aexoutput\devices\create_devices.log. The log

OrCAD/Allegro to Xpedition Design Translation 6

skill axlDeleteObject(axlDBFindByName(`refdes "LB1M1"))

3.6 Set Up User Layer Mapping

3.6.1 Create a text file called aexuserlayers.txt.

3.7 Run pre-translation check script

▪ Open the layout (.brd) in Allegro PCB Editor.

3.7.1 Enter skill load “transcheck.il” in the command window.

3.7.2 Enter transcheck in the command window.

OrCAD/Allegro to Xpedition Design Translation 7

4 Translate Allegro PCB to Xpedition Layout

4.1 Run Allegro to Xpedition Layout Translator

4.1.2 Enter “all2layout” and select the Enter key.

OrCAD/Allegro to Xpedition Design Translation 8

4.1.5 Select the Translate button.

4.2 Create a Central Library

4.2.2 Select File► New

OrCAD/Allegro to Xpedition Design Translation 9

4.2.4 Select the OK button.

4.2.6 Add a Cell Partition. In this case Design was used.

4.3 Load Cells and Padstacks into the Central Library.

4.3.1 Use Tools ► Library Services.

OrCAD/Allegro to Xpedition Design Translation 10

4.3.3 Select the Library Database option for Import From.

OrCAD/Allegro to Xpedition Design Translation 11

4.3.7 Navigate to and select the translated design.pcb file.

4.3.8 Select the Open button.

4.3.10 Select the Apply button.

4.3.11 Select the Close button to exit Library Services.

4.3.12 Close the Central Library.

4.4 Open the Translated Design and Forward Annotate

4.4.1 Open the translated .pcb file in Xpedition Layout.

4.4.3 Select OK.

OrCAD/Allegro to Xpedition Design Translation 12

4.4.5 Select Setup ► Project Integration.

4.4.8 Check Use Constraint Manager for constraint entry switch.

OrCAD/Allegro to Xpedition Design Translation 13

4.4.10 Click OK in the next pop-up

4.4.11 Run Forward Annotation with the following options

OrCAD/Allegro to Xpedition Design Translation 14

4.4.13 Close the Project Integration dialog.

4.4.17 File ► Save the design.

OrCAD/Allegro to Xpedition Design Translation 15

4.6 [optional] Constraints Update

4.6.1 The steps to update the constraints

OrCAD/Allegro to Xpedition Design Translation 16

5.1 Create New Project