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CURRICULUM I SEMESTER (FULL TIME) M.E. APPLIED ELECTRONICS SEMESTER I SL. COURSE NO CODE THEORY MA9217 1 2 AP9211 3 AP9212 4 VL9212 5 AP9213 E1 PRACTICAL 6 AP9217 COURSE TITLE Applied Mathematics for Electronics Engineers Advanced Digital Signal Processing Advanced Digital System Design VLSI Design Techniques Advanced Microprocessors and Micro Controllers Elective I Electronics Design Lab I TOTAL LIST OF ELECTIVES M.E. APPLIED ELECTRONICS SL. NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 COURSE CODE AP9251 AP9252 AP9253 VL9211 VL9261 AP9260 NE9251 AP9256 CP9212 AP9258 VL9252 VL9253 VL9254 VL9221 AP9259 COURSE TITLE Digital Image Processing Neural Networks and Its Applications ROBOTICS DSP Integrated Circuits ASIC Design Design and Analysis of Algorithms Reliability Engineering Electromagnetic Interference and Compatibility in System Design High Performance Computer Networks RF system Design Low Power VLSI Design VLSI Signal Processing Analog VLSI Design CAD for VLSI Circuits Hardware Software Co-design Special Elective L 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 L 3 3 3 3 3 3 0

T 1 0 0 0 0 0 0

P 0 0 0 0 0 0 4

C 4 3 3 3 3 3 2




LTPC 310 4 12

UNIT I FUZZY LOGIC Classical logic – Multivalued logics – Fuzzy propositions – Fuzzy quantifiers.

UNIT II MATRIX THEORY 12 Some important matrix factorizations – The Cholesky decomposition – QR factorization – Least squares method – Singular value decomposition - Toeplitz matrices and some applications. UNIT III ONE DIMENSIONAL RANDOM VARIABLES 12

Random variables - Probability function – moments – moment generating functions and their properties – Binomial, Poisson, Geometric, Uniform,
Exponential, Gamma and Normal distributions – Function of a Random Variable. UNIT IV DYNAMIC PROGRAMMING 12 Dynamic programming – Principle of optimality – Forward and backward recursion – Applications of dynamic programming – Problem of dimensionality. UNIT V QUEUEING MODELS 12 Poisson Process – Markovian queues – Single and Multi-server Models – Little’s formula - Machine Interference Model – Steady State analysis – Self Service queue. L = 45: T=15; TOTAL: 60 PERIODS REFERENCES: 1. George J. Klir and Yuan, B., Fuzzy sets and fuzzy logic, Theory and applications, Prentice Hall of India Pvt. Ltd., 1997. 2. Moon, T.K., Sterling, W.C., Mathematical methods and algorithms for signal processing, Pearson Education, 2000. 3. Richard Johnson, Miller & Freund’s Probability and Statistics for Engineers, 7th Edition, Prentice – Hall of India, Private Ltd., New Delhi (2007). 4. Taha, H.A., Operations Research, An introduction, 7th edition, Pearson education editions, Asia, New Delhi, 2002. 5. Donald Gross and Carl M. Harris, Fundamentals of Queuing theory, 2nd edition, John Wiley and Sons, New York (1985).


LTPC 3 003 UNIT I DISCRETE RANDOM SIGNAL PROCESSING 9 Discrete Random Processes- Ensemble Averages, Stationary processes, Bias and Estimation, Autocovariance, Autocorrelation, Parseval’s theorem, Wiener-Khintchine relation, White noise, Power Spectral Density, Spectral factorization, Filtering Random Processes, Special types of Random Processes – ARMA, AR, MA – Yule-Walker equations.



Dimitris G. John Wiley and Sons.State diagram. Manolakis. Proakis. Hayes. Solution using Levinson-Durbin algorithm UNIT III LINEAR ESTIMATION AND PREDICTION 9 Linear prediction – Forward and Backward prediction. Bartlett. Parametric methods – ARMA. FIR and IIR Wiener filters. Polyphase filter structures. Inc. Decimation by an integer factor. Pearson Education Inc. Wiener filter for filtering and prediction. Gonzalez. Sampling rate conversion by a rational factor. Adaptive noise cancellation. Normalized LMS algorithm. AR and MA model based spectral estimation. Richard E. RLS adaptive algorithm. Adaptive echo cancellation. : Digital Signal Processing’. Rafael C. Solution of Prony’s normal equations. 2002 2. Woods. Adaptive channel equalization. 2004 (For Wavelet Transform Topic) AP9212 ADVANCED DIGITAL SYSTEM DESIGN LT PC 30 0 3 UNIT I SEQUENTIAL CIRCUIT DESIGN 9 Analysis of clocked synchronous sequential circuits and modeling.Widrow-Hopf LMS algorithm. Discrete Kalman filter UNIT IV ADAPTIVE FILTERS 9 FIR adaptive filters – adaptive filter based on steepest descent method. Modified periodogram. Singapore. Multistage implementation of multirate system. “ Digital Image Processing”. Interpolation by an integer factor. UNIT V MULTIRATE DIGITAL SIGNAL PROCESSING 9 Mathematical description of change of sampling rate – Interpolation and Decimation. Monson H.Second Edition. dynamic and essential hazards – data synchronizers – mixed operating mode asynchronous circuits – designing vending machine controller 3 . Least mean-squared error criterion. ‘Statistical Digital Signal Processing and Modeling”. 2002 3. Application to subband coding – Wavelet transform TOTAL: 45 PERIODS REFERENCES: 1.. state table assignment and reduction-Design of synchronous sequential circuitsdesign of iterative circuits-ASM chart and realization using ASM UNIT II ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN 9 Analysis of asynchronous sequential circuit – flow table reduction-races-state assignment-transition table and problems in transition table. state table.UNIT II SPECTRAL ESTIMATION 9 Estimation of spectra from finite duration of asynchronous sequential circuit-Static. Nonparametric methods Periodogram. Pearson Education. John J. Welch and Blackman-Tukey methods.

Parag K. Charles H. Inverter ratio. Douglas L.Divider – Design of simple microprocessor TOTAL : 45 PERIODS REFERENCES: 1. Inductance. switching times. MOS models and small signal AC characteristics. transistor sizing. Transmission gates.UNIT III FAULT DIAGNOSIS AND TESTABILITY ALGORITHMS 9 Fault table method-path sensitization method – Boolean difference method-D algorithm -Tolerance techniques – The compact algorithm – Fault in PLA – Test generation-DFT schemes – Built in self test UNIT IV SYNCHRONOUS DESIGN USING PROGRAMMABLE DEVICES 9 Programming logic device families – Designing a synchronous sequential circuit using PLA/PAL – Realization of finite state machine using PLD – FPGA – Xilinx FPGA-Xilinx 4000 UNIT V SYSTEM DESIGN USING VHDL 9 VHDL operators – Arrays – concurrent and sequential statements – packages.Lala “Digital system Design using PLD” B S Publications. Charge sharing . Nripendra N Biswas “Logic Design Theory” Prentice Hall of India. Stick diagram.Lala “Fault Tolerant and Fault Testable Hardware Design” B S Publications. Charles H Roth Jr. Parag K.Hill .2002 4. 4 .2003 5.Roth Jr “Fundamentals of Logic Design” Thomson Learning 2004 2.Body effect.2001 3. power dissipation and design margining. switching characteristics. Static CMOS design. Basic CMOS technology.Scaling. UNIT III CIRCUIT CHARACTERIZATION AND PERFORMANCE ESTIMATION 9 Resistance estimation.Data flow – Behavioral – structural modeling – compilation and simulation of VHDL code –Test bench .”Digital System Design using VHDL” Thomson learning. Driving large capacitance loads.2006 VL9212 VLSI DESIGN TECHNIQUES LT PC 3 0 0 3 UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY 9 NMOS and PMOS transistors. CMOS logic structures . Capacitance estimation. UNIT II INVERTERS AND LOGIC GATES 9 NMOS and CMOS Inverters.Realization of combinational and sequential circuits using HDL – Registers – counters – sequential machine – serial adder – Multiplier.Design equationsSecond order effects. Threshold voltage. Super buffers.Perry “VHDL programming by Example” Tata McGraw. dynamic CMOS design. DC and transient characteristics . 2004 6.

High-speed adders. John P. hierarchical modeling concepts. Clock distribution. UNIT V VERILOG HARDWARE DESCRIPTION LANGUAGE 9 Overview of digital design with Verilog HDL. UNIT II HIGH PERFORMANCE CISC ARCHITECTURE – PENTIUM 9 CPU Architecture. modules and port definitions.Bhasker. Shift registers.addressing modes – Programming the ARM processor. comparators. “A Verilog HDL Primer”.Uyemura “Introduction to VLSI Circuits and Systems”. 2001. Basics of CMOS testing. 2002. Samir Palnitkar.Thumb Instruction set. data flow modeling. power distribution. Physical design – Delay modelling . McGraw Hill International Editions. 2. Weste and Kamran Eshraghian.. task & functions. 5. Principles of CMOS VLSI Design. Multipliers. AP9213 ADVANCED MICROPROCESSORS AND MICROCONTROLLERS L T P C 30 03 UNIT I MICROPROCESSOR ARCHITECTURE 9 Instruction Set – Data formats –Addressing modes – Memory hierarchy –register file – Cache – Virtual memory and paging – Segmentation. Inc. 1990. 4. 2nd Edition. behavioral modeling. Wayne Wolf “Modern VLSI Design System on chip. “Verilog HDL”. Pearson Education. Carry look ahead adders. “Introduction to VLSI Design”. 2004. Decoders. UNIT III HIGH PERFORMANCE RISC ARCHITECTURE – ARM 9 Organization of CPU – Bus architecture –Memory management unit . 6.2002. Neil H. Prentice Hall of India Publication. J. 2nd edition.UNIT IV VLSI SYSTEM COMPONENTS CIRCUITS AND SYSTEM LEVEL PHYSICAL DESIGN 9 Multiplexers.S. 5 . TOTAL : 45 PERIODS REFERENCES: 1.Publications. floor planning.Bus Operations – Pipelining – Brach predication – floating point unitOperating Modes –Paging – Multitasking – Exception and Interrupts – Instruction set – addressing modes – Programming the Pentium processor.pipelining –the instruction pipeline – pipeline hazards – instruction level parallelism – reduced instruction set –Computer principles – RISC versus CISC. gate level modeling. Eugene D.ARM instruction set. Pucknell. 1995. John Wiley & Sons. 2nd Edition.Fabricius. Pearson Education ASIA.E. 3. Pearson Education. Test Bench. “Basic VLSI Design”. B. Arithmetic circuits – Ripple carry adders. 2000.cross talk. 7. priority encoders.

periodogram and multistage multirate system in DSP Processor 3.H.RTC-Serial Communication Interface – A/D Converter PWM and UART.UNIT IV MOTOROLA 68HC11 MICROCONTROLLERS 9 Instruction set addressing modes – operating modes. System design using 16.” The Intel Microprocessors Architecture . TOTAL : 45 PERIODS REFERENCES : 1.I2C Interfacing –UART. UNIT V PIC MICROCONTROLLER 9 CPU Architecture – Instruction set – interrupts. System design using PIC Microcontroller. Design and Implementation of ALU using FPGA. Programming and Interfacing “ .Interrupsystem. 8.Breg.Timers. Simulation of QMF using Simulation Packages 4. 7.” An Introduction to the Intel family of Microprocessors ‘’ Pearson Education 1999. 6. PHI. James L.B.Peatman . Implementation of Adaptive Filters. 5. ‘’ Advanced Microprocessors” McGraw Hill. 6.B.. 3. 7. Gene .Inc. 1997. Modeling of Sequential Digital system using Verilog. 2.” Pearson Education . Antonakos . “ The Pentium Microprocessor ‘’ Pearson Education .” Micro Computer Engineering . 8. 1997. 2003. 2000. Valvano "Embedded Microcomputer Systems" Thomson Asia PVT LTD first reprint 2001. ‘’ ARM System –On –Chip architecture “Addision Wesley . 2. Barry. Steve Furber .A/D Converter –PWM and introduction to C-Compilers. TOTAL : 60 PERIODS 6 . “ Design with PIC Microcontroller .Miller . 1995 James L. John . AP9217 ELECTRONICS DESIGN LABORATORY I LTPC 004 2 1. Simulation of NMOS and CMOS circuits using SPICE.2002.bit Microprocessor. 5. Daniel Tabak . Prentice hall.Antonakos . 4. Modeling of Sequential Digital system using VHDL.

Shift codes. UNIT II IMAGE TRANSFORMS 9 1D DFT. “Fundamentals of Digital Image Processing”.. Design of 2D FIR filters. Wavelet transform. UNIT III IMAGE ENHANCEMENT AND RESTORATION 9 Histogram modification. Woods. Region growing. D. Dudgeon and R. Sid Ahmed. 2004.. JPEG standard. William K. Inc. Hadamard. Richard E. Gonzalez. Neural networks-Backpropagation network and training. Walsh. Geometric transformations-spatial transformations. Pearson Education. Pratt. Noise distributions. Neural network to recognize shapes. 2002. 2nd edition. Transform coding. Elements of visual perception. Geometric mean. Woods. Block Truncation Coding. New York. 7. Gray Level interpolation. Analysis and Machine Vision”.M.. Matching by correlation.DFT. Anil K. Harmonic mean. 7 . contrast. “ Digital Image Processing”. 2002. “ Image Processing Theory. SVD. brightness. . Inc. Median.. Prentice Hall Professional Technical Reference. Huffman. “ Digital Image Processing”. Algorithms and Architectures”. Gonzalez. Brookes/Cole. Second Edition. Mersereau. Quantization. EZW. Rafael C. TOTAL: 45 PERIODS REFERENCES: 1. Rafael C. Milan Sonka et al. Unconstrained and Constrained restoration.Patterns and pattern classes. Image sampling. Steven Eddins. Contraharmonic and Yp mean filters . 1995. KLT. M. “Image Processing. SPIHT. UNIT IV IMAGE SEGMENTATION AND RECOGNITION 9 Image segmentation . hue. Dither.” Digital Image Processing using MATLAB”. Richard E.AP9251 DIGITAL IMAGE PROCESSING LTPC 3 003 UNIT I DIGITAL IMAGE FUNDAMENTALS 9 Elements of digital image processing systems. saturation. 3. 2D transforms . Prentice Hall of India. UNIT V IMAGE COMPRESSION 9 Need for data compression. Arithmetic coding. 6.Edge detection.E. 1999. 2004 2. Jain. Wiener filtering. DCT. Image Recognition . Edge linking and boundary detection.degradation model. Mach Band effect. Matching by minimum distance classifier. 5. Vidicon and Digital Camera working principles. Region splitting and Merging. Pearson Education. Inverse filtering-removal of blur caused by uniform linear motion. Run Length Encoding. Image restoration . Vikas Publishing House. McGrawHill. 1990. Vector Quantization. Discrete Sine. “Multidimensional Digital Signal Processing”. Spatial averaging. Haar.A. Two dimensional mathematical preliminaries. Slant. John Wiley. 4. JPEG 2000. Directional Smoothing. MPEG.

Statistical Learning Theory – Single Layer Perceptron – Perceptron Learning Algorithm – Perceptron Convergence Theorem – Least Mean Square Learning Algorithm – Multilayer Perceptron – Back Propagation Algorithm – XOR problem – Limitations of Back Propagation Algorithm.Applications: XOR Problem – Image Classification. Support Vector Machines: Optimal Hyperplane for Linearly Separable Patterns and Nonseparable Patterns – Support Vector Machine for Pattern Recognition – XOR Problem . UNIT IV ATTRACTOR NEURAL NETWORKS: 9 Associative Learning – Attractor Neural Network Associative Memory – Linear Associative Memory – Hopfield Network – Content Addressable Memory – Strange Attractors and Chaos .Applications of Hopfield Networks – Simulated Annealing – Boltzmann Machine – Bidirectional Associative Memory – BAM Stability Analysis – Error Correction in BAMs .Beamforming – Memory – Adaptation .AP9252 NEURAL NETWORKS AND ITS APPLICATIONS LTPC 3 003 UNIT I BASIC LEARNING ALGORITHMS 9 Biological Neuron – Artificial Neural Model .EM Algorithm – Applications of EM Algorithm to HME Model NEURODYNAMICS SYSTEMS: Dynamical Systems – Attractors and Stability – Non-linear Dynamical SystemsLyapunov Stability – Neurodynamical Systems – The Cohen-Grossberg Theorem. UNIT II RADIAL-BASIS FUNCTION NETWORKS AND SUPPORT VECTOR MACHINES RADIAL BASIS FUNCTION NETWORKS: 9 Cover’s Theorem on the Separability of Patterns .Exact Interpolator – Regularization Theory – Generalized Radial Basis Function Networks .Solving Noise-Saturation Dilemma – Recurrent On-center – Off-surround Networks – Building Blocks of Adaptive Resonance – Substrate of Resonance Structural Details of Resonance Model – Adaptive Resonance Theory – Applications 8 .Error Performance of Hopfield Networks .Boltzman Learning – Supervised and Unsupervised Learning – Learning Tasks: Pattern Space – Weight Space – Pattern Association – Pattern Recognition – Function Approximation – Control – Filtering .Boosting – Associative Gaussian Mixture Model – Hierarchical Mixture of Experts Model(HME) – Model Selection using a Standard Decision Tree – A Priori and Postpriori Probabilities – Maximum Likelihood Estimation – Learning Strategies for the HME Model .Types of activation functions – Architecture: Feedforward and Feedback – Learning Process: Error Correction Learning –Memory Based Learning – Hebbian Learning – Competitive Learning .Memory Annihilation of Structured Maps in BAMS – Continuous BAMs – Adaptive BAMs – Applications ADAPTIVE RESONANCE THEORY: Noise-Saturation Dilemma .Learning in Radial Basis Function Networks .insensitive Loss Function – Support Vector Machines for Nonlinear Regression UNIT III COMMITTEE MACHINES: 9 Ensemble Averaging .

3. “Neural Networks Algorithms. Convolution . Introduction to sensing Light sensing. Probabilistic Reasoning . Skapura. The A* algorithm . Heat sensing. Martin T. UNIT III SENSORS AND SENSING DEVICES 9 Introduction to various types of sensor. Planning State-Space Planning . and Multi-agent planning 2. AP9253 ROBOTICS LTPC 3 0 03 UNIT I INTRODUCTION TO ROBOTICS 9 Motion . Addison Wesley Longman (Singapore) Private Limited. Delhi.Transformation matrix and DH transformation. 2. Inverse Kinematics . Iterative and deepening depth first search and Bidirectional search. Kinematics. Tata McGraw-Hill Publishing Company Limited. “Neural Networks: A Comprehensive Foundation”. TOTAL: 45 PERIODS REFERENCES: 1. Simon Haykin. Freeman and David M.Geometric methods and Algebraic methods. Multi-agent planning 1. and Mark Beale. Delhi. Plan-Space Planning. Thresholding. Cell decomposition and Sensor and sensor planning. Pearson Education (Singapore) Private Limited. 2003.. Image Processing .Hagan. Touch sensing and Position sensing. Blob Filling. Graphplan/SatPlan and their Comparison. Howard B. UNIT II COMPUTER VISION 9 Projection .Breadth first. Satish Kumar. Projection on the Image Plane and Radiometry.Vector Quantization – Mexican Hat Networks Self-organizing Feature Maps – Applications PULSED NEURON MODELS: Spiking Neuron Model – Integrate-and-Fire Neurons – Conductance Based Models – Computing with Spiking Neurons. 2001. and Programming Techniques. Edge Detection . New Delhi. Demuth.Ladar (laser distance and ranging). Radar and Infra-red.Potential Function. Sonar.Connectivity.Digital Convolution and Filtering and Masking Techniques. 2004. 2ed. “Neural Networks: A Classroom Approach”.Optics. Histogram. UNIT IV ARTIFICIAL INTELLIGENCE 9 Uniform Search strategies . Decision Trees and Bayes net inference 9 . “Neural Network Design”. Thomson Learning. Depth first. New Delhi. James A. 2003. Images-Gray Scale and Binary Images. Road maps. 4. Applications. Resistive sensors.Mono and Stereo Vision.UNIT V SELF ORGANISING MAPS: 9 Self-organizing Map – Maximal Eigenvector Filtering – Sanger’s Rule – Generalized Learning Law – Competitive Learning . Non-Holonomic constraints. Range sensors . Forward and Inverse Kinematics . Depth limited.Bayesian Networks.

Multirate systems. DFT-The Discrete Fourier Transform. Frequency response. UNIT III DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS 9 FIR filters. Integrated circuit design. Sampling rate change with a ratio L/M.Vision System for pattern detection . Mapping of analog transfer functions. Finite word length effects -Parasitic oscillations. Application specific IC’s for DSP. Adaptive DSP algorithms. 2000. Signal-processing systems. Image coding. Roundoff noise. Scaling of signal levels. Analysis and control By Robert Schilling and Craig. FIR filter structures. 5. UNIT IV DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES 9 DSP system architectures. Implementation based on complex PEs. Selection of sample frequency. Signal flow graphs. DSP system design. Computer Vision.Sensors for obstacle detection . 2004 4. Specifications of IIR filters. A modern Approach By Forsyth and Ponce. UNIT II DIGITAL SIGNAL PROCESSING 9 Digital signal processing. 3. Systolic and Wave front arrays. 10 . Cambridge. MOS transistors. Duda. Mapping of analog filter structures. Artificial Intelligence-A Modern Approach By Stuart Russell and Peter Norvig. Coefficient sensitivity. Transfer functions. Shared memory architecture with Bit – serial PEs. 2000. FIR chips. Hart and Stork. 2. Trends in CMOS technologies. Mapping of DSP algorithms onto hardware. Sampling of analog signals. VLSI process technologies. Multiprocessors and multicomputers.AI algorithms for path finding and decision making TOTAL: 45 PERIODS REFERENCES: 1. 2003. Hall of India Private Limied. Sensitivity and noise. Interpolation with an integer factor L. Computational Vision: Information Processing in Perception and Visual Behavior. 2003. VL9211 DSP INTEGRATED CIRCUITS LTPC 300 3 UNIT I DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES 9 Standard digital signal processors. Wiley-Interscience. MA: MIT Press. Standard DSP architecture. MOS logic. Pattern Recognition. IIR filters. Discrete cosine transforms. Mallot. New Delhi. FFT-The Fast Fourier Transform Algorithm. Shared memory architectures. DSP systems. Multirate filters. Filter structures. Fundamentals of Robotics.UNIT V INTEGRATION TO ROBOT 9 Building of 4 axis or 6 axis robot . Measuring round-off noise. Ideal DSP architectures. Pearson Education Series in Artificial Intelligence. Person Education.

“ Digital signal processing – A practical approach”.Transistors as Resistors .PREP benchmarks . Bit-parallel and Bit-Serial arithmetic. Emmanuel C. Lars Wanhammer.fault simulation .UNIT V ARITHMETIC UNITS AND INTEGRATED CIRCUIT DESIGN 9 Conventional number system.EPROM and EEPROM technology . Cordic algorithm. Basic shift accumulator. A. 11 . Reducing the memory size.Altera MAX 5000 and 7000 . “DSP Integrated Circuits”. Complex multipliers. 1999.Xilinx EPLD .Logical effort –Library cell design .Combinational Logic Cell – Sequential logic cell .al.Altera MAX DC & AC inputs and outputs .Oppenheim et.Low level design language . PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY 9 Actel ACT -Xilinx LCA . 4. “VLSI Digital Signal Processing Systems design and Implementation”.Logic Synthesis . Barrie W. UNIT III PROGRAMMABLE ASIC INTERCONNECT. SIMULATION AND TESTING 9 Verilog and logic synthesis -VHDL and logic synthesis . TOTAL: 45 PERIODS REFERENCES: 1. UNIT IV LOGIC SYNTHESIS.Parhi. Improved shift-accumulator. PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC I/O CELLS 9 Anti fuse . Asia. 2000. 3.Xilinx LCA –Altera FLEX .Xilinx I/O blocks.Clock & Power inputs .Actel ACT . Second Edition.Half gate ASIC -Schematic entry . Pearson Education. “Discrete-time Signal Processing”.CFI design representation.Altera FLEX –Design systems .CMOS transistors CMOS Design rules .Library architecture .V.Transistor Parasitic Capacitance.types of simulation -boundary scan test . Layout of VLSI circuits. Residue Number System. DCT processor and Interpolator as case studies. Pearson Education. Ifeachor. UNIT II PROGRAMMABLE ASICS. CMOS LOGIC AND ASIC LIBRARY DESIGN 9 Types of ASICs .Data path logic cell . New York 2.PLA tools -EDIF.automatic test pattern generation. 1999 Academic press. FFT processor. Keshab K. VL9261 ASIC DESIGN LTPC 300 3 UNIT I INTRODUCTION TO ASICS.Design flow .static RAM . John Wiley & Sons.Altera MAX 9000 . Jervis. Redundant Number system.

UNIT II DESIGN TECHNIQUES 9 Subgoals method.circuit extraction DRC. Monte-Carlo Methods. bucket sorting. FLOOR PLANNING. block search. Wayne Wolf. CA: Artech House Publishers.Smith. 2. R.. Prentice Hall PTR. average case and worst case behavior UNIT IV GRAPH ALGORITHMS 9 Minimum spanning. FPGA-Based System Design. bubble sort. 3. binary search. big "oh" and small "oh" notation. Addison -Wesley Longman Inc.special routing . Timing Verification of Application-Specific Integrated Circuits (ASICs). branch and bound algorithms for traveling salesman problem and knapsack problem. 2000. Prentice Hall PTR. work tracking. Amortised Analysis. PLACEMENT AND ROUTING 9 System partition . F. R-connected graphs.detailed routing . max-flow min cut theorem. 5. divide and conquer method. hill climbing techniques. Even's and Kleitman's algorithms. TOTAL: 45 PERIODS REFERENCES: 1. working backwards. 2003. System-on-a-Chip Design and Test.placement physical design flow –global routing . Introduction To Parallel Algorithms and Genetic Algorithms. stepwise refinement.FPGA partitioning . Magic Squares. heap sort. Fibonacci search. UNIT V SELECTED TOPICS 9 NP Completeness Approximation Algorithms. tree. "Application Specific Integrated Circuits. Nekoogar. From ASICs to SOCs: A Practical Approach. NP Hard Problems. UNIT III SEARCHING AND SORTING 9 Sequential search. Strasseu's Matrix Multiplication Algorithms. dynamic programming. Steiglitz's link deficit algorithm. static and dynamic complexity.J.UNIT V ASIC CONSTRUCTION. exact algorithms and heuristics. greedy methods. shortest path algorithms. Farzad Nekoogar and Faranak Nekoogar. Santa Clara. direct / indirect / deterministic algorithms. TOTAL: 45PERIODS DESIGN AND ANALYSIS OF ALGORITHMS 12 . AP9260 LTPC 3 0 03 UNIT I INTRODUCTION 9 Polynomial and Exponential algorithms. 2004.S . M. Prentice Hall PTR.partitioning methods . Rajsuman. 1999. 4. quick sort. 1997.floor planning .

component types and failure mechanisms. Pareto analysis. statistical confidence and hypothesis testing .Rivest.hazard. "Fundamentals of Computer Algorithms". 4. Analysis of load – strength interference . Design analysis methods – quality function deployment. Quality control and stress screening. specifying reliability.E. 2. Design for maintainability. quality and safety. software reliability. 1994. Reliability in electronic system design. UNIT V MANUFACTURE AND RELIABILITY MAQNAGEMENT 9 Control of production variability.L. Safety margin and loading roughness on reliability. Reliability modeling. failure reporting. Monte carlo simulation. prediction and measurement. TOTAL: 45 PERIODS 13 .E. C. Exploratory data analysis and proportional hazards modeling.H. Reliability prediction. T. Acceptance sampling. software structure and modularity.REFERENCES: 1. "Computer Algorithms : Introduction to Design and Analysis". UNIT IV RELIABILITY TESTING AND ANALYSIS 9 Test environments. Galgotia Publications. reliability growth monitoring. 3. Sara Baase. reliability demonstration. testing for reliability and durability. extreme value . hardware/software interfaces. binomial data. Electronic system reliability prediction. effects and criticality analysis. MODELLING AND DESIGN 9 Statistical design of experiments and analysis of variance Taguchi method. standard for reliability. E. Block diagram and Fault tree Analysis . failure modes.Horowitz and S. preventive maintenance strategy.Leiserson and R. Mc Graw Hill. 1988. "Genetic Algorithms : Search Optimization and Machine Learning". State space Analysis. Addison Wesley.petric Nets. Accelerated test data analysis. load strength analysis. NE9251 RELIABILITY ENGINEERING LTPC 3 0 03 UNIT I PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE 9 Statistical distribution . Addison Wesley. UNIT III ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY 9 Reliability of electronic components.Cormen. Integrated reliability programmes . Maintenance schedules. 1989.Sahni. organization for reliability. CUSUM charts. Production failure reporting. 1988. D. "Introduction to Algorithms". reliability and costs. UNIT II RELIABILITY PREDICTION. software errors.Goldberg.probability plotting techniques – Weibull. fault tolerance.

Common mode and ground loop coupling . AP9256 ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN SYSTEM DESIGN LTPC 3 003 UNIT I EMI/EMC CONCEPTS 9 EMI-EMC definitions and Units of parameters.White Consultant Incorporate. John Wiley and Sons.Ott. Transient EMI. UNIT IV EMC DESIGN OF PCBS 9 Component selection and mounting. IEC. 1998. “Engineering EMC Principles. Bonding. ESD. A Wiley Inter Science Publications. Tx /Rx Antennas. 2002 David J. Power distribution decoupling. 2000. Klinger. FCC. Cross talk control. “Principles of Electromagnetic Compatibility”. cross talk . O’Connor. Civilian standards-CISPR. Wiley International. Menendez. Measurements and Technologies”. "AT & T Reliability Manual". UNIT V EMI MEASUREMENTS AND STANDARDS 9 Open area test site. EN. VIAs connection.P. John Wiley and Sons. 1986. Sensors. Routing. TEM cell. 3. Patrick D.. 14 . Injectors / Couplers. 2. 2. Inc. Filtering. 5. Lewis. 5th Edition. David Newton and Richard Bromley.Paul. Grounding. Common ground impedance coupling . Artech house. Grounding. Yoshinao Nakada and Maria A. Military standards-MIL461E/462. 1996.HALT and HASS". V. Field to cable coupling . Terminations. 3rd Ed. Sources and victim of EMI. 4. 2nd Edition. 1988.J. "Introduction to Reliability Engineering". 1996. Bemhard Keiser. Isolation transformer.”Noise Reduction Techniques in Electronic Systems”. Henry W. New York. "Accelerated Reliability Engineering . Radiation Hazards. John Wiley & Sons. Fourth edition.T. C. Conducted and Radiated EMI Emission and Susceptibility. 4. Newyork. 1992. Gregg K. 3. John Wiley & Sons. Transient suppressors. Differential mode coupling . and coupling factors. UNIT II EMI COUPLING PRINCIPLES 9 Conducted. Don R. “Handbook of EMI/EMC” . IEEE Press. Practical Reliability Engineering. Newyork. UNIT III EMI CONTROL TECHNIQUES 9 Shielding. TOTAL: 45 PERIODS REFERENCES: 1. EMI test shielded chamber and shielded ferrite lined anechoic chamber. Cable routing. 1988.”Introduction to Electromagnetic Compatibility” .R. Norwood. Power mains and Power supply coupling. Signal control.REFERENCES: 1. Hobbs.Kodali. Von Nostrand Reinhold. New York. PCB trace impedance. EMI Rx and spectrum analyzer. Near field cable to cable coupling. radiated and transient coupling. Zoning. Vol I-V.

WIDJAJA.ATM.CP9212 HIGH PERFORMANCE COMPUTER NETWORKS LTPC 30 0 3 9 UNIT I INTRODUCTION Review of OSI.A top down approach featuring the internet”.differentiated services. site-to-site VPN. Traffic Engineering.Mir . 6. 5.J. TMH seventh reprint 2002. Kurose & K. MPLS based VPN. UNIT III ADVANCED NETWORKS CONCEPTS 9 VPN-Remote-Access VPN. UNIT IV TRAFFIC MODELLING 8 Little’s theorem. SNMP. “Communication networks”. Poisson modeling and its failure. overlay networks-P2P connections. Larry l. Ross. UNIT V NETWORK SECURITY AND MANAGEMENT 10 Principles of cryptography – Authentication – integrity – key distribution and certification – Access control and: fire walls – attacks and counter measures – security in many layers. Security and administration – ASN. Walrand . Security in VPN. Fred Halsall and Lingana Gouda Kulkarni. “IP Telephony. Network performance evaluation. SONET – DWDM – DSL – ISDN – BISDN. Modes of Communication. 2nd edition. High performance communication network.W.David.1 TOTAL:45 PERIODS REFERENCES: 1. Morgan Kaufmann Publishers. Routing. 4.”Computer Networking. Aunurag kumar. “Communication Networking”. “Computer Networks: A System Approach”1996 15 . first edition. Joy kuri.F. 7 8. 2. Tunneling and use of FEC. LEOM-GarCIA. Pearson education 2003. Need for modeling .MPLSoperation. TCP/IP. MIB. Ltd. MAnjunath. Hersent Gurle & petit. 2000.Computer and Communication Networks. Routing. Switching. Pearson education Nader F. 2nd Edition.poisson models. Varatya. Morgan Kauffman – Harcourt Asia Pvt. 2003. 3. J. Pearson. Infrastructure for network management – The internet standard management framework – SMI. packet Pored Multimedia communication Systems”. Tunneling to PPP.”Computer Networking and the Internet” fifth edition. 1ed 2004.Peterson & Bruce S. D. UNIT II MULTIMEDIA NETWORKING APPLICATIONS 9 Streaming stored Audio and Video – Best effort service – protocols for real time interactive applications – Beyond best effort – scheduling and policing mechanism – integrated services – RSVP. Multiplexing. Non.

Colpitts oscillators – Resonators – Tuned Oscillators – Negative resistance oscillators – Phase noise TOTAL: 45 PERIODS TEXT BOOKS: 1. C. B. Sensitivity. popcorn noise Transceiver Specifications: Two port Noise theory. Root-locus techniques – Time and Frequency domain considerations – Compensation Power Amplifiers: General model – Class A. “Design of CMOS RF Integrated Circuits”. 2001. Noise Figure. Kluwer Academic Publishers. Common Source Amplifiers – OC Time constants in bandwidth estimation and enhancement – High frequency amplifier design Low Noise Amplifiers: Power match and Noise match – Single ended and Differential LNAs – Terminated with Resistors and Source Degeneration LNAs.AP9258 UNIT I RF SYSTEM DESIGN LTPC 3 003 CMOS PHYSICS. shot. Low IF Architectures – Transmitter: Direct upconversion.Impedance matching networks Amplifiers: Common Gate. 1997 4. 1997 3. “CMOS Wireless Transceiver Design”. D. Cambridge. T. B. 16 . “Design of Analog CMOS Integrated Circuits”.Specification distribution over a communication link Transceiver Architectures: Receiver: Homodyne. McGraw Hill. Image reject. Two step upconversion UNIT II IMPEDANCE MATCHING AND AMPLIFIERS 9 S-parameters with Smith chart – Passive IC components . TRANSCEIVER SPECIFICATIONS AND ARCHITECTURES 9 CMOS: Introduction to MOSFET Physics – Noise: Thermal. 2004 2. B. flicker. Heterodyne. IP2.Razavi. THD.Razavi. AB. UNIT III FEEDBACK SYSTEMS AND POWER AMPLIFIERS 9 Feedback Systems: Stability of feedback systems: Gain and phase margin. Jan Crols. Michiel Steyaert.Lee. “RF Microelectronics”. Pearson Education. E and F amplifiers – Linearisation Techniques – Efficiency boosting techniques – ACPR metric – Design considerations UNIT IV PLL AND FREQUENCY SYNTHESIZERS 9 PLL: Linearised Model – Noise properties – Phase detectors – Loop filters and Charge pumps Frequency Synthesizers: Integer-N frequency synthesizers – Direct Digital Frequency synthesizers UNIT V MIXERS AND OSCILLATORS 9 Mixer: characteristics – Non-linear based mixers: Quadratic mixers – Multiplier based mixers: Single balanced and double balanced mixers – subsampling mixers Oscillators: Describing Functions. IP3. SFDR. Phase noise .

6. DESIGNING CMOS CIRCUITS FOR LOW POWER.B.VL9252 LOW POWER VLSI DESIGN LTPC 300 3 UNIT I POWER DISSIPATION IN CMOS 9 Hierarchy of limits of power – Sources of power consumption – Physics of power dissipation in CMOS FET devices. Low power digital VLSI design.1995. Abdellatif Bellaouar. Low power digital CMOS design. UNIT V SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER 9 Synthesis for low power –Behavioral level transforms.Chandrakasan and R.Mohamed. Kluwer. Practical low power digital VLSI design. K. Wiley.2000 2. UNIT II POWER OPTIMIZATION 9 Logical level power optimization – Circuit level low power design – Circuit techniques for reducing power consumption in adders and multipliers. Elmasry.s Kluwer. Low voltage CMOS VLSI Circuits. 5. 7. Kluwer. 4. Kluwer. Costas Goutis.W.I. UNIT III DESIGN OF LOW POWER CMOS CIRCUITS 9 Computer Arithmetic techniques for low power systems – Reducing power consumption in memories – Low power clock.2002 3.1998. Prasad . Dimitrios Soudris. Low voltage SOI CMOS VLSI Devices and Circuits. Wiley 1999. A. Shin – chia Lin. James B.H Lou. J.P. Kuo. LOW POWER CMOS VLSI circuit design. Kuo and J. Chirstian Pignet.C. Gary Yeap. Interconnect and layout design – Advanced techniques – Special techniques UNIT IV POWER ESTIMATION 9 Power estimation techniques – Logic level power estimation – Simulation power analysis – Probabilistic power analysis. Broadersen. John Wiley and sons. inc 2001 17 .Roy and S. 1995.Basic principle of low power design.Software design for low power TOTAL : 45 PERIODS REFERENCES: 1.

multiple constant multiplication. iteration bound. combined pipelining and parallel processing of IIR filters. WAVE AND ASYNCHRONOUS PIPELINING 9 Numerical strength reduction – subexpression elimination. DCT architecture. Wiley. modified Cook-Toom algorithm. Unfolding – an algorithm for unfolding. “ VLSI Digital Signal Processing Systems. UNIT III FAST CONVOLUTION. 2007. Loop bound. Interscience. 2004 18 . 2-parallel fast FIR filter. Longest path matrix algorithm. parallel carry-ripple and carry-save multipliers. Parallel processing of IIR filters. wave pipelining. state variable description of digital filters. scaling and round-off noise computation. Springer. PIPELINING AND PARALLEL PROCESSING OF IIR FILTERS 9 Fast convolution – Cook-Toom algorithm. Distributed Arithmetic fundamentals and FIR filters UNIT V NUMERICAL STRENGTH REDUCTION. synchronous pipelining and clocking styles. sample period reduction and parallel processing application. Bit-level arithmetic architectures – parallel multipliers with sign extension. two-phase clocking. Odd-Even merge-sort architecture. properties of unfolding. Clustered look-ahead pipelining. ALGORITHMIC STRENGTH REDUCTION 9 Retiming – definitions and properties.VL9253 VLSI SIGNAL PROCESSING LT PC 3 0 0 3 UNIT I INTRODUCTION TO DSP SYSTEMS. round-off noise in pipelined IIR filters. clock skew in edge-triggered single phase clocking. parallel rankorder filters. Keshab K. TOTAL : 45 PERIODS REFERENCES: 1. CSD representation. Algorithmic strength reduction in filters and transforms – 2-parallel FIR filter. bit-serial FIR filter. round-off noise. SYNCHRONOUS. Look-Ahead pipelining with power-of-2 decomposition. Pipelining and Parallel processing for low power. iterative matching. rank-order filters. Second Edition. U. Pipelined and parallel recursive filters – Look-Ahead pipelining in first-order IIR filters. PIPELINING AND PARALLEL PROCESSING OF FIR FILTERS 9 Introduction to DSP systems – Typical DSP algorithms. Asynchronous pipelining bundled data versus dual rail protocol. 2. CSD multiplication using Horner’s rule for precision improvement. “ Digital Signal Processing with Field Programmable Gate Arrays”. Parhi. Meyer – Baese. ROUND-OFF NOISE. Data flow and Dependence graphs . UNIT II RETIMING.critical path. BIT-LEVEL ARITHMETIC ARCHITECTURES 9 Scaling and round-off noise – scaling operation. Design of Lyon’s bit-serial multipliers using Horner’s rule. Design and implementation “. UNIT IV SCALING. Pipelining and Parallel processing of FIR filters.

Mc Graw Hill International Company. 1998. 2.May. Terri Fiez. Lan C. ANALOG COMPUTERAIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT 9 Review of Statistical Concepts . “Analog VLSI signal and Information Processing ".Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS. Phillip E.Haskard. " Noel K. VLSI Design Techniques for Analog and Digital Circuits ". “Design of Analog-Digital VLSI Circuits for Telecommunication and signal Processing ". Malcom R. 1994. Yannis Tsividis.Floating . OVER SAMPLED A/D CONVERTERS AND ANALOG INTEGRATED SENSORS 9 First-order and Second SC Circuits-Bilinear Transformation . Prentice Hall. Jose E. 1994 19 .NMOS and CMOS ".Statistical Circuit SimulationAutomation Analog Circuit Design-automatic Analog Layout-CMOS Transistor LayoutResistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout. Randall L Geiger. Mohammed Ismail. TOTAL : 45 PERIODS REFERENCES: 1.France. UNIT V STATISTICAL MODELING AND SIMULATION.VL9254 ANALOG VLSI DESIGN LTPC 3 00 3 UNIT I BASIC CMOS CIRCUIT TECHNIQUES. “Analog VLSI Design .Statistical Device Modeling. Humidity and Magnetic Sensors-Sensor Interfaces. CONTINUOUS TIME AND LOWVOLTAGESIGNAL PROCESSING 9 Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOSTransistor. CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING 9 Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks . Low-Power Neural Networks-CMOS Technology and ModelsDesign Methodology-Networks-Contrast Sensitive Silicon Retina. Prentice Hall. McGraw-Hill International Editons.Nyquist rate A/D ConvertersModulators for Over sampled A/D Conversion-First and Second Order and Multibit SigmaDelta Modulators-Interpolative Modulators –Cascaded Architecture-Decimation Filtersmechanical. 4. Thermal. 1990. UNIT IV DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS 9 Fault modelling and Simulation . 3. UNIT II BASIC BICMOS CIRCUIT TECHNIQUES.Gate. Allen. UNIT III SAMPLED-DATA ANALOG FILTERS.Cascade Design-SwitchedCapacitor Ladder Filter-Synthesis of Switched-Current Filter.Strader. Bipolar and Low-Voltage BiCMOS OpAmp Design-Instrumentation Amplifier Design-Low Voltage Filters.Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test BusesDesign for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits.

Circuit representation .problem formulation . UNIT II DESIGN RULES 9 Layout Compaction .Assignment problem .global routing .Placement algorithms . 2.Types of local routing problems .Algorithmic Graph Theory and Computational Complexity . CAD FOR VLSI CIRCUITS AP9259 HARDWARE SOFTWARE CO-DESIGN LTPC 3 0 03 UNIT I SYSTEM SPECIFICATION AND MODELLING 9 Embedded Systems .2002. UNIT IV SIMULATION 9 Simulation .Internal representation . TOTAL: 45 PERIODS REFERENCES : 1. Single-Processor Architectures with one ASIC .A. UNIT V MODELLING AND SYNTHESIS 9 High level Synthesis .Design rules .VL9221 LTPC 3 003 UNIT I VLSI DESIGN METHODOLOGIES 9 Introduction to VLSI Design methodologies .algorithms for constraint graph compaction .Two Level Logic Synthesis.placement and partitioning .Binary Decision Diagrams .general purpose methods for combinatorial optimization. Models of Computation .shape functions and floorplan sizing .Simple scheduling algorithm . Co-Design for System Specification and Modelling .Hardware models .partitioning UNIT III FLOOR PLANNING 9 Floor planning concepts . 20 .Area routing . Hardware/Software Co-Design . John Wiley & Sons. Multi-Processor Architectures .channel routing .Allocation assignment and scheduling . Co-Design for Heterogeneous Implementation .Gate-level modeling and simulation .Requirements for Embedded System Specification . Kluwer Academic Publishers. Single-Processor Architectures with many ASICs.High level transformations. 2002. Sherwani.algorithms for global routing.Switch-level modeling and simulation .Tractable and Intractable problems .Review of Data structures and algorithms Review of VLSI Design automation tools . N. S.H. "Algorithms for VLSI Physical Design Automation". "Algorithms for VLSI Design Automation". Comparison of CoDesign Approaches . Gerez.Processor Synthesis .Combinational Logic Synthesis .

Specification Specification simulation DESIGN SPECIFICATION AND VERIFICATION 9 Coordinating Concurrent Computations. Target Architectures and Application System Classes.Design Representation for System Level Synthesis. Verification . Prototyping and Emulation Techniques . Refinement and Controller Generation. Optimization . 3.1997. System Level Languages. Kluwer Academic Pub. HW/SW Partitioning based on Genetic Algorithms . Hardware-Software Cost Estimation.Target ArchitectureArchitecture Specialization Techniques . Ralf Niemann . HW/SW Partitioning based on Heuristic Scheduling. Architectures for Data-Dominated Systems .”Hardware/Software Co-Design: Principles and Practice” .Future Developments in Emulation and Prototyping . Kluwer Academic Pub. State-Transition Graph. Generation of the Partitioning Graph . 2.System Communication Infrastructure. Heterogeneous Specification and Multi-Language CoTOTAL: 45 PERIODS REFERENCES: 1. Prototyping and Emulation Environments .Mixed Systems and Less Specialized Systems UNIT V Concurrency. UNIT III HARDWARE/SOFTWARE CO-SYNTHESIS 9 The Co-Synthesis Problem. Languages for System-Level Specification and Design System-Level . Rolf Ernst Morgon. Distributed System Co-Synthesis UNIT IV PROTOTYPING AND EMULATION 9 Introduction. “Hardware/Software Co-Design for Data Flow Dominated Embedded Systems”. Formulation of the HW/SW Partitioning Problem . Interfacing Components. Wayne Wolf . Architectures for Control-Dominated Systems.2001. 1998. 21 .” Reading in Hardware/Software Co-Design “ Kaufmann Publishers. Jorgen Staunstrup .UNIT II HARDWARE/SOFTWARE PARTITIONING 9 The Hardware/Software Partitioning Problem. Giovanni De Micheli .