EECS140 ANALOG CIRCUIT DESIGN INTRODUCTION

University of California
Berkeley
College of Engineering
Department of Electrical Engineering
and Computer Science

Robert W. Brodersen
EECS140
Analog Circuit Design

ROBERT W. BRODERSEN LECTURE 1

EECS140 ANALOG CIRCUIT DESIGN INTRODUCTION

I-1
EECS 140
ANALOG INTEGRATED CIRCUITS

Robert W. Brodersen, 2-1779, 402 Cory Hall, rb@eecs.berkeley.edu

This course will focus on the design of MOS analog integrated circuits with extensive use of Spice for the simulations.
In addition, some applications of analog integrated circuits will be covered which will include RF amplification and dis-
crete and continuous time filtering. Though the focus will be on MOS implementations, comparison with bipolar circuits
will be given.

Required Text
Analysis and Design of Analog Integrated Circuits, 4th Edition, P.R. Gray, P. Hurst, S. Lewis and R.G. Meyer, John Wiley
and Sons, 2001

Supplemental Texts
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
Thomas Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press, 1998
The SPICE Book, Andre Vladimirescu, John Wiley and Sons, 1994
Prerequisites
EECS 105: Microelectronic Devices and Circuits

ROBERT W. BRODERSEN LECTURE 1

EECS140 ANALOG CIRCUIT DESIGN INTRODUCTION

IC Design Course Structure at Berkeley I-2

EE40

EE105

EE140 EE142 EE141

Linear/Analog Non-Linear Digital

Linear Design

Sensors, Interface Digital

Transducers Circuits Processing

Amplifiers, Filters, A/D & D/A’s

ROBERT W. BRODERSEN LECTURE 1

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

University of California
Berkeley
College of Engineering
Department of Electrical Engineering
and Computer Science

Robert W. Brodersen
EECS140
Analog Circuit Design

Lectures
on
MOS DEVICE MODELS

ROBERT W. BRODERSEN LECTURE 2

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

M-1
Assumed Knowledge

a) KCL, KVL - Kirchoff Laws

b) Voltage, Current Dividers

c) Thevenin, Norton Equivalents

d) 2-Port Equivalents

e) Phasors, Frequency Response

ROBERT W. BRODERSEN LECTURE 2

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

2-Port Equivalent Circuit M-2

RL → ∞
(Voltage in - Voltage out) ν
i in iout R in = -----in
iin iout → 0
+
Rs + Rout ν out
+- ν in +- νout R out = -------
i out
Vs
Rin a ν ⋅ ν in RL
RS = ν i n = 0

- - ν out
A ν = -------
νin RL → ∞

i in iout
+ + + +
Rout1 Rout2
+- νin1 +- ν out1 νin2 +- νout
Vs
Rin1 a ν1 ⋅ ν in1 -
Rin2 a ν2 ⋅ ν in2
- - -

ν out = aν2 ⋅ νin2 = aν2 ⋅ νout1 = aν2 ⋅  a ν1 ⋅ ν in1 ⋅  -----------------------

R in2 - 
R out1 + R in 2 
ROBERT W. BRODERSEN LECTURE 2
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

M-3
MOS Large Signal Equations

D
n-channel
IDS

G B
VDSAT
VGS
IDS
NMOS
Saturation S

G
Linear
Cutoff
S D
L
VDS
n n
p

ROBERT W. BRODERSEN LECTURE 2

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

M-4
MOS Large Signal Equations (Cont.)
Cutoff :
V GS < V T

Linear :
V GS > V T
VDS < V DSAT = VGS – VT

I DS = k' ⋅ ----- ⋅  V GS – VT – -------  ⋅ V DS

W VDS
L  2
Saturated :
V GS > V T
VDS > V DSAT = VGS – VT

I DS = k'
--- ⋅ W
----- ⋅ ( VGS – VT ) 2 ( 1 + λ ⋅ VDS )
2 L
ROBERT W. BRODERSEN LECTURE 2
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

MOS Large Signal Equations (Cont.) M-5

1 1
-- --
V T = V To + γ ⋅ [ ( 2 ⋅ φ f + V SB ) – ( 2 ⋅ φf ) ]
2 2

( VS B > 0 )
V To ≡ Threshold Voltage @ V S B = 0
φ f ≡ Fermi Potential ≈ 0.3 µ

γ ≡ Body Effect Factor

λ ≡ Short Channel Effect E = VDS /L

W ≡ Width of Device
L ≡ Length νε

k' = µ ⋅ C ox
Oxide Capacitance E
mobility

ROBERT W. BRODERSEN LECTURE 2

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

MOS Large Signal Equations (Cont.) M-6

Body Effect :
G
1
-- VT
V To + γ ⋅ V 2
SB S ++++++++ D

n n

1 ⋅ 2⋅ q⋅ ε⋅ N
γ = ------ A
Cox VTo

VBS

ROBERT W. BRODERSEN LECTURE 2

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

MOS Large Signal Equations (Cont.) M-7

Short Channel Effect (λ):

S G D

XJ = Junction Depth
XD

LD = Lateral Diffusion ~ 0.75 XJ

Ldrawn

L = Ldrawn – 2 ⋅ L D
L EFF = L – X D
XD = f ( VDS )

ROBERT W. BRODERSEN LECTURE 2

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

MOS Large Signal Equations (Cont.) M-8

I D( A) = k' W ⋅ ( V – V )2
--- ⋅ -------- GS T
2 LEFF
Modeled as
I D( B ) = k'
--- ⋅ W
----- ⋅ ( VGS – VT ) 2 ⋅ ( 1 + λ ⋅ VDS )
2 L
∂I D( B)
= λ ⋅ I DS
∂ V DS

∂I (DA) k' W dL EFF

= – --- ⋅ -------- ⋅ ( V – V ) 2
⋅
∂ VDS 2 L 2EFF GS T
d V DS

∂I (DA) I D dXD
= -------- ⋅ = λ ⋅ ID
∂ VDS L EFF d VDS

ROBERT W. BRODERSEN LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

MOS Large Signal Equations (Cont.)

λ = -------- ⋅  D  ≈ --- ⋅  D 
1 dX 1 dX
L EFF d VDS L d V DS
Weak function of VDS
1
2 ⋅ ε ⋅ ( VDS – V DSAT )
-
2
XD ≈ -------------------------------------------
q ⋅ NA

Fixed → ε = Dielectric constant of silicon

NA = Substrate doping

1 1
1  2 ⋅ ε 2 
- -
dX D 1 
= --- ⋅  -------------  ⋅  ------------------------ 
2

d V DS 2 q ⋅ NA V DS – VDSAT

ROBERT W. BRODERSEN LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

M-9
MOS Large Signal Equations (Cont.)

λIDS
IDS
W
S D
Ideal Longer Channel L
(Increasing L)

VDS
W/L is the parameter of interest

CG ∝ W ⋅ L ⋅ C OX

ROBERT W. BRODERSEN LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

M-10
M-11
MOS Small Signal Model (Low Frequency)

IDS
G D
+ gmνgs
VGS ro
gmbsνbs
-
S B
VSB -
+

dI DS dI DS dI DS
I DS = ⋅ ν gs + ⋅ νbs + ⋅ ν ds
d V GS d V BS d VDS











gm gmbs 1/ro

ROBERT W. BRODERSEN LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

MOS Small Signal Model (Cont.) M-12

In Saturation :
dI DS W
gm = = k' ⋅ ----- ⋅ ( V GS – VT ) ⋅ ( 1 + λ ⋅ VDS )
d V GS L
1
--

g m ≈ k' ⋅ ----- ⋅ ( V GS – V T ) = k' ⋅ ----- ⋅ VDSAT =  2 ⋅ k' ⋅ ----- ⋅ I DS

W W W 2

L L L
What is VDSAT ?
I DS = k'
--- ⋅ W
----- ⋅ ( VGS – VT ) 2 = k'
--- ⋅ W
----- ⋅ V 2DSAT and from above,
G 2 L 2 L
+
g m = k' ⋅ W
----- ⋅ VDSAT so,
S L
- 1
2 ⋅ I DS 
-

V DSAT =  --------------------
2
VGS = VT + V DSAT
k' ⋅ W ⁄ L

ROBERT W. BRODERSEN LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

MOS Small Signal Model (Cont.) M-13

gmbs calculation :
dI DS W dV
g mbs = g mb = = – k' ⋅ ----- ⋅ ( V GS – VT ) ⋅ ( 1 + λ ⋅ VDS ) ⋅ T
d V BS L d VBS
dV T γ - ≡ –χ
= – ----------------------------------------
d VBS 2 ⋅ ( 2 ⋅ φf + V S B ) 0.5

g mbs = k' ⋅ W
----- ⋅ ( V GS – V T ) ⋅ ( 1 + λ ⋅ VDS ) ⋅ χ
L












 gm

g
-------
mbs
= χ γ
χ = ----------------------------------------
-
gm 2 ⋅ ( 2 ⋅ φ f + V SB ) 0.5

ROBERT W. BRODERSEN LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

MOS Small Signal Model (Cont.) M-14

Cox

0.23 G

g-------
= χ
mbs
S D
gm
n n

0.1 Cjs
-5V VBS 0V
Qchannelduetovgs ≈ Cox ⋅ ν gs
γ = 0.5
φf = 0.3 Qchannel duetovbs ≈ Cjs ⋅ νbs
k’ = 90e-6 Cjs
λ = 0.01 χ = ------
C ox
VTo=0.7

ROBERT W. BRODERSEN LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

MOS Small Signal Model (Cont.) M-15

ro calculation :
1
--- 
= g mds =
dI DS
=
d  k' W
--- ⋅ ----- ⋅ ( V GS – V T ) 2 ⋅ ( 1 + λ ⋅ V DS ) 
ro  d V DS d V DS 2 L 

1 k' W
--- = --- ⋅ ----- ⋅ ( VGS – VT ) 2 ⋅ λ
ro 2 L

1
--- = λ ⋅ I DS
ro

1
r 0 = -------------
λ ⋅ I DS

ROBERT W. BRODERSEN LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

MOS Small Signal Model (Cont.) M-16

Comparison with Spice Level 1:

VTO = V To ∼ 0.5 → 1.0V

PHI = 2 ⋅ φf ∼ 0.6

GAMMA = γ ∼ 0.05 → 0.5

LAMBDA = λ ∼ 0.01 → 0.1

A-
KP = k' = µ ⋅ Cox ∼ nmos → 50 – 100µ ----
V2
pmos ≈ 1--- nmos
3

ROBERT W. BRODERSEN LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

MOS Small Signal Model (Cont.)

Summary:
1
--
2 ⋅ I DS
g m ≈  2 ⋅ k' ⋅ ----- ⋅ I DS = k' ⋅ ----- ⋅ V DSAT = -------------
W W2

L L VDSAT
g mbs = χ ⋅ gm
γ
χ = ----------------------------------------
- V DSAT = V GS – V T
2 ⋅ ( 2 ⋅ φ f + VSB ) 0.5

1
2 ⋅ I DS 
-

V GS = VT +  --------------------
1 2
r 0 = -------------
λ ⋅ I DS k' ⋅ W ⁄ L
I-----DS V GS – V T VDSAT
gm
= ------------------ = ----------
2 2 I DS = k'
--- ⋅ W
----- ⋅ ( V GS – V T ) 2
1
2 L
2 ⋅ I DS 
--

=  --------------------
2 1- 1-
VDSAT V T = V To + γ ⋅ [ ( 2 ⋅ φ f + VSB ) – ( 2 ⋅ φ f ) ]
2 2

k' ⋅ W ⁄ L

ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

University of California
Berkeley
College of Engineering
Department of Electrical Engineering
and Computer Science

Robert W. Brodersen
EECS140
Analog Circuit Design

Lectures
on
SPICE

ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-1
Spice Transistor Model :
M1 1 2 3 4 nch L=1µ W=10µ

AD=( ) AS=( ) PD=( ) PS=( ) NRD=( )

parasitic resistors

G area of drain

1
W
S D 2 4
L
3

ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-2
SPICE
Initial Operationg Point
DC currents and Voltages

Linearize New Operating

Around OP Point Point
No Analysis Types :
DC op point .op
Solve Eqn. DC Converge? DC sweeps
Yes AC & Transient
Increment Time

No End of Yes STOP

Time Interval

ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

4 VA SP-3

+-
R4 I4 Gi = 1/Ri
2
1 3
I1 +- VB R1 R2 R3

Node 1 : ( G 1 + G4 ) ⋅ V 1 – G 1 ⋅ V2 – G 4 ⋅ V4 + I 1 = 0
Node 2 : – G 1 ⋅ V 1 + ( G 1 + G 2 + G3 ) ⋅ V 2 – G 3 ⋅ V 3 = 0

Node 3 : – G 3 ⋅ V2 + G 3 ⋅ V 3 – I4 = 0
Node 4 : –G 4 ⋅ V1 – G 4 ⋅ V4 + I 4 = 0
V1 = VB

–V3 –V4 = VA

ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-4

G1+G4 -G1 0 -G4 1 0 V1 0

-G1 G1+G2+G3 -G3 0 0 0 V2 0
0 -G3 -G3 0 0 -1 V3 0
=
-G4 0 0 -G4 0 1 V4 0
1 0 0 0 0 0 I1 VB
0 0 -1 1 0 0 I4 VA
Current src

G F V C Total # of EQNS N=n + nv + nl

= n = # of circuit nodes
nv= # of independent voltage srcs
B R I E
nl= # of inductors
Votlage src
ROBERT W. BRODERSEN LECTURE 4
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-5
Matrix Solution

A x = b
we need
Solve by Gaussian Elimination
(0) denotes iteration step

e (10) a (110) a (120) a(130) x 1 b (10)

e (20) a (210) a (220) a(230) x 2 = b (20)
e (30) a (310) a (320) a(330) x 3 b (30)

Eliminate a21,a31
(0 ) (0 )
x x x
e (11) = e (10) e (21) = e (20) – a------
21
⋅ e (0 )
1 e (31) = e (30) – a------
31
⋅ e (0 )
1 0 x x
a (110) a (110)
0 x x

ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-6
Then eliminate a32(1)
e (12) = e (11) x x x
e (22) = e (21) Upper triangular matrix
0 x x
a (1 ) can be solved
e ( 2)
3
( 1)
= e – ------
3
32
⋅ e (1 )
2
00 x
a (221)

a (112) a (122) a(132) x 1 b (10)

0 a (222) a(232) x 2 = b (21)
0 0 a(332) x 3 b (32)
b (32 )
x 3 = ------
a (332)
( b (21 ) – a (231) ⋅ x 3 ) Solution
x 2 = --------------------------------
( 1)
-
a 22
( b (10) – a (130) ⋅ x 3 – a (120) ⋅ x 2 )
x 1 = ------------------------------------------------------
a (110)

ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-7
Accuracy
Can’t divide by 0 or small numbers, so pivoting is used
to reorder eqn’s (Basically renumbering nodes). Puts
maximum values on diagonal.
R1=1Ω
1 –1 V1 = 1
– 1 1.0001 V 2 0
1 1-
-- – -------- = G1 + G 2
1 10k
1A R2=10kΩ
If the computer only has 4
digits of precision then we get,

Actually, V1 – V2 = 1
1 –1 V 1 = 1
–V1 + V2 = 0
V 1 = 10, 001V –1 1 V2 0
V 1, V 2 = ∞
V 2 = 10, 000V

ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-8
To control accuracy
.options PIVTOL = <values> (1018)
This sets the allowable range of conductance values.

*ERROR* : Maximum entry ......at

STEP ....... is less than PIVTOL
-Probably means you have an incorrect element
or floating node

ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-9
Solution of the DC equations with non-linear models

VD

ID = I S ⋅  e – 1
---------
VTH

 

IG = G ⋅ V

Need to find
+ IA this point
IG
VD
IA G
IG - ID ID,G
ID

ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-10
Newton-Raphson Iteration :

- Make guess of next operation point in iteration

Start at initial guess and linearize diode eqn.

VD(0) ID0
IA G GD0
-

ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-11

Current value Solution finds this point

ID0
Slope of GD0
ID

VD

Solve for VD,

Linearize at this point
becomes VD(1)
Find new point

ROBERT W. BRODERSEN LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE

SP-12
Convergence

Keep iterating until all voltages and currents are within a

a tolerance value.
V(ni) = node voltage n at iteration i
ε Vn = REL ( V ) ⋅ max ( V(ni + 1) , V (ni ) ) + ABS ( V )

The convergence check is :

V (ni + 1) – V (ni ) ≤ ε Vn
REL ( V ) ∼ 10 –4 (Default 10 –3 )
ABS ( V ) ∼ 10 –6 (Default 50µV )
ABS(V) should be at least two orders of magnitude below
required accuracy.
These values would give 1 part in 104 accuracy down to
100µV resolution
ROBERT W. BRODERSEN LECTURE 4
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS

SP-13

Current convergence is broken into two types; MOS and NOT MOS
ABSMOS ∼ ABSOLUTE ( 10 –6 )
MOS
RELMOS ∼ RELATIVE ( 0.5 )

ABSI ∼ ABSOLUTE( 10 – 9 )
NOTMOS
RELI ∼ RELATIVE ( 0.01 )

ITL = # of steps in iteration (200)

When you get
*ERROR* no convergence in DC analysis and the last node voltages
Then it hasn’t converged in 200 times - something is probably
wrong with your netlist

ROBERT W. BRODERSEN LECTURE 2