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IEEE TRANSACTIONS ON ELECTRON DEVICES 1

Evaluation of Monolayer and Bilayer

2-D Transition Metal Dichalcogenide
Devices for SRAM Applications
Chang-Hung Yu, Student Member, IEEE, Ming-Long Fan, Kuan-Chin Yu,
Vita Pi-Ho Hu, Member, IEEE, Pin Su, Member, IEEE, and Ching-Te Chuang, Fellow, IEEE

Abstract— For the first time, we comprehensively evaluate

6T SRAM stability and performance using monolayer and bilayer
transition metal dichalcogenide (TMD) devices based on the
ITRS 2028 (5.9 nm) node. Our study indicates that, with excellent
device electrostatics and superior stability, the monolayer TMD
is favored for low-power SRAM applications, while the bilayer
TMD, with higher carrier mobility, is more suitable for relaxed
channel length and high-performance SRAM applications.
Index Terms— 2-D materials, bilayer, monolayer, SRAM cell,
transition metal dichalcogenide (TMD).

I. I NTRODUCTION

C ONTINUAL lateral scaling of channel length and vertical

scaling of gate-dielectric thickness and channel thickness
of CMOS transistors have led to enhanced density, power–
speed performance, and functionality of VLSI chips [1].
Because of their atomic-scale thickness and pristine surfaces
(without dangling bonds) [2], [3], 2-D semiconducting tran-
sition metal dichalcogenides (TMDs), such as MoS2 and
WSe2 , have emerged as potential channel materials for future
ultimately scaled low-power (LP) CMOS devices [3]–[16].
In addition, unlike graphene with zero bandgap (E g ) [17],
these 2-D TMD materials inherently possess adequate E g
(e.g., E g ∼ 1.8 and ∼1.6 eV for monolayer MoS2 and WSe2 ,
respectively [3]), making them suitable for low-power logic
applications. Fig. 1(a) shows the schematic atomic structure
of monolayer and bilayer MoS2 and WSe2 .
Bilayer TMD devices have been shown to exhibit higher
mobility at the expense of device electrostatics compared with
monolayer TMD devices [8], [11]–[15]. The higher mobility
of bilayer TMD may stem from the partially screened interface
scattering [11]. Wang et al. [12], [13] have reported that the
mobility of bilayer TMD can be ∼1.6× of monolayer TMD.
W. Cao et al. [6] have pointed out that the mobility ratio
may be ∼2×. It has also been experimentally demonstrated
Manuscript received August 17, 2015; revised November 9, 2015; accepted
November 25, 2015. This work was supported in part by the Ministry of
Science and Technology, Taiwan, under contracts MOST 104-2221-E-009-
119 and MOST 104-2911-I-009-301 (I-RiCE), and in part by the Ministry of
Education, Taiwan, under the ATU program. The review of this paper was
arranged by Editor G.-H. Koh. (Corresponding authors: Pin Su.)
The authors are with the Department of Electronics Engineering, Insti-
tute of Electronics, National Chiao Tung University, Hsinchu 30010,
Taiwan (e-mail: pinsu@faculty.nctu.edu.tw).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2015.2505064
0018-9383 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Fig. 1. (a) Schematic atomic structure of MoS2 /WSe2 . The thickness
of monolayer TMDs is ∼0.7 nm [3]. Layers are held together by weak
van der Waals interactions. (b) Circuit schematic of a 6T SRAM cell. The
PU, PD, and PG stand for pull-up, pull-down, and pass-gate transistors,
respectively. The WL and BL stand for word-line and bit-line, respectively.
(c) SRAM cell composed of extremely scaled MoS2-n/WSe2-p devices.
up to ∼6× at room temperature in [14]. In addition, it is
believed that the contact resistance (and hence source/drain
series resistance) can be different for monolayer and bilayer
TMD devices [11], [26], [28], [29], even though the underlying
mechanism is unclear yet. The monolayer MoS2 devices have
been reported to possess higher contact resistance (compared
with bilayer or few layer MoS2 ) in [11] and [28], whereas con-
trary results (monolayer MoS2 with lower contact resistance)
have also been found in [26]. These uncertainties (mobility
ratio and contact resistance) may influence the benchmarking
of monolayer and bilayer SRAMs.
While the scalability and performance potential of the MoS2
and WSe2 devices have been investigated [6]–[10], a thorough
study of the extremely scaled TMD devices for SRAM appli-
cations is lacking. In this paper, for the first time, we evaluate
the SRAM stability and performance using monolayer and
bilayer TMD devices based on the ITRS 2028 (5.9 nm) tech-
nology node. The tradeoff between electrostatic integrity (EI)
(monolayer favored) and carrier mobility (bilayer favored),
the impacts of the mobility ratio and source/drain series
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2 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 2. IDS –VGS characteristics of MoS2 -n and WSe2 -p devices with equal
IOFF at VDS = VDD . The bilayer TMD devices show larger subthreshold
swing (SS) and higher threshold voltage (VT ). The mobility of bilayer TMDs
is assumed to be 1.6× of that for monolayer TMDs [11]–[13]. The gate width
is set to be 5.9 nm.

TABLE I
BANDGAP, E LECTRON A FFINITY, D IELECTRIC C ONSTANT, AND E FFECTIVE
M ASSES FOR M ONOLAYER /B ILAYER MoS 2 AND WSe2 U SED IN T HIS
PAPER [9], [10], [19]–[24]. m e AND m h D ENOTE THE E LECTRON
AND H OLE E FFECTIVE M ASSES , R ESPECTIVELY.
m 0 I S THE F REE E LECTRON M ASS

resistance (RSD ), the gate-to-source/drain underalp design, and
the IOFF spec. on the SRAM stability and performance are
comprehensively addressed.
This paper is organized as follows. Section II describes the
device design and TCAD simulation methodology used in this
paper. In Section III, we investigate and compare the stability,
leakage, and read/write performance of 6T SRAM cells using
monolayer and bilayer MoS2 -n/WSe2 -p devices. Finally, the
conclusions are drawn in Section IV.
II. D EVICE D ESIGN AND TCAD S IMULATION
M ETHODOLOGY
In this work, monolayer and bilayer MoS2 -n/WSe2 -p
devices are designed with equal OFF-current (IOFF ) of 5 nA/μm
and pertinent device parameters based on the ITRS 2028
technology node, as shown in Fig. 2. To evaluate the stability
and performance of the TMD-based 6T SRAM, 2-D TCAD
mixed-mode simulations [18] are performed with the physical
properties of the atomically thin TMDs, as listed in Table I.
These material parameters are judiciously chosen from pub-
lished experimental and theoretical data [9], [10], [19]–[24].
The transport model (drift-diffusion model) is calibrated with
the dissipative quantum transport model using non-equilibrium
Green’s function (NEGF) formalism in [6] to accurately
Fig. 3. (a) RSNM and (b) WSNM comparisons of SRAM cells with mono-
layer and bilayer MoS2 -n/WSe2 -p devices. The butterfly curves (right insets)
illustrate the better RSNM and worse WSNM of monolayer SRAM.
VREAD,0 is the read disturb voltage determined by the voltage divider effect
between the PG and PD transistors. VWRITE,0 is determined by the voltage
divider effect between the PG and PU transistors. The upper and lower bounds
indicate the best and worst RSNM if L g has 10% process variation.
assess the power-performance of monolayer MoS2 device.
For WSe2 devices, the mobility ratio of monolayer WSe2
to MoS2 devices is based on their intrinsic phonon-limited
mobility ratio [25]. In the comparison between the monolayer
and bilayer TMD devices, the mobility of bilayer TMDs is
assumed to be 1.6× of that for monolayer TMDs (if not
otherwise stated) based on the experimental data in [11]–[13].
According to [6] and [8], source-to-drain direct tunneling is
assumed to be negligible due to the relatively large effective
masses of TMDs. Source/drain series resistance of 128  μm
is adopted from the ITRS 2028 node spec.
III. SRAM S TABILITY /P ERFORMANCE U SING
M ONOLAYER AND B ILAYER MoS2 -n/WSe2 -p D EVICES
Fig. 3(a) compares the read static noise margin (RSNM) for
monolayer and bilayer MoS2 -n/WSe2 -p 6T SRAM cells. The
RSNM is defined as the minimum noise voltage present at each
storage node that flips the state of the cell. It is shown that, for
a given VDD , the monolayer MoS2 -n/WSe2 -p 6T SRAM cell
possesses a larger nominal RSNM than the bilayer counterpart.
This can be explained in Fig. 3(a) (right inset). It shows that
although the monolayer SRAM cell possesses slightly larger
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YU et al.: EVALUATION OF MONOLAYER AND BILAYER 2-D TMD DEVICES
Fig. 4. Cell leakage comparison of 6T SRAM cells with monolayer
and bilayer MoS2 -n/WSe2 -p devices. Despite the same nominal leakages at
VDD = 0.64 V, the worst-case leakage of monolayer SRAM under 10% L g
variation is much smaller than the bilayer counterpart.
VREAD,0 (slightly larger read disturb), its better subthresh-
old swing (SS) (and thus steeper transition of the butterfly
curve) benefits the RSNM. The better SS also results in
less RSNM variation (assuming 10% variation in L g ) for
monolayer SRAM cell. Fig. 3(b) compares the write static
noise margin (WSNM) and results indicate that the monolayer
MoS2 -n/WSe2 -p SRAM cell exhibits worse WSNM than the
bilayer counterpart. It is also found that the WSNM for
both the monolayer and bilayer SRAM cells is much larger
compared with RSNM [Fig. 3(a)]. In other words, the stability
is limited by RSNM rather than WSNM. Fig. 4 compares
the cell leakage of monolayer and bilayer SRAM cells under
various VDD values. It can be seen that, due to the worse
DIBL (and larger VT ,lin ) of bilayer MoS2 -n/WSe2 -p devices,
the nominal cell leakage of bilayer SRAM cell is smaller
than that of monolayer SRAM cell for VDD < 0.64 V.
However, if 10% process variation in L g is considered, the cell
leakage variation of bilayer SRAM is drastically larger than
the monolayer counterpart because of the worse EI of bilayer
devices. Namely, the worst-case cell leakage of monolayer
SRAM cell is significantly smaller than the bilayer SRAM
cell leakage at VDD = 0.64 V.
To evaluate the cell performance, the bit-line (BL) load-
ing is estimated based on the actual layouts with 64 cells
per BL. For the read performance, the cell read access time
is defined as the time required for developing BL differential
voltage = 10% VDD after the word-line (WL) is activated
during a read operation. For write performance, the time-to-
write is defined as the time from the 50% activation of the
WL to the time when the voltages of two storage nodes cross
each other. Because the mobility ratio of bilayer TMD to
monolayer TMD (μBilayer /μMonolayer ) reported to date varies
substantially (∼1.6× to ∼5× [11]–[15]), Fig. 5 reveals the
impacts of μBilayer /μMonolayer on the 6T SRAM cell stability
and performance. It is shown that the RSNM and WSNM
essentially remain the same within the mobility ratio range
due to the unchanged relative strength of pass-gate (PG)/pull-
down (PD) and pull-up(PU)/PD. With μBilayer /μMonolayer =
3×, the performance of bilayer SRAM cell can be ∼25%
3
Fig. 5. Impacts of bilayer-to-monolayer mobility ratio on the per-
formance gain of bilayer SRAM (against monolayer SRAM). With
μBilayer /μMonolayer = 3×, the performance of bilayer SRAM cell
can be ∼25% better than that of monolayer SRAM cell.
Fig. 6. Read/write performance of monolayer and bilayer SRAM cells at
VDD = 0.64 and 0.4 V. The performance metrics are normalized with respect
to monolayer SRAM at VDD = 0.64 V. Inset: IDsat comparison of monolayer
and bilayer MoS2 devices at VDD = 0.64 V. Note that the higher VT
at VDD = 0.64 V and higher DIBL degrade the performance of bilayer SRAM
at VDD = 0.4 V. The mobility of bilayer TMDs is 1.6× of that for monolayer
TMDs.
better than that of monolayer SRAM cell. In Fig. 6, we com-
pare the read/write performance for monolayer and bilayer
SRAM at VDD = 0.64 V (superthreshold) and 0.4V (near-
threshold or subthreshold). It can be seen that, although the
bilayer MoS2 device possesses much higher IDsat than the
monolayer one at VDD = 0.64 V [see Fig. 6 (inset)], the
cell read access time and time-to-write of bilayer SRAM cell
are comparable with the monolayer because of the impact of
DIBL. As VDD reduces to a lower value (e.g., 0.4 V), the
read performance and write performance of the bilayer SRAM
become much worse than the monolayer counterparts. This can
be elucidated by the fact that the higher VT at VDD = 0.64 V
and worse DIBL (and thus much higher VT ,lin ) degrade the
cell performance of bilayer SRAM at VDD = 0.4 V.
The contact resistance has been a critical issue for
TMD devices [11], [27]. The reported source/drain series
resistance (RSD ) to date is significantly larger than the
ITRS 2028 spec. [11], [26], [27], and whether monolayer or
bilayer TMD devices possess lower RSD is still under debate
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4 IEEE TRANSACTIONS ON ELECTRON DEVICES
Fig. 7. Impacts of RSD on (a) stability and (b) performance of mono-
layer and bilayer SRAM cells. The read/write performance metrics are
normalized with respect to the monolayer SRAM with RSD = 128  μm
(ITRS 2028 spec.).
(as mentioned in Section I) [11], [26]. The impacts of RSD
on 6T SRAM cell stability and performance are shown in
Fig. 7. Fig. 7(a) reveals that the RSNM and WSNM for
both the monolayer and bilayer SRAMs decrease with increas-
ing RSD . The decreasing RSNM may stem from the weaker
PD (compared with the PG), because it operates in the linear
region. Moreover, when RSD becomes high, the bilayer SRAM
may possess larger RSNM than the monolayer counterpart
due to its smaller sensitivity of RSNM to RSD . Fig. 7(b)
shows that the cell read access time and time-to-write for both
the monolayer and bilayer SRAMs are significantly degraded
as RSD increases. Furthermore, the performance of bilayer
SRAM exhibits higher sensitivity to RSD compared with the
monolayer counterpart owing to its higher mobility (and thus
smaller channel resistance).
Fig. 8(a) shows the impacts of gate-to-source/drain under-
lap on the stability of bilayer and monolayer SRAM
cells. It shows that, with the source/drain underlap design
(e.g., L underlap = 2 nm), the RSNM of bilayer SRAM
improves and becomes slightly larger than the monolayer
SRAM counterpart. This can be attributed to the improved
SS due to the increased effective channel length. Furthermore,
compared with the bilayer SRAM without source/drain under-
lap, the bilayer SRAM with underlap possesses substantially
Fig. 8. (a) With 2-nm L underlap , the RSNM of bilayer SRAM cell is
improved because of the increased effective channel length and improved SS
of the bilayer TMD device. (b) While the performance of monolayer SRAM
degrades with 2-nm L underlap , the performance of bilayer SRAM virtually
remains the same due to the improved SS. The read performance/write
performance is normalized with respect to monolayer SRAM with
L underlap = 0 nm.
more superior cell read access time and time-to-write to the
monolayer SRAM, as shown in Fig. 8(b).
Fig. 9 compares the stability and performance of monolayer
and bilayer SRAMs for LP and high-performance (HP) appli-
cations. It is shown in Fig. 9(a) that, by relaxing IOFF from
the LP to HP specs, both the monolayer and bilayer SRAMs
exhibit degraded RSNM. This is because the read disturb
increases due to the decreased VT (and thus the stronger
PG transistors). However, in the comparison of monolayer
and bilayer SRAMs with HP IOFF spec., the bilayer SRAM
exhibits better RSNM than the monolayer SRAM. From the
perspective of read/write performance, the bilayer SRAM
shows more improvement in cell read access time and time-
to-write than the monolayer one, as shown in Fig. 9(b). This
can be explained by the fact that the relevance of mobility to
performance increases with increasing (VDD − VT ). In other
words, the bilayer SRAM, with higher channel mobility, is
more suitable for relaxed channel length and HP applications.
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YU et al.: EVALUATION OF MONOLAYER AND BILAYER 2-D TMD DEVICES
Fig. 9. Impacts of the IOFF spec. on (a) stability and (b) performance of
monolayer and bilayer SRAMs. The read/write performance of bilayer SRAM
shows much larger enhancement with a higher IOFF , because the mobility
becomes more important with increasing (VDD − VT ).
IV. C ONCLUSION
For the first time, we have comprehensively evaluated
the stability, performance, and cell leakage of 6T SRAM
cell using monolayer and bilayer TMD devices based on
the ITRS 2028 (5.9 nm) node. The impacts of the bilayer-
to-monolayer mobility ratio, source/drain series resistance,
underalp device design, and IOFF spec. on the stability and
performance of monolayer and bilayer SRAMs are addressed.
Our study indicates that, due to the excellent device electro-
statics stemming from its single atomic layer, the monolayer
SRAM exhibits superior stability and immunity to process
variations, and therefore, the monolayer SRAM is favored
for low-power applications. With higher channel mobility, the
bilayer SRAM is more suitable for relaxed channel length and
high-performance applications.
R EFERENCES
[1] ITRS. (2013). Table PIDS 3. [Online]. Available : http://www.itrs.net
[2] W. Cao, J. Kang, S. Bertolazzi, A. Kis, and K. Banerjee, “Can
2D-nanocrystals extend the lifetime of floating-gate transistor based
nonvolatile memory?” IEEE Trans. Electron Devices, vol. 61, no. 10,
pp. 3456–3464, Oct. 2014.
[3] W. Cao, J. Kang, W. Liu Y. Khatami, D. Sarkar, and K. Banerjee,
“2D electronics: Graphene and beyond,” in Proc. ESSDERC, Sep. 2013,
pp. 37–44.
[4] B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti, and A. Kis,
“Single-layer MoS2 transistors,” Nature Nanotechnol., vol. 6, no. 3,
pp. 147–150, 2011.
5
[5] H. Fang, S. Chuang, T. C. Chang, K. Takei, T. Takahashi, and A. Javey,
“High-performance single layered WSe2 p-FETs with chemically doped
contacts,” Nano Lett., vol. 12, no. 7, pp. 3788–3792, 2012.
[6] W. Cao, J. Kang, D. Sarkar, W. Liu, and K. Banerjee, “Performance
evaluation and design considerations of 2D semiconductor based FETs
for sub-10 nm VLSI,” in IEDM Tech. Dig., Dec. 2014, pp. 30.5.1–30.5.4.
[7] L. Liu, Y. Lu, and J. Guo, “On monolayer MoS2 field-effect transistors
at the scaling limit,” IEEE Trans. Electron Devices, vol. 60, no. 12,
pp. 4133–4139, Dec. 2013.
[8] V. Mishra, S. Smith, K. Ganapathi, and S. Salahuddin, “Dependence of
intrinsic performance of transition metal dichalcogenide transistors on
materials and number of layers at the 5 nm channel-length limit,” in
IEDM Tech. Dig., Dec. 2013, pp. 5.6.1–5.6.4.
[9] L. Liu, S. Bala Kumar, Y. Ouyang, and J. Guo, “Performance limits
of monolayer transition metal dichalcogenide transistors,” IEEE Trans.
Electron Devices, vol. 58, no. 9, pp. 3042–3047, Sep. 2011.
[10] K. Alam and R. K. Lake, “Monolayer MoS2 transistors beyond the
technology road map,” IEEE Trans. Electron Devices, vol. 59, no. 12,
pp. 3250–3254, Dec. 2012.
[11] W. Liu et al., “High-performance few-layer-MoS2 field-effect-transistor
with record low contact-resistance,” in IEDM Tech. Dig., Dec. 2013,
pp. 19.4.1–19.4.4.
[12] H. Wang et al., “Large-scale 2D electronics based on single-layer MoS2
grown by chemical vapor deposition,” in IEDM Tech. Dig., Dec. 2012,
pp. 4.6.1–4.6.4.
[13] H. Wang et al., “Integrated circuits based on bilayer MoS2 transistors,”
Nano Lett., vol. 12, no. 9, pp. 4674–4680, 2012.
[14] B. W. H. Baugher, H. O. H. Churchill, Y. Yang, and P. Jarillo-Herrero,
“Intrinsic electronic transport properties of high-quality monolayer and
bilayer MoS2 ,” Nano Lett., vol. 13, no. 9, pp. 4212–4216, 2013.
[15] G.-H. Lee et al., “Flexible and transparent MoS2 field-effect transis-
tors on hexagonal boron nitride-graphene heterostructures,” ACS Nano,
vol. 7, no. 9, pp. 7931–7936, 2013.
[16] W. Cao, J. Kang, W. Liu, and K. Banerjee, “A compact current–voltage
model for 2D semiconductor based field-effect transistors considering
interface traps, mobility degradation, and inefficient doping effect,”
IEEE Trans. Electron Devices, vol. 61, no. 12, pp. 4282–4290,
Dec. 2014.
[17] K. S. Novoselov et al., “Electric field effect in atomically thin carbon
films,” Science, vol. 306, pp. 666–669, Oct. 2004.
[18] Sentaurus TCAD, G2012-06-SP2 Manual.
[19] D. Wickramaratne, F. Zahid, and R. K. Lake, “Electronic and ther-
moelectric properties of few-layer transition metal dichalcogenides,”
J. Chem. Phys., vol. 140, no. 12, p. 124710, 2014.
[20] K. F. Mak, C. Lee, J. Hone, J. Shan, and T. F. Heinz, “Atomically thin
MoS2 : A new direct-gap semiconductor,” Phys. Rev. Lett., vol. 105,
no. 13, p. 136805, 2010.
[21] H. Sahin et al., “Anomalous Raman spectra and thickness-dependent
electronic properties of WSe2 ,” Phys. Rev. B, vol. 87, no. 16, p. 165409,
2013.
[22] J. Kang, S. Tongay, J. Zhou, J. Li, and J. Wu, “Band offsets and
heterostructures of two-dimensional semiconductors,” Appl. Phys. Lett.,
vol. 102, no. 1, p. 012111, 2013.
[23] J. Chang, L. F. Register, and S. K. Banerjee, “Ballistic perfor-
mance comparison of monolayer transition metal dichalcogenide
MX2 (M = Mo, W; X = S, Se, Te) metal-oxide-semiconductor field
effect transistors,” J. Appl. Phys., vol. 115, no. 8, p. 084506, 2014.
[24] A. Kumar and P. K. Ahluwalia, “Tunable dielectric response of transition
metals dichalcogenides MX2 (M = Mo, W; X = S, Se, Te): Effect
of quantum confinement,” Phys. B, Condens. Matter, vol. 407, no. 24,
pp. 4627–4634, 2012.
[25] Z. Jin, X. Li, J. T. Mullen, and K. W. Kim, “Intrinsic transport properties
of electrons and holes in monolayer transition-metal dichalcogenides,”
Phys. Rev. B, vol. 90, no. 4, p. 045422, 2014.
[26] J. Na et al., “Separation of interlayer resistance in multilayer MoS2
field-effect transistors,” Appl. Phys. Lett., vol. 104, no. 23, p. 233502,
2014.
[27] L. Yang et al., “High-performance MoS2 field-effect transistors enabled
by chloride doping: Record low contact resistance (0.5 k · μm) and
record high drain current (460 μA/μm),” in VLSI Symp. Tech. Dig.,
Jun. 2014, pp. 1–2.
[28] H. Liu, A. T. Neal, and P. D. Ye, “Channel length scaling of MoS2
MOSFETs,” ACS Nano, vol. 6, no. 10, pp. 8563–8569, 2012.
[29] M. M. Perera et al., “Improved carrier mobility in few-layer MoS2 field-
effect transistors with ionic-liquid gating,” ACS Nano, vol. 7, no. 5,
pp. 4449–4458, 2013.
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6 IEEE TRANSACTIONS ON ELECTRON DEVICES

Chang-Hung Yu (S’11) received the B.S. degree Vita Pi-Ho Hu (S’09–M’13) received the
from National Taiwan University, Taipei, Taiwan, B.S. degree in materials science and engineering
in 2007, and the M.S. degree from National Chiao and the Ph.D. degree in electronics engineering and
Tung University, Hsinchu, Taiwan, in 2011, where the Institute of Electronics, National Chiao Tung
he is currently pursuing the Ph.D. degree with the University, Hsinchu, Taiwan, in 2004 and 2011,
Institute of Electronics. respectively.
His current research interests include design and She is currently an Assistant Professor with
modeling of emerging CMOS devices, analysis and National Central University, Taoyuan, Taiwan.
design of low-power SRAMs in ultrascaled
technologies, and device-circuit interaction.

Pin Su (S’98–M’02) received the Ph.D. degree

Ming-Long Fan received the Ph.D. degree from the University of California at Berkeley,
from the Department of Electronics Engineer- Berkeley, CA, USA.
ing, Institute of Electronics, National Chiao Tung He is currently a Professor with the Department
University, Hsinchu, Taiwan, in 2014. of Electronics Engineering, National Chiao Tung
He is currently with Taiwan Semiconductor University, Hsinchu, Taiwan. He has authored over
Manufacturing Company, Ltd., Hsinchu. 200 technical papers. His current research interests
include modeling and design for exploratory/post
CMOS devices, and their interactions with
low-power circuits.

Kuan-Chin Yu received the B.S. and M.S. degrees Ching-Te Chuang (S’78–M’82–SM’91–F’94)
from National Chiao Tung University, Hsinchu, received the Ph.D. degree in electrical engineering
Taiwan, in 2013 and 2015, respectively. from the University of California at Berkeley,
She is currently with Taiwan Semiconductor Berkeley, CA, USA, in 1982.
Manufacturing Company, Ltd., Hsinchu. He is currently a Life Chair Professor with the
Department of Electronics Engineering, National
Chiao Tung University, Hsinchu, Taiwan. He holds
64 U.S. patents, and has authored or co-authored
over 410 papers.