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Vol. 35, No. 5 Journal of Semiconductors May 2014

A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer
in 0.13 m CMOS
Lü Wei(吕伟)1 , Luo Duona(罗多纳)1 , Mei Fengcheng(梅逢城)1 , Yang Jiaqi(杨家琪)1 ,
Yao Libin(姚立斌)2 , He Lin(贺林)1; Ž , and Lin Fujiang(林福江)1
1 Department of Electronic Science and Technology, University of Science and Technology of China, Hefei 230027, China
2 Kunming Institute of Physics, Kunming 650223, China

Abstract: This paper presents a 0.6 V 10 bit successive approximation register (SAR) ADC design dedicated to
the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and
power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the
associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional
constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode
stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified
through both simulation and measurement results. Fabricated with 1P8M 0.13 m CMOS technology, the proposed
SAR ADC consumes 6.3 W at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency
and FOM of 21 fJ/conversion-step. The core area is only 120  300 m2 .

Key words: SAR ADC; monotonic switching; common mode stabilizer; comparator offset
DOI: 10.1088/1674-4926/35/5/055006 EEACC: 2570

1. Introduction One drawback associated with the MS scheme is that it

Wireless sensor networks (WSN) contain multiple sensor
nodes. In most cases, changing their batteries is impractical or
impossible, therefore battery-less devices that harvest energy
from the environment are required. A variety of energy har-
vesting technologies, such as solar power, RF power and me-
chanical vibration, can be utilized as power sources to provide
a supply voltage of around 0.6 VŒ1 . Therefore, ultra low volt-
age operation with high power efficiency is desirable for WSN
applicationsŒ2 4 .
The analog-to-digital converter (ADC) is a fundamen-
tal block for every sensor node. Among different conversion
topologies, the SAR ADC is known for its low power, small
area and ability to operate under a low supply voltage. SAR
ADCs with a supply voltage of 0.6 V or below were reported
in Refs. [5–7]. The time domain comparator in Refs. [5, 6] was
proposed to reduce the input-referred noise and offset, so that
the total power can be reduced, but at the cost of a slow conver-
sion speed. The choice of capacitive DAC is also critical. The
monotonic switching (MS) schemeŒ8 and Vcm -based switching
schemeŒ9 are among the most energy-efficient DAC topolo-
gies. With these topologies, the energy loss due to switching
is reduced by 81% and 88% respectively, compared to the
conventional structureŒ10 . Although the Vcm -based switching
scheme is slightly more power efficient than the MS scheme,
it is not suitable for ultra-low voltage operation, as the transis-
tor cannot be fully turned on at the Vcm . Overall, the MS DAC
topology is an ideal candidate for ultra-low voltage, not only
for its power efficiency, but also for its high speed and simpli-
fied digital logic.
causes a large shift of the common mode (CM) voltage, which
in turn leads to a large variation of the offset in the dynamic
comparator. The varying offset is the major source of integral
nonlinearity (INL) in the MS schemeŒ11 . To solve this prob-
lem, Reference [8] used a fixed bias current in the dynamic
comparator; however, it is not suitable for a 0.6 V design due to
the limited headroom. Reference [7] proposed a supply-boost
technique to increase the supply voltage of the comparator to
2VDD , which allows constant current biasing but significantly
increases the power consumption.
This paper introduces a novel common mode stabilizer
(CMS) network to the conventional MS DAC array to stabi-
lize the CM at the instant of comparison; it allows the use of
the MS technique under 0.6 V or even below while it does not
suffer from the power issue in Ref. [7].
2. Architecture design
2.1. Monotonic switching
Figure 1 shows the architecture of the monotonic switching
SAR ADCŒ8 , which consists of a pair of sample/hold switches,
a differential capacitive DAC array, a dynamic comparator,
as well as SAR control logic. The capacitive DAC array is
used both for sampling the input signal and subtracting the
sampled input with a digital approximation. The sample/hold
(S/H) switches are implemented by NMOS transistors, with
their sampling clock boosted to maintain the on-resistances
constant.
During the sampling phase, the sample/hold switches are

* Project supported by the National Natural Science Foundation of China (No. 61204033) and the Natural Science Foundation of Jiangsu
Province (No. BK2012214).
† Corresponding author. Email: helin77@ustc.edu.cn
Received 21 October 2013, revised manuscript received 5 November 2013 © 2014 Chinese Institute of Electronics

055006-1
J. Semicond. 2014, 35(5) Lü Wei et al.

Fig. 1. Block diagram of SAR ADC based on monotonic switching (MS) scheme.

term depends on the overdrive voltage. When the MS structure

is used, the input CM of the comparator gradually decreases. To
save power, the preamplifier is used dynamically, which means
that its tail transistor is turned on and off by the clock signal.
Once the tail transistor is turned on, it operates in linear region,
and the voltage drop over the tail transistor can be practically
ignored. Thus the overdrive voltage of the input pair suffers the
same variation as the input CM.
In Ref. [8], an additional fixed current biasing transistor is
used in serial with the clocked tail transistor to provide a con-
stant current to the input pair even in the presence of large CM
variation. It effectively reduced the variation range of the input-
Fig. 2. Waveform of the MS procedure as well as its associated com-
referred offset. However, such a strategy cannot be applied to
mon mode (CM) shift.
a 0.6 V design due to the limited voltage headroom.

turned on and all the bottom plates are reset to VDD . Since 2.3. Architecture of the proposed SAR ADC
the S/H switches turn off, the signal is sampled on the DAC,
Figure 3 shows the block diagram of the proposed SAR
and the conversion begins. At first, the comparator directly
ADC, which adds an additional CMS circuit to the existing MS
performs the first comparison without switching any capaci-
SAR ADC to stabilize the input CM of the dynamic amplifier.
tor. Then one of the MSB capacitors is switched from VDD to
The CMS circuit is actually a binary weighted capacitive array
ground, while the other one remains unchanged, according to
sharing the same top plates with the MS DAC. Each unit of the
the comparison result. This procedure is repeated until the LSB
CMS circuit contains two identical capacitors whose bottom
is resolved.
plates will experience a transition from VSS to VDD to compen-
Figure 2 shows the waveform of the MS procedure. After
sate for the CM drop of the MS DAC. The size of capacitors in
the comparison, only one side of the DAC is switched while the
the CMS array is half of their corresponding capacitors in the
other side stays unchanged, which causes not only a differential
MS DAC. The VSS to VDD transition is implemented by an OR
change of the DAC output, but also a gradual decreasing in
gate whose inputs are 1P–4P and 1N–4N, the control signals
the CM from 0.5VDD to VSS . This large CM shift leads to a
of the DAC. Since most of the CM variation happens around
significant variation of the offset in the dynamic comparator,
the MSB, only four bits of CMS are applied. The CM varia-
which is the main source of integral nonlinearity (INL) of the
tion after the fourth bit will cause negligible error in the ADC
SAR ADCŒ11 .
output. Figure 4 shows the first four bit-cycles waveform of
MS DAC with CMS applied. During the i th comparison, the
2.2. Common mode-dependent offset of the comparator
voltage swing on each side of the DAC is given by
In the MS structure, the offset variation in the comparator
degrades the performance of the ADC. Assume that the offset 2n i 1
Cu 2n i 2
Cu
voltage of the comparator is dominated by the preamplifier, VPi D Bi  VDD C VDD ; (2)
CT CT
whose offset voltage can be expressed asŒ12
 
VGS VTH S R 2n i 1
Cu 2n i 2
Cu
Vos D VTH C C ; (1) VNi D .Bi 1/  VDD C VDD ; (3)
2 S R CT CT
where VTH is the threshold voltage mismatch of the input pair, where VPi and VNi are the i th voltage swing on the positive
S=S is the size mismatch of the input pair, and R=R is the and negative side of the DAC, Cu is the unit capacitance, CT
resistance mismatch of the loading pair. From Eq. (1), we can is the total capacitance of the DAC, and Bi is the ith compar-
find that the offset voltage is related to the device mismatches ison result. The first and second terms in Eq. (2) represent the
and bias conditions. The first term in Eq. (1) is a static error contributions from the MS network and the CMS network, re-
which does not affect the performance of the ADC. The second spectively. No matter what Bi is, the summation of VPi and

055006-2
J. Semicond. 2014, 35(5)
Fig. 3. Block diagram of the proposed SAR ADC with CMB.
Fig. 4. Timing of comparison, CMS, and DAC settling.
VNi remains zero, which means that the input CM keeps con-
stant at the comparison instant.
3. Implementation and simulation results
3.1. Dynamic comparator
In this design, the comparator is actually a dynamic pre-
amplifier followed by a dynamic latch (shown in Fig. 5)Œ13 .
Since the CM sticks to 0.5VDD , a NMOS input stage is chosen
to enhance the comparison speed. The incoming rising edge of
CLKC turns on the tail transistor M1 and turns off the loading
transistors M3, which causes the discharge of the nodes FN and
FP. The discharging rate depends on the magnitude of the in-
put signal and thus can be treated as a time-varying gain stage.
The dynamic latch is activated slightly after the dynamic pre-
amplifier.
3.2. Asynchronous control logic
Asynchronous logicŒ14 is adopted that removes the need
for an extra high frequency clock, to save power and improve
conversion speed. Figure 6 shows the diagram of the asyn-
chronous control logic, which is comprised of three parts: self-
oscillator, shift register and data register. The self-oscillator is
used to generate the clock signal CLKC for the comparatorŒ15 .
The comparator itself is embedded in the self-oscillator. An OR
055006-3
Lü Wei et al.
Fig. 5. Circuit of double tail dynamic comparator.
gate is used to detect whether the comparison is completed. Af-
ter the signal Valid, the output of the OR gate feeds back to reset
the comparator. The alternation of comparison and reset builds
a self-oscillation. The self-oscillator can be turned on and off
by the system sampling clock CLKS. It is important to note that
the CLKC generator should provide an adequate DAC settling
time to meet the accurate requirement.
The signal Valid is used to trigger the shift register. As a
result, the outputs of the shift register (CK1–CK10) will suc-
cessively transit from low to high, which in turn triggers the
corresponding D flip–flop in the data register and stores the
current comparison result. The outputs of the data register are
used directly to control the switches in the DAC.
3.3. Simulation results of the CMB
The proposed CMS is simulated and compared against the
conventional MS scheme, with comparator offset taken into ac-
count. The transistor-level implementation of the comparator
is replaced with a behavioral model. Monte Carlo simulation
is employed to determine the variance of the offset at differ-
ent CM input. It is worth mentioning that the comparator used
in the MS scheme has a p-type input pair due to the decreas-
ing CM. Figure 7 plots the simulated offset variance of the p-
type comparator versus different CM input. It is easy to iden-
tify two operation regions in the figure: strong inversion and
sub-threshold. In the strong inversion region, the offset volt-
age depends linearly with the input common mode. In the sub-
threshold region, the offset voltage is almost constant due to
the almost constant overdrive voltage in this region. Although
it looks like operating the comparator in the sub-threshold re-
gion can minimize the offset variation as well as its associated
J. Semicond. 2014, 35(5) Lü Wei et al.

Fig. 6. Block circuit of asynchronous control logic.

Fig. 7. Simulated offset voltage of the p-type input comparator versus

CM.

Table 1. Monte Carlo simulation results.

Parameter ENOB (bit) DNL (LSB) INL (LSB)
Without CMS 9.07 5.2 6.3
With CMS 9.9 0.25 0.3

ADC conversion error, the comparator is relatively slow in this

region.
The simulated offset variance can be best fitted to two seg-
mental straight-lines and included in the behavioral model of
the comparator. Transient simulation is performed to check the
ADC performance degradation due to the CM-dependent off- Fig. 8. Simulation results of (a) DNL and (b) INL without CMS.
set. It should be noted that the capacitor mismatch is not in-
cluded in this simulation. Both the conventional MS scheme
and the MS C CMS scheme are simulated. Their simulated
DNL and INL are plotted in Figs. 8 and 9 and summarized in are utilized, and an attenuation capacitor with a unit cell is used
Table 1. The soundness of the CMS method is clearly seen. to separate the split capacitive array into a 7 bits MSB and a
2 bits LSB arrayŒ16 .
3.4. Layout implementation
The mismatch on the DAC has a major impact on the lin-
The core layout area of the ADC is only 120  300 m2 , earity of the ADC, so the symmetrical layout structure of the
and the DAC array occupies more than 60% of the total area. DAC was critical. To ease the routing between the DAC and
The unit capacitor is implemented by the metal–oxide–metal the SAR control logic, only the first three bits in the DAC ar-
(MOM) capacitors with a unit capacitance of 3.6 fF for the re- ray are symmetrically-arranged. An array of dummy capacitors
quirement of capacitor matching. Split DAC capacitor arrays is used around the capacitor to ensure a uniform environment.

055006-4
J. Semicond. 2014, 35(5)
Fig. 9. Simulation results of (a) DNL and (b) INL with CMS.
Fig. 10. Die photograph of the proposed SAR ADC.
4. Measurement results
The proposed ADC was fabricated using the 1P8M 0.13-
m CMOS process. A die photograph of the chip is shown
in Fig. 10. The chip was directly mounted on a printed circuit
board. The analog input signal and clock are both provided by
an Agilent 33250A function arbitrary waveform generator. The
digital outputs of the proposed ADC are captured by an Agi-
lent 1681A logic analyzer and processed using Matlab to obtain
their static and dynamic performance.
Figure 11 shows the measured DNL and INL. The
measured peak DNL and INL are 0:91/C1:58 LSB and
1:15/C1:99 LSB, respectively. Figure 12 shows 16384 point
055006-5
Lü Wei et al.
Fig. 11. Measured (a) DNL and (b) INL of the proposed SAR ADC.
FFT of the ADC output for fin D 40.039 kHz and 489.2578
kHz at 1 MS/s. Figure 13 plots the measured SNDR and SFDR
versus the input frequency at 1 MS/s. At low input frequency,
the measured SNDR, SFDR and ENOB are 52.6 dB, 67.95
dB and 8.44 bit respectively. At near Nyquist frequency, the
SNDR and SFDR drop by 1.35 dB (loss of 0.22 bit ENOB)
and 1.5 dB, respectively. Figure 13 also shows the measure-
ment results of SNDR/SFDR against the sampling frequency
with the Nyquist rate input. The ENOB degradation is mainly
caused by the noise from the dynamic comparator.
The total power consumption of the SAR ADC is 6.3 W
at 0.6 V and 1 MS/s sampling rate. The analog power, including
the capacitive DAC array, CMS circuit is 2.1 W. The digital
power, including clock generator and output register is 2.3 W.
The power of the comparator is 1.9 W. The proposed ADC
achieves 21 fJ/conversion-step at the Nyquist frequency with
1 MS/s.
The performance of the proposed SAR ADC is summa-
rized in Table 2, and compared with several recently published
SAR ADCs. The proposed ADC achieved a comparable per-
formance to the published 0.6 V designs. The speed advantage
of our design over the time-domain comparator based approach
can also be clearly seen.
5. Conclusion
This paper presents a 0.6 V 10 bit monotonic switching
SAR ADC with a novel common mode stabilizer to address
J. Semicond. 2014, 35(5) Lü Wei et al.

Fig. 12. 16384 points of FFT spectrum at (a) fin D 40.039 kHz and (b) 489.2578 kHz.

Fig. 13. Measured (a) dynamic performance versus input frequency at 1 MS/s, (b) dynamic performance versus sampling frequency with Nyquist
rate input.

Table 2. Performance comparison with other published SAR ADC.

Parameter Ref. [5] Ref. [6] Ref. [7] Ref. [8] This work
Sample rate (MHz) 1.1 0.1 0.5 50 1
Supply voltage (V) 0.5 0.6 0.6 1.2 0.6
Power (W) 1.2 1.3 5 826 6.3
ENOB (bit) Nyquist input 7.5 8.64 9.45 9.18 8.22
FOM D Power/2ENOB *2fin 6.3 32 14.3 29 21
Technology 40 nm 0.18 m 0.18 m 0.13 m 0.13 m
Chip area (mm2 / 0.0112 0.125 0.05 0.052 0.036

the offset variation problem in the dynamic comparator. Simu- Acknowledgment

lation results show that without DAC capacitor mismatch, the
proposed CMS method improves the peak DNL from 5.2 LSB
to 0.25 LSB, and the peak INL from 6.3 LSB to 0.3 LSB.
The measured peak DNL and INL are –0.91/+1.58 LSB and
–1.15/+1.99 LSB, which are still well below the simulation re-
sults without CMS. The first prototype achieved a SNDR of
51.25 dB at the Nyquist frequency with 1 MS/s, and consumes
6.3 W at the 0.6 V supply. The proposed ADC with common
mode stabilizer avoids the use of the constant current biasing
or supply boosting technique, and can operate at 0.6 V, which
is perfectly suitable for WSN application.
The authors would like to thank the lab center of informa-
tion science in USTC for EDA tools support, and Prof. Huang
Lu for tapeout support, IMECAS for scholarship support, Zhu
Guanglong, Cheng Gong, and Yu Mingyuan for measurement
support.
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