Kingdom of Saudi Arabia ‫المملكة العربية السعودية‬

‫وزارة التعليم‬
Ministry of Education
‫جامعة جدة‬
University of Jeddah ‫كلية علوم و هندسة الحاسب‬
College of Computer Science & Engineerin g ‫قسم علوم الحاسب اآللي و الذكاء االصطناعي‬
Department of Computer Science & AI

CCCS217 Computer Organization and Architecture

Assignment4 Fall 2023 /1444

Answer the following:
Chapter 4:
4.1 What are the differences among sequential access, direct access, and random access?
4.2 What is the general relationship among access time, memory cost, and capacity?
4.3 What are the differences among direct mapping, associative mapping, and set-associative mapping?
4.4 For a direct-mapped cache, a main memory address is viewed as consisting of three fields. List and define
the three fields.
4.5 For an associative cache, a main memory address is viewed as consisting of two fields. List and define the
two fields.
4.6 For a set-associative cache, a main memory address is viewed as consisting of three fields. List and define
the three fields.
4.7 A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K
blocks of 128 words each. Show the format of main memory addresses.
4.8 A two-way set-associative cache has lines of 16 bytes and a total size of 8 kB. The 64-MB main memory is
byte addressable. Show the format of main memory addresses.
4.9 For the hexadecimal main memory addresses 111111, 666666, BBBBBB, show the following information,
in hexadecimal format:
a. Tag, Line, and Word values for a direct-mapped cache, using the format of Figure 4.10
b. Tag and Word values for an associative cache, using the format of Figure 4.12
c. Tag, Set, and Word values for a two-way set-associative cache, using the format of Figure 4.15
4.10 List the following values:
a. For the direct cache example of Figure 4.10: address length, number of addressable units, block size,
number of blocks in main memory, number of lines in cache, size of tag
b. For the associative cache example of Figure 4.12: address length, number of addressable units, block
size, number of blocks in main memory, number of lines in cache, size of tag.
c. For the two-way set-associative cache example of Figure 4.15: address length, number of
addressable units, block size, number of blocks in main memory, number of lines in set, number of
sets, number of lines in cache, size of tag.
4.11 Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes. Assume
that a direct mapped cache consisting of 32 lines is used with this machine.
a. How is a 16-bit memory address divided into tag, line number, and byte number?
b. Into what line would bytes with each of the following addresses be stored?
0001 0001 0001 1011
1100 0011 0011 0100
1101 0000 0001 1101
1010 1010 1010 1010
c. Suppose the byte with address 0001 1010 0001 1010 is stored in the cache. What are the addresses of
the other bytes stored along with it?
d. How many total bytes of memory can be stored in the cache?
e. Why is the tag also stored in the cache?
 Kingdom of Saudi Arabia ‫المملكة العربية السعودية‬
‫وزارة التعليم‬
Ministry of Education
‫جامعة جدة‬
University of Jeddah ‫كلية علوم و هندسة الحاسب‬
College of Computer Science & Engineerin g ‫قسم علوم الحاسب اآللي و الذكاء االصطناعي‬
Department of Computer Science & AI

Chapter 7:

7.1 List three broad classifications of external, or peripheral, devices.

7.2 What are the major functions of an I/O module?

7.3 List and briefly define three techniques for performing I/O.

7.4 What is the difference between memory mapped I/O and isolated I/O?

7.5 When a device interrupt occurs, how does the processor determine which device issued the interrupt?

7.6 When a DMA module takes control of a bus, and while it retains control of the bus, what does the processor
do?

7.7 For programmed I/O, Figure 7.5 indicates that the processor is stuck in a wait loop doing status checking of
an I/O device. To increase efficiency, the I/O software could be written so that the processor periodically checks
the status of the device. If the device is not ready, the processor can jump to other tasks. After some timed
interval, the processor comes back to check status again.
a. Consider the above scheme for outputting data one character at a time to a printer that operates at 10
characters per second (cps). What will happen if its status is scanned every 200 ms?
b. Next consider a keyboard with a single character buffer. On average, characters are entered at a rate
of 10 cps. However, the time interval between two consecutive key depressions can be as short as 60
ms. At what frequency should the keyboard be scanned by the I/O program?

7.8 In virtually all systems that include DMA modules, DMA to main memory is given higher priority than CPU
access to main memory. Why?

7.9 A DMA module is transferring characters to memory using cycle stealing, from a device transmitting at
9600 bps. The processor is fetching instructions at the rate of 1 million instructions per second (1 MIPS). By
how much will the processor be slowed down due to the DMA activity?