General Instructions about the Format of Training Report

B.Tech 5th SEM

1) Project Report should be spiral bound.

2) Report’s Cover Page should be as given below.
3) Each student must submit a training certificate and training report.

All students should use the same format and font size. Do not alter the
PRELIMINARIES font and format. For the report you should use the following
font size in Times New Roman.

Title of chapter : 20 (Bold face)

Heading : 16 (Bold face)
Sub-Heading : 14 (Bold face)
Sub-Subheading : 12 (Bold face)
Paragraph Text : 12
Line Spacing : 1.5 Lines
Alignment : Justify

Margin of page should be:

Top : 1 Inch
Bottom : 1 Inch
Left : 1.25 Inch
Right : 1 Inch

4) Table of contents should cover all the sections of the report.

5) Use Romanized Number (i, ii, iii…) for Title page, certificates and Use
Numerals (1,2,3…) for report page number.
6) Declaration by the student and acknowledgement pages must be
signed by the students.
 An

Training Report

on

“------------------- Title-----------------”

Submitted in partial fulfillment for the award of the degree of

Bachelor of Technology

in

Computer Science & Engineering

By

Student Name
(University Roll No.)

Department of Computer Science and Engineering

Ganga Institute of Technology & Management,
Kablana, Jhajjar-124104 (Haryana)
 CONTENTS
Certificate i
Candidate’s Declaration ii
Acknowledgements iii
Abstract v
Contents vii
List of Tables xiv
List of Figures xvi
1. INTRODUCTION 1-16
1.1 Introduction 1
1.2 Sources of Power Dissipation in CMOS Circuit 3
1.2.1 Dynamic Power Dissipation 4
1.2.2 Short Circuit Power Dissipation 5
1.2.3 Glitching Power Dissipation 7
1.2.4 Static Power Dissipation 7
1.3 Circuit Level Power Reduction Techniques 10
1.4 Motivations 11
1.4.1 Need for Portability 12
1.4.2 High Performance 12
1.4.3 Reliability 13
1.5 Objectives of the Research Work 14
1.6 Publications 14
1.6.1 International Journals (04 Articles) 14
1.6.2 International Conference (03 Articles) 15
1.6.3 Research Paper Communicated (01 Articles) 15
1.7 Thesis Organization 15
2. NAME OF SECOND CHAPTER 17-41

2.1 Introduction 34
2.2 Design of XNOR and XOR Gates 37
 LIST OF TABLES
Table Title Page
1.1 Truth table of full adder 35
1.2 Output voltage levels of proposed XNOR gate 40
1.3 Output voltage levels of 5T XNOR/XOR cell 40
2.1 Output level variations versus supply voltage for 3T XOR & 5T XNOR 43
2.2 Performance of 8T full adder 45
3.1 Power dissipation of MCML and proposed PFD 47
3.2 Transistor sizing with L = 0.18 µm 55
 LIST OF FIGURES
Figure Title Page
1.1 Circuit transition (a) Dynamic charging (b) Dynamic discharging 3
1.2 Short circuit current 4
1.3 Leakage current components 5
2.1 Structure of single bit full adder 35
2:1 multiplexer circuit with (a) Pass transistor logic (b) Transmission
2.2 36
gate
2.3 Design of proposed 3 transistors XNOR gate 39