UNIVERSITI KUALA LUMPUR

ASSESSMENT BRIEF

COURSE DETAILS
INSTITUTE UniKL BRITISH MALAYSIAN INSTITUTE
COURSE NAME ANALOG AND DIGITAL IC DESIGN
COURSE CODE BEB46503
COURSE LEADER SUHAIMI BAHISHAM JUSOH@YUSOFF
LECTURER SUHAIMI BAHISHAM JUSOH@YUSOFF
SEMESTER & YEAR FEBRUARY 2023

ASSESSMENT DETAILS
TITLE/NAME LAB 1
WEIGHTING 30%
DATE/DEADLINE 7/4/2023, 4.00PM
COURSE LEARNING CLO 2: Perform simulation of basic, simple and complex CMOS circuit using
OUTCOME(S) EDA tools. (P4, PLO5)

INSTRUCTIONS Perform the following tasks:

1. Submit the report in group or individual as instructed by Course Lecturer.
2. All answers must be in English language only.

Student Name: ID: Group:

Mior Muhammad Mustaqim Bin Mior Darul Ikram 51221120198 L01_B01

Assessor’s Comment: Marks:

Verified by: Course Leader [SBJ] QSC format PC/HOS content

Prepared by: [SBJ] verification validation

I hereby declare that all my team members have agreed

with this assessment. All team members are certain that
this assessment complies with the Course Syllabus.

Signature: ___ _________________________

Date : ___9/3/2023_______________________
TASK NO CLO MARKING SCHEME MARKS
1 25
Simulation of CMOS basic logic gate
(transistor level and verilog) using DSch

2
2 Simulation of CMOS simple circuit (transistor
25
level and verilog) using DSch

3
Simulation of transistor level CMOS complex
16
circuit using DSch

4
Simulation of transistor level CMOS complex
34
circuit using DSch (on site)

TOTAL 100
 INFORMATION ON SK_SP-TA FOR COURSE

Course Code & Name : BEB46503 ANALOG AND DIGITAL IC DESIGN

PLOs : 5

Please tick (  ) in the box provided.

Knowledge Profiles (SK) A programme that builds this type of knowledge and develops the attributes listed below is typically
achieved in 4 years of study
SK1 A systematic, theory-based understanding of the natural sciences applicable to the sub-discipline
Conceptually-based mathematics, numerical analysis, statistics and aspects of computer and information
SK2
science to support analysis and use of models applicable to the sub-discipline
A systematic , theory-based formulation of engineering fundamentals required in an accepted sub-
SK3
discipline
Engineering specialist knowledge that provides theoretical frameworks and bodies of
SK4
knowledge for an accepted sub-discipline
SK5 Knowledge that supports engineering design using the technologies of a practice area
SK6 Knowledge of engineering technologies applicable in the sub-discipline 
Comprehension of the role of technology in society and identified issues in applying
SK7 engineering technology: ethics and impacts: economic, social, environmental and
sustainability
SK8 Engagement with the technological literature of the discipline

Definition of Broadly-Defined Problem Solving (SP)

Broadly-defined Engineering Problems have characteristic SP1 and some or all of
No. Attribute
SP2 to SP7:
Cannot be resolved without engineering knowledge at the level of one or
SP1 Depth of Knowledge Required more of SK 4, SK5, and SK6 supported by SK3 with a strong emphasis on 
the application of developed technology
Range of conflicting
SP2 Involve a variety of factors which may impose conflicting constraints.
requirements
SP3 Depth of analysis required Can be solved by application of well-proven analysis techniques 
Belong to families of familiar problems which are solved in well-accepted
SP4 Familiarity of issues
ways
May be partially outside those encompassed by standards or codes of
SP5 Extent of applicable codes
practice
Extent of stakeholder
Involve several groups of stakeholders with differing and occasionally
SP6 involvement and level of
conflicting needs
conflicting requirements
SP7 Interdependence Are parts of, or systems within complex engineering problems 

Range of Engineering Activities (TA)

No. Attribute Broadly-defined activities
Involve a variety of resources (and for this purposes resources includes people,
TA1 Range of resources
money, equipment, materials, information and technologies)
Require resolution of occasional interactions between technical, engineering and
TA2 Level of interactions
other issues, of which few are conflicting
TA3 Innovation Involve the use of new materials, techniques or processes in non-standard ways
Consequences to
Have reasonably predictable consequences that are most important locally, but
TA4 society and the
may extend more widely
environment
TA5 Familiarity Require a knowledge of normal operating procedures and processes
Task 1 (Design CMOS Basic Logic Gates) – 25% (SK6, SP3)

Referring to Figure 1, design and simulate a transistor level CMOS XNOR

gate using DSCH Software.

Figure 1

The simulation should include:

a) Schematic diagram for each input (00 01 10 11) (8 marks)

b) Output waveform (6 marks)

Simulate a transistor level CMOS XNOR gate by using Verilog HDL as design

entry. The simulation should include:

a) Verilog Coding (5 marks)

b) Output waveform (6 marks)

Task 2 (Design CMOS Simple Circuit) – 25% (SK6, SP3)

Referring to Figure 2, design and simulate a transistor level CMOS 4 to 1

Multiplexer using DSCH Software.

Figure 2
 The simulation should include:

a) Schematic diagram for each input (select = 00,01,10,11) (8 marks)

b) Output waveform (6 marks)

Simulate a transistor level CMOS 4 to 1 Multiplexer by using Verilog HDL as

design entry. The simulation should include:

a) Verilog Coding (5 marks)

b) Output waveform (6 marks)

Task 3 (Design CMOS Complex Circuit) – 16% (SK6, SP1, SP3, SP7)

Simulate a transistor level CMOS using DSCH Software for the given Boolean

equation:

𝐶𝐶 + 𝐴𝐴𝐴𝐴) + 𝐵𝐵(𝐴𝐴 + 𝐶𝐶̅ )

𝑓𝑓 = (����������

The simulation should include:

a) Schematic diagram for each input (8 marks)

b) Output waveform (8 marks)

Task 4 (Design CMOS Complex Circuit) – 34% (SK6, SP1, SP3, SP7)

For Task 4, the Boolean equation will be given during the lab session and is

different for each student. Design and verify your outputs. You are required to

complete this task within 40 minutes. Simulate a transistor level CMOS using

DSCH Software for the given Boolean equation:

The simulation should include:

a) Schematic diagram for each input (16 marks)

b) Output waveform (8 marks)

c) Verilog Coding (6 marks)

d) Truth table (4 marks)

 ASSESSMENT COVERSHEET

Attach this coversheet as the cover of your submission. All sections must be completed.

Section A: Submission Details

Student Name : Mior Muhammad Mustaqim Bin Mior Darul Ikram

Student ID : 51221120198

Programme : BENET

Course Code & Name : BEB46503 & ANALOG AND DIGITAL IC DESIGN

Course Lecturer(s) SBJ

Submission Title : LAB 1

Deadline :
Day 7 Month 4 Year 2023 Time 4:00 PM

Penalties • 5% will be deducted per day to a maximum of four (4) working days, after which
the submission will not be accepted.
• Plagiarised work is an Academic Offence as stated in University Rules &
Regulations and will be penalised accordingly.

Section B: Declaration of Academic Integrity

Tick (✓) each box below if you agree:

/ I have read and understood the UniKL’s policy on Plagiarism in University Rules & Regulations.

/ This submission is my own, unless indicated with proper referencing.

/ This submission has not been previously submitted or published.

/ This submission follows the requirements stated in the course.

Section C: Details of the Submitter

Check that all the details above are filled in, then sign below with the date of submission:

Signature: MYO

Date: 30 APRIL 2023

TASK 1 (xnor)

A B Output

0 0 1

1 0 0
A B Output

0 1 0

1 1 1
TASK 2 (4 to 1 MUX)

S0 S1 D0 Output

0 0 0 0

0 0 1 1
S0 S1 D1 Output

0 1 0 0

0 1 1 1
S0 S1 D2 Output

1 0 0 0

1 0 1 1
S0 S1 D3 Output

1 1 0 0

1 1 1 1
TASK 3 ( )

A B C Output

0 0 0 1

0 0 1 0
A B C Output

0 1 0 1

0 1 1 0
A B C Output

1 0 0 1

1 0 1 0
A B C Output

1 1 0 1

1 1 1 1
TASK 4 ( )

INPUT OUTPUT
A B C Z
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
A B C Output

0 0 0 1

0 0 1 1
A B C Output

0 1 0 1

0 1 1 1
A B C Output

1 0 0 1

1 0 1 1
A B C Output

1 1 0 0

1 1 1 0