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Previous Question Papers solved
ECT 201 SOLID STATE DEVICES

DEC 2021,DEC 2020 SOLUTIONS
Part A - 3 Marks
3. What is the significance of quasi fermi level? If there is gradient in quasi fermi
level, what does it indicates?
SAME AS 2
Gradient indicates the current density
4. With suitable examples, distinguish between elemental and compound

semiconductors. Give their applications.
Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram
Downloaded from Ktunotes.in

5. Draw the energy band diagrams under equilibrium for the following semiconductors.
i) intrinsic ii) n type iii) p type

6. State and explain the terms in Einstein relation
7. Distinguish between drift and diffusion mechanisms. Write the expression for the
corresponding currents

8. Write down the current equations in a semiconductor.

Same as 7
9. Draw the V-I characteristics of a P N junction diode & mark the regions of operation.
Write down the ideal diode equation.
10. Explain Early effect and its impact on collector and base currents.

11. Derive the expression for built in potential of a PN junction diode

12.Draw the structure of a PNP transistor. Clearly Indicate the current components
on the figure.
13. Draw the energy band diagram of a MOS capacitor at equilibrium, accumulation and
strong inversion condition
14.Plot the transfer characteristics of an n-channel MOSFET. Give the current equation.

15. Plot the transfer characteristics of an n-channel MOSFET. Give the current equation.
Same as 14
16. An nMOS transistor has W/L= 4/2, gate oxide thickness 40 Ao, Mobility of electrons
180 cm2/Vsec. The threshold voltage is 0.4 V, relative permittivity of gate oxide 𝝐ox =3.9.
Calculate the drain current when Vgs = 1.5 V, Vds = 1.8 V.
17. What is channel length modulation in MOSFETs? How does it affect the output
characteristics of the MOSFET?
As we keep on increasing VDS, the region for which the inversion charge is zero keeps on
increasing for a constant value of VGS maintained. Thus channel length keeps on decreasing.
This phenomenon is called Channel Length Modulation. This is a similar to “Base Width
Modulation” Thus we get a VDS term in the expression for ID even when we are operating in
the saturation region. Generally, the fabrication of the MOSFET devices is done in a way such
that the change in length given by ΔL=L-L’ is low with a change in VDS.

18. Explain Drain induced barrier lowering?

When the depletion regions surrounding the drain extends to the source, so that the two-
depletion layer merge (i.e., when xdS + xdD = L), punch through occurs.
Punch through can be minimized with thinner oxides, larger substrate doping, shallower
junctions, and obviously with longer channels.
If the drain voltage is increased, the potential barrier in the channel decreases, leading to drain-
induced barrier lowering (DIBL).
The reduction of the potential barrier eventually allows electron flow between the source and
the drain, even if the gate-to-source voltage is lower than the threshold voltage.
The channel current that flows under this condition (VGS <VT)is called the sub-threshold
current
19. Explain the principle of operation and advantage of FinFET.

FinFET, also known as Fin Field Effect Transistor, is a type of non-planar or "3D" transistor
used in the design of modern processors . FinFETs are new generation transistors which utilize
tri-gate structure. In contrast to planar transistors where the Gate electrode was (usually) above
the channel, the Gate electrode "wraps" the channel
The distinguishing characteristic of the FinFET is that the conducting channel is wrapped by
a thin silicon "fin", which forms the body of the device. The conducting channel is greatly
controlled by the gate. The thickness of the fin (measured in the direction from source to
drain) determines the effective channel length of the device.
20. Draw and label the structure of a FINFET.

Same as 19

PART B
21 a) Define Fermi Dirac distribution function. Explain with relevant figures Fermi
Dirac distribution of intrinsic and extrinsic materials. (10)
To obtain the equations for concentration, the distribution of carriers over the available energy
needs to be studied. This is done by statistical methods. le, studying the property or behaviours
of a group as a whole instead of as an Individual particle.
Fermi Dirac distribution of intrinsic and extrinsic materials
For intrinsic semiconductors, probability of occupancy in conduction band equals probability

of vacancy in valence band. 1-f(Ev) = f(Ec)
For an n-type semiconductor probability of occupancy in the conduction band is much than the
probability of vacancy in the valence band f(Ec)» 1- f(Ev)
For a p-type semiconductor, probability of vacancy in valence band is much greater than
probability of occupancy in the conduction band. 1- f(Ev) » f(Ec)

21b) The Fermi level in a Si sample at 300K is located at 0.3eV below the bottom of the
conduction band. The effective density of states NC=3.22x1019cm-3 and NV=1.83x1019cm-
3. Determine (i) the electron and hole concentration at 300K (ii) the intrinsic carrier
concentration at 300K (4)
22. An n-type Si sample with Nd = 1016 cm-3 is steadily illuminated such that gop = 1021
EHP/cm3s. If Ʈn= Ʈp = lμs for this excitation, calculate the separation in the quasi-Fermi
levels, (EFn - EFp).(7)

22b) Illustrate the direct and indirect recombination process of excess carriers in
Semiconductors (7)
Direct band to band recombination
In direct band to band recombination an electron at conduction band minimum directly falls
into a hole at the valence band maximum, releasing the difference energy as a photon. As a
result an electron pair vanishes. This type of recombination mechanism is seen in direct band
gap semiconductor as GaAs, InP, etc. Generation and recombination are continuous process in
a semiconductor. is average time for which a charge carrier survives without recombination
after it is generated.

Indirect recombination via deep energy levels in the band gap
Impurity atoms other than donors and acceptors and crystal defects in a semiconductor
introduce localised energy levels deep in the band gap, away from the band edges. These levels
act as stepping stones for electrons between conduction band and valence band, making a
substantial enhancement in the recombination process. Depending on the location in the band
gap this level can act as a trap or recombination center for electron or hole. An electron trap
has a high probability of capturing a conduction band electron and setting it free. after
sometime. A hole trap has high probability of capturing a hole and subsequently releasing it to
the valence band. At a recombination centre, the probability of electron and hole captures are
nearly equal, thus an electron capture is followed by a hole capture, and this results in the
elimination of an EHP
(a) Capture of electron from conduction band by centre located at E,.
(b) Emission of an electron from the centre to the conduction band.
(c) Capture of a hole from the valence band. Here, the centre emits electron to the valence
band which is equivalent to the capture of a hole.
(d) Centre captures an electron from the valence band, which is equivalent to the emission of a
For the level to act as a recombination centre, the electron capture process (a) must be foll the
hole capture process (c) and both these processes should have nearly equal probability. If
capture (a) is followed by electron emission (b), this centre acts as electron trap. If hole cap is
followed by a hole emission (d) the centre acts as a hole trap.
23 a)Plot and explain the temperature dependence of intrinsic carrier concentration in

semiconductors (4) OUT OF SYLLABUS
b) With suitable sketches explain the indirect recombination mechanism via traps.(5)
Same as 22(b)

c)An n-type Si sample with Nd = 1016 cm-3 is steadily illuminated such that gop = 1021
EHP/cm3s. If Ʈn= Ʈp = lμs for this excitation, calculate the separation in the quasi-Fermi
levels, (EFn - EFp).(5)
Same as 22(a)
24a) Derive the equation for hole concentration in a semiconductor under thermal
equilibrium in terms of ni, Ef and Ei.(8)
Po = Nv [1-f(Ev)]

24 b) A silicon sample doped with 2x1016cm-3 of Boron atoms. ( ni= 1.5x1010cm-3

for Silicon at 300 K) Determine,
i. The equilibrium electron and hole concentrations
ii. Position of fermi energy level in the band gap
iii. Plot the energy band diagram
Na= 2x1016cm-3
P0= Na = 2x1016cm-3
n0= ni2/P0 = (1.5x1010)2/ 2x1016 = 1.125x104 cm-3
P0= ni exp(Ei-Ef)/KT
Ei-Ef =kT ln(P0/ni) = 0.026 ln(2x1016/1.5x1010) = 0.366 eV
25(a) Explain Hall effect? Derive the expression for determining carrier concentration in
a semiconductor bar using Hall effect. (7)



25b) Show when the minimum conductivity of a semiconductor sample occurs (ii) What
is the expression for the minimum conductivity σmin? (iii) Calculate σmin for Si at 300
K and compare with the intrinsic conductivity.

26 a) Derive the expression for drift current density, mobility of carriers and conductivity
of a semiconductor.


26 b) A Si sample with 1015/cm3 donors is uniformly optically excited at room

temperature such that 1019/cm3 electron-hole pairs are generated per second. Find the
separation of the quasi-Fermi levels and the change of conductivity upon shining the light.
Electron and hole lifetimes are both 10 ìs. Dp = 12 cm2/s. (6)

27. a) Explain the term mobility with respect to semiconductors. What are the factors on
which the mobility depends on? Explain the variation of mobility with temperature and
doping.(8)
Same as 25.a
27 b) A potential of 100 mV is applied across a semiconductor bar, and the resulting
current is 1 mA. A magnetic field of 10-4 Wb/cm2 is applied perpendicular to this
semiconductor bar. The hall voltage measured is -2 mV. The dimensions of the bar are
width = 0.1 mm, length = 5 mm and thickness = 10 μm. Find
i. the type of the semiconductor bar
ii. the concentration and the mobility of majority carriers (6)
VAB = 100 mV , I = 1 mA, Bz 10-4 Wb/cm2

VCD = VH =-2 mV. w = 0.1 mm, l = 5 mm
t = 10 μm
i. Hall Voltage -ve, n type
ii. 𝑛𝑜=𝐼𝑥𝐵𝑧 / 𝑞𝑡𝑉AB = 3.125x1017 cm-3
R = V/ I=100 Ω, 𝝆 =AR/l =2 mS
μ𝑛=1/𝑞𝑛𝜌
= 10,000 cm2/ Vsec
28a) Derive continuity equation for holes. Solve the continuity equation, under steady
state conditions assuming the semiconductor is long and no drift current is present. Plot
the solution.(10)


c) A p type semiconductor injected at one end with minority carrier electrons, under
steady state conditions. Na = 1015 cm-3 , Ʈn = 0.l us, Dn = 700 cm2/V Sec. Calculate the
electron diffusion length.(4)
Na = 1015 cm-3 , τn = 0.l μs, μn = 700 cm2/V Sec

Dn = (kT/q) μn = 18.2 cm2/sec
𝐿𝑛 = √𝐷𝑛τn = 1.35x10-3 cm
29 (a) Draw the energy band diagram of a metal N type semiconductor with 𝝓m ˃ 𝝓s
under equilibrium condition and on biasing. Is the contact rectifying or ohmic. Justify
your answer.(9)

Contact is Schottky
29(b) Assume that a p-n-p transistor is doped such that the emitter doping is 20 times that
in the base, the minority carrier mobility in the emitter is one fourth that in the base, and
the base width is one-tenth the minority carrier diffusion length. The carrier lifetimes are
equal. Calculate α and β for this transistor.(5)

30 (a) Derive ideal diode equation. (8)


30(b) A Schottky barrier diode is formed from n type Si of a doping 1016cm-3 and area
103cm2. A Si PN junction has the same area and NA=1019cm-3, ND=1016cm-3, τn=τp=1μs.
(i)Calculate the Schottky barrier diode current at 0.4V and 300K. (ii) Calculate the value
of forward bias to obtain same current for a PN junction.[R*=110A/K2, Electron affinity
of Si=4.15eV, metal work function=4.9eV,Diffusion constant=12cm2/s]

31 a) With the help of energy band diagrams, explain the behaviour of the contact
between a metal and an n -type semiconductor. Clearly distinguish between Schottky and
ohmic contacts.(10)

31 b) What is base width modulation? How does it affect the input and output
characteristics of a BJT? (4)
Same as 10
32 a) Derive the equation for the built in potential of a PN junction under thermal
equilibrium.(7)
Same as 11
b) A PN junction, doped on one side with 1018 cm-3 Boron atoms and the other side with
1016 cm-3of Arsenic atoms at 300 K. (ni = 1.5x1010cm-3 at 300 K and 𝝐r =11.9 for Silicon).
Calculate, the built-in potential.(3)
c) The following parameters are given for a PNP transistor. IEP= 2 mA, IEn= 0.01 mA,
IcP= 1.98 mA and Icn= 0.001mA. Determine
i. The base transport factor
ii. The emitter injection efficiency
iii. α and β
IEP= 2 mA, IEn= 0.01 mA, IcP= 1.98 mA and Icn= 0.001mA
𝐵𝑎𝑠𝑒 𝑇𝑟𝑎𝑛𝑠𝑝𝑜𝑟𝑡 𝑓𝑎𝑐𝑜𝑟, 𝐵 = 𝐼Cp/𝐼Ep = 0.99
𝐸𝑚𝑖𝑡𝑡𝑒𝑟 𝐼𝑛𝑗𝑒𝑐𝑡𝑖𝑜𝑛 𝑒𝑓𝑓𝑖𝑐𝑖𝑒𝑛𝑐𝑦, 𝛾=𝐼Ep/(𝐼Ep+𝐼En) = 0.995
𝛼 = 𝛽𝛾 = 0.985
𝛽 = 𝛼(1−𝛼) = 65.67
33 a) Draw and explain the CV characteristics of a MOS capacitor (8)
OUT OF SYLLABUS
(b) For a long channel n-MOSFET with W = 1V, calculate the VG required for an ID(sat.)
of 0.1 mA and VD(sat.) of 5V. Calculate the small-signal output conductance g and the
transconductance g m(sat.) at VD = 10V. Recalculate the new ID for VG - VT = 3V and
VD = 4V
WRONG DATA

34 (a) Draw and explain the drain characteristics and transfer characteristics of a
MOSFET. (8)
For linear region (VGS-VT) >VDS and for saturation (VGS-VT) < VDS
Explanation of the two regions
34(b) An Al-gate p-channel MOS transistor is made on an n-type Si substrate with Nd =

5x1017 cm- 3. The SiO2 thickness is 100 Å in the gate region, and the effective interface
charge Qi is 5 x 1010 q C/cm2 and the work function difference between metal and
semiconductor is 0.15V. Find Wmax , VFB , and VT of the device
MISSED DATA
35 a) Draw and explain the C-V Characteristics of an Ideal MOS capacitor. Derive
the expression for threshold voltage.(8)

CV Characteristics-Out of Syllabus
Threshold voltage
35 b) Draw the energy band diagrams, of an ideal MOS capacitor under equilibrium, and
strong inversion conditions (6)
Same as 13
36 (a) Draw the structure of n channel MOSFET. Derive the expression for drain current
of a MOSFET in the two regions of operation. What are the assumptions made in deriving
the expression? (10)



36 b) What is meant by body effect in MOSFET? How does it affect the threshold
voltage of the MOSFET? (4)
When VSB is positive, there is reveres bias between source and bulk. This causes depletion
layer to widen.

The electrons in the bulk are repelled by the body terminal and are now attracted by the gate
toward the oxide layer.
The threshold voltage of the MOS is also proportional to the density of electrons in the
depletion layer.
Hence as we accumulate more and more electrons in the depletion layer below the oxide
interface, there will be an increase in the value of threshold voltage.
As depletion region is widened, larger charge density is occupied. Therefore, the threshold
required to achieve inversion increases.
37 a) Distinguish between constant voltage scaling and constant field scaling (8)
Scaling of a MOS transistor means reducing the critical parameters of the device in accordance
with a given criterion in order to improve some performance features such as Speed,
Application, Power Dissipation, and so on while keeping the basic operational characteristics
unchanged.
scaling requires all device dimensions to reduce proportionally. The main device dimensions
are the channel length, channel width, and oxide thickness.
Lateral dimensions such as channel length and width are reduced by a factor of k, so should
the vertical dimensions such as source/drain junction depths and gate insulator thickness
Scaling of depleton width is achieved indirectly by scaling up doping conentrations.If we
simply reduce the dimensions of the device and kept the power supply voltages same,the
internal electric field in the device would increase.

Need for scaling

Scaling improves
1. Packing density: The packing density of the device improves as a result of scaling hence
we can fit more transistors in the same space as before.
2. Speed
3. Power dissipation
Two types of scaling are common:
(i) constant field scaling
(ii) constant voltage scaling.
Full scaling (constant-field scaling) –
▪ All dimensions are scaled by k and the supply voltage and other voltages are so
scaled
▪ Magnitude of internal electic field is kept constant
▪ Only lateral dimensions are changed
▪ Threshold voltage is also affected
Constant field scaling yields the largest reduction in the power-delay product of a single
transistor. However, it requires a reduction in the power supply voltage as one decreases the
minimum feature size.
For ideal scaling, power supply voltages should be reduced to keep the internal electric field
reasonably constant from one technology generation to the next.But power supply voltages are
not scaled hand in hand with the device dimensions, partly because of other system related
constraints. The longitudinal electric field in the pinch off region and the transverse electric
field across the gate oxide increase with MOSFET scaling which causes hot electron effects
and short channel effects.

Constant voltage scaling does not have this problem and is therefore the preferred scaling
method since it provides voltage compatibility with older circuit technologies.
Constant-voltage scaling: In Constant voltage scaling, all dimensions of the MOSFET are
reduced by a factor of ‘k’, but power supply & terminal voltage remain unchanged.
The voltages are not scaled and, in some cases, dimensions associated with voltage are not
scaled.
The disadvantage of constant voltage scaling is that the electric field increases as the minimum
feature length is reduced.
Quantity Sensitivity Constant Constant

Field Voltage
Scaling Parameters
Length L 1/S 1/S
Width W 1/S 1/S
Gate Oxide Thickness tox 1/S 1/S
Supply Voltage Vdd 1/S 1
Threshold Voltage VT0 1/S 1
Doping Density N A, N D S S2
Device Characteristics
Area (A) WL 1/S2 1/S2
D-S Current (IDS) (Vdd - vT)2 1/S S
Gate Capacitance (Cg) WL/tox 1/S 1/S

Power Dissipation (P) IDSVdd 1/S2 S
Power Dissipation Density P/A 1 S3
(P/A)
37 (b) Illustrate the operation of FinFET (6)
FinFET, also known as Fin Field Effect Transistor, is a type of non-planar or "3D" transistor
used in the design of modern processors
FinFETs are new generation transistors which utilize tri-gate structure. In contrast to planar
transistors where the Gate electrode was (usually) above the channel, the Gate electrode
"wraps" the channel
The distinguishing characteristic of the FinFET is that the conducting channel is wrapped by
a thin silicon "fin", which forms the body of the device.

The fact that the current can't flow "underneath" the gate when the transistor is in OFF state
reduces the leakage current.
Alternative techniques for stopping leakage current from flowing in the bulk were introduced
later, which allowed for manufacturing of Bulk finFETs.
Output Characteristics
Drain Characteristics
Transfer Characteristics
38.a) What is meant by scaling in MOSFETs? Explain the challenges involved in device
scaling? (7)

Same as 37
38b) Explain the concept of constant voltage scaling and its limitations.(7)
Same as 37
39.Explain any four short channel effects in MOSFET (14)
Short-channel effects occur in MOSFETs in which the channel length is comparable to
the depletion layer widths of the source and drain junctions.
A MOSFET device is considered to be short channel device when the channel length is the
same order of magnitude as the depletion-layer widths (xdD, xdS) of the source and drain
junction. (That is, the effective channel length Leff is approximately equal to the source and
drain junction depth x).
As the channel length L is reduced to increase both the operation speed and the number of
components per chip, the so-called short-channel effects arise.
The short-channel effects are attributed to two physical phenomena:
1. The limitation imposed on electron drift characteristics in the channel

2. The modification of the threshold voltage due to the shortening channel length.
This occurs due to the charge sharing between source/drain and gate. A triangle region forms
at both ends. Hence the rectangular area under the gate becomes Trapizoid
Different short-channel effects include
1. Channel Length Modulation
2. Drain-induced barrier lowering and “Punch through”
3.Velocity saturation
4.Threshold voltage variations

5. Hot carrier effects

Channel Length Modulation(CLM)
As we keep on increasing VDS, the region for which the inversion charge is zero keeps on
increasing for a constant value of VGS maintained. Thus channel length keeps on decreasing.
This phenomenon is called Channel Length Modulation.
This is a similar to “Base Width Modulation” Thus we get a VDS term in the expression for ID
even when we are operating in the saturation region.
Generally, the fabrication of the MOSFET devices is done in a way such that the change in
length given by ΔL=L-L’ is low with a change in VDS.
Drain Induced Barrier Lowering (DIBL)
When the depletion regions surrounding the drain extends to the source, so that the two-
depletion layer merge (i.e., when xdS + xdD = L), punch through occurs.
Punch through can be minimized with thinner oxides, larger substrate doping, shallower
junctions, and obviously with longer channels.
The current flow in the channel depends on creating and sustaining an inversion layer on the
surface. If the drain voltage is increased, the potential barrier in the channel decreases, leading
to drain-induced barrier lowering (DIBL).
The reduction of the potential barrier eventually allows electron flow between the source and
the drain, even if the gate-to-source voltage is lower than the threshold voltage.
The channel current that flows under this condition (VGS <VT)is called the sub-threshold
current

Velocity Saturation
The velocity of charge carriers, such as electrons or holes, is proportional to the electric field
that drives them, but that is only valid for small fields.
As the field gets stronger, their velocity tends to saturate. That means that above a critical
electric field, they tend to stabilize their speed and eventually cannot move faster.
Velocity saturation is specially seen in short-channel MOSFET transistors, because they have
higher electric fields
The drift velocity of the electrons in the inversion layer to be proportional to the lateral electric
field applied. The proportionality constant was given by .
The key point to understand the effect of velocity saturation is that the linearity of the drift
velocity only holds true for low values of the applied electric field. The actual variation of drift
velocity with respect to the applied electric field is shown in figure 6.
Figure 6: Variation of drift velocity of electron w.r.t. applied electric field
Threshold Variations
The threshold voltage is only a function of the manufacturing technology and the applied body
bias VSB.

The threshold can therefore be considered as a constant over all NMOS (PMOS) transistors in
a design. As the device dimensions are reduced, this model becomes inaccurate, and the
threshold potential becomes a function of L, W, and VDS.
Two-dimensional second-order effects that were ignorable for long-channel devices suddenly
become significant.
In the traditional derivation of the VTO, for instance, it is assumed that the channel depletion
region is solely due to the applied gate voltage and that all depletion charge beneath the gate
originates from the MOS field effects.
This ignores the depletion regions of the source and reverse-biased drain junction, which
become relatively more important with shrinking channel lengths.
Since a part of the region below the gate is already depleted (by the source and drain fields), a
smaller threshold voltage suffices to cause strong inversion.
In other words, VT0 decreases with L for short-channel devices (Figure 3.35a).
40 a) What is meant by DIBL in MOSFETs? How does it affect the threshold voltage of
a MOSFET? (7)
REFER QUESTION 39
b) Explain the concepts of velocity saturation and hot carrier effects in a MOSFET. (7)
REFER QUESTION 39
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Previous Question Papers solved

ECT 201 SOLID STATE DEVICES

Gradient indicates the current density

4. With suitable examples, distinguish between elemental and compound

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

6. State and explain the terms in Einstein relation

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

8. Write down the current equations in a semiconductor.

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

11. Derive the expression for built in potential of a PN junction diode

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

18. Explain Drain induced barrier lowering?

19. Explain the principle of operation and advantage of FinFET.

20. Draw and label the structure of a FINFET.

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

Fermi Dirac distribution of intrinsic and extrinsic materials

For intrinsic semiconductors, probability of occupancy in conduction band equals probability

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

Indirect recombination via deep energy levels in the band gap

(a) Capture of electron from conduction band by centre located at E,.

(b) Emission of an electron from the centre to the conduction band.

23 a)Plot and explain the temperature dependence of intrinsic carrier concentration in

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

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24 b) A silicon sample doped with 2x1016cm-3 of Boron atoms. ( ni= 1.5x1010cm-3

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

26 b) A Si sample with 1015/cm3 donors is uniformly optically excited at room

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

VAB = 100 mV , I = 1 mA, Bz 10-4 Wb/cm2

ii. 𝑛𝑜=𝐼𝑥𝐵𝑧 / 𝑞𝑡𝑉AB = 3.125x1017 cm-3

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram

Downloaded from Ktunotes.in

Prepared by: Ms. Faseela K P, Dept. of ECE, MESCE, Kuttippuram