6-71-W24v0-D02a GP

W243HVQ Series
Preface
Notebook Computer
W243HVQ
Service Manual
Preface
I
Preface
Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained
herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent ven-
dor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are
they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication.
This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publica-
tion, except for copies kept by the user for backup purposes.
Brand and product names mentioned in this publication may or may not be copyright s and/or registered trademarks of
their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement
of that product or its manufacturer.
Preface
Version 1.1
May 2011
Trademarks
Intel and Intel Core are trademarks of Intel Corporation.
Windows® is a registered trademark of Microsoft Corporation.
Other brand and product names are trademarks and /or registered trademarks of their respective companies.
II
Preface
About this Manual

This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and
inspection of personal computers.
It is organized to allow you to look up basic information for servicing and/or upgrading components of the W243HVQ
series notebook PC.
The following information is included:
Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade
elements of the system.
Appendix A, Part Lists
Preface
Appendix B, Schematic Diagrams
Appendix C, Updating the FLASH ROM BIOS
III
Preface
IMPORTANT SAFETY INSTRUCTIONS

Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to per-
sons when using any electrical equipment:
1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of elec-
trical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit with an AC Input of 100 - 240V, 50 - 60Hz, DC Output
of 19V, 3.42A or 18.5V, 3.5A (65W) minimum AC/DC Adapter.
Preface
CAUTION
This Computer’s Optical Device is a Laser Class 1 Product
FCC Statement
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
This device may not cause harmful interference.
This device must accept any interference received, including interference that may cause undesired operation.
IV
Preface
Instructions for Care and Operation

The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions:
1. Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer Do not place it on an unstable Do not place anything heavy
to any shock or vibration. surface. on the computer.
2. Keep it dry, and don’t overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not expose it to excessive Do not leave it in a place Don’t use or store the com- Do not place the computer on
Preface
heat or direct sunlight. where foreign matter or mois- puter in a humid environment. any surface which will block
ture may affect the system. the vents.
3. Follow the proper working procedures for the computer. Shut the computer down properly and don’t forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power Do not turn off any peripheral Do not disassemble the com- Perform routine maintenance
until you properly shut down devices when the computer is puter by yourself. on your computer.
all programs. on.
V
Preface
4. Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong mag-
netic fields. These can hinder proper performance and damage your data.
5. Take care when using peripheral devices.
Use only approved brands of Unplug the power cord before

peripherals. attaching peripheral devices.
Power Safety
Preface
The computer has specific power requirements:

• Only use a power adapter approved for use with this computer.
• Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are
 unsure of your local power specifications, consult your service representative or local power company.
Power Safety • The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do
Warning not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one.
Before you undertake • When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire.
any upgrade proce- • Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices.
dures, make sure that • Before cleaning the computer, make sure it is disconnected from any external power supplies.
you have turned off the
power, and discon-
nected all peripherals Do not plug in the power Do not use the power cord if Do not place heavy objects
and cables (including cord if you are wet. it is broken. on the power cord.
telephone lines). It is
advisable to also re-
move your battery in
order to prevent acci-
dentally turning the
machine on.
VI
Preface
Battery Precautions
• Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer.
• Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the
computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire.
• Recharge the batteries using the notebook’s system. Incorrect recharging may make the battery explode.
• Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service
personnel.
• Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode
or leak if exposed to fire, or improperly handled or discarded.
• Keep the battery away from metal appliances.
• Affix tape to the battery contacts before disposing of the battery.
• Do not touch the battery contacts with your hands or metal objects.
Battery Guidelines
The following can also apply to any backup batteries you may have.
Preface
• If you do not use the battery for an extended period, then remove the battery from the computer for storage.
• Before removing the battery for storage charge it to 60% - 70%.
• Check stored batteries at least every 3 months and charge them to 60% - 70%.

Battery Disposal
The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under var-
ious state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste
officials for details in your area for recycling options or proper disposal.
Caution
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer.
Discard used battery according to the manufacturer’s instructions.
Battery Level
Click the battery icon in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10%
will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week.
VII
Preface
Related Documents
You may also need to consult the following manual for additional information:
User’s Manual on CD/DVD

This describes the notebook PC’s features and the procedures for operating the computer and its ROM-based setup pro-
gram. It also describes the installation and operation of the utility programs provided with the notebook PC.
System Startup
1. Remove all packing materials.
2. Place the computer on a stable surface.
3. Insert the battery and make sure it is locked in position.
4. Securely attach any peripherals you want to use with the computer
(e.g. keyboard and mouse) to their ports.
Preface
5. Attach the AC/DC adapter to the DC-In jack at the rear of the
computer, then plug the AC power cord into an outlet, and connect
the AC power cord to the AC/DC adapter.
6. Use one hand to raise the lid/LCD to a comfortable viewing angle (do
not exceed 130 degrees); use the other hand (as illustrated in Figure
1) to support the base of the computer (Note: Never lift the computer
by the lid/LCD).

Shut Down
7. Press the power button to turn the computer “on”.
Note that you should
always shut your
computer down by
130 ﾟ choosing Shut Down
Figure 1 from the Start Menu.
Opening the Lid/LCD/ This will help prevent
Computer with AC/DC hard disk or system
Adapter Plugged-In problems.
VIII
Preface
Contents
Introduction ..............................................1-1 Top ................................................................................................. A-3
Bottom with 3G ............................................................................. A-4
Overview ......................................................................................... 1-1 Bottom without 3G ........................................................................ A-5
Specifications ..................................................................................1-2 SATA BLU-RAY COMBO .......................................................... A-6
External Locator - Top View with LCD Panel Open ......................1-4 SATA DVD SUPER MULTI ........................................................ A-7
External Locator - Front & Right Side Views .................................1-5 LCD ............................................................................................... A-8
External Locator - Left Side & Rear View .....................................1-6 HDD ............................................................................................... A-9
External Locator - Bottom View .....................................................1-7
Mainboard Overview - Top (Key Parts) .........................................1-8 Schematic Diagrams................................. B-1
Mainboard Overview - Bottom (Key Parts) ....................................1-9 System Block Diagram ...................................................................B-2
Mainboard Overview - Top (Connectors) .....................................1-10 PROCESSOR/ DMI, PEG, FDI ......................................................B-3
Mainboard Overview - Bottom (Connectors) ...............................1-11 PROCESSOR/ CLK, MISC, JTAG ................................................B-4
Disassembly ...............................................2-1 PROCESSOR/ DDR3 .....................................................................B-5
Preface
PROCESSOR/ POWER1 ...............................................................B-6
Overview ......................................................................................... 2-1
PROCESSOR/ POWER2 ...............................................................B-7
Maintenance Tools ..........................................................................2-2 PROCESSOR/ GND .......................................................................B-8
Connections .....................................................................................2-2
PROCESSOR/ RESERVED ...........................................................B-9
Maintenance Precautions .................................................................2-3 DDR3 SO-DIMM_0 .....................................................................B-10
Disassembly Steps ...........................................................................2-4 DDR3 SO-DIMM_1 .....................................................................B-11
Removing the Battery ......................................................................2-5
LVDS, Inverter .............................................................................B-12
Removing the Hard Disk Drive .......................................................2-6 HDMI, CRT ..................................................................................B-13
Removing the Optical (CD/DVD) Device ......................................2-8 PCH/ HDA, JTAG. SATA ............................................................B-14
Removing and installing the ODD Bezel .......................................2-9 PCH/ PCI-E, SMBUS, CLK .........................................................B-15
Removing the System Memory (RAM) ........................................2-10 PCH/ DMI, FDI, GPIO ................................................................. B-16
Removing and Installing a Processor ............................................2-12 PCH/ LVDS, DDI, CRT ...............................................................B-17
Removing the Wireless LAN Module ...........................................2-15 PCH/ PCI, USB, NVRAM ............................................................B-18
Removing the 3.75G Module ........................................................2-16 PCH/ GPIO, VSS_NCTF, RSVD .................................................B-19
Removing the Keyboard ................................................................2-17 PCH/ POWER1 ............................................................................B-20
Removing the Top Case module ...................................................2-19 PCH/ POWER2 ............................................................................B-21
Part Lists ..................................................A-1 PCH/ GND ....................................................................................B-22
Part List Illustration Location ........................................................ A-2 New Card, Mini PCIE ...................................................................B-23
XI
Preface
CCD, 3G, TPM ............................................................................. B-24 Use the flash tools to update the BIOS ...........................................C-2
Card Reader/LAN JMC261C ....................................................... B-25 Restart the computer (booting from the HDD) ...............................C-2
INTEL LAN 82579 ...................................................................... B-26
LAN (82579), SATA HDD, ODD ............................................... B-27
USB3.0 NEC, USB CHARGER .................................................. B-28
KBC-ITE IT81518 ....................................................................... B-29
LED, MDC, BT ............................................................................ B-30
AUDIO CODEC ALC269 VIA1802 ........................................... B-31
USB, FAN, TP, MULTI CON ..................................................... B-32
5VS, 3VS, 1.5V/0.75VS, 1.5VS CPU .......................................... B-33
VDD3, VDD5 ............................................................................... B-34
Power 1.05VS/0.75V, 1.8VS ....................................................... B-35
Power 1.05VS LAN M ................................................................. B-36
Power 0.85VS ............................................................................... B-37
Preface
Power V-Core1 ............................................................................. B-38

Power V-Core2 VGFX ................................................................. B-39
AC IN, CHARGER ...................................................................... B-40
CLICK & FINGER BOARD ....................................................... B-41
AUDIO BOARD/ USB ................................................................ B-42
Power Switch & LID Board ......................................................... B-43
EXTERNAL ODD BOARD ........................................................ B-44
FINGERPRINT BOARD ............................................................. B-45
POWER SEQUENCE .................................................................. B-46
POWER SEQUENCE 1 ............................................................... B-47
...................................................................................................... B-48
Updating the FLASH ROM BIOS......... C-1
To update the FLASH ROM BIOS you must: C-1
Download the BIOS ....................................................................... C-1
Unzip the downloaded files to a bootable CD/DVD/ or USB Flash
drive ................................................................................................ C-1
Set the computer to boot from the external drive ........................... C-1
XII
Introduction
Chapter 1: Introduction
Overview
This manual covers the information you need to service or upgrade the W243HVQ series notebook computer. Informa-
tion about operating the computer (e.g. getting started, and the Setup utility) is in the User’s Manual. Information about
dri-vers (e.g. VGA & audio) is also found in the User’s Manual. The manual is shipped with the computer.
Operating systems (e.g. Window 7, etc.) have their own manuals as do applic ation softwares (e.g. word processing and
database programs). If you have questions about those programs, you should consult those manuals.
The W243HVQ series notebook is designed to be upgradeable. See Disassembly on page 2 - 1 for a detailed description
1.Introduction
of the upgrade procedures for each specific component. Please take note of the warning and safety information indicated
by the “” symbol.
The balance of this chapter reviews the computer’s technical specifications and features.
Overview 1 - 1
Introduction
Specifications Processor Options Audio
Intel® Core™ i7 Processor High Definition Audio Compliant Interface

i7-2620M (2.70GHz) 2 * Built-In Speakers
4MB L3 Cache, 32nm, DDR3-1333MHz, TDP 35W Built-In Microphone
 Intel® Core™ i5 Processor
Latest Specification Information Security
i5-2540M (2.60GHz), i5-2520M (2.50GHz)
The specifications listed here are correct at the 3MB L3 Cache, 32nm, DDR3-1333MHz, TDP 35W Security (Kensington® Type) Lock Slot
time of sending them to the press. Certain items BIOS Password
(particularly processor types/speeds) may be Core Logic
Intel® vPro technology
changed, delayed or updated due to the manu-
Intel® QM67 Chipset TPM v1.2
facturer's release schedule. Check with your
service center for more details. (Factory Option) Fingerprint Reader
LCD
Keyboard
14" (35.56cm), 3.6mm, HD TFT LCD
1.Introduction
“WinKey” keyboard (with embedded numeric keypad)

Memory
Pointing Device
Two 204 Pin SO-DIMM Sockets Supporting DDR3 1333MHz
 Memory Built-in Touchpad
CPU Memory Expandable up to 8GB
Interface
The CPU is not a user serviceable part. Ac- (The real memory operating frequency depends on the FSB
cessing the CPU in any way may violate your of the processor.) Two USB 2.0 Ports
warranty.
One USB 3.0 Ports
Video Adapter
One HDMI-Out Port
Intel® HD Graphics 3000 One Headphone-Out Jack
Shared Memory Architecture of up to 1748MB One Microphone-In Jack
MS DirectX® 10 compatible One RJ-45 LAN Jack
One DC-in Jack
BIOS
One External Monitor Port
Two 32Mb SPI Flash ROM
AMI BIOS
Storage
(Factory Option) One Changeable 12.7mm(h) Optical

Device Type Drive (Super Multi Drive Module or Blu-Ray
Combo Drive Module)
One Changeable 2.5" 9.5mm (h) SATA HDD
1 - 2 Specifications
Introduction
Communication Dimensions & Weight
Intel® 82579LM GbE Network Adapter 340mm (w) * 238mm (d) * 33.50 - 25.05mm (h)
(Factory Option) 1.3M Pixel USB PC Camera Module 2.147 kg (with 48.84WH Battery and ODD)
(Factory Option) 3.75G/HSPA Mini-Card Module
WLAN/ Bluetooth Half Mini-Card Modules:
(Factory Option) Intel® Centrino® Advanced-N 6230 Wire-
less LAN (802.11a/g/n)
(Factory Option) Intel® Centrino® Advanced-N 6205 Wire-
less LAN (802.11a/g/n)
Mini Card Slots
Slot 1 for WLAN Module or Combo WLAN and Bluetooth

Module
(Factory Option) Slot 2 for 3.75G/HSPA Module
1.Introduction
Card Reader
Embedded Multi-In-1 Card Reader

MMC (MultiMedia Card) / RS MMC
SD (Secure Digital) / Mini SD / SDHC/ SDXC
MS (Memory Stick) / MS Pro / MS Duo
Power
6 Cell Smart Lithium-Ion Battery Pack, 48.84WH

(Factory Option) 6 Cell Smart Lithium-Ion Battery Pack,
62.16WH
Full Range AC/DC Adapter

AC Input: 100 - 240V, 50 - 60Hz
DC Output: 19V, 3.42A or 18.5V, 3.5A (65W)
Environmental Spec
Temperature
Operating: 5°C - 35°C
Non-Operating: -20°C - 60°C
Relative Humidity
Operating: 20% - 80%
Non-Operating: 10% - 90%
Specifications 1 - 3
Introduction
Figure 1
External Locator - Top View with LCD Panel Open
Top View
1
1. PC Camera
(Optional)
2. LCD
3. Power Button
4. Hot-Key Buttons
5. LED Status
Indicators
6. Keyboard 2
1.Introduction
7. Built-In
Microphone
8. Touchpad &
Buttons
9. Fingerprint
Reader (Optional)
5 4 3
1 - 4 External Locator - Top View with LCD Panel Open

Introduction
External Locator - Front & Right Side Views Figure 2

Front View
1. LED Power
Indicators
FRONT VIEW
1.Introduction
Figure 3
Right Side View
1. Microphone-In
RIGHT SIDE VIEW Jack
2. Headphone-Out
Jack
3. USB 2.0 Port
3 4 4. Optical Device
1 2 6
5 Drive Bay
5. Emergency Eject
Hole
6. Security Lock
Slot
External Locator - Front & Right Side Views 1 - 5

Introduction
External Locator - Left Side & Rear View

Figure 4
Left Side View
1. DC-In Jack
2. External Monitor /
Port LEFT SIDE VIEW
3. RJ-45 LAN Jack
4. HDMI-Out Port
5. USB 3.0 Port
6. Vent 4 5 7
2 3 8
7. USB 2.0 Port
1 6
8. Multi-in-1 Card
1.Introduction
Reader
Figure 5 REAR VIEW

Rear View
1. Battery
1 - 6 External Locator - Left Side & Rear View

Introduction
External Locator - Bottom View

Figure 6
Bottom View
1. Battery
2. Component Bay
Cover
3. Vent
1 4. Hard Disk Bay
Cover
5. Speakers
1.Introduction
6. USIM Card Cover
3
2
3
6
3

4 3 3 Overheating
To prevent your com-

5 5 puter from overhea-
ting, make sure no-
thing blocks any vent
while the computer is
in use.
External Locator - Bottom View 1 - 7

Introduction
Figure 7 Mainboard Overview - Top (Key Parts)

Mainboard Top
Key Parts
1. JMICRO JMC261
2. ITE IT8518E
3. AZALIA CODEC
REALTEK
ALC269
1.Introduction
1 2
1 - 8 Mainboard Overview - Top (Key Parts)

Introduction
Mainboard Overview - Bottom (Key Parts) Figure 8

Mainboard Bottom
Key Parts
1. Memory Slots
DDR3 SO-DIMM
2. CPU Socket (no
CPU installed)
3. Platform Controller
Hub
4. Mini-Card
Connector (WLAN
Module)
1.Introduction
2 5. SIMLOCK
6. 3.75G/HSPA
1
Module Connector
6 5 4
Mainboard Overview - Bottom (Key Parts) 1 - 9

Introduction
Figure 9 Mainboard Overview - Top (Connectors)

Mainboard Top
Connectors
1. HDMI-Out Port
2. USB Port 3.0
3. USB Port 2.0
4. Speaker Cable
Connector
5. Microphone
9
Cable Connector
6. Audio Board
Connector
1.Introduction
7. TouchPad Cable
Connector 1
8. Keyboard Cable
Connector
9. Switch Board 2
Cable Connector
5 7
1 - 10 Mainboard Overview - Top (Connectors)

Introduction
Mainboard Overview - Bottom (Connectors) Figure 10

Mainboard Bottom
9 Connectors
1. Battery
Connector
10 8
11 2. ODD Connector
1 3. HDD Connector
4. CMOS Battery
Connector
7 5. CPU Fan Cable
Connector
6. Multi-in-1 Card
1.Introduction
Reader
7. RJ-45 LAN Jack
8. External Monitor
Port
9. DC-In Jack
10. CCD Cable
4 Connector
2 11. LCD Cable
Connector
3 6
Mainboard Overview - Bottom (Connectors) 1 - 11

Introduction
1.Introduction
1 - 12
Disassembly
Chapter 2: Disassembly
Overview
This chapter provides step-by-stepinstructions for disassembling theW243HVQ series notebook’s parts and subsystems.
When it comes to reassembly, reverse the procedures (unless otherwise indicated).
We suggest you completely review any procedure before you take the computer apart.
Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are
repeated here for your convenience.
2.Disassembly
To make the disassembly process easier each section may have a box in the page margin. In formation contained under
the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a  
lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the dis-
Information
assembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previ-
ous disassembly procedure. The amount of screws you should be left with will be listed here also.
A box with a  will also provide any possible helpful information. A box with a  contains warnings.
An example of these types of boxes are shown in the sidebar.


Warning
Overview 2 - 1
Disassembly
NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
battery is removed too).
Maintenance Tools
The following tools are recommended when working on the notebook PC:
• M3 Philips-head screwdriver
• M2.5 Philips-head screwdriver (magnetized)
• M2 Philips-head screwdriver
• Small flat-head screwdriver
• Pair of needle-nose pliers
• Anti-static wrist-strap
2.Disassembly
Connections
Connections within the computer are one of four types:
Locking collar sockets for ribbon connectors To release these connectors, use a small flat-head screwdriver to
gently pry the locking collar away from its base. When replac-
ing the connection, make sure th e connector is oriented in the
same way. The pin1 side is usually not indicated.
Pressure sockets for multi-wire connectors To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.
Pressure sockets for ribbon connectors To release these connectors, use a small pair of needle-nose pli-
ers to gently lift the connector awa y from its socket. When re -
placing the connection, make sure the connector is orie nted in
the same way. The pin1 side is usually not indicated.
Board-to-board or multi-pin sockets To separate the boards, gently rock them from side to side as
you pull them apart. If the connec tion is very tight, use a small
flat-head screwdriver - use just enough force to start.
2 - 2 Overview
Disassembly
Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a re- 
moval and/or replacement job, take the following precautions: Power Safety
Warning
1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other
Before you undertake
components could be damaged. any upgrade proce-
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight. dures, make sure that
3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong mag- you have turned off the
netic fields. These can hinder proper performance and damage components and/or data. You should also monitor power, and discon-
the position of magnetized tools (i.e. screwdrivers). nected all peripherals
and cables (including
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly telephone lines). It is
damaged. advisable to also re-
5. Be careful with power. Avoid accidental shocks, discharges or explosions. move your battery in
2.Disassembly
•Before removing or servicing any part from the computer, turn the computer off and detach any power supplies. order to prevent acci-
•When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire. dentally turning the
6. Peripherals – Turn off and detach any peripherals. machine on.
7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity.
Before handling any part in the computer, discharge any static electricity inside the computer. When handling a
printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that
you use an anti-static wrist strap instead.
8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands pro-
duce oils which can attract corrosive elements.
9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted
to charged surfaces, reducing performance.
10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as
screws, loose inside the computer.
Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth.
Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.
Overview 2 - 3
Disassembly
Disassembly Steps
The following table lists the disassembly steps, and on which pageto find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.
To remove the Battery: To remove the 3.75G Module:

1. Remove the battery page 2 - 5 1. Remove the battery page 2 - 5
2. Remove the 3.75G module page 2 - 15
To remove the HDD:
1. Remove the battery page 2 - 5
To remove the Keyboard:
2. Remove the HDD page 2 - 6
To remove the Optical Device: 2. Remove the keyboard page 2 - 17
2.Disassembly

To remove the Top Case module:
2. Remove the Optical device page 2 - 8
3. Removing and installing the  1. Remove the battery page 2 - 5
ODD Bezel page 2 - 9 2. Remove the HDD page 2 - 6
3. Remove the system memory page 2 - 9
To remove the System Memory: 4. Remove the processor page 2 - 12
1. Remove the battery page 2 - 5 5. Remove the WLAN module page 2 - 15
2. Remove the system memory page 2 - 10 6. Remove the 3.75G module page 2 - 15
7. Remove the keyboard page 2 - 17
To remove and install a Processor: 8. Remove the Top Case module page 2 - 19
2. Remove the processor page 2 - 12
3. Install the processor page 2 - 14
To remove the Wireless LAN Module:
2. Remove the WLAN module page 2 - 15
2 - 4 Disassembly Steps
Disassembly
Removing the Battery Figure 1

1. Turn the computer off, and turn it over. Battery Removal
2. Slide the latch 1 in the direction of the arrow (Figure 1a).
a. Slide the latch and hold it
3. Slide the latch 2 in the direction of the arrow, and hold it in place (Figure 1a). in place.
4. Slide the battery 63 in the direction of the arrow 4 (Figure 1b). b. Slide the battery in the di-
rection of the arrow.
a. b.
3
2 1
2.Disassembly
4

3. Battery
Removing the Battery 2 - 5

Disassembly
Removing the Hard Disk Drive

Figure 2 The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 9.5mm
HDD Assembly (h). Follow your operating system’s installation instructions, and install all necessary drivers and utilities (as outlined in
Removal Chapter 4 of the User’s Manual) when setting up a new hard disk.
a. Locate the HDD bay cover Hard Disk Upgrade Process

and remove the screws.
1. Turn off the computer, and remove the battery (page 2 - 5).
2. Locate the hard disk bay cover and remove screws 1 & 2 (Figure 2a).

2.Disassembly
a.
HDD System Warning
New HDD’s are blank. Before you

begin make sure:
You have backed up any data

you want to keep from your old
HDD.
You have all the CD-ROMs and

FDDs required to install your op-
erating system and programs.
1 2
If you have access to the internet,
download the latest application
and hardware driver updates for
 the operating system you plan to
install. Copy these to a remov-
able medium.
• 2 crews
S
2 - 6 Removing the Hard Disk Drive

Disassembly
3. Remove the hard disk bay cover 63 (Figure 3b). Figure 3

4. Grip the tab and slide the hard disk in the direction of arrow 4 (Figure 3c). HDD Assembly
5. Lift the hard disk out of the bay 5 (Figure 3d). Removal (cont’d.)
6. Remove the screws 6 - 9 and the mylar cover 10 from the hard disk 11 (Figure 3e).
7. Reverse the process to install a new hard disk (do not forget to replace all the screws and covers). b. Remove the HDD bay
cover.
c. Grip the tab and slide the
b. d. HDD in the direction of
the arrow.
d. Lift the HDD assembly
5 out of the bay.
e. Remove the screws and
mylar cover.
2.Disassembly
3
c. e. 9
8 6
4 10
7 
3. HDD Bay Cover
10. Mylar Cover
11. HDD
11
• 4 crews
S
Removing the Hard Disk Drive 2 - 7

Disassembly
Figure 4 Removing the Optical (CD/DVD) Device

Optical Device
1. Turn off the computer, and remove the battery (page 2 - 5).
Removal
2. Locate the RAM & CPU bay cover 1 , and remove screws 2 - 5 (Figure 4a).
3. Carefully (a fan and cable are attached to the under side of the cover) lift up the bay cover.
a. Remove the screws.
b. Remove the cover. 4. Carefully disconnect the fan cable 6 , and remove the cover 1 (Figure 4b).
c. Remove the screw and 5. Remove the screw at point 7 , and use a screwdriver to carefully push out the optical device 9 at point 8 (Fig-
push the optical device ure 4c).
out off the computer at 6. Insert the new device and carefully slide it into the computer (the device only fits one way. DO NOT FORCE IT; The
point 8 . screw holes should line up).
7. Restart the computer to allow it to automatically detect the new device.
a. c.
2
2.Disassembly
1
4 7
8
5
b.

1. Component Bay Cov-
er 1
9. Optical Device 9
• 5 crews
S 6
2 - 8 Removing the Optical (CD/DVD) Device

Disassembly
Removing and installing the ODD Bezel Figure 5

ODD Bezel
1. Turn off the computer, remove the battery and remove the ODD(page 2 - 5).
2. Carefully unsnap the ODD Bezel 1 from ODD in the direction of the arrow 2 .
a. Unsnap the ODD Bezel
in the direction of the ar-
a. row 2 .
b. Snap the bezel onto the
ODD at points 3 and
4 .
2
2.Disassembly
3. Snap the bezel onto the ODD at points 3 and 4 .
b.
4

3
1. ODD Bezel
Removing and installing the ODD Bezel 2 - 9

Disassembly
Figure 6 Removing the System Memory (RAM)

RAM Module
Removal The computer has two memory socketsfor 200 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting
DDR3 1333MHz. The main memory can be expanded up to 8GB. The SO-DIMM modules supported are 1GB, 2GB and
a. Locate the memory 4GB and DDRIII Modules. The total memory size is automatically detected by the POST routine once you turn on your
socket. computer.
b. Pull the release
latches.
c. Remove the mod- Memory Upgrade Process
ule. 1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 8).
2. The RAM modules will be visible at point 1 on the main board (Figure 6a).
3. Gently pull the two release latches ( 2 & 3 ) on the sides of the memory socket in the direction indicated by the
arrows (Figure 6b).
2.Disassembly

Contact Warning a. b. c.
Be careful not to touch

the metal pins on the
module’s connecting 1 2
edge. Even the clean-
est hands have oils 4
which can attract parti-
cles, and degrade the
module’s perfor-
mance.
3
 4. The RAM module 4 will pop-up (Figure 6c), and you can then remove it.
4. RAM Module 5. Pull the latches to release the second module if necessary.
6. Insert a new module holding it at about a 30° angle and fit the connectors firmly into the memory slot.
7. The module’s pin alignment will allow it to only fit one way. Make sure the module is seated as far into the slot as it
will go. DO NOT FORCE the module; it should fit without much pressure.
8. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.
2 - 10 Removing the System Memory (RAM)

Disassembly
9. Replace the bay cover and screws (make sure you reconnect the fan cable before screwing down the bay Figure 7
cover). RAM Module
Note that there are four 5 - 8 cover pins which need to be aligned with slots in the case, to insure a proper cover Removal (cont’d.)
fit, before screwing down the bay cover (Figure 7d).
d. Properly re-insert the
d. 5 bay cover pins.
2.Disassembly
8
10. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.
Removing the System Memory (RAM) 2 - 11

Disassembly
Figure 8 Removing and Installing a Processor

Processor Removal
Processor Removal Procedure
a. The CPU heat sink will 1. Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 8).
be visible at point A . 2. The CPU heat sink will be visible at point A (Figure 8a).
Remove the screws from 3. Loosen the CPU heat sink screws in the order 3 , 2 & 1 (the reverse order as indicated on the label Figure 8a).
the CPU heatsink.
4. Grip the heat sink tab and carefully lift the heat sink 4 up and off the computer (Figure 8b).
b. Grip the heat sink tab
and carefully lift the heat
sink up and off the com-
a.
puter.
3
2.Disassembly
1
A
2
b.
 4
4. Heat Sink
• 3 crews
S
2 - 12 Removing and Installing a Processor

Disassembly
5. Turn the release latch 5 towards the unlock symbol to release the CPU (Figure 9d).
6. Carefully (it may be hot) lift the CPU 6 up and out of the socket (Figure 9e). Figure 9
7. Reverse the process to install a new CPU. Processor Removal
8. When re-inserting the CPU, pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!). (cont’d)
c. Turn the release latch to

c. unlock the CPU.
d. Lift the CPU out of the
socket.
5 5
2.Disassembly
Unlock Lock
d.

Caution
6 The heat sink, and CPU area in
general, contains parts which are
subject to high temperatures. Allow
the area time to cool before remov-
ing these parts.

6. CPU
Removing and Installing a Processor 2 - 13

Disassembly
Figure 10 Processor Installation Procedure

Processor 1. Insert the CPU A (Figure 10a), pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE
Installation IT!), and turn the release latch B towards the lock symbol (Figure 10b).
2. Remove the sticker C (Figure 10c) from the heat sink.
a. Insert the CPU. 3. Insert the heat sink D as indicated in Figure 10d.
b. Turn the release latch to- 4. Tighten the CPU heat sink screws in the order 1 , 2 & 3 (the order as indicated on the label and Figure 10d).
wards the lock symbol.
5. Replace the component bay cover (don’t forget to replace the fan cable) and tighten the screws (page 2 - 9).
c. Remove the sticker from
the heat sink and insert
the heat sink. a. c.
d. Tighten the screws.
A
C
2.Disassembly
b. d.
D
3
B
1
 2
A. CPU
Note:
D. Heat Sink Tighten th e scre ws
in the order as indi-
• 3 crews
S cated on the label.
2 - 14 Removing and Installing a Processor

Disassembly
Removing the Wireless LAN Module Figure 11

Wireless LAN
1. Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
Module Removal
2. The Wireless LAN module will be visible at point 1 on the mainboard (Figure 11a).
3. Carefully disconnect the cable 2 , and then remove the screw 3 (Figure 11b).
a. Locate the WLAN.
4. The Wireless LAN module 4 (Figure 11c) will pop-up, and you can remove it from the computer (Figure 11d). b. Disconnect the cable
and remove the screw.
c. The WLAN module will
a. c. pop up.
d. Remove the Wireless
LAN module.
Note: Make sure you
2.Disassembly
reconnect the antenna
4 cable to the “1 + 2”
socket (Figure 11b).
1
b. d.
3
2 
4 4.Wireless LAN Module
• 1 crew
S
Removing the Wireless LAN Module 2 - 15

Disassembly
Figure 12 Removing the 3.75G Module

3.75G Module
Removal 1. Turn off the computer, remove the battery (page 2 - 5) and the component bay cover (page 2 - 8).
2. The 3.75G module will be visible at point 1 on the mainboard.
a. Remove the cover. 3. Carefully disconnect the cable 2 , then remove the screw 3 from the module socket.
b. Disconnect the cable 4. The 3.75G module 4 will pop-up.
and remove the screw. 5. Lift the 3.75G module (Figure 12d) up and off the computer.
c. The 3.75G module will
pop up. a. c.
d. Lift the 3.75G module
out.
2.Disassembly
1 1
d.
b.
2

4. 3.75G Module.
• 1 crew
S 3
4
2 - 16
Disassembly
Removing the Keyboard Figure 13

Keyboard Removal
1. Turn off the computer, and remove the battery (page 2 - 5),and the component bay cover (page 2 - 8)
2. Remove screws 1 - 2 from the bottom of the computer and use the Eject Pin Tool to carefully push out the key- a. Remove screws from the
board at point 3 bottom of the computer
and use the Eject Pin
3. Carefully lift the keyboard up, being careful not to bend the keyboard ribbon cable.
Tool to push out the key-
board at point 3 .
b.Carefully lift the keyboard
a. up.
c. 3
2.Disassembly
2
1
b.

4. Keyboard
• 2 crews
S
Removing the Keyboard 2 - 17

Disassembly
Figure 14 4. Disconnect the keyboard ribbon cable 5 from the locking collar socket 6 (Figure 13c)
Keyboard Removal 5. Carefully lift up the keyboard 4 (Figure 13d) off the computer.
(cont’d)
c. d.
c. Carefully lift the key-
board up and disconnect
the keyboard ribbon ca-
ble from the locking col-
lar socket.
d. Remove the keyboard. 5
6
 4
2.Disassembly
Re-Inserting the
Keyboard
When re-inserting the

keyboard firstly align the
four keyboard tabs at
the bottom (Figure 14d)
at the bottom of the key-
board with the slots in
the case. Keyboard Tabs

6. Keyboard
2 - 18 Removing the Keyboard

Disassembly
Removing the Top Case module Figure 15

Top Case module
1. Turn off the computer, and remove the battery (page 2 - 5), remove the HHD (page 2 - 6), remove the ODD (page Removal
2 - 8), remove the Memory (page 2 - 10) , remove Processor (page 2 - 12), remove the WLAN (page 2 - 15) and
the remove Keyboard (page 2 - 17). a. Remove screws and the
2. Remove screws 1 - 2 and carefully disconnect the cables 3 - 5 from the Top Case module 6 .. cables.
b. Remove screws from the
a. bottom of the computer
and use the Eject Pin
3 Tool to push out the key-
board at point 27 .
6
1 2
5 4
2.Disassembly
3. Remove screws 7 - 26 from the bottom of the computer and use the Eject Pin Tool to carefully push out the hinge
cover at point 27 .
b.
8 16
27
7 11 12 14 15
9
10 13 17
26
18
24 25 19 
6. Top Case module
• 23 crews
S
23 22 21 20
Removing the Top Case module 2 - 19

Disassembly
Figure 16 4. Carefully lift up the hinge cover 28 off the computer.

Top Case module c.
Removal (cont’d)
28
c. Remove the hinge cov-
er.
d. Remove the top case
module.
28
5. Carefully unsnap the top case 29 from computer at point 30 .

2.Disassembly
d.
29
30

28. Hinge cover
29. TopCase module
2 - 20 Removing the Top Case module

Appendix A:Part Lists
This appendix breaks down the W243HVQ series notebook’s construction into a series of illustrations. The component
part numbers are indicated in the tables opposite the drawings.
Note: This section indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure
to cross-check any relevant documentation.
Note: Some assemblies may have parts in common ( especially screws). However, the part lists DO NOT in dicate the
total number of duplicated parts used.
Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the
A.Part Lists
time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers.
A - 1
Part List Illustration Location
The following table indicates where to find the appropriate part list illustration.
Table A - 1
Part List Illustration
Part W243HVQ
Location
Top page A - 3
Bottom (w/ 3G) page A - 4
Bottom (w/o 3G) page A - 5
SATA BLU-RAY page A - 6
COMBO
A.Part Lists
SATA DVD SUPER page A - 7

MULTI
LCD page A - 8
HDD page A - 9
A - 2
Top
Figure A - 1
A.Part Lists
Top
黑色
(灰色)
Top A - 3
Bottom with 3G
Figure A - 2
A.Part Lists
Bottom with SIM

(W240HUQ/
W241HUQ/
W245HUQ Series)
A - 4 Bottom with 3G
Bottom without 3G
Figure A - 3
Bottom without 3G
A.Part Lists
Bottom without 3G A - 5
SATA BLU-RAY COMBO
Figure 4
A.Part Lists
SATA BLU-RAY
COMBO
A - 6 SATA BLU-RAY COMBO

SATA DVD SUPER MULTI
Figure 5
A.Part Lists
SATA DVD SUPER
MULTI
SATA DVD SUPER MULTI A - 7

LCD
Figure A - 6
A.Part Lists
LCD
銘板
銅箔接地
A - 8
HDD
Figure A - 7
HDD
A.Part Lists
無鉛
(無鉛)
HDD A - 9
A.Part Lists
A - 10
Schematic Diagrams
Appendix B: Schematic Diagrams

This appendix has circuit diagrams of the W243HVQ notebook’s PCB’s. The followingtable indicates where to find the
appropriate schematic diagram.
Diagram - Page Diagram - Page Diagram - Page

Table B - 1
System Block Diagram - Page B - 2 PCH/ GPIO, VSS_NCTF, RSVD - Page B - 19 Power 1.05VS LAN M - Page B - 36 SCHEMATIC
PROCESSOR/ DMI, PEG, FDI - Page B - 3 PCH/ POWER1 - Page B - 20 Power 0.85VS - Page B - 37 DIAGRAMS
PROCESSOR/ CLK, MISC, JTAG - Page B - 4 PCH/ POWER2 - Page B - 21 Power V-Core1 - Page B - 38
B.Schematic Diagrams
PROCESSOR/ DDR3 - Page B - 5 PCH/ GND - Page B - 22 Power V-Core2 VGFX - Page B - 39
PROCESSOR/ POWER1 - Page B - 6 New Card, Mini PCIE - Page B - 23 AC IN, CHARGER - Page B - 40
PROCESSOR/ POWER2 - Page B - 7 CCD, 3G, TPM - Page B - 24 CLICK & FINGER BOARD - Page B - 41
PROCESSOR/ GND - Page B - 8 Card Reader/LAN JMC261C - Page B - 25 AUDIO BOARD/ USB - Page B - 42
PROCESSOR/ RESERVED - Page B - 9 INTEL LAN 82579 - Page B - 26 Power Switch & LID Board - Page B - 43

DDR3 SO-DIMM_0 - Page B - 10 LAN (82579), SATA HDD, ODD - Page B - 27 EXTERNAL ODD BOARD - Page B - 44 Version Note
DDR3 SO-DIMM_1 - Page B - 11 USB3.0 NEC, USB CHARGER - Page B - 28 FINGERPRINT BOARD - Page B - 45 The schematic dia-
grams in this chapter
LVDS, Inverter - Page B - 12 KBC-ITE IT81518 - Page B - 29 POWER SEQUENCE - Page B - 46
are based upon ver-
HDMI, CRT - Page B - 13 LED, MDC, BT - Page B - 30 POWER SEQUENCE 1 - Page B - 47 sion 6-7P-W24V6-002.
If your mainboard (or
PCH/ HDA, JTAG. SATA - Page B - 14 AUDIO CODEC ALC269 VIA1802 - Page B - 31
other boards) are a lat-
PCH/ PCI-E, SMBUS, CLK - Page B - 15 USB, FAN, TP, MULTI CON - Page B - 32 er version, please
check with the Service
PCH/ DMI, FDI, GPIO - Page B - 16 5VS, 3VS, 1.5V/0.75VS, 1.5VS CPU - Page B - 33
Center for updated di-
PCH/ LVDS, DDI, CRT - Page B - 17 VDD3, VDD5 - Page B - 34 agrams (if required).
PCH/ PCI, USB, NVRAM - Page B - 18 Power 1.05VS/0.75V, 1.8VS - Page B - 35
B - 1
Schematic Diagrams
System Block Diagram
CLICK & FINGER BOARD

6 -7 1- W2 40 2-D 01
AUDIO BOARD
Huron River System Block Diagram VDD3,VDD5
U SB +E AR PH ONE +E XT .M IC
6 -7 1- C4 50 8-D 03
5V,3V,5VS,3VS,1.5VS,
1.5VS_CPU
POWER SWITCH BOARD Memory Termination
P OW ER S WI TCH +H OT KE Y X 3 Sandy Bridge 800/1067 MHz 1.5V,0.75VS(VTT_MEM)
6 -7 1- E5 1Q S-D 02 DDR3 / 1.5V 1.8VS
37.5*37.5 mm DDRIII
EXTERNAL ODD BOARD SO-DIMM0 1.05V_LAN_M,
E XT . OD D PROCESSOR SHEET 10
6 -7 1- E5 1Q N-D 01
SYSTEM SMBUS 1.05VS_VTT
rPGA989/988 0 .1 "~1 3 DDRIII
SO-DIMM1
SHEET 11 0.85VS
FDI DMI*4
HD MI 0. 5" ~6 .5 " <= 8" VCORE
Sheet 1 of 46 CLICK BOARD

T OU CH P AD CR T CO NN EC TO R
<1 5"
CR T S WI TC H
INTERNAL
AU DI O BO AR D
VGFX_CORE
GRAPHICS CougarPoint
System Block S yn ap ti c
810602-1703 Platform
MIC
IN
HP
OUT
Diagram L CD C ON NE CT OR , <8 "
L VD S S WI TC H
INTERNAL
GRAPHICS Controller
Hub (PCH) INT SPK R
32.768 KHz
EC Az al ia C od ec INT SPK L
S PI TP M 25x25x0.6 mm
IT E 85 18 E REALTEK ALC269
128pins LQFP 989 Balls FCBGA
14 *14*1 .6 mm 33 MHz INT MIC
LPC
0. 5" ~1 1" B IO S AZALIA LINK 24 MHz
S PI
EC SMBUS
PCIE 100 MHz <1 2"
I NT . K/ B TH ER MA L S MA RT SM AR T
SE NS OR FA N B AT TE RY
32.768KHz
W 83 L7 71 AW G
I nt el L AN Mi ni P CI E Mi ni P CI E NEC JMICRO
S OC KE T S OC KE T
< 12 "
USB2.0 8 25 79 3 G CA RD WL AN uPD720200 JMC261 C
SATA I/II 3.0Gb/s 480 Mbps ( US B4 )
( US B2 ) USB3.0 IC CARD READER 25
1" ~1 6" (Optional)
M Hz
7 IN 1
SO CK ET
USB P OR T U SB P OR T US B PO RT C CD RJ-45
SA TA H DD S AT A OD D Fi ng er Pr in t
( US B3 ) (U SB 0) (U SB 1) ( US B9 ) (U SB 5)
US B3 .0 A UD IO
12 MHz
(Optional) B OA RD
B - 2 System Block Diagram

Schematic Diagrams
PROCESSOR/ DMI, PEG, FDI

Sandy Bridge Processor 1/7
( DMI,PEG,FDI )
1. 0 5 V S _ V T T
U3 4 A 20 mil
J 22 P E G_ C O MP R6 3 24 . 9 _ 1 %_ 0 4
P E G_ I C O MP I J 21
B2 7 P E G _I C O MP O H2 2
15 DM I _ T XN 0 B2 5 DM I _ R X # [ 0] P E G_ R C O MP O
15 DM I _ T XN 1 A2 5 DM I _ R X # [ 1]
15 DM I _ T XN 2 B2 4 DM I _ R X # [ 2] K3 3
15 DM I _ T XN 3 DM I _ R X # [ 3] PE G _ RX# [0 ] M3 5
B2 8 PE G _ RX# [1 ] L 34
15 D M I _ T XP 0 B2 6 DM I_ RX [0 ] PE G _ RX# [2 ] J 35
15 D M I _ T XP 1 A2 4 DM I_ RX [1 ] PE G _ RX# [3 ] J 32
15 D M I _ T XP 2 B2 3 DM I_ RX [2 ] PE G _ RX# [4 ] H3 4
15 D M I _ T XP 3 DM I_ RX [3 ] PE G _ RX# [5 ] H3 1
DMI
G 21 PE G _ RX# [6 ] G3 3
15 DM I_ RXN 0 DM I _ TX # [ 0 ] PE G _ RX# [7 ]
E2 2 G3 0
15 DM I_ RXN 1 F21 DM I _ TX # [ 1 ] PE G _ RX# [8 ] F35 Q 17 SC70-5 & SC70-3 Co-lay
15 DM I_ RXN 2 D 21 DM I _ TX # [ 2 ] PE G _ RX# [9 ] E3 4 5 1
15 DM I_ RXN 3 DM I _ TX # [ 3 ] P E G_ R X # [ 1 0 ] E3 2 GN D NC 2
G 22 P E G_ R X # [ 1 1 ] D3 3 G ND
15 DM I_ RXP 0 D 22 DM I _ TX [ 0 ] P E G_ R X # [ 1 2 ] D3 1 4 3
15 DM I_ RXP 1 F20 DM I _ TX [ 1 ] P E G_ R X # [ 1 3 ] B3 3 VC C VO
15 DM I_ RXP 2 DM I _ TX [ 2 ] P E G_ R X # [ 1 4 ]
C 21 C3 2 * TM P 2 0
15 DM I_ RXP 3 DM I _ TX [ 3 ] P E G_ R X # [ 1 5 ] 3 .3 V
PCI EXPRESS* - GRAPHICS

J 33 Q 16
P E G _R X [ 0 ] L 35 2 1
P E G _R X [ 1 ] VC C OU T 1 :2 ( 4m il s: 8m il s) T H E R M_ V O L T 2 8
K3 4
A2 1 P E G _R X [ 2 ] H3 5 C 99
15 F DI_ T X N0 H 19 F D I 0 _ T X #[ 0 ] P E G _R X [ 3 ] H3 2 3
15 F DI_ T X N1 C1 0 0
E1 9 F D I 0 _ T X #[ 1 ] P E G _R X [ 4 ] G3 4 0 . 1 u _ 10 V _ X 7 R _ 0 4 GN D
15 F DI_ T X N2 F18 F D I 0 _ T X #[ 2 ] P E G _R X [ 5 ] G3 1
G7 1 1 S T9 U 0. 1u _ 1 0V _X 7 R _ 0 4
15 F DI_ T X N3 B2 1 F D I 0 _ T X #[ 3 ] P E G _R X [ 6 ] F33
15 F DI_ T X N4 F D I 1 _ T X #[ 0 ] P E G _R X [ 7 ] 1
C 20 F30
3
Intel(R) FDI
15 F DI_ T X N5 D 18 F D I 1 _ T X #[ 1 ] P E G _R X [ 8 ] E3 5
15 F DI_ T X N6 E1 7 F D I 1 _ T X #[ 2 ] P E G _R X [ 9 ] E3 3
15 F DI_ T X N7 F D I 1 _ T X #[ 3 ] PE G _ RX[1 0 ] F32
9 /2 0 2
A2 2
PE G _ RX[1 1 ]
PE G _ RX[1 2 ]
D3 4
E3 1 E VT
PL A CE NE A R U3
15 F DI_ T X P 0 G 19 F D I 0 _ T X [ 0] PE G _ RX[1 3 ] C3 3
CAD NOTE: DP_COMPIO and ICOMPO signals
should be shorted near balls and routed with
15
15
15
F DI_ T X P 1
F DI_ T X P 2
F DI_ T X P 3
E2 0
G 18
B2 0
F D I 0 _ T X [ 1]
F D I 0 _ T X [ 2]
F D I 0 _ T X [ 3]
PE G _ RX[1 4 ]
PE G _ RX[1 5 ]
B3 2
M2 9
Sheet 2 of 46
15 F DI_ T X P 4 C 19 F D I 1 _ T X [ 0] P E G _T X # [ 0 ] M3 2
- typical impedance < 25 mohms 15
15
15
F DI_ T X P 5
F DI_ T X P 6
F DI_ T X P 7
D 19
F17
F D I 1 _ T X [ 1]
F D I 1 _ T X [ 2]
F D I 1 _ T X [ 3]
P E G _T X # [ 1 ]
P E G _T X # [ 2 ]
P E G _T X # [ 3 ]
M3 1
L 32
L 29
PROCESSOR/ DMI,
1. 0 5 V S _ V T T 1 . 05 V S _ V T T J18 P E G _T X # [ 4 ] K3 1
15
15
F DI_ F S Y NC 0
F DI_ F S Y NC 1
J17
H 20
F DI0 _ F S Y NC
F DI1 _ F S Y NC
P E G _T X # [ 5 ]
P E G _T X # [ 6 ]
P E G _T X # [ 7 ]
K2 8
J 30
J 28
PEG, FDI
15 F DI_ IN T F DI_ IN T P E G _T X # [ 8 ] H2 9
J19 P E G _T X # [ 9 ] G2 7
R 38 9 R 3 90 15
15
F DI_ L S Y N C0
F DI_ L S Y N C1
H 17 F DI0 _ L S Y N C
F DI1 _ L S Y N C
P E G _ TX # [ 1 0 ]
P E G _ TX # [ 1 1 ]
E2 9 On Board CPU Thermal Sensor
F27
1 K_ 0 4 2 4 . 9 _ 1% _ 0 4 P E G _ TX # [ 1 2 ] 3 .3 V
ED P F unc ti on Di sa bl e D2 8
P E G _ TX # [ 1 3 ] F26
ED P_ HP D: Pu ll -u p1 0K - DI SA BL ED P E G _ TX # [ 1 4 ] E2 5 Analog Thermal Sensor
E D P _ C O MP A 1 8 P E G _ TX # [ 1 5 ]
A1 7 e D P _ C O MP I O M2 8
DP Compensation Signal ED P_ HPD # B 1 6 e D P _ I C O MP O P E G_ T X [ 0 ] M3 3 C 97
e DP _ HP D# P E G_ T X [ 1 ]
D
M3 0
P Q 47 P E G_ T X [ 2 ] L 31 * 0. 1 u _ 1 6V _ Y 5V _0 4
G *M T N 7 0 0 2Z H S 3 C3 2 5 * 0 . 1u _ 1 0 V _ X7 R _0 4 D P _ A UX_ P C 1 5 P E G_ T X [ 3 ] L 28 U1 1
11 E M B _ HP D 11 D P _ A UXP e DP _ A U X P E G_ T X [ 4 ]
C3 2 4 * 0 . 1u _ 1 0 V _ X7 R _0 4 D P _ A UX_ N D 1 5 K3 0 1 4 R 1 22 *1 0 mi l _ 04
11 D P _ A UXN C R I T _T E M P _ R E P # 1 8
S
e D P _ A U X# P E G_ T X [ 5 ] K2 7 D+ _ CP U 2 V DD T HE RM 6
P E G_ T X [ 6 ] D+ AL ER T T S # _ D I M M0 _ 1 9, 1 0
C
R3 8 8 J 29
C3 3 0 * 0 . 1u _ 1 0 V _ X7 R _0 4 D P _ TX P _ 0 P E G_ T X [ 7 ]
eDP
*1 0 0 K _0 4 C 17 J 27 Q 18 B
11 D P _ T XP 0 D P _ TX P _ 1 F16 e D P _ T X[ 0] P E G_ T X [ 8 ] H2 8
C3 2 9 * 0 . 1u _ 1 0 V _ X7 R _0 4
11 D P _ T XP 1 C3 2 7 * 0 . 1u _ 1 0 V _ X7 R _0 4 D P _ TX P _ 2 C 16 e D P _ T X[ 1] P E G_ T X [ 9 ] G2 8 *2 N 39 0 4 D -_ C P U 3 7
11 D P _ T XP 2 S MD _C P U _T H E R M 1 4, 2 8
E
C5 4 0 * 0 . 1u _ 1 0 V _ X7 R _0 4 D P _ TX P _ 3 G 15 e D P _ T X[ 2] P E G _T X [ 1 0 ] E2 8 5 D- S D A TA 8
11 D P _ T XP 3 e D P _ T X[ 3] P E G _T X [ 1 1 ] F28 GN D S C LK S MC _C P U _T H E R M 1 4, 2 8
C3 3 1 * 0 . 1u _ 1 0 V _ X7 R _0 4 D P _ TX N _0 C 18 P E G _T X [ 1 2 ] D2 7 *W 8 3 L 7 71 A W G
11 D P _ T XN 0 D P _ TX N _1 E1 6 e D P _ T X# [ 0 ] P E G _T X [ 1 3 ] E2 6
11 D P _ T XN 1 C3 2 8 * 0 . 1u _ 1 0 V _ X7 R _0 4
C3 2 6 * 0 . 1u _ 1 0 V _ X7 R _0 4 D P _ TX N _2 D 16 e D P _ T X# [ 1 ] P E G _T X [ 1 4 ] D2 5
11 D P _ T XN 2 D P _ TX N _3 F15 e D P _ T X# [ 2 ] P E G _T X [ 1 5 ]
C5 4 1 * 0 . 1u _ 1 0 V _ X7 R _0 4
11 D P _ T XN 3 e D P _ T X# [ 3 ]
11/0 3
P Z 9 8 8 27 -3 6 4 B -0 1F
3, 8 , 1 1 , 1 3, 1 5 , 1 7 , 19 , 2 0 , 2 2 , 23 , 2 7 , 2 9, 3 1 , 3 2 , 3 4, 3 6 3 . 3 V
3 , 5 , 1 8 , 1 9, 2 0 , 3 5 , 37 1 . 0 5 V S _ V T T
PROCESSOR/ DMI, PEG, FDI B - 3

Schematic Diagrams
PROCESSOR/ CLK, MISC, JTAG

Processor Pullups/Pull downs
1. 0 5 V S _ V T T
PU/PD for JTAG signals

1. 0 5 V S _ V T T
Sandy Bridge Processor 2/7 H _P R OC H O T#
H _ C P U P W R GD _ R
6 2 _ 04
1 0 K_ 0 4
R4 1 0
R4 1 2
5 1 _ 04
5 1 _ 04
*5 1 _ 04
R4 1 6
R1 0 8
R1 0 9
XD
XD
XD
P _T M S
P _T D I _R
P _P R E Q #
( CLK,MISC,JTAG ) *0 . 1 u _1 0 V _ X 7R _0 4 C 5 85
11/03
5 1 _ 04 R4 1 5 XD P _T D O_ R
5 1 _ 04 R4 1 4 XD P _T C LK U 3 4B
5 1 _ 04 R9 5 XD P _T R S T #
TR AC E WI DTH 1 0M IL , LEN GT H <5 00 MIL S
A2 8
H_ S N B _ IV B # C2 6 BC L K A2 7 C L K _ E X P _P 14
18 H_ S N B _ IV B # P R OC _S E L E C T # B CL K # C L K _ E X P _N 14 DDR3 Compensation Signals
CLOCKS
3. 3V S
MISC
A N3 4 S M_ R C OM P _ 0 R4 1 3 14 0 _ 1% _ 0 4
XD P _ D B R _ R S K T OC C # A1 6
R 40 7 1 K_ 0 4
DP L L _ RE F _ S S C L K A1 5 CL K _ DP _ P 1 4 S M_ R C OM P _ 1 R3 8 2 25 . 5 _ 1% _ 0 4
D P LL _ R E F _S S C L K # C L K _ D P _ N 14
S M_ R C OM P _ 2 R3 8 1 20 0 _ 1% _ 0 4
H _ C A TE R R # A L3 3
C A TE R R #
R 41 1 * 10 m i _l 0 4 H_ P E C I_ R A N3 3 R8 C P UD RA M RS T #
THERMAL
18 , 2 8 H _P E C I PEC I S M_ D R A M R S T #
DDR3
MISC
R 40 5 5 6_ 1 % _0 4 H _ P R O C H OT # _D A L3 2 AK1 S M _R C O MP _ 0
37 H _ P R O C H OT # P R OC H OT # S M_ R C OM P [ 0 ] A5 S M _R C O MP _ 1
S M_ R C OM P [ 1 ] A4
If P ROC HO T# i s n ot u se d, th en i t mu st S M _R C O MP _ 2
S M_ R C OM P [ 2 ] S3 circuit:- DRAM PWR GOOD logic
be t erm in at ed wi th a 6 8- O + -5 % pu ll -up A N3 2
re si sto r to 1 .05 VS _V TT . T H E R MT R I P #
Sheet 3 of 46 1 8 H _ T H R MT R I P #
R 41 7 * 10 m i _l 0 4 H _ TH R M T R I P # _ R
AP2 9 X DP _ P R DY # 3 . 3V 1 . 5V S _C P U 1230 D02
PROCESSOR/ CLK, P RDY #
P RE Q #
AP2 7
A R2 6
X D P _ P R E Q#
X DP _ T CL K
TC K A R2 7 X D P _ T MS
MISC, JTAG R 41 9 * 10 m i _l 0 4 P M_ S Y N C _ R A M3 4 TM S AP3 0 X DP _ T RS T #

R 73 R5 7
PWR MANAGEMENT
JTAG & BPM

15 H _ P M_ S Y N C P M _S Y N C T RS T #
* 2 00 _ 1 %_ 0 4 1 0 K _0 4
A R2 8 X DP _ T DI_ R D2 0
TD I AP2 6 X DP _ T DO _ R 1 A
AP3 3 T DO 1 5 P M_ D R A M_ P W R GD C 3
R 41 8 * 10 m i _l 0 4 H _ CP U P W RG D_ R P M S Y S _P W R GD _ B U F
18 H _C P U P W R G D U N C O R E P W R G OOD 2
1 5, 3 4 1 . 8 V S _ P W R G D A
A L 35 X DP _ D B R_ R *B A T 5 4 A W GH
P MS Y S _ P W R GD _ B U F R6 0 1 30 _ 1 %_ 0 4 V D D P W R GOO D _ R V 8 DB R # R 58
S M _D R A M P W R OK
* 39 _ 0 4
A T 28 X DP _ B P M 0 _R
BP M# [ 0 ] A R2 9 X DP _ B P M 1 _R
BP M# [ 1 ] A R3 0 X DP _ B P M 2 _R R 59 0_04
Buffered reset to CPU BP M# [ 2 ]
D
1 . 0 5 V S _ V TT B U F _C P U _ R S T# A R3 3 A T 30 X DP _ B P M 3 _R Q1 0
R ESET # BP M# [ 3 ] AP3 2 X DP _ B P M 4 _R
BP M# [ 4 ] A R3 1 X DP _ B P M 5 _R G
R1 0 5 7 5 _1 % _ 0 4 R1 0 4 3 2, 3 4 , 3 5 S U S B
43 _ 1 % _0 4 BP M# [ 5 ] A T 31 X DP _ B P M 6 _R *M T N 7 0 02 Z H S 3
11/0 4 BP M# [ 6 ]
S
6 A R3 2 X DP _ B P M 7 _R
3 . 3V S D BP M# [ 7 ]
Q3 6 A
R5 3 0 10 K _ 0 4 2 G MT D N 7 00 2 Z H S 6 R
S
3 1 P Z 9 8 82 7 -3 64 B -0 1 F
D 1 0/ 29
5 G Q3 6 B
S MT D N 7 00 2 Z H S 6 R H _P R OC H O T# S3 circuit:- DRAM_RST# to memory
4 should be high during S3
D
Q 14
R1 1 2 *1 . 5 K _1 % _ 04 C 5 15 1 . 5V
1 7 , 23 P L T _ R S T # R5 3 1 C9 6 G
2 8 H _ P R O C H OT _ E C
4 7 p _5 0 V _ N P O _ 04
M T N 7 00 2 Z H S 3
S
R1 0 6 R 47 *0 _ 0 4 R4 5
*6 8 p_ 5 0 V _N P O_ 0 4
10/1 1K _ 0 4
* 75 0 _ 1% _ 0 4 R 91 1 0 0 K _0 4
1 0 0K _0 4
Q8
CAD Note: Capacitor need to be placed MT N 70 0 2 Z H S 3
close to buffer output pin R 90 *0 _ 04 C P UD RA M RS T # S D 1 K_ 0 4
D D R 3 _ D R A MR S T # 9 , 1 0
R 48
R4 6
D R A MR S T _C N T R L 8 , 1 4
G
C2 2
4 . 99 K _ 1 % _0 4
0 . 0 47 u _ 10 V _ X 7R _ 04
2 , 5 , 1 8 , 19 , 2 0 , 3 5, 3 7 1 . 05 V S _ V T T
6, 3 2 1 . 5V S _C P U
6, 8 , 9 , 1 0 , 20 , 2 7 , 3 2, 3 4 1 . 5V
2, 8 , 1 1 , 13 , 1 5 , 1 7, 1 9 , 2 0, 2 2 , 2 3, 27 , 2 9 , 31 , 3 2 , 3 4, 3 6 3 . 3V
9 , 1 0 , 1 1, 1 2 , 1 3, 1 4 , 1 5 , 16 , 1 7 , 18 , 1 9 , 2 0, 2 3 , 2 4, 2 5 , 2 6, 28 , 2 9 , 30 , 3 1 , 3 2, 3 7 3 . 3V S
B - 4 PROCESSOR/ CLK, MISC, JTAG

Schematic Diagrams
PROCESSOR/ DDR3
Sandy Bridge Processor 3/7 ( DDR3 )
U34C U34D
AB6 AE2
9 M_A_DQ[63:0] SA_CLK[0] AA6 M_A_CLK_DDR0 9 10 M_B_DQ[63:0] SB_CLK[0] AD2 M_B_CLK_DDR0 10
M_A_DQ0 C5 SA_CLK#[0] V9 M_A_CLK_DDR#0 9 M_B_DQ0 C9 SB_CLK#[0] R9 M_B_CLK_DDR#0 10
SA_
DQ[0] SA_CKE[0] M_A_CKE0 9 SB_DQ[0] SB_CKE[0] M_B_CKE0 10
M_A_DQ1 D5 M_B_DQ1 A7
M_A_DQ2 D3 SA_
DQ[1] M_B_DQ2 D10 SB_DQ[1]
D2 SA_
DQ[2] C8 SB_DQ[2]
M_A_DQ3 M_B_DQ3
M_A_DQ4 D6 SA_
DQ[3] AA5 M_B_DQ4 A9 SB_DQ[3] AE1
M_A_DQ5 C6 SA_
DQ[4] SA_CLK[1] AB5 M_A_CLK_DDR1 9 M_B_DQ5 A8 SB_DQ[4] SB_CLK[1] AD1 M_B_CLK_DDR1 10
M_A_DQ6 C2 SA_
DQ[5] SA_CLK#[1] V10 M_A_CLK_DDR#1 9 M_B_DQ6 D9 SB_DQ[5] SB_CLK#[1] R10 M_B_CLK_DDR#1 10
SA_
DQ[6] SA_CKE[1] M_A_CKE1 9 SB_DQ[6] SB_CKE[1] M_B_CKE1 10
M_A_DQ7 C3 M_B_DQ7 D8
M_A_DQ8 F10 SA_
DQ[7] M_B_DQ8 G4 SB_DQ[7]
F8 SA_
DQ[8] F4 SB_DQ[8]
M_A_DQ9 M_B_DQ9
M_A_DQ1
0 G10 SA_
DQ[9] AB4 M_B_DQ10 F1 SB_DQ[9] AB2
M_A_DQ1
1 G9 SA_
DQ[10] SA_CLK[2] AA4 M_B_DQ11 G1 SB_DQ[10] SB_CLK[2] AA2
M_A_DQ1
2 F9 SA_
DQ[11] SA_CLK#[2] W9 M_B_DQ12 G5 SB_DQ[11] SB_CLK#[2] T9
M_A_DQ1
3 F7 SA_
DQ[12] SA_CKE[2] M_B_DQ13 F5 SB_DQ[12] SB_CKE[2]
M_A_DQ1
4 G8 SA_
DQ[13] M_B_DQ14 F2 SB_DQ[13]
G7 SA_
DQ[14] G2 SB_DQ[14]
M_A_DQ1
5 M_B_DQ15
M_A_DQ1
6 K4 SA_
DQ[15] AB3 M_B_DQ16 J7 SB_DQ[15] AA1
M_A_DQ1
7 K5 SA_
DQ[16] SA_CLK[3] AA3 M_B_DQ17 J8 SB_DQ[16] SB_CLK[3] AB1
M_A_DQ1
8 K1 SA_
DQ[17] SA_CLK#[3] W10 M_B_DQ18 K10 SB_DQ[17] SB_CLK#[3] T10
M_A_DQ1
9 J1 SA_
DQ[18] SA_CKE[3] M_B_DQ19 K9 SB_DQ[18] SB_CKE[3]
M_A_DQ2
0 J5 SA_
DQ[19] M_B_DQ20 J9 SB_DQ[19]
J4 SA_
DQ[20] J10 SB_DQ[20]
M_A_DQ2
1 M_B_DQ21
M_A_DQ2
2 J2 SA_
DQ[21] AK3 M_B_DQ22 K8 SB_DQ[21] AD3
M_A_DQ2
3 K2 SA_
DQ[22] SA_CS#[0] AL3 M_A_CS#0 9 M_B_DQ23 K7 SB_DQ[22] SB_
CS#[0] AE3 M_B_CS#0 10
M_A_DQ2
4 M8 SA_
DQ[23] SA_CS#[1] AG1 M_A_CS#1 9 M_B_DQ24 M5 SB_DQ[23] SB_
CS#[1] AD6 M_B_CS#1 10
M_A_DQ2
5 N10 SA_
DQ[24] SA_CS#[2] AH1 M_B_DQ25 N4 SB_DQ[24] SB_
CS#[2] AE6
M_A_DQ2
6
M_A_DQ2
7
M_A_DQ2
8
N8
N7
M10
SA_
DQ[25]
SA_
DQ[26]
SA_
DQ[27]
SA_CS#[3] M
M
M
_B_DQ26
_B_DQ27
_B_DQ28
N2
N1
M4
SB_DQ
SB_DQ
SB_DQ
[25]
[26]
[27]
SB_
CS#[3]
Sheet 4 of 46
PROCESSOR/
M_A_DQ2
9 M9 SA_
DQ[28] AH3 M_B_DQ29 N5 SB_DQ[28] AE4
SA_
DQ[29] SA_ODT[0] M_A_ODT0 9 SB_DQ[29] SB_ODT[0] M_B_ODT
0 10
M_A_DQ3
0 N9 AG3 M_B_DQ30 M2 AD4
M7 SA_
DQ[30] SA_ODT[1] AG2 M_A_ODT1 9 M1 SB_DQ[30] SB_ODT[1] AD5 M_B_ODT
1 10
M_A_DQ3
1 M_B_DQ31
AG6 SA_
DQ[31] SA_ODT[2] AH2 AM5 SB_DQ[31] SB_ODT[2] AE5
DDR SYSTEM MEMORY B

M_A_DQ3
2 M_B_DQ32
DDR3
DDR SYSTEM MEMORY A
AG5 SA_
DQ[32] SA_ODT[3] AM6 SB_DQ[32] SB_ODT[3]
M_A_DQ3
3 M_B_DQ33
M_A_DQ3
4 AK6 SA_
DQ[33] M_B_DQ34 AR3 SB_DQ[33]
M_A_DQ3
5 AK5 SA_
DQ[34] M_B_DQ35 AP3 SB_DQ[34]
M_A_DQ3
6 AH5 SA_
DQ[35] M_B_DQ36 AN3 SB_DQ[35]
AH6 SA_
DQ[36] C4 M_A_DQS#[7:0] 9 AN2 SB_DQ[36] D7 M_B_DQS#[ 7
: 0] 10
M_A_DQ3
7 M_A_DQS#0 M_B_DQ37 M_B_DQS#0
M_A_DQ3
8 AJ5 SA_
DQ[37] SA_DQS#[0] G6 M_A_DQS#1 M_B_DQ38 AN1 SB_DQ[37] SB_DQS#[0] F3 M_B_DQS#1
AJ6 SA_
DQ[38] SA_DQS#[1] J3 AP2 SB_DQ[38] SB_DQS#[1] K6
M_A_DQ3
9 M_A_DQS#2 M_B_DQ39 M_B_DQS#2
M_A_DQ4
0 AJ8 SA_
DQ[39] SA_DQS#[2] M6 M_A_DQS#3 M_B_DQ40 AP5 SB_DQ[39] SB_DQS#[2] N3 M_B_DQS#3
M_A_DQ4
1 AK8 SA_
DQ[40] SA_DQS#[3] AL6 M_A_DQS#4 M_B_DQ41 AN9 SB_DQ[40] SB_DQS#[3] AN5 M_B_DQS#4
M_A_DQ4
2 AJ9 SA_
DQ[41] SA_DQS#[4] AM8 M_A_DQS#5 M_B_DQ42 AT5 SB_DQ[41] SB_DQS#[4] AP9 M_B_DQS#5
M_A_DQ4
3 AK9 SA_
DQ[42] SA_DQS#[5] AR12 M_A_DQS#6 M_B_DQ43 AT6 SB_DQ[42] SB_DQS#[5] AK12 M_B_DQS#6
M_A_DQ4
4 AH8 SA_
DQ[43] SA_DQS#[6] AM15 M_A_DQS#7 M_B_DQ44 AP6 SB_DQ[43] SB_DQS#[6] AP15 M_B_DQS#7
AH9 SA_
DQ[44] SA_DQS#[7] AN8 SB_DQ[44] SB_DQS#[7]
M_A_DQ4
5 M_B_DQ45
M_A_DQ4
6 AL9 SA_
M_A_DQ4
7 AL8 SA_
M_A_DQ4
8 AP11 SA_
AN11 SA_
DQ[48] D4 M_A_DQS[7:0] 9 AJ11 SB_DQ[48] C7 M_B_DQS[ 7:0] 10
M_A_DQ4
9 M_A_DQS0 M_B_DQ49 M_B_DQS0
M_A_DQ5
0 AL12 SA_
DQ[49] SA_DQS[0] F6 M_A_DQS1 M_B_DQ50 AT8 SB_DQ[49] SB_DQS[0] G3 M_B_DQS1
M_A_DQ5
1 AM12 SA_
DQ[50] SA_DQS[1] K3 M_A_DQS2 M_B_DQ51 AT9 SB_DQ[50] SB_DQS[1] J6 M_B_DQS2
M_A_DQ5
2 AM11 SA_
DQ[51] SA_DQS[2] N6 M_A_DQS3 M_B_DQ52 AH11 SB_DQ[51] SB_DQS[2] M3 M_B_DQS3
M_A_DQ5
3 AL11 SA_
DQ[52] SA_DQS[3] AL5 M_A_DQS4 M_B_DQ53 AR8 SB_DQ[52] SB_DQS[3] AN6 M_B_DQS4
M_A_DQ5
4 AP12 SA_
DQ[53] SA_DQS[4] AM9 M_A_DQS5 M_B_DQ54 AJ12 SB_DQ[53] SB_DQS[4] AP8 M_B_DQS5
M_A_DQ5
5 AN12 SA_
DQ[54] SA_DQS[5] AR11 M_A_DQS6 M_B_DQ55 AH12 SB_DQ[54] SB_DQS[5] AK11 M_B_DQS6
M_A_DQ5
6 AJ14 SA_
DQ[55] SA_DQS[6] AM14 M_A_DQS7 M_B_DQ56 AT11 SB_DQ[55] SB_DQS[6] AP14 M_B_DQS7
M_A_DQ5
7 AH14 SA_
DQ[56] SA_DQS[7] M_B_DQ57 AN14 SB_DQ[56] SB_DQS[7]
M_A_DQ5
8 AL15 SA_
M_A_DQ5
9 AK15 SA_
DQ[58] M_B_DQ59 AT14 SB_DQ[58]
M_A_DQ6
0 AL14 SA_
DQ[59] M_B_DQ60 AT12 SB_DQ[59]
AK14 SA_
DQ[60] AD10 M_A_A[15:0] 9 AN15 SB_DQ[60] AA8 M_B_B[15:0] 10
M_A_DQ6
1 M_A_A0 M_B_DQ61 M_B_B0
AJ15 SA_
DQ[61] SA_MA[0] W1 AR15 SB_DQ[61] SB_MA[0] T7
M_A_DQ6
2 M_A_A1 M_B_DQ62 M_B_B1
M_A_DQ6
3 AH15 SA_
DQ[62] SA_MA[1] W2 M_A_A2 M_B_DQ63 AT15 SB_DQ[62] SB_MA[1] R7 M_B_B2
SA_
DQ[63] SA_MA[2] W7 M_A_A3 SB_DQ[63] SB_MA[2] T6 M_B_B3
SA_MA[3] V3 M_A_A4 SB_MA[3] T2 M_B_B4
SA_MA[4] V2 M_A_A5 SB_MA[4] T4 M_B_B5
SA_MA[5] W3 M_A_A6 SB_MA[5] T3 M_B_B6
AE10 SA_MA[6] W6 AA9 SB_MA[6] R2
M_A_A7 M_B_B7
9 M_A_BS0 AF10 SA_
BS[0] SA_MA[7] V1 M_A_A8 10 M_B_BS0 AA7 SB_BS[ 0] SB_MA[7] T5 M_B_B8
9 M_A_BS1 V6 SA_
BS[1] SA_MA[8] W5 M_A_A9 10 M_B_BS1 R6 SB_BS[ 1] SB_MA[8] R3 M_B_B9
9 M_A_BS2 SA_
BS[2] SA_MA[9] AD8 M_A_A10 10 M_B_BS2 SB_BS[ 2] SB_MA[9] AB7 M_B_B10
SA_MA[10] V4 M_A_A11 SB_MA[ 1
0] R1 M_B_B11
SA_MA[11] W4 M_A_A12 SB_MA[ 1
1] T1 M_B_B12
AE8 SA_MA[12] AF8 AA10 SB_MA[ 1
2] AB10
M_A_A13 M_B_B13
9 M_A_CAS# AD9 SA_
CAS# SA_MA[13] V5 M_A_A14 10 M_B_CAS# AB8 SB_CAS# SB_MA[ 1
3] R5 M_B_B14
9 M_A_RAS# AF9 SA_
RAS# SA_MA[14] V7 M_A_A15 10 M_B_RAS# AB9 SB_RAS# SB_MA[ 1
4] R4 M_B_B15
9 M_A_WE# SA_
WE# SA_MA[15] 10 M_B_WE# SB_WE# SB_MA[ 1
5]
PZ98
827-364B- 0
1F PZ98827-364B-01F
PROCESSOR/ DDR3 B - 5
Schematic Diagrams
PROCESSOR/ POWER1
layout? check
U 34F POWER
layout? check
V CO RE
48A PROCESSOR UNCORE POWER 8.5A 1 .0 5 VS _ V T T
A G3 5
PROCES SOR CORE POWER A G3 4
A G3 3
VC
VC
C
C
1
2 V C C I O1
A H1 3
A H1 0
A G3 2 VC C 3 V C C I O2 A G1 0 C 361 C 357 C 365 C 3 98 C 3 50 C 402
ICCMAX Maximum Process or SV 48 A G3 1
A G3 0
VC
VC
C
C
4
5
V C C I O3
V C C I O4
A C1 0
Y1 0
+
2 2 u _ 6 . 3 V _ X5 R _ 0 8 2 2 u _ 6 . 3V _ X5 R _ 0 8 2 2 u _ 6. 3V _X 5 R _ 08 * 22 u _ 6 . 3 V _ X 5 R _ 0 8 * 22 u _ 6 . 3 V _ X 5R _ 0 8
V C OR E A G2 9 VC C 6 V C C I O5 U1 0 2 2 0 u _ 6. 3 V _6 . 3 * 6 . 3* 4 . 2
A G2 8 VC C 7 V C C I O6 P1 0
C 353 2 2u _ 6 . 3 V _ X 5 R _ 0 8 A G2 7 VC C 8 V C C I O7 L 10
A G2 6 VC C 9 V C C I O8 J 14
AF3 5 VC C 10 V C C I O9 J 13
C 371 2 2u _ 6 . 3 V _ X 5 R _ 0 8 C 355 C 344 C 364 C 3 58 C 3 46 C 417
AF3 4 VC C 11 V C C I O 10 J 12 +
C 366 2 2u _ 6 . 3 V _ X 5 R _ 0 8 AF3 3 VC C 12 V C C I O 11 J 11 * 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 * 2 2u _ 6 . 3 V _ X 5 R _ 0 8 * 2 2u _ 6 . 3 V _ X 5 R _ 0 8 * 22 u _ 6 . 3 V _ X 5 R _ 0 8 2 2 u _6 . 3 V _ X 5 R _0 8
AF3 2 VC C 13 V C C I O 12 H1 4 2 2 0 u _ 6. 3 V _6 . 3 * 6 . 3* 4 . 2
C 354 2 2u _ 6 . 3 V _ X 5 R _ 0 8 AF3 1 VC C 14 V C C I O 13 H1 2
AF3 0 VC C 15 V C C I O 14 H1 1
AF2 9 VC C 16 V C C I O 15 G1 4
C 359 2 2u _ 6 . 3 V _ X 5 R _ 0 8
AF2 8 VC C 17 V C C I O 16 G1 3 C 396 C 419 C 406 C 3 97 C 3 84
AF2 7 VC C 18 V C C I O 17 G1 2
C 363 2 2u _ 6 . 3 V _ X 5 R _ 0 8
P EG AND DDR
AF2 6 VC C 19 V C C I O 18 F14 * 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 * 2 2u _ 6 . 3 V _ X 5 R _ 0 8 * 2 2u _ 6 . 3 V _ X 5 R _ 0 8 * 22 u _ 6 . 3 V _ X 5 R _ 0 8 2 2 u _6 . 3 V _ X 5 R _0 8
A D3 5 VC C 20 V C C I O 19 F13
C 337 2 2u _ 6 . 3 V _ X 5 R _ 0 8
A D3 4 VC C 21 V C C I O 20 F12
C 332 2 2u _ 6 . 3 V _ X 5 R _ 0 8 A D3 3 VC C 22 V C C I O 21 F11
A D3 2 VC C 23 V C C I O 22 E1 4
C 351 2 2u _ 6 . 3 V _ X 5 R _ 0 8 A D3 1 VC C 24 V C C I O 23 E1 2 C 321 C 418 C 375 C 3 83 C 3 82
A D3 0 VC C 25 V C C I O 24
A D2 9 VC C 26 E1 1
C 336 2 2u _ 6 . 3 V _ X 5 R _ 0 8 * 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 * 2 2u _ 6 . 3 V _ X 5 R _ 0 8 2 2 u _ 6. 3V _X 5 R _ 08 2 2 u _ 6. 3 V _X 5 R _ 08 * 22 u _ 6 . 3 V _ X 5R _ 0 8
VC C 27 V CC IO 25
Sheet 5 of 46 A D2 8
A D2 7
A D2 6
A C3 5
VC
VC
VC
C
C
C
28
29
30
V
V
V
CC
CC
CC
IO
IO
IO
26
27
28
D1 4
D1 3
D1 2
D1 1
PROCESSOR/ V C OR E A C3 4 VC C 31 V CC IO 29 C1 4 C 407 C 372 C 352 C 3 67 C 3 85

A C3 3 VC C 32 V CC IO 30 C1 3
A C3 2 VC C 33 V CC IO 31 C1 2
C 69 1 0u _ 6 . 3 V _ X 5 R _ 0 6 * 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 2 2 u _ 6 . 3V _ X5 R _ 0 8 2 2 u _ 6. 3V _X 5 R _ 08 2 2 u _ 6. 3 V _X 5 R _ 08 2 2 u _6 . 3 V _ X 5 R _0 8
A C3 1 VC C 34 V CC IO 32 C1 1
POWER1 C 33
C 74
1 0u _ 6 . 3 V _ X 5 R _ 0 6
1 0u _ 6 . 3 V _ X 5 R _ 0 6
A C3 0
A C2 9
A C2 8
A C2 7
VC
VC
VC
VC
C
C
C
C
35
36
37
38
V
V
V
V
CC
CC
CC
CC
IO
IO
IO
IO
33
34
35
36
B1 4
B1 2
A1 4
A1 3 C 381 C 394 C 420 C 3 68
C 56 1 0u _ 6 . 3 V _ X 5 R _ 0 6 A C2 6 VC C 39 V CC IO 37 A1 2
AA3 5 VC C 40 V CC IO 38 A1 1 * 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 * 2 2u _ 6 . 3 V _ X 5 R _ 0 8 * 2 2u _ 6 . 3 V _ X 5 R _ 0 8 * 22 u _ 6 . 3 V _ X 5 R _ 0 8
C 34 1 0u _ 6 . 3 V _ X 5 R _ 0 6 AA3 4 VC C 41 V CC IO 39
AA3 3 VC C 42 J 23 + V 1 .0 5 S _ V CC P _ F R6 2 *2 0 m i l _0 4
AA3 2 VC C 43 V C C I O 40 1 . 0 5V S _ V T T
C 53 1 0u _ 6 . 3 V _ X 5 R _ 0 6
AA3 1 VC C 44
AA3 0 VC C 45
AA2 9 VC C 46
V C OR E AA2 8 VC C 47
AA2 7 VC C 48
C 362 *2 2 u _ 6. 3V _X 5 R _ 08 AA2 6 VC C 49
Y3 5 VC C 50
CAD Note: H_CPU_SVIDALRT#_R,H_CPU_SVIDDAT_R
CORE SUPPL Y
C 360 *2 2 u _ 6. 3V _X 5 R _ 08 Y3 4 VC C 51
Y3 3 VC C 52 Place the PU resistors close to CPU
Y3 2 VC C 53
C 334 *2 2 u _ 6. 3V _X 5 R _ 08
Y3 1 VC C 54
C 333 *2 2 u _ 6. 3V _X 5 R _ 08 Y3 0 VC C 55
Y2 9 VC C 56 SVID Signals
Y2 8 VC C 57
C 356 *2 2 u _ 6. 3V _X 5 R _ 08
Y2 7 VC C 58 1 .0 5 V S _ VT T
C 62 *1 0 u _ 6. 3V _X 5 R _ 06 Y2 6 VC C 59
V3 5 VC C 60
V3 4 VC C 61 AJ 2 9 H _ C P U _ S V I D A L R T #_ R H _ C P U_ S V IDA L R T #
C 72 *1 0 u _ 6. 3V _X 5 R _ 06 R4 0 6 4 3_ 1 % _ 0 4 7 5 _ 1 % _0 4 R4 0 8
SVI D
V3 3 VC C 62 V I D A L E R T# AJ 3 0 H _ C P U _S V I D A L R T # 3 7
H _ C P U _ S V I D C LK _ R R8 8 0 _0 4 H _ C P U_ S V IDC L K * 5 4. 9_ 1 % _ 0 4 R8 9
V3 2 VC C 63 V IDS CL K AJ 2 8 H _ C P U _S V I D C L K 3 7
C 59 *1 0 u _ 6. 3V _X 5 R _ 06 H _ CP U_ S VID D A T _ R R8 5 0 _0 4 H _ C P U_ S V IDD A T _ R 1 3 0 _ 1 %_ 0 4 R8 6
V3 1 VC C 64 V ID S O UT H _ C P U _S V I D D A T 3 7
C 66 *1 0 u _ 6. 3V _X 5 R _ 06 V3 0 VC C 65
V2 9 VC C 66
V2 8 VC C 67
V2 7 VC C 68
V2 6 VC C 69
CAD Note: H_CPU_SVIDCLK_R
U3 5 VC C 70 Place the PU
U3 4 VC C 71
U3 3 VC C 72 resistors close to VR
U3 2 VC C 73
U3 1 VC C 74
U3 0 VC C 75
U2 9 VC C 76
U2 8 VC C 77 V C OR E _ V C C _ S E N S E 3 7
U2 7 VC C 78 V C OR E _ V S S _ S E N S E 3 7
U2 6 VC C 79
R3 5 VC C 80
R3 4 VC C 81
R3 3 VC C 82
R3 2 VC C 83
R3 1 VC C 84 1126 V C OR E 1 . 0 5 V S _V TT
R3 0 VC C 85
R2 9 VC C 86
R2 8 VC C 87
SEN SE LIN ES
R2 7 VC C 88 AJ 3 5 R 6 87 R3 7 9
R2 6 VC C 89 V CC _ S E N S E AJ 3 4
P3 5 VC C 90 V SS_ SEN SE
P3 4 VC C 91
* 10 _ 0 4 10 _ 0 4
P3 3 VC C 92
P3 2 VC C 93 B1 0 V CC IO _ S E N S E _ R R 38 4 * 0 _ 04
P3 1 VC C 94 V C CIO _ S E N SE A1 0 V SS IO _ S E N SE V CC IO _ SE N S E 3 5
P3 0 VC C 95 V SS IO _ S E N S E 3 7 , 3 8 V C OR E
P2 9 VC C 96 2 , 3 , 18 , 1 9 , 2 0 , 3 5 , 3 7 1 . 0 5V S _ V T T
P2 8 VC C 97
P2 7 VC C 98
R 38 3
P2 6 VC C 99
VC C 10 0
1 0 _0 4
P Z 9 88 2 7 -3 6 4 B -0 1 F
B - 6 PROCESSOR/ POWER1
Schematic Diagrams
PROCESSOR/ POWER2
Sandy Bridge Processor 5/7 ( GRAPHICS POWER )

layout? check
U 34 G
POWER 1. 5 V
V G F X _C OR E
All VAXG = 33A R 11 9
AT2 4 AK3 5
SENSE
LINES
AT2 3 V A X G1 V A X G _S E N S E AK3 4 V C C _ GT _ S E N S E 3 7 Q1 5 1 K _ 1 %_ 0 4
AT2 1 V A X G2 V S S A X G _S E N S E V S S _ G T_ S E N S E 3 7
C 39 1 C 3 92 C 3 69 C3 8 8 C 3 87 *A O 3 40 2 L
AT2 0 V A X G3 V _S M _ V R E F S D V _ S M_ V R E F _ C N T
2 2 u_ 6 . 3 V _ X5 R _0 8 2 2 u _6 . 3 V _ X 5R _ 08 *2 2u _ 6 . 3 V _X 5 R _ 0 8 22 u _ 6. 3V _ X 5 R _ 0 8 2 2 u _6 . 3 V _ X 5R _ 08 AT1 8 V A X G4
AT1 7 V A X G5 R1 1 4
A R2 4 V A X G6 *1 0 0K _1 % _ 04 R 11 7
V A X G7
G
A R2 3
A R2 1 V A X G8 11/03
11/03 1 K _ 1 %_ 0 4
A R2 0 V A X G9
C5 8 6 * 0 . 1u _ 1 0V _ X 7 R _ 0 4 SU SB# 1 5 , 27 , 2 8 , 3 2
C 38 6 C 3 76 C 3 74 C3 1 7 C 3 77 A R1 8 V A X G1 0
VREF
A R1 7 V A X G1 1
2 2 u_ 6 . 3 V _ X5 R _0 8 2 2 u _6 . 3 V _ X 5R _ 08 22 u _ 6. 3 V _ X 5 R _ 08 22 u _ 6. 3V _ X 5 R _ 0 8 2 2 u _6 . 3 V _ X 5R _ 08 AP2 4 V A X G1 2 A L1 V _ S M _ V R E F 0 _0 4 R 1 16 V _ S M _V R E F _ C N T
AP2 3 V A X G1 3 S M _ V RE F
AP2 1 V A X G1 4
AP2 0 V A X G1 5
AP1 8 V A X G1 6 CAD Note: +V_SM_VREF should
AP1 7 V A X G1 7 have 10 mil trace width
A N2 4 V A X G1 8
V A X G1 9
layout? check
C 31 5 C 3 14 C 3 18 C 37 3 A N2 3
+ + A N2 1 V A X G2 0
* 33 0 U _ 2 . 5 V _D 2 _D * 2 2u _ 6 . 3V _X 5 R _ 0 8 2 2 u_ 6 . 3 V _ X5 R _0 8 A N2 0 V A X G2 1
5 6 0 u_ 2 . 5 V _ 6. 6 * 6. 6 *5 . 9 A N1 8 V A X G2 2 1 . 5V S _C P U
DDR3 -1.5V RAILS

A N1 7 V A X G2 3
A M2 4 V A X G2 4 AF7
All VDDQ = 12A
GRAPHICS
1230 D02
A M2 3
A M2 1
A M2 0
V A X G2 5
V A X G2 6
V A X G2 7
V A X G2 8
V D DQ 1
V D DQ 2
V D DQ 3
V D DQ 4
AF4
AF1
A C7
C6 0 C6 7 C 63 C6 5 C 58
+
C4 0 0 Sheet 6 of 46
A M1 8 A C4 1 0u _ 6 . 3V _X 5 R _ 0 6 10 u _ 6. 3 V _ X 5 R _ 06 1 0 u_ 6 . 3 V _ X5 R _0 6 1 0u _ 6 . 3V _X 5 R _ 0 6 1 0 u _ 6. 3 V _ X 5R _ 06 33 0 U _ 2 V _ D 2 _ D
C 38 9
2 2 u_ 6 . 3 V _ X5 R _0 8
C3 9 0
2 2u _ 6 . 3V _X 5 R _ 0 8
C 3 22
2 2 u _ 6. 3 V _ X 5R _ 08
A M1 7
AL 2 4
AL 2 3
V A X G2 9
V A X G3 0
V A X G3 1
V D DQ 5
V D DQ 6
V D DQ 7
A C1
Y7
Y4
PROCESSOR/
AL 2 1 V A X G3 2 V D DQ 8 Y1
AL 2 0
AL 1 8
AL 1 7
V A X G3 3
V A X G3 4
V A X G3 5
V D DQ 9
V D DQ 1 0
V D DQ 1 1
U7
U4
U1
C7 1
1 0u _ 6 . 3V _X 5 R _ 0 6
1124 for ? ? ? ?
POWER2
AK2 4 V A X G3 6 V D DQ 1 2 P7
AK2 3 V A X G3 7 V D DQ 1 3 P4
AK2 1 V A X G3 8 V D DQ 1 4 P1
AK2 0 V A X G3 9 V D DQ 1 5
AK1 8 V A X G4 0
AK1 7 V A X G4 1
AJ 2 4 V A X G4 2
AJ 2 3 V A X G4 3
AJ 2 1 V A X G4 4
AJ 2 0 V A X G4 5
AJ 1 8 V A X G4 6 1229 D02(W240HU)
AJ 1 7 V A X G4 7
A H2 4 V A X G4 8 0. 8 5 V S
A H2 3 V A X G4 9
All VDDQ = 6A
SA RAIL
A H2 1 V A X G5 0 M2 7
A H2 0 V A X G5 1 VC CS A 1 M2 6
A H1 8 V A X G5 2 VC CS A 2 L2 6
A H1 7 V A X G5 3 VC CS A 3 J2 6 C3 2 3 C 3 45 C 28 C8 1 1
V A X G5 4 VC CS A 4 J2 5
VC CS A 5 +P C 1 67
J2 4 1 0u _ 6 . 3V _X 5 R _ 0 8 10 u _ 6. 3 V _ X 5 R _ 08 1 0 u_ 6 . 3 V _ X5 R _0 6 *1 0u _ 6 . 3 V _X 5 R _ 0 6
VC CS A 6 H2 6 * 3 30 U _ 2 V _ D2 _ D
VC CS A 7 H2 5
VC CS A 8
1.8V RAIL
1 .5 V S _ CP U
1 .8 V S 1230 D02
All VCCPLL = 1.2A B6 H2 3 V CC S A _ S E N SE
A6 VCC P L L 1 V C C S A _S E N S E V C C S A _S E N S E 36
MISC
A2 VCC P L L 2 * 1 0K _ 0 4
+ C4 5 8 C3 1 6 C3 1 9 C 3 20
VCC P L L 3
R 53 2 * 0_ 0 4 R 3 93
V CC S A _ V ID0 3 6
3 3 0 uF _2 .5 V _ 9 m_ 6 . 3 *6 10 u _ 6. 3 V _ X 5 R _ 0 6 1 u_ 6 . 3 V _ X5 R _ 0 4 1 u _ 6. 3V _ X 5 R _ 0 4 C2 2 R 56 1 0 K_ 0 4
F C _C 2 2 C2 4
V C CS A _ V ID 1 V CC S A _ V ID1 3 6
P Z 9 8 8 27 -3 6 4B -01 F
1 0 K _ 04
R 3 86
36 0 . 85 V S
1 9 , 30 , 3 2 1 . 5V S
1 8 , 19 , 3 4 1 . 8V S
3 , 8 , 9 , 1 0, 20 , 2 7 , 32 , 3 4 1 . 5V
3 ,3 2 1 . 5V S _C P U
38 V GF X_ C OR E
3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4 , 15 , 1 6 , 1 7, 1 8 , 1 9, 2 0 , 2 3 , 24 , 2 5 , 2 6, 2 8 , 2 9, 30 , 3 1 , 32 , 3 7 3 . 3V S
PROCESSOR/ POWER2 B - 7
Schematic Diagrams
PROCESSOR/ GND
Sandy Bridge Processor 6/7 ( GND )

U3 4H U34I
AT35 AJ22
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30
CAD Note: 0 ohm resistor AT10 VSS9 VSS89 AJ1 T28 VSS167 VSS240 E15
should be placed close AT7 VSS1 0 VSS90 AH35 T27 VSS168 VSS241 E13
AT4 VSS1 1 VSS91 AH34 T26 VSS169 VSS242 E10
to CPU AT3 VSS1 2 VSS92 AH32 P9 VSS170 VSS243 E9
AR25 VSS1 3 VSS93 AH30 P8 VSS171 VSS244 E8

AR10 VSS1 8 VSS98 AH22 N 35 VSS176 VSS249 E3
AR2 VSS2 1 VSS101 AH7 N 32 VSS179 VSS252 D3 5
AP34 VSS2 2 VSS102 AH4 N 31 VSS180 VSS253 D3 2
AP31 VSS2 3 VSS103 AG9 N 30 VSS181 VSS254 D2 9
VSS2 4 VSS104 VSS182 VSS255
Sheet 7 of 46 AP28
AP25
AP22
VSS2 5
VSS2 6
VSS105
VSS106
AG8
AG4
AF6
N 29
N 28
N 27
VSS183
VSS184
VSS256
VSS257
D2 6
D2 0
D1 7
AP19 VSS2 7 VSS107 AF5 N 26 VSS185 VSS258 C3 4
CPU 6/7 (GND) AP16
AP13
VSS2 8
VSS2 9
VSS108
VSS109
AF3
AF2
M34
L 33
VSS186
VSS187
VSS259
VSS260
C3 1
C2 8
AP10 VSS3 0 VSS110 AE35 L 30 VSS188 VSS261 C2 7
AP7 VSS3 1 VSS111 AE34 L 27 VSS189 VSS262 C2 5
AP4 VSS3 2 VSS112 AE33 L9 VSS190 VSS263 C2 3
AP1 VSS3 3 VSS113 AE32 L8 VSS191 VSS264 C1 0
AN30 VSS3 4 VSS114 AE31 L6 VSS192 VSS265 C1
AN27 VSS3 5 VSS115 AE30 L5 VSS193 VSS266 B22
AN25 VSS3 6 VSS116 AE29 L4 VSS194 VSS267 B19
AN22
AN19
VSS3 7
VSS3 8
VSS3 9
VSS VSS117
VSS118
VSS119
AE28
AE27
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE26 L1 B13
AN13 VSS4 0 VSS120 AE9 K35 VSS198 VSS271 B11
AN10 VSS4 1 VSS121 AD7 K32 VSS199 VSS272 B9
AN7 VSS4 2 VSS122 AC9 K29 VSS200 VSS273 B8
AN4 VSS4 3 VSS123 AC8 K26 VSS201 VSS274 B7
AM29 VSS4 4 VSS124 AC6 J 34 VSS202 VSS275 B5
AM25 VSS4 5 VSS125 AC5 J 31 VSS203 VSS276 B3
AM22 VSS4 6 VSS126 AC3 H 33 VSS204 VSS277 B2
AM19 VSS4 7 VSS127 AC2 H 30 VSS205 VSS278 A35
AM16 VSS4 8 VSS128 AB35 H 27 VSS206 VSS279 A32
AM2 VSS5 4 VSS134 AB29 H 10 VSS212 VSS285
AM1 VSS5 5 VSS135 AB28 H9 VSS213
AL34 VSS5 6 VSS136 AB27 H8 VSS214
AL31 VSS5 7 VSS137 AB26 H7 VSS215
AL28 VSS5 8 VSS138 Y9 H6 VSS216
AL10 VSS6 4 VSS144 W35 G 35 VSS222
AL7 VSS6 5 VSS145 W34 G 32 VSS223
AL4 VSS6 6 VSS146 W33 G 29 VSS224
AL2 VSS6 7 VSS147 W32 G 26 VSS225
AK33 VSS6 8 VSS148 W31 G 23 VSS226
AK30 VSS6 9 VSS149 W30 G 20 VSS227
AK27 VSS7 0 VSS150 W29 G 17 VSS228
AK25 VSS7 1 VSS151 W28 G 11 VSS229
AK22 VSS7 2 VSS152 W27 F34 VSS230
AK19 VSS7 3 VSS153 W26 F31 VSS231
AK16 VSS7 4 VSS154 U9 F29 VSS232
AK13 VSS7 5 VSS155 U8 VSS233
AK10 VSS7 6 VSS156 U6
AJ25 VSS7 9 VSS159 U2
VSS8 0 VSS160
PZ98827 -364B-0 1F PZ98 827-3 64B-01F
B - 8 PROCESSOR/ GND
Schematic Diagrams
PROCESSOR/ RESERVED

CFG Straps for Processor
( RESERVED )
PEG Static Lane Reversal - CFG2 is for the 16x U3 4 E
L7
CFG2 1:(Default) Normal Operation; Lane # R S V D2 8 AG 7
definition matches socket pin map definition AK2 8 R S V D2 9 AE7
CF G 0
AK2 9 CF G [ 0] R S V D3 0 AK2
0:Lane Reversed CF G 2 AL 2 6 CF G [ 1] R S V D3 1 W8
AL 2 7 CF G [ 2] R S V D3 2
CF G 4 AK2 6 CF G [ 3]
CF G 5 AL 2 9 CF G [ 4] AT2 6
CF G 2 R 11 1 *1 K _ 0 4 CF G 6 AL 3 0 CF G [ 5] R S V D3 3 A M 33
CF G 7 AM 3 1 CF G [ 6] R S V D3 4 AJ 2 7
AM 3 2 CF G [ 7] R S V D3 5
AM 3 0 CF G [ 8]
AM 2 8 CF G [ 9]
AM 2 6 CF G [ 10 ]
AN 2 8 CF G [ 11 ]
AN 3 1 CF G [ 12 ] T8
Display Port Presence Strap AN 2 6 CF G [ 13 ] R S V D3 7 J16
AM 2 7 CF G [ 14 ] R S V D3 8 H1 6
1:(Default) Disabled; No Physical Display Port AK3 1 CF G [ 15 ] R S V D3 9 G1 6
CFG4 attached to Embedded Display Port AN 2 9 CF G
CF G
[ 16 ]
[ 17 ]
R S V D4 0
0:Enabled; An external Display Port device is

connected to the Embedded Display Port
A R 35
Sheet 8 of 46
1 AJ 3 1 R S V D4 1 AT3 4
PROCESSOR/
H _ CP U _R SVD
H _ CP U _R SVD 2A H 3 1 V A X G_ V A L _ S E N S E R S V D4 2 AT3 3
H _ CP U _R SVD 3 AJ 3 3 V S S A X G_ V A L _ S E N S E R S V D4 3 AP3 5
CF G 4 H _ CP U _R SVD 4A H 3 3 V C C _V A L_ S E N S E R S V D4 4 A R 34
R 11 0 *1 K _ 0 4
AJ 2 6
V S S _ V A L _S E N S E
RS VD 5
R S V D4 5
RESERVED
RESERVED
B3 4
V R E F _ C H _ A _ D I MM B 4 R S V D4 6 A3 3
PCIE Port Bifurcation Straps V R E F _ C H _ B _ D I MM D 1 RS VD 6 R S V D4 7 A3 4
RS VD 7 R S V D4 8 B3 5
R S V D4 9 C3 5
11: (Default) x16 - Device 1 functions 1 and 2 disabled R S V D5 0
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled F25 1. 5 V
F24 RS VD 8
CFG[6:5] 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) F23 RS VD
RS VD
9
10
R 40 * 0_ 0 4
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled D 24 AJ 3 2
G 25 RS VD 11 R S V D5 1 AK3 2 R 38
G 24 RS VD 12 R S V D5 2
E2 3 RS VD 13 Q7 1 K _ 1 % _0 4
CF G 5 R 99 *1 K _ 0 4 D 23 RS VD 14 * A O3 4 02 L
C 30 RS VD 15 A H 27 V R E F _C H _ A _ D I M M S D MV R E F _ D Q _D I M0
A3 1 RS VD 16 V CC _ DIE _ S E N S E M V R E F _ D Q_ D I M MA 9
CF G 6 R 92 *1 K _ 0 4 B3 0 RS VD 17
B2 9 RS VD 18
R3 9 R 31 1 0/ 29
G
D 30 RS VD 19 A N 35 *1 K _ 04
B3 1 RS VD 20 R S V D5 4 A M 35 1 K _ 1 % _0 4
A3 0 RS VD 21 R S V D5 5
C 29 RS VD 22
RS VD 23
PEG DEFER TRAINING J20

B1 8 RS VD 2 4 AT2 D R A MR S T _C N T R L 3 , 1 4
1: (Default) PEG Train immediately following xxRESETB de assertion A1 9 RS VD 2 5 R S V D5 6 AT1
CFG7 0: PEG Wait for BIOS for training V C C I O_ S E L R S V D5 7
R S V D5 8
AR 1 1 .5 V
J15 R 44 * 0_ 0 4
RS VD 2 7
CF G 7 R 93 *1 K _ 0 4 B1 R2 8
KEY
Q6
* A O3 4 02 L 1 K _1 % _ 0 4
V R E F _C H _ B _ D I M M S D MV R E F _ D Q _ D I M 1
M V R E F _ D Q_ D I M MB 1 0
1 0/ 29
R4 9 R2 9
G
1 0/2 9 P Z 9 8 82 7 -3 64 B -0 1 F *1 K _ 04
R3 9 2 10 K _ 0 4 1 K _1 % _ 0 4
3 .3 V
R3 9 1 * 10 m i l_ 0 4 H _ S N B _ I V B # _P W R C TR L
D R A MR S T _C N T R L
On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
3 , 6 , 9 , 1 0, 2 0 , 2 7, 3 2 , 3 4 1. 5 V
2 , 3 , 11 , 1 3 , 1 5, 1 7 , 1 9, 20 , 2 2 , 23 , 2 7 , 2 9, 3 1 , 3 2, 3 4 , 3 6 3. 3 V
PROCESSOR/ RESERVED B - 9
Schematic Diagrams
DDR3 SO-DIMM_0
SO-DIMM A CHANGE TO STANDARD
4 M_ A _ A [ 1 5: 0] J D I MM2 A M_ A _ D Q [ 6 3: 0 ] 4
M_ A _ A 0 98 5 M_ A _ D Q 0 J D I M M2 B
M_ A _ A 1 97 A0 DQ 0 7 M_ A _ D Q 1
M_ A _ A 2 96 A1 DQ 1 15 M_ A _ D Q 2
M_ A _ A 3 95 A2 DQ 2 17 M_ A _ D Q 3 1 .5 V
M_ A _ A 4 92 A3 DQ 3 4 M_ A _ D Q 4
91 A4 DQ 4 6 75 44
M_ A _ A 5 M_ A _ D Q 5
M_ A _ A 6 90 A5 DQ 5 16 M_ A _ D Q 6 76 V DD 1 VSS1 6 48
M_ A _ A 1 0 107 A9 DQ 9 33 M_ A _ D Q 10 88 V DD 5 VSS2 0 60
M_ A _ A 1 1 84 A 1 0 /A P DQ 1 0 35 M_ A _ D Q 11 93 V DD 6 VSS2 1 61
M_ A _ A 1 2 83 A1 1 DQ 1 1 22 M_ A _ D Q 12 94 V DD 7 VSS2 2 65
M_ A _ A 1 3 119 A 1 2 /B C# DQ 1 2 24 M_ A _ D Q 13 3 .3 V S 99 V DD 8 VSS2 3 66
A1 3 DQ 1 3 V DD 9 VSS2 4
M_ A _ A 1 4 80 34 M_ A _ D Q 14 100 71
M_ A _ A 1 5 78 A1 4 DQ 1 4 36 M_ A _ D Q 15 2 0 mil s 105 V DD 10 VSS2 5 72
A1 5 DQ 1 5 39 M_ A _ D Q 16 106 V DD 11 VSS2 6 127
109 DQ 1 6 41 M_ A _ D Q 17 C1 0 1 C 1 02 111 V DD 12 VSS2 7 128
4 M _ A_ BS0 108 BA0 DQ 1 7 51 112 V DD 13 VSS2 8 133
M_ A _ D Q 18
4 M _ A_ BS1 79 BA1 DQ 1 8 53 M_ A _ D Q 19 117 V DD 14 VSS2 9 134
4 M _ A_ BS2 1u _ 6 . 3V _Y 5 V _0 4 0 . 1 u _ 16 V _ Y 5 V _ 0 4
114 BA2 DQ 1 9 40 M_ A _ D Q 20 118 V DD 15 VSS3 0 138
4 M _ A_ CS # 0 121 S0 # DQ 2 0 42 M_ A _ D Q 21 123 V DD 16 VSS3 1 139
4 M _ A_ CS # 1 S1 # DQ 2 1 V DD 17 VSS3 2
101 50 M_ A _ D Q 22 124 144
Sheet 9 of 46 4
4
4
M_ A _ C L K _ D D R
0
#0
1
103
102
104
CK 0
C K 0#
CK 1
DQ 2 2
DQ 2 3
DQ 2 4
52
57
59
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
23
24
25
199
V DD 18
V DD S P D
VSS3 3
VSS3 4
VSS3 5
145
150
151
4 M_ A _ C L K _ D D R #1 C K 1# DQ 2 5 VSS3 6
DDR3 SO-DIMM_0 4 M _ A_ CK E0
4 M _ A_ CK E1
4 M_ A _ C A S #
73
74
115
110
CK E 0
CK E 1
CA S #
DQ 2 6
DQ 2 7
DQ 2 8
67
69
56
58
M_ A _ D Q
M_ A _ D Q
M_ A _ D Q
26
27
28
3 .3 V S
R 12 4 *1 0 K _ 0 4
77
122
125
NC 1
NC 2
N C TE S T
VSS3 7
VSS3 8
VSS3 9
155
156
161
162
M_ A _ D Q 29
4 M_ A _ R A S # 113 RA S # DQ 2 9 68 M_ A _ D Q 30 198 VSS4 0 167
4 M_ A _ W E # 197 W E# DQ 3 0 70 2, 10 T S # _ D I M M0 _ 1 30 E VE NT # VSS4 1 168
S A 0 _D I M0 M_ A _ D Q 31
S A 1 _D I M0 201 SA0 DQ 3 1 12 9 M_ A _ D Q 32 3, 10 D D R 3_ D R A M R S T # RES E T # VSS4 2 172
202 SA1 DQ 3 2 13 1 M_ A _ D Q 33 C2 4 1 u _ 6 . 3V _X 5 R _ 0 4 VSS4 3 173
10 , 1 4 S MB _C L K 200 SC L DQ 3 3 14 1 M_ A _ D Q 34 1 VSS4 4 178
1 0 , 1 4 S MB _ D A T A C2 3 0 . 1 u _ 10 V _ X 5 R _ 0 4
3 .3 VS SD A DQ 3 4 14 3 M_ A _ D Q 35 126 V RE F _ D Q VSS4 5 179
116 DQ 3 5 13 0 8 M V R E F _ D Q_ D I M MA V RE F _ C A VSS4 6 184
M_ A _ D Q 36
4 M _ A _ OD T 0 120 OD T 0 DQ 3 6 13 2 M_ A _ D Q 37 R4 1 *0 _ 04 VSS4 7 185
4 M _ A _ OD T 1 OD T 1 DQ 3 7 14 0 2 VSS4 8 189
RN 2 M_ A _ D Q 38
11 DQ 3 8 14 2 M_ A _ D Q 39 M V R E F _D I M0 3 VSS1 VSS4 9 190
1 0 K _8 P 4 R _0 4
1 8 S A 1_ D I M1 28 DM 0 DQ 3 9 14 7 M_ A _ D Q 40 C9 2 1 u _ 6 . 3V _X 5 R _ 0 4 8 VSS2 VSS5 0 195
2 7 S A 0_ D I M1 S A 1 _ D I M 1 10 46 DM 1 DQ 4 0 14 9 M_ A _ D Q 41 9 VSS3 VSS5 1 196
S A 0 _ D I M 1 10 C9 1 0 . 1 u _ 10 V _ X 5 R _ 0 4
3 6 S A 1_ D I M0 63 DM 2 DQ 4 1 15 7 M_ A _ D Q 42 13 VSS4 VSS5 2
4 5 S A 0_ D I M0 136 DM 3 DQ 4 2 15 9 M_ A _ D Q 43 14 VSS5
153 DM 4 DQ 4 3 14 6 M_ A _ D Q 44 19 VSS6
170 DM 5 DQ 4 4 14 8 M_ A _ D Q 45 20 VSS7 V T T _M E M
187 DM 6 DQ 4 5 15 8 M_ A _ D Q 46 25 VSS8
DM 7 DQ 4 6 16 0 M_ A _ D Q 47
CLOS E TO SO- DIM M_ 0 26 VSS9 203
4 M_ A _ D Q S [ 7 : 0 ] M_ A _ D Q S0 12 DQ 4 7 16 3 M_ A _ D Q 48 31 VSS1 0 V TT 1 204
M_ A _ D Q S1 29 DQ S0 DQ 4 8 16 5 M_ A _ D Q 49 32 VSS1 1 V TT 2
M_ A _ D Q S2 47 DQ S1 DQ 4 9 17 5 M_ A _ D Q 50 37 VSS1 2 G ND 1
M_ A _ D Q S3 64 DQ S2 DQ 5 0 17 7 M_ A _ D Q 51 R9 4 1K _ 1 % _ 04 M V R E F _ D I M0 38 VSS1 3 G1 G ND 2
M_ A _ D Q S4 137 DQ S3 DQ 5 1 16 4 M_ A _ D Q 52 1 .5 V 43 VSS1 4 G2
M_ A _ D Q S5 154 DQ S4 DQ 5 2 16 6 M_ A _ D Q 53 VSS1 5
M_ A _ D Q S6 171 DQ S5 DQ 5 3 17 4 M_ A _ D Q 54 R1 0 3 D D R S K - 20 4 0 1-T R 5B
M_ A _ D Q S7 188 DQ S6 DQ 5 4 17 6 M_ A _ D Q 55
DQ S7 DQ 5 5 18 1 M_ A _ D Q 56 1 K _ 1% _ 0 4
4 M_ A _ D QS # [ 7 : 0 ] M_ A _ D Q S# 0 10 DQ 5 6 18 3 M_ A _ D Q 57
27 DQ S0 # DQ 5 7 19 1
M_ A _ D Q S# 1 M_ A _ D Q 58
M_ A _ D Q S# 2 45 DQ S1 # DQ 5 8 19 3 M_ A _ D Q 59
M_ A _ D Q S# 3 62 DQ S2 # DQ 5 9 18 0 M_ A _ D Q 60
M_ A _ D Q S# 4 135 DQ S3 # DQ 6 0 18 2 M_ A _ D Q 61
M_ A _ D Q S# 5 152 DQ S4 # DQ 6 1 19 2 M_ A _ D Q 62
M_ A _ D Q S# 6 169 DQ S5 # DQ 6 2 19 4 M_ A _ D Q 63
M_ A _ D Q S# 7 186 DQ S6 # DQ 6 3
DQ S7 #
D D R S K -2 0 40 1 -T R 5 B
V T T _ ME M ? ? ? DIMM SLOT? ?
C1 0 3 C1 0 5 C1 0 4 C 1 06 C 1 11
1 u_ 6 . 3 V _ X5 R _0 4 1u _ 6 . 3 V _ X5 R _0 4 1u _ 6 . 3V _X 5 R _ 0 4 1 u _ 6 . 3V _X 5 R _ 0 4 1 0 u _6 . 3 V _ X 5R _ 06
1 .5 V
C3 7 0 C 64 C5 7 C5 5 C6 1 C4 0 C 70 C 84 C 46
+ C3 4 7 +
*2 2 0u _ 4 V _ V _ A 1 0 u_ 1 0 V _ Y 5 V _ 08 1 0u _ 1 0 V _Y 5 V _ 08 1 0u _ 6 . 3V _X 5 R _ 0 6 1u _ 6 . 3 V _X 5 R _0 4 1u _ 6 . 3V _X 5 R _ 0 4 1 u _ 6 . 3V _ X 5 R _ 0 4 1 u _ 6. 3 V _ X 5 R _ 0 4 1 u _ 6. 3 V _ X 5 R _ 0 4 3 , 6 , 8, 10 , 2 0 , 2 7, 3 2 , 3 4 1. 5 V
5 6 0 u_ 2 . 5 V _ 6. 6 * 6. 6 * 5. 9
1 0 , 3 4 V T T_ M E M
3 , 1 0, 1 1 , 1 2 , 13 , 1 4 , 1 5, 1 6 , 1 7 , 18 , 1 9 , 2 0, 23 , 2 4 , 25 , 2 6 , 2 8, 29 , 3 0 , 3 1, 3 2 , 3 7 3. 3 V S
1 9, 3 0 , 3 2 1. 5 V S
1 . 5V
C3 7 C8 6 C6 8 C 82 C 48 C 49 C 51 C5 0 C5 2 C4 7
0 . 1u _ 1 0 V _X 5 R _ 0 4 0. 1u _ 1 0V _X 5 R _ 0 4 0. 1 u _ 10 V _ X 5 R _ 0 4 0 . 1 u _ 10 V _ X 5 R _ 0 4 0 . 1 u _1 0 V _ X 5R _ 04 0 . 1 u _1 0 V _ X 5R _ 04 0 . 1 u_ 1 0 V _ X5 R _0 4 0 . 1 u_ 1 0 V _ X5 R _0 4 0 . 1u _ 1 0 V _X 5 R _ 0 4 0 . 1u _ 1 0V _X 5 R _ 0 4
B - 10 DDR3 SO-DIMM_0
Schematic Diagrams
DDR3 SO-DIMM_1
JD I MM 1 A
4 M _B _ B [1 5 : 0 ] M _B _ B 0 98 5 M_ B _ DQ 0 M _ B _ D Q[ 6 3 : 0 ] 4
J D I MM 1B
M _B _ B 1 97 A 0 DQ 0 7 M_ B _ DQ 1
M _B _ B 2 96 A 1 DQ 1 15 M_ B _ DQ 2 1 .5 V
M _B _ B 3 95 A 2 DQ 2 17 M_ B _ DQ 3
M _B _ B 4 92 A 3 DQ 3 4 M_ B _ DQ 4
M _B _ B 5 91 A 4 DQ 4 6 M_ B _ DQ 5 75 44
M _B _ B 6 90 A 5 DQ 5 16 M_ B _ DQ 6 76 VD D1 V SS1 6 48
89 A 7 DQ 7 21 82 VD D3 V SS1 8 54
M _B _ B 8 M_ B _ DQ 8
M _B _ B 1 0 1 07 A 9 DQ 9 33 M_ B _ DQ 10 88 VD D5 V SS2 0 60
M _B _ B 1 1 84 A 10 / A P D Q1 0 35 M_ B _ DQ 11 93 VD D6 V SS2 1 61
M _B _ B 1 2 83 A 11 D Q1 1 22 M_ B _ DQ 12 94 VD D7 V SS2 2 65
M _B _ B 1 3 1 19 A 12 / B C # D Q1 2 24 M_ B _ DQ 13 99 VD D8 V SS2 3 66
M _B _ B 1 4 80 A 13 D Q1 3 34 M_ B _ DQ 14 10 0 VD D9 V SS2 4 71
M _B _ B 1 5 78 A 14 D Q1 4 36 M_ B _ DQ 15 10 5 VD D1 0 V SS2 5 72
A 15 D Q1 5 39 M_ B _ DQ 16 10 6 VD D1 1 V SS2 6 12 7
1 09 D Q1 6 41 M_ B _ DQ 17 11 1 VD D1 2 V SS2 7 12 8
4 M_ B _ B S 0 1 08 B A0 D Q1 7 51 11 2 VD D1 3 V SS2 8 13 3
M_ B _ DQ 18
4 M_ B _ B S 1 79 B A1 D Q1 8 53 M_ B _ DQ 19 11 7 VD D1 4 V SS2 9 13 4
4 M_ B _ B S 2 B A2 D Q1 9 VD D1 5 V SS3 0
1 14 40 M_ B _ DQ 20 11 8 13 8
4 M_ B _ CS #0 1 21 S 0# D Q2 0 42 M_ B _ DQ 21 12 3 VD D1 6 V SS3 1 13 9
4 M_ B _ CS #1 1 01 S 1# D Q2 1 50 M_ B _ DQ 22 3 .3 V S 12 4 VD D1 7 V SS3 2 14 4
4 M _ B _C L K _ DD R 0 1 03 C K0 D Q2 2 52 M_ B _ DQ 23 VD D1 8 V SS3 3 14 5
4 M _ B _C L K _ DD R #0 1 02 C K0 # D Q2 3 57 M_ B _ DQ 24 2 0 mi ls 19 9 V SS3 4 15 0
4 M _ B _C L K _ DD R 1 1 04 C K1 D Q2 4 59 V D DS P D V SS3 5 15 1
M_ B _ DQ 25
4 M _ B _C L K _ DD R #1 73 C K1 # D Q2 5 67 M_ B _ DQ 26 C 41 6 C 4 15 77 V SS3 6 15 5
4 M_ B _ CK E 0
74 C KE0 D Q2 6 69 M_ B _ DQ 27 12 2 N C1 V SS3 7 15 6
4 M_ B _ CK E 1 1 15 C KE1 D Q2 7 56 M_ B _ DQ 28 1 u _6 . 3 V _ Y 5 V _ 0 4 0 .1 u _1 6 V _ Y 5 V _ 0 4 12 5 N C2 V SS3 8 16 1
4 M _B _C A S # 1 10 C AS# D Q2 8 58 N CT E ST V SS3 9 16 2
M_ B _ DQ 29
4 M _B _R A S # 1 13 R AS# D Q2 9 68 M_ B _ DQ 30 19 8 V SS4 0 16 7
4 M _B _W E # 1 97 W E# D Q3 0 70 2 , 9 TS # _ D I M M0 _ 1 30 EVEN T# V SS4 1 16 8
S A 0 _D I M1 M_ B _ DQ 31
9 S A 0 _ D IM 1 S A 1 _D I M1 2 01 S A0 D Q3 1 1 29 M_ B _ DQ 32 3 , 9 D D R3 _D R A MRS T# R ESET# V SS4 2 17 2
9 S A 1 _ D IM 1 2 02 S A1 D Q3 2 1 31 V SS4 3 17 3
M_ B _ DQ 33 C 26 1 u_ 6 . 3 V _ X5 R _0 4
9 , 14 S M B _ C L K
9, 14 S M B _ DA T A
2 00
1 16
S CL
S DA
D Q3 3
D Q3 4
D Q3 5
1 41
1 43
1 30
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
34
35
36 8 M V R E F _D Q_ D I MM B
C 25 0 . 1u _ 1 0V _X 5 R _ 0 4 1
12 6 V R EF _ DQ
V R EF _ CA
V
V
V
SS4 4
SS4 5
SS4 6
17 8
17 9
18 4
Sheet 10 of 46
4 M_ B _ OD T 0 O DT 0 D Q3 6 V SS4 7
4 M_ B _ OD T 1
1 20
11
O DT 1
D M0
D Q3 7
D Q3 8
D Q3 9
1 32
1 40
1 42
M_ B _ DQ
M_ B _ DQ
M_ B _ DQ
37
38
39 M V R E F _D I M1
R4 2 *0 _ 0 4
2
3 VSS1
VSS2
V
V
V
SS4 8
SS4 9
SS5 0
18 5
18 9
19 0
DDR3 SO-DIMM_1
28 1 47 M_ B _ DQ 40 C8 9 1 u _ 6. 3V _ X 5 R _ 0 4 8 19 5
46 D M1 D Q4 0 1 49 M_ B _ DQ 41 C8 8 0 . 1 u _ 10 V _ X 5R _ 04 9 VSS3 V SS5 1 19 6
63 D M2 D Q4 1 1 57 13 VSS4 V SS5 2
M_ B _ DQ 42
1 36 D M3 D Q4 2 1 59 M_ B _ DQ 43 14 VSS5
1 53 D M4 D Q4 3 1 46 M_ B _ DQ 44 19 VSS6
1 70 D M5 D Q4 4 1 48 M_ B _ DQ 45 20 VSS7 V T T _ ME M
1 87 D M6 D Q4 5 1 58 M_ B _ DQ 46 25 VSS8
D M7 D Q4 6 1 60 M_ B _ DQ 47 26 VSS9 20 3
4 M_ B _ D Q S [ 7 : 0 ]
M _B _ D QS 0 12 D Q4 7 1 63 M_ B _ DQ 48 CLOS E TO SO-DIMM_ 1 31 VSS1 0 VTT1 20 4
M _B _ D QS 1 29 D QS 0 D Q4 8 1 65 M_ B _ DQ 49 32 VSS1 1 VTT2
M _B _ D QS 2 47 D QS 1 D Q4 9 1 75 M_ B _ DQ 50 37 VSS1 2 GN D 1
M _B _ D QS 3 64 D QS 2 D Q5 0 1 77 M_ B _ DQ 51 38 VSS1 3 G1 GN D 2
M _B _ D QS 4 1 37 D QS 3 D Q5 1 1 64 M_ B _ DQ 52 R9 7 1K _ 1 % _ 04 MV R E F _ D IM 1 43 VSS1 4 G2
M _B _ D QS 5 1 54 D QS 4 D Q5 2 1 66 M_ B _ DQ 53 1. 5V VSS1 5
M _B _ D QS 6 1 71 D QS 5 D Q5 3 1 74 M_ B _ DQ 54 D D R S K -2 0 40 1 -T R 9 D
M _B _ D QS 7 1 88 D QS 6 D Q5 4 1 76 M_ B _ DQ 55 R9 8
D QS 7 D Q5 5 1 81 M_ B _ DQ 56
4 M_ B _ D QS # [ 7 : 0 ] M _B _ D QS # 0 10 D Q5 6 1 83 M_ B _ DQ 57 1K _1 % _ 04
M _B _ D QS # 1 27 D QS 0 # D Q5 7 1 91 M_ B _ DQ 58
45 D QS 1 # D Q5 8 1 93
M _B _ D QS # 2 M_ B _ DQ 59
M _B _ D QS # 3 62 D QS 2 # D Q5 9 1 80 M_ B _ DQ 60
M _B _ D QS # 4 1 35 D QS 3 # D Q6 0 1 82 M_ B _ DQ 61
M _B _ D QS # 5 1 52 D QS 4 # D Q6 1 1 92 M_ B _ DQ 62
M _B _ D QS # 6 1 69 D QS 5 # D Q6 2 1 94 M_ B _ DQ 63
M _B _ D QS # 7 1 86 D QS 6 # D Q6 3
D QS 7 #
D D R S K -2 0 4 01 -T R9 D
La yout Note : ? ? ? DIMM SLOT? ?

SO -D IMM_1 is pla ce d fa rthe r from the GMCH tha n SO -DI MM_0
V T T _ ME M
C1 1 0 C 1 09 C 10 7 C1 0 8 C 1 12
1u _ 6 . 3 V _X 5 R _ 0 4 1 u _ 6. 3V _ X 5 R _ 0 4 1 u _6 . 3 V _ X 5R _ 04 1 u_ 6 . 3 V _ X5 R_ 0 4 1 0 u _6 . 3 V _ X 5R _ 06
1 .5 V
C3 7 9 C 78 C 38 0 C4 4 C 83 C 76 C3 9 C7 3
19 ,3 0 ,3 2 1 .5 VS
10 u _ 1 0V _ Y 5V _ 0 8 1 0 u _1 0 V _ Y 5 V _ 0 8 1 0 u_ 1 0 V _ Y 5 V _ 08 1 u_ 6 . 3 V _ X5 R_ 0 4 1 u _ 6. 3V _ X 5 R_ 0 4 1 u _6 .3 V _ X 5R _ 04 1 u_ 6 . 3 V _ X5 R _0 4 1u _ 6 . 3V _ X 5 R _ 0 4
3 , 6,8 , 9 , 2 0 , 27 ,3 2 ,3 4 1 .5 V
9 ,3 4 V TT _ ME M
3 , 9 , 1 1,1 2 ,1 3, 14 , 1 5 , 16 , 1 7 , 1 8, 1 9 ,2 0 ,23 , 2 4 , 25 , 2 6 , 2 8, 2 9 , 3 0 , 31 ,3 2 ,3 7 3 .3 VS
1. 5V
C4 5 C 42 C 41 C8 1 C 36 C 85 C3 5 C3 8 C 75 C4 3
0. 1u _ 1 0V _ X 5 R_ 0 4 0 . 1 u _ 10 V _ X 5R _ 04 0 . 1 u_ 1 0 V _ X5 R _0 4 0 . 1u _ 1 0V _X 5 R _ 0 4 0 . 1 u _ 10 V _ X 5R _ 04 0 .1 u_ 1 0 V _ X5 R _0 4 0 . 1u _ 1 0V _X 5 R _ 0 4 0. 1 u _ 10 V _ X 5 R _ 04 0 . 1 u _1 0 V _ X5 R _0 4 0 . 1u _ 1 0V _X 5 R_ 0 4
DDR3 SO-DIMM_1 B - 11
Schematic Diagrams
LVDS, Inverter
3 . 3V S
PANEL CONNECTOR 30Pin & 40 Pin Co-layout--LED

30Pin R 10 R9
VIN V IN
L2
V LE D
2 . 2K _ 0 4 2.2 K _ 0 4
PANEL.
* H C B 16 0 8K F -12 1 T2 5 J_ L C D 2
2A 2A
. 1
3 1 2
2
4
P _ DDC _ DA T A
P _ DDC _ CL K
PLVDD
3 4 HI LVDS:3.3V 3A PLVDD_SEL
C 8 13 P L V D D _S E L 5 6
8 7 5 6 8 B R IG H T N E S S HI ? 5V 3A
Q4 7 3 7 9 7 8 10 B o ard ID _R R 7 2 0 *0 _ 0 4 HI eDP:3.3V 3A
2 6 11 9 10 12 I N V _ B L ON B o ard ID 13
LOW eDP;5V 3A LOW ? 3.3V 3A
* 0. 1 u _5 0 V _ Y 5 V _ 06 C 5 17
P 2 0 0 3E V G 1 5 13 11 12 14
L V D S -L C L K N 15 13 14 16 L V D S -L 2 N 1229 D02(W240HU)
0. 1 u _5 0 V _ Y 5V _0 6
C 8 1 2 0 .2 2u _ 50 V _ Y 5 V _ 0 6 L V D S -L C L K P 17 15 16 18 L V D S -L 2 P
17 18
4
19 20 3 .3 VS
L V D S -L 1 N 21 19 20 22 E MB _ H P D P LV D D
L V D S -L 1 P 23 21 22 24
R6 0 7 1A
25 23 24 26 3 .3 VS R 5 79 0 _0 6
1 M_ 0 4 L V D S -L 0 N 27 25 26 28 5V S
29 27 28 30
3A
L V D S -L 0 P
R 72 7 1 00 K _ 0 4 29 30 3 . 3V S Q4 3 Q4 1 P LV D D
3A 3A
D02A R3.3A_2_18.DSN 8 72 1 6 -30 0 6 R5 8 0 * A O3 4 1 5 >100 mil A O3 4 15 >100mil
C 5 18 C 51 9 C5 2 0 S D S D
D
C5 8 7 Q5 3 R 5 81 *1 0 0K _ 0 4 >100 mil
2 N 7 0 02 W 4 . 7 u_ 2 5 V _X 5 R _ 0 8 C5 4 2 C 5 43 C 54 5 R5 7 7 R 6 08
*0 . 1 u_ 5 0V _Y 5V _ 0 6 G NB _ E N A V DD 0 . 1 u _1 6 V _ Y 5 V _ 04 0 .1u _ 1 6V _ Y 5 V _ 0 4 *1 00 K _ 0 4
G
C 54 4 *0 . 1 u _1 6 V _ Y 5 V _ 04
* 10 u _ 10 V _ Y 5 V _0 8
1 0 0 _1 % _ 04
0. 1u _ 16 V _ Y 5 V _ 04
0. 1 u _1 6 V _ Y 5 V _0 4
D
S
* 10 0 K _0 4
5 VS
Sheet 11 of 46
Q4 4 Q4 5 R 2 44
3 .3V P LV D D _ S E L G *M TN 70 0 2 Z H S 3 * A O3 4 1 5 1228 D02
S D 1.5 M_ 0 4
40Pin
S
VL ED >100 mil R 57 8 3 3 0 K _0 4
LVDS, Inverter
D
R7 2 1
G
*1 0 K _ 04 V LE D Q4 2
R6 4 6 D02A J _ LC D 1 G MT N 7 0 02 Z H S 3
1 6, 28 N B _E N A V D D
*2 0 0 _0 6 2A * 87 2 16 -4 0 06
S
P _ DD C_ DA T A R3 7 0
1 2 P _ DD C_ CL K P _ DD C_ DA T A 1 6
6 Q 51 A P _ DD C_ CL K 1 6
D
3 Q 51 B D *M TD N 7 0 02 Z H S 6R P L V DD_ S E L 3 4 1 00 K _ 0 4
* MT D N 7 0 0 2Z H S 6 R 5 6 B RIG HT NE S S
D Q 49
G 2 7 8 B o ard I D _R B R IGH TN E S S 2 8 G M T N 7 00 2 Z H S 3
5 G V L E D_ E N # S 9 10 I N V _ B L ON 1230 D02
S
S 1 11 12
4 L V D S -L C L K N 13 14 L V D S -L 2 N
16 L V D S -LC LK N L V D S -L C L K P 15 16 L V D S -L 2 P L V D S -L 2 N 1 6
W243 1117 ? ? 3.2 16 L V D S -LC LK P 17 18 L V D S -L 2 P 1 6
L V D S -L 1 N 19 20 E MB _ H P D 3 . 3V S
16 LV D S -L 1N E M B _H P D 2 1228 D02
L V D S -L 1 P 21 22
16 LV D S -L 1P 23 24 1A
P LV D D R N1 2 8 1 0 _8 P 4 R _ 0 4 MU X_ 2 N
25 26 16 L V D S -U 2N 7 2
L V D S -L 0 N 3A MU X_ 2 P
16 L V D S -L0 N L V D S -L 0 P 27 28 16 L V D S -U 2 P 6 3 MU X_ 1 N
16 LV D S -L 0P 29 30 16 L V D S -U 1 N 5 4 MU X_ 1 P
31 32 MU X_ 2 N 16 L V D S -U 1 P R N1 3 8 1 0 _8 P 4 R _ 0 4 MU X_ 0 N
16 LV D S -U C LK N 33 34 16 L V D S -U 0N 7 2
MU X_ 2 P MU X_ 0 P
16 LV D S -U C LK P M U X _ 1N 35 36 MU X_ 0 N 16 L V D S -U 0 P 6 3
37 38 5 4
M U X _ 1P MU X_ 0 P
G1
G2
39 40 R N1 4 8 1 *0 _ 8P 4 R _0 4
2 D P _ TX N 1 7 2
2 DP _ T X P 1 D P _T X P 2 2
G1
G2
6 3
2 D P _ TX N 0 5 4 D P _ TX N 2 2
2 DP _ T X P 0
R N1 5 8 1 *0 _ 8P 4 R _0 4
2 D P _ A UX N 7 2 D P _T X P 3 2
2 D P _ A U XP 6 3 D P _ TX N 3 2
? 4 0p in con ne cto r? , ? ? 30p in con ne cto r? ? ? ? p in pad ? ? ? ?
5 4
INVERTER CONNECTOR
3 . 3V
3 .3 V 3 .3 V
R2 6 8 *1 0 0 K _0 4
U1 6 A
14
74 L V C 0 8 P W U 1 6B C2 1 4
14
B K L_ E N 1 74 L V C 0 8 P W
28 B K L_ E N 3 4 *0 . 1 u _1 0 V _ Y 5 V _ 04
BL O N 2 6
16 B LO N 5
7
R2 6 7 1 0 0K _ 0 4
7
U 16 C
11/18
14
7 4 LV C 0 8P W
9
18 S B _ B L ON 8 IN V _ B L ON 12 ,1 9, 20 , 2 6,3 0 ,3 1, 3 2 , 3 7,3 8 5 VS
R2 8 1 0_ 0 4
3 .3 V 10 31 ,3 2, 33 , 3 4,3 5 ,3 6, 3 7 , 3 8,3 9 VIN
2 , 3 , 8 , 13 , 1 5 ,17 , 1 9 , 20 ,2 2, 23 , 2 7,2 9 ,3 1, 3 2 , 3 4,3 6 3 . 3V
R 26 6 *1 00 K _ 0 4 3, 9 , 1 0 , 12 ,1 3 , 14 , 1 5 , 16 , 1 7 , 18 , 1 9 ,20 , 2 3 , 24 ,2 5, 26 , 2 8,2 9 ,3 0, 3 1 , 3 2,3 7 3 . 3V S
U 1 6D R 2 80 C2 1 3
3 2 , 3 3,3 5 SYS1 5 V
14
7
74 L V C 0 8 P W
12 1 M _0 4 0 . 1 u_ 1 6V _ Y 5V _ 0 4
28 ,3 1 LID _ S W # 11
13
15 , 2 8 , 37 A L L _S Y S _ P W R G D
7
B - 12 LVDS, Inverter
Schematic Diagrams
HDMI, CRT
HDMI PORT 5V S _H D MI
For ESD
FOR INTEL GRAPHIC
C
A
A
R 40 3 R 4 04
U5
2 2. K _0 4
2. 2K _ 04
5V S _H D MI RD3 RD2 RD1
AC
AC
AC
39 22 H D MI B _D A TA 2 P 5 VS * BA V 99 R EC T I FI E R *B A V 99 R EC T I FI E R
16 H D MI B _ D 2B P 38 I N _ D 1+ OU T _D 1 + 23
16 H D MI B _ D 2B N H D MI B _D A TA 2 N *B A V9 9 R E C TI F I E R
I N _ D 1- OU T_ D 1- R 40 0 1_0 4 5V S _H D MI _ I N R 40 1 1 _0 4 H D MI B_ E XT 1_S C L
42 19 H D MI B _D A TA 1 P
16 H D MI B _ D 1B P 41 I N _ D 2+ OU T _D 2 + 20 H D MI B _D A TA 1 N H D MI B_ E XT 1_S D A
16 H D MI B _ D 1B N I N _ D 2- OU T_ D 2-
45 16 H D MI B _D A TA 0 P J _H D MI 1 H D MI _H P D -C
16 H D MI B _ D 0B P 44 I N _ D 3+ OU T _D 3 + 17 H D MI B _D A TA 0 N
16 H D MI B _ D 0B N I N _ D 3- OU T_ D 3- C 34 8 C 3 49
16 H D MI B _ C LK B P 48 13 H D MI B _C L OC KP
47 I N _ D 4+ OU T _D 4 + 14 H D MI B _C L OC KN 10 u_ 10 V_ Y 5V _ 08 1 0u _10 V _Y 5 V_ 08
16 H D MI B _ C LK B N I N _ D 4- OU T_ D 4- 19 H D MI _H P D -C
H D MI_ C TR L C LK 9 28 H D MI B _E XT 1_ SC L 18 H OT PL U G D E TE C T
1 6 H D MI _C T R LC L K 8 S CL S C L_ S IN K 29 + 5V 17
16 H D MI_ C TR L D A TA H D MI_ C TR L D A TA H D MI B _E XT 1_ SD A
S DA S D A_ S IN K H D MI B _E XT 1_ SD A 16 D D C C/ E C GN D
S DA
16 P OR T C _H P D R 39 8 *1 0m li _0 4 M_ P OR TB _H P D # _R 7 HP D H PD _ S IN K
30 H D MI _H P D -C R5 5 10 0K _0 4 S CL
15 H D MI B_ E XT1 _S C L
14
R 61 * 4. 7K _ 04 25 2 R ES E R V ED 13 H D M I_ C E C
3 .3 V S R 68 * 0_0 4 OE # V C C [ 1] 11 3 . 3V S TMD S _ C LOC K # 12 CE C
D C C _ EN # 32 V C C [ 2] 15 C 33 8 C 33 9 T MD S C LOC K - 11 R 70 *0 _0 4
? ? ? 10 DCC_ E N# V C C [ 3] 21 TMD S _ C LOC K 10 C L K S H I E LD
R T _E N # V C C [ 4] 26 0. 1u _1 6V _Y 5 V _0 4 0. 1 u_1 6V _ Y 5V _0 4 T MD S C LOC K + 9 T MD S _D A TA 0# 4 3 H D MI B_ D AT A 0N
P C0 3 V C C [ 5] 33 8 TMD S D A TA 0- L10
P C1 4 P C0 V C C [ 6] 40 S H I E LD 0 7 T MD S _D A TA 0 1 2 H D MI B _D A TA 0P
10/28 6 P C1 V C C [ 7] 46 6 T MD S D A T A0 +
R 39 6 4 . 02 K_ 1% _04 TMD S _ D AT A 1# *WC M2 01 2F 2S -S H OR T
RE X T V C C [ 8] T MD S D AT A 1- 5 R 69 *0 _0 4
1 TMD S _ D AT A 1 4 S H I EL D 1
GN D [ 1] T MD S D AT A 1+ R 72 *0 _0 4
3. 3V S R5 3 * 4. 7K _ 04 34 5 C 31 C 34 0 3 T MD S _D A TA 2# 4 3 H D MI B_ D AT A 2N
R5 1 * 4. 7K _ 04 35 OE _ 1 GN D [ 2] 12 2 TMD S D A TA 2- L12
QE _ 2 GN D [ 3] S H I E LD 2
? ? ? GN D [ 4]
GN D [ 5]
GN D [ 6]
18
24
27
31
0. 1u _1 6V _Y 5 V _0 4 0. 1 u_1 6V _ Y 5V _0 4
T MD S D A T A2 +
1 T MD S _D A TA 2 1 2
*WC M2 01 2F 2S -S H OR T
R 71 *0 _0 4
H D MI B _D A TA 2P
Sheet 12 of 46
GN D 2 GND
GN D 3 GND
G ND4 GND
GND
GN D [ 7] 36
49
GN D
GN D [ 8]
GN D [ 9]
37
43 C 30 HDMI, CRT
GN D 1
GN D 1[ 0]
S N 75 D P1 39 0. 1u _1 6V _Y 5 V _0 4 R 64 *0 _0 4
P I N 49 = GN D
H D MI B _C LOC K P 4 3 T MD S_ C LOC K C 1 28 17 -11 9A 5-L
L9
H D MI B _C LOC K N 1 2 T MD S_ C LOC K #
PS8101 (6-03-08101-032) PIN TO PIN *W C M20 12F 2 S-S H OR T
R 65 *0 _0 4
R 66 *0 _0 4
3 . 3V S R5 4 4. 7K _ 04 D C C _E N #
H D MI B _D AT A1 P 4 3 T MD S_ D A TA 1
R5 2 4. 7K _ 04 PC 0 L1 1
H D MI B _D AT A1 N 1 2 T MD S_ D A TA 1#
R 3 95 *4. 7 K_ 04 PC 1 *W C M20 12F 2 S-S H OR T
? ? ?
R 67 *0 _0 4
3. 3 VS 5V S
J _C R T 1 6- 20-14X30-015
6-19-31001-264 1 08 A H 15 FS T0 4A 1 C C
CRT PORT R ED 1
10/29
1
2
3
4
9
L7 F C M1 005 MF -600 T0 1 L8 F C M1 005 MF -600 T0 1 2
16 D A C _R E D . . GR N 241 0 mi l
R N1 16 D A C _GR EE N L6 . F C M1 005 MF -600 T0 1 L5 . F C M1 005 MF -600 T0 1
2. 2 K_ 8P 4R _ 04 L4 . F C M1 005 MF -600 T0 1 L3 . F C M1 005 MF -600 T0 1 BL U E 3
16 D A C _B L U E
8
7
6
5
11
1 50 _1% _0 4
1 0p_ 50 V _N P O _0 4
22 p_ 50 V_ N P O _0 4
1 0p _5 0V _N P O _ 04
2 2p _5 0V _N P O _ 04
2 2p _50 V _N P O _0 4
1 0p _50 V _N P O _0 4
4
15 0_ 1% _04
15 0_1 %_ 04
10 p_ 50 V_ N PO _04
10 p_ 50 V_ N PO _04
10p _5 0V _N P O _ 04
12 D D C D A TA
U 33 5
10 9 D D C D A TA 13 HS Y NC
1 6 D A C _D D C A D A TA D D C _ IN 1 D D C _ OU T1 6
11 12 D D C LK 14 V SY N C
1 6 D A C _D D C A C L K D D C _ IN 2 D D C _ OU T2 7
1 6 D A C _H S Y N C
13
S Y N C _I N 1 SY N C _ OU T1
14 C R T_ H SY N C R 3 72 33 _0 4 HS Y NC 1207 8
15 D D C LK
R1 5
C1 3
C1 7
C 12
C1 6
C1 9
15 16 C R T_ VS Y N C R 3 73 33 _0 4 V SY N C
R 14
R 13
C 21
C 20
C 14
C 18
C 15 10 00p _5 0V _X 7 R _0 4
C 1 1 2 20 p_ 50V _ N PO _ 04
C 9 22 0p _5 0V _N P O _ 04
C 7 1 00 0p _5 0V _X 7 R _04
1 6 D A C _V S Y N C S Y N C _I N 2 SY N C _ OU T2
GND1
GND2
1 3 B LU E
5 VS V C C _S Y N C VI D E O_1
2 4 GR N
3 3. V S V C C _V I D E O VI D E O_2
7 5 RE D
3 . 3V S V C C _D D C VI D E O_3
8 6
BYP GN D
0. 22 u_ 10 V_ Y 5V _0 4
0 . 22 u_1 0V _ Y5 V _04
0. 2 2u _1 0V _Y 5V _ 04
TP D 7S 01 9
C 31 3
C 3 11
C 312
3 , 9, 1 0, 11 , 13 1, 4, 1 5, 16 , 17 , 18, 1 9, 2 0, 23 , 24 ,2 5, 2 6, 28 , 29 , 30, 3 1, 3 2, 37 3. 3V S
11 1, 9, 2 0, 26 , 30 , 31, 3 2, 3 7, 38 5V S
HDMI, CRT B - 13
Schematic Diagrams
PCH/ HDA, JTAG. SATA

RT C V CC
VDD 3
20mil D 17
B A T5 4 C S 3
1 A
C 3
20mil
C 4 66 1 u_ 6 . 3 V _ X5 R _0 6 C4 6 8
CougarPoint - M 3 .3 V S
R T C_ V B A T _ 1
R 47 6
2 A
11/ 05
R4 7 7
2 0K _1 % _ 04 R TC CL EA R
1 8 p _5 0 V _ N P O _ 04
(HDA,JTAG,SATA) S A T A _L E D # R 4 4 5
S E RIR Q R1 6 8
*1 0 K _0 4
10 K _ 0 4
2
1
2
1
X1 2 GP I O 21 R1 8 3 10 K _ 0 4
1 K_ 0 4 X1 3 R4 7 8
U3 7 A
*3 2 . 7 68 K H z
C4 6 5 JO P E N 1 MC -3 06 _ 3 2. 7 6 8 K H z
10 M _0 4
A2 0 C 38
3
4
3
4
J_ R TC 1 1 u _6 . 3 V _ X5 R _0 6 *O P E N _ 1 0m i l -1 MM C4 6 3 R T C _X 1
R T C_ V BA T 1 R TC X 1 FW H 0 / L AD0 A3 8 L P C _ A D 0 2 3, 2 8
1 8 p _5 0 V _ N P O _ 04 L P C _ A D 1 2 3, 2 8
1 C2 0 FW H 1 / L AD1 B3 7
2
10mil RT C_ X 2
LPC
R TC X 2 FW H 2 / L AD2 C 37 L P C _ A D 2 2 3, 2 8
J_RTC1 2 R2 3 7
Zo= 50O? 5 % R T C _R S T # D2 0 FW H 3 / L AD3 L P C _ A D 3 2 3, 2 8
R2 3 0
R TC R S T # D 36 3. 3 V S
2 0K _1 % _ 04 L P C _ F R A ME # 2 3 , 2 8
85 2 0 5- 02 7 0 1 S R T C _R S T # G2 2 F W H 4 / L F R A ME # 1 0 K _0 4
S R TC R S T # E3 6
K2 2 L D R Q0 # K3 6
RTC
1 2 R 2 36 C2 0 6 S M_ I N TR U D E R # B oa rd I D R 2 29
I N TR U D E R # LD R Q 1# / G P I O2 3
*1 0K _0 4
1 M _0 4 1 u _6 . 3 V _ X5 R _0 6 R2 3 5 33 0 K _ 04 P CH _ INT V RM E N C1 7 V5
RT CVC C I N TV R ME N S E R IRQ S ER IRQ 2 3, 2 8 B o ard I D 11
AM 3
S A TA 0 R XN S A T A R XN 0 26
H DA_ BIT CL K _ R N3 4 AM 1
H DA _ B CL K S A T A 0 RX P AP7 S A T A R XP 0 26
SATA HDD
S A T A 0 T XN S AT AT XN0 26
SATA 6G
R2 2 4 1K _ 0 4 H D A _ S Y N C _R L3 4 AP5
3. 3 V S NO REBOOT STRAP 3 . 3A _1 . 5 A _ H D A _ I O H DA _ S Y N C S A TA 0T X P SAT AT XP0 26
H DA_ SP KR T1 0 A M 10
30 H DA_ SP KR SPKR S A TA 1 R XN AM 8
R 19 5 *1 K _ 04 HD A _ S P K R H D A _ R S T# _ R K3 4 S A T A 1 RX P AP1 1
H DA _ RS T # S A T A 1 T XN AP1 0
S A TA 1T X P
NO R EB OO T ST RAP : HD A_ SP KR Hi gh E na bl e
E3 4 AD 7
30 H DA_ SD IN0 H DA _ S DI N0 S A TA 2 R XN S A T A R XN 2 26
Sheet 13 of 46 3. 3 V S iTPM ENABLE/DISABLE

HD A _ S DIN 1 G3 4
C3 4
H DA _ S DI N1
S A T A 2 RX P
S A T A 2 T XN
S A TA 2T X P
AD
AH
AH
5
5
4
S A T A R XP 2 2 6
S A T A T X N2 2 6
S A T A T X P 2 26
SATA ODD
PCH/ HDA, JTAG. W243 1117 H DA _ S DI N2 AB8
10/29
IHDA
R 16 7 *1 K _ 04 SP I_ SI R2 6 9 *1 K _ 0 4 A3 4 S A TA 3 R XN AB1 0
3. 3 A _ 1 . 5 A _H D A _I O H DA _ S DI N3 S A T A 3 RX P AF3
R B 7 5 1 S -4 0C 2 D 12 S A T A 3 T XN AF1
TP M FU NC TI ON :SP I_ SI H ig h Ena bl e
SATA 28 M E_ W E
R 4 68 * 2 8m i l _0 6 A C H D A _ S D OU T_ R A3 6
H DA _ S DO
S A TA 3T X P
Y 7
SATA
S A TA 4 R XN Y 5
R 53 8 *1 0 K _0 4 C3 6 S A T A 4 RX P AD 3
3. 3V H D A _ D O C K _ E N # / GP I O 33 S A T A 4 T XN AD 1
Flash Descriptor Security Overide R 53 9 0_ 0 4 N3 2 S A TA 4T X P
27 U S B 3 0 _S M I # H D A _ D O C K _ R S T# / G P I O1 3 Y 3
1201 S A TA 5 R XN Y 1
HDA_SDOUT HIGH = Enable Flash Descriptor S A T A 5 RX P AB3
LOW = Disable Security Overide P C H _J T A G_ T C K _B U F J3 S A T A 5 T XN AB1
J T A G_ T C K S A TA 5T X P
Low = Disabled-(Default) P C H _J T A G_ T MS H7 Y 11 S A TA I C O MP R 1 72 3 7 . 4 _ 1% _ 0 4
J T A G_ T MS S A T A I C O MP O 1 .0 5 VS
High = Enabled
JTAG
P C H _J T A G_ T D I K5 Y 10
J T A G_ T D I S A T A I C OM P I
P C H _J T A G_ T D O H1
3. 3 V _ M 11/18 J T A G_ T D O AB1 2 S A TA 3C OM P R 1 71 4 9 . 9 _ 1% _ 0 4
NC1 BIOS ROM 11/19

S A T A 3 R C O MP O
S A T A 3C OM P I
AB1 3
1 .0 5 VS
NC_ 0 4 SPI_* = 1.5"~6.5"

C 22 1 S PI_ SC L K R 44 4 0_ 0 4 S P I _S C L K _ R T3 AH 1 RB IAS _ S AT A3 R 4 32 7 5 0 _1 % _ 0 4
S P I _ C LK S AT A3 R B IA S
0 . 1 u_ 1 6 V _ Y 5 V _ 04
S PI_ C S0 # R 17 6 0_ 0 4 S P I _C S 0 # _R Y1 4
U 17
32Mbit S P I _ C S 0#
3 .3 VS _ S PI 8 5 SP I_ SI S PI_ C S1 # R 17 7 0_ 0 4 S P I _C S 1 # _R T1
VD D SI S P I _ C S 1# P3
SPI
S A T A _ L E D#
R2 9 4 2 SP I_ SO S AT AL ED# S A T A _L E D # 29
3. 3 K _ 1 % _0 4 SO R444 R176 R177 R178 R441 RN16 S PI_ SI R 17 8 0_ 0 4 S P I _S I _R V4 V1 4 GP I O2 1
S P I _W P # 3 1 S P I_ CS 0 # S P I _ M OS I S A T A 0 GP / G P I O2 1
W P# CE # S PI_ SO R 44 1 3 3 _0 4 S P I _S O_ R U3 P1
R2 9 1 6 SP I_ SCL K W243HWQ X X X X X O S PI_ M ISO S A T A 1 GP / G P I O1 9 BBS_ BIT 0 1 7
3. 3 K _ 1 % _0 4 S CK
S P I _H OL D # 7
HO L D# VSS
4 W243HVQ O O O O O X C o ug a rP o in t _ R e v _ 1 p 0
M X2 5 L 32 0 6 E
P C B F o o t pri n t = M-S O P 8 B
W243HVQ 11/18
3. 3 V _ M V DD3 H D A _S D OU T _R 4 5
H D A _S Y N C _ R 3 6 H D A _ S D OU T 3 0
2 7 HD A _ S YN C 3 0
NC4 H D A _R S T #_ R
H D A _B I TC LK _R 1 8 H D A _R S T # 30
C2 2 6 H DA _ B IT CL K 3 0
NC_ 0 4 0. 1 u _ 16 V _ Y 5V _ 0 4
R2 3 8 R 21 8 R 22 3 3 3_ 8 P 4 R _ 0 4
U 18 32Mbit RN 1 8
1 5 , 19 , 2 5 , 2 6, 3 2 3 . 3 V _M
2 0 3 . 3A _1 . 5 A _ H D A _I O
3 .3 VS _ S PI 8 5 SP I_ SI 2 1 0_ 1 % _0 6 2 1 0_ 1 % _0 6 2 1 0_ 1 % _ 06
VD D SI 1 5 ,2 0 R T CV C C
2 SP I_ SO P C H _ J T A G_ T MS 1 1 , 1 2, 1 9 , 2 0 , 26 , 3 0 , 31 , 3 2 , 3 7, 3 8 5 V S
R2 9 5
3. 3 K _ 1 % _0 4 SO P C H _ J T A G_ T D I 1 4 , 15 , 1 7 , 18 , 2 0 , 2 2, 2 3 , 2 4 , 25 , 2 8 , 32 , 3 3 , 3 5, 3 9 V D D 3
S P I _W P # 3 1 S P I_ CS 1 # P C H _ J T A G_ T D O 2 , 3 , 8 , 11 , 1 5 , 17 , 1 9 , 2 0, 2 2 , 2 3 , 27 , 2 9 , 31 , 3 2 , 3 4, 3 6 3 . 3 V
W P# CE # 11/19 3 , 9 , 10 , 1 1 , 1 2, 1 4 , 1 5, 1 6 , 1 7 , 18 , 1 9 , 20 , 2 3 , 2 4, 2 5 , 2 6 , 28 , 2 9 , 30 , 3 1 , 3 2, 3 7 3 . 3 V S
1 4 , 15 , 1 9 , 2 0, 3 2 1 . 0 5V S
R2 9 6 6 SP I_ SCL K
3. 3 K _ 1 % _0 4 S CK
S P I _H OL D # 7 4 R4 5 9 R 21 1 R 20 9 RN 1 6
HO L D# VSS *0 _ 8 P 4 R _ 04
M X2 5 L 32 0 6 E 10 0 _ 1% _ 0 4 1 0 0_ 1 % _0 4 1 0 0_ 1 % _ 04 S P I _ S C LK _R 8 1
H S P I_ S CL K 2 8
P C B F oo t p ri nt = M -S OP 8 B SP I_ SI_ R 7 2
6 3 H S P I _ MS I 2 8
S P I _ S O _R H S P I _ MS O 2 8
S P I _ C S 0# _ R 5 4
W243HVQ H SP I_ CE# 2 8
11/19 R 4 58 5 1 _0 4 P C H _ J T A G_ T C K _ B U F
B - 14 PCH/ HDA, JTAG. SATA

Schematic Diagrams
PCH/ PCI-E, SMBUS, CLK

11/19 V DD 3
CougarPoint - M (PCI-E,SMBUS,CLK) SM B _ CL K 8
7
RN 9
2. 2K _ 8 P 4 R _0 4
1
2
SM B _ D A TA
SM L 0 _D A T A 6 3
SM L 0 _C L K 5 4
U 3 7B S M C _C P U _T H E R M R 24 9 2 .2 K _ 0 4
S M D _C P U _T H E R M R 25 6 2 .2 K _ 0 4
T 71 P CIE _R X N 1 B G3 4 D R A MR S T _C N T R L R 48 2 1 K_ 0 4
T 72 P CIE _R X P 1 B J3 4 P E RN 1 E1 2 B T_ S B D #
P CIE _T X N 1 AV3 2 P E RP 1 S MB A L E R T # / GP I O 1 1 BT_ SBD # 2 2 BT_ SBD #
T 12 R 24 8 1 0 K_ 0 4
T 13 P CIE _T X P 1 AU3 2 P E T N1 H1 4 S MB _ C LK L P D _ S P I_ INT R # R 25 0 1 0 K_ 0 4
P ETP1 S M B C LK S MB _C L K 9 , 1 0
P E G_ B _ C L K R Q# R 48 1 * 10 K _ 0 4
BE3 4 C9 S MB _ D A T A P C IE C L K RQ 0 # R 54 0 * 10 K _ 0 4
27 P C I E _ R XN 2 _ USB3 0 BF 3 4 P E RN 2 S M B D A TA S MB _D A T A 9 , 1 0
P C IE C L K RQ 7 # R 54 1 * 10 K _ 0 4
27 P C I E _ R XP 2_ U S B 3 0 P C I E _T X N 2_ C BB3 2 P E RP 2
C1 3 1 0 . 1 u_ 1 0 V _ X 7R _ 0 4
27 P C I E _ T XN 2 _ USB3 0 C1 3 2 0 . 1 u_ 1 0 V _ X 7R _ 0 4 P C I E _T X P 2 _ C AY3 2 P E T N2 P E G_ C L K R E Q # R 21 9 * 10 K _ 0 4
27 P C I E _ T XP 2_ U S B 3 0 P ETP2
SMBUS
A1 2 D R A MR S T _ C N TR L 3 G _B _C L K R Q # R 26 2 * 10 K _ 0 4
B G3 6 S M L0 A L E R T # / GP I O 6 0 D R A MR S T _ C N T R L 3 , 8
22 P C I E _ R XN 3 _ W L A N B J3 6 P E RN 3 C8 3. 3 V S
S ML 0 _ C L K
22 P C I E _ R XP 3_ W L A N P C I E _T X N 3_ C AV3 4 P E RP 3 S M L0 C LK S ML 0 _ C L K 2 5
C1 4 2 0 . 1 u_ 1 0 V _ X 7R _ 0 4
22 P C I E _ T X N 3 _ W L A N C1 4 3 0 . 1 u_ 1 0 V _ X 7R _ 0 4 P C I E _T X P 3 _ C AU3 4 P E T N3 G1 2 S ML 0 _ D A T A P C IE C L K RQ 1 # R 54 3 * 10 K _ 0 4
2 2 P C I E _ T XP 3_ W L A N P ETP3 S ML 0 D A TA S ML 0 _ D A T A 25
D GP U _ P R S N T # R 46 3 * 10 K _ 0 4
BF 3 6 P C IE C L K RQ 2 # R 16 9 * 10 K _ 0 4
24 P C I E _ R X N 4_ G LA N BE3 6 P E RN 4
24 P C I E _ R X P 4 _ GL A N P C I E _T X N 4_ C AY3 4 P E RP 4 C1 3 LP D _ S P I _ I N TR #
C1 3 0 0 . 1 u_ 1 0 V _ X 7R _ 0 4
24 P C I E _ T XN 4 _G L A N C1 2 9 0 . 1 u_ 1 0 V _ X 7R _ 0 4 P C I E _T X P 4 _ C BB3 4 P E T N4 S ML 1 A L E R T # / P C H H O T # / GP I O 7 4
24 P C I E _T X P 4 _ GL A N P ETP4 E1 4 S MC _ C P U _ TH E R M
S ML 1 C LK / GP I O 5 8 S MC _ C P U _ T H E R M 2 , 2 8
PCI-E*
B G3 7
BH3 7 P E RN 5 M1 6 S MD _ C P U _ TH E R M
AY3 6 P E RP 5 S ML 1 D A TA / GP I O 7 5 S MD _ C P U _ T H E R M 2 , 2 8
BB3 6 P E T N5
P ETP5
B J3 8 C L K _ B UF _ C P Y C L K _ N R 1 32 1 0 K_ 0 4
11/19 25
25
P C I E _ R X N 6_ I G L A N
P C I E _ R X P 6 _ I GL A N
B G3 8 P
P
E RN 6
E RP 6
C L K _ B UF _ C P Y C L K _ P R 1 34 1 0 K_ 0 4
Controller
C1 7 2 0 . 1 u_ 1 0 V _ X 7R _ 0 4 P C I E _T X N 6_ C AU3 6 M7 CL _ CL K 1 C L K _ B U F _ D OT 9 6 _ N R 2 32 1 0 K_ 0 4
CL _ CL K 1 2 2
25
25
P C I E _ T XN 6 _I GL A N
P C I E _T X P 6 _ I GL A N
C1 7 5 0 . 1 u_ 1 0 V _ X 7R _ 0 4 P C I E _T X P 6 _ C AV3 6 P
P
E T N6
ETP6
C L _C L K 1 C L K _ B U F _ D OT 9 6 _ P R 2 40 1 0 K_ 0 4
Sheet 14 of 46
Link
B G4 0 T11 CL _ DA T A 1 R N1 9
P E RN 7 C L_ D A T A 1 CL _ DA T A 1 2 2
B J4 0 1 0K _8 P 4 R _0 4
PCI-E x1 Usage AY4 0
BB4 0
P E RP 7
P E T N7
P ETP7 C L _ RS T 1 #
P1 0 CL _ RS T # 1
CL _ RS T # 1 2 2
C L K _ P C I E _I C H
C L K _ P C I E _I C H #
C L K_ SAT A#
8
7
6
1
2
3
PCH/ PCI-E,
Lane 1 X
Lane
Lane
2
3
USB3.0
WLAN
BE3 8
BC3 8
AW 3 8
P
P
P
E RN 8
E RP 8
E T N8
C L K_ SAT A 5 4
SMBUS, CLK
AY3 8 P E G_ C L K R E Q # R 21 2 * 10 K _ 0 4
Lane 4 CARD READER P ETP8 P C IE C L K RQ 2 # R 17 5 1 0 K_ 0 4
M1 0 P E G _ C L K R E Q# C L K _ B UF _ R E F 1 4 R 20 8 1 0 K_ 0 4
Lane 5 X Y4 0 P E G_ A _ C LK R Q # / GP I O 4 7 L A N _ C L K R E Q# R 23 9 * 10 K _ 0 4
Y3 9 C L K OU T _ P C I E 0 N IG L A N_ C L K RE Q # R 25 5 * 10 K _ 0 4
Lane 6 GLAN INTEL 82579 C L K OU T _ P C I E 0 P AB3 7
Lane 7 X J2 C L K OU T _P E G_ A _ N AB3 8
CLOCKS
P C I E C L K R Q0 #
P C I E C L K R Q 0 # / GP I O 7 3 C L K O U T _ P E G _A _P
Lane 8 X
AB4 9 AV2 2 1 00 MHz
AB4 7 C L K OU T _ P C I E 1 N C LK OU T_ D MI _ N A U 22 CL K_ EXP_ N 3
C L K OU T _ P C I E 1 P C L K OU T _ D M I _P CL K_ EXP_ P 3
P C I E C L K R Q1 # M1
P C I E C L K R Q 1 # / GP I O 1 8 A M 12 C LK _D P _ N _ R R 1 54 *1 0 m li _ 0 4 1 20 MHz
C L K OU T _ D P _ N A M 13 C L K _ DP _ N 3
C LK _D P _ P _ R R 1 50 *1 0 m li _ 0 4
AA4 8 C L K O U T _ D P _P C L K _ DP _ P 3
2 7 C LK _P C I E _ U S B 3 0# C L K OU T _ P C I E 2 N
AA4 7
2 7 C L K _ P C I E _ U S B 30 C L K OU T _ P C I E 2 P BF1 8 C LK _P C I E _ I C H # 1 00 MHz
P C I E C L K R Q2 # V1 0 C L K I N _ D MI _ N BE1 8 C LK _P C I E _ I C H
2 7 P C I E C L K R Q2 # P C I E C L K R Q 2 # / GP I O 2 0 C L K I N _ D M I _P
1 00 M Hz Y3 7 BJ 3 0 C LK _B U F _ C P Y C L K _ N
2 2 C LK _P C I E _ M I N I # Y3 6 C L K OU T _ P C I E 3 N C LK I N _ GN D 1 _ N B G 30 C LK _B U F _ C P Y C L K _ P
2 2 C L K _ P C I E _ MI N I C L K OU T _ P C I E 3 P C L K I N _ G N D 1 _P
A8
22 W LA N _ C L K R E Q# P C I E C L K R Q 3 # / GP I O 2 5 G2 4 C LK _B U F _ D OT 9 6_ N 9 6M H z
C L K I N _ D O T _9 6 N E2 4 C LK _B U F _ D OT 9 6_ P
Y4 3 C L K I N _ D OT _ 9 6P
2 5 C L K _ P C I E _ I GL A N # Y4 5 C L K OU T _ P C I E 4 N
25 C L K _ P C I E _ I G L A N C L K OU T _ P C I E 4 P AK7 C LK _S A T A # 10 0M H z
I GL A N _C L K R E Q# L1 2 C LK I N _ S A T A _ N AK5 C LK _S A T A
R 17 3 0_04
2 5 I GL A N _ C L K R E Q# P C I E C L K R Q 4 # / GP I O 2 6 C L K I N _S A TA _P * X 8A 02 5 0 0 0F G1 H _ 2 5 MH z
C 447 2 2 p _ 50 V _ N P O_ 0 4
10 0M H z V4 5 K4 5 C LK _B U F _ R E F 1 4 14 .3 18 M Hz
24 C L K _ P C I E _G L A N # V4 6 C L K OU T _ P C I E 5 N R E F CL K 1 4 IN
2 4 C L K _ P C I E _ GL A N C L K OU T _ P C I E 5 P
1
R4 3 8
33 MHz 1126
4
L A N _ C L K R E Q# L1 4 H4 5 X1 X1 1
P C I E C L K R Q 5 # / GP I O 4 4 C L K I N _ P C I LO OP B A C K CL K _ P C I_ F B 1 7
1124 change for layout F S X 5L _ 2 5 MH Z
3
AB4 2 V4 7
2
X T A L 25 _ I N 1 M _0 4
AB4 0 C L K OU T _ P E G_ B _ N X T A L 25 _ I N V4 9 X T A L 25 _ O U T C 444 2 2 p _ 50 V _ N P O_ 0 4
C L K OU T _ P E G_ B _ P X TA L2 5 _ OU T
O nly PC IECLKRQ [2 :1 ]# on PCH a re core w e l l pow e re d. P E G _B _C L K R Q # E6
P E G_ B _ C LK R Q # / GP I O 5 6
Al l othe r PC IECLKRQ x # a re suspe nd w e ll pow e red.
Y4 7 X C L K _ R C O MP R4 3 7 9 0. 9 _ 1 % _ 04
V4 0 X C LK _R C O MP 1. 0 5 V S
V4 2 C L K OU T _ P C I E 6 N 90.9-O ? % pullup to +VccIO 13 , 1 5 , 1 7 , 18 , 2 0 , 2 2 , 2 3, 2 4 , 2 5 , 2 8, 3 2 , 3 3 , 3 5, 3 9 VD D3
C L K OU T _ P C I E 6 P 2 , 3 , 8 , 11 , 1 3 , 1 5 , 17 , 1 9 , 2 0 , 2 2, 2 3 , 2 7 , 2 9, 3 1 , 3 2 , 3 4, 3 6 3 .3 V
3G _ B _ C L K R Q# T1 3 (1.05V, S0 rail)close to 3 , 9, 10 , 1 1 , 1 2, 13 , 1 5 , 1 6 , 17 , 1 8 , 1 9 , 20 , 2 3 , 2 4 , 2 5, 2 6 , 2 8 , 2 9, 3 0 , 3 1 , 3 2, 3 7 3 .3 V S
P C I E C L K R Q 6 # / GP I O 4 5 1 3, 1 5 , 1 9 , 2 0, 3 2 1 .0 5 V S
PCH
V3 8 K4 3
C L K OU T _ P C I E 7 N C L K OU T F L E X 0 / GP I O 6 4
FLEX CLOCKS
V3 7
C L K OU T _ P C I E 7 P F47
P C I E C L K R Q7 # K1 2 C L K OU T F L E X 1 / GP I O 6 5
P C I E C L K R Q 7 # / GP I O 4 6 H4 7
AK1 4 C L K OU T F L E X 2 / GP I O 6 6
AK1 3 C L K OU T _ I TP XD P _ N K4 9 D GP U _ P R S N T #
C L K OU T _ I TP XD P _ P C L K OU T F L E X 3 / GP I O 6 7
C o u g arP oi n t _ R e v _ 1 p 0
PCH/ PCI-E, SMBUS, CLK B - 15

Schematic Diagrams
PCH/ DMI, FDI, GPIO
3 .3 V
CougarPoint -M (DMI,FDI,GPIO)
A C_ P RE S E NT R 5 44 10 K _ 0 4 R 63 5 * 0 _0 4
U3 7 C
P CIE _ W A K E # R 4 86 10 K _ 0 4
V D D3
BC 2 4 B J1 4 P M_ S L P _ LA N # R 2 47 *1 0K _0 4
2 D MI _ R X N 0 BE2 0 D MI 0 R X N F DI_ R XN 0 AY1 4 F D I _ TX N 0 2
2 D MI _ R X N 1 BG 1 8 D MI 1 R X N F DI_ R XN 1 B E 14 F D I _ TX N 1 2
S W I# R 4 85 10 K _ 0 4 R 63 6 0_04
2 D MI _ R X N 2 BG 2 0 D MI 2 R X N F DI_ R XN 2 BH1 3 F D I _ TX N 2 2
2 D MI _ R X N 3 D MI 3 R X N F DI_ R XN 3 BC1 2 F D I _ TX N 3 2 P W R_ B T N# R 2 52 10 K _ 0 4
BE2 4 F DI_ R XN 4 B J1 2 F D I _ TX N 4 2 V DD3
2 D MI _ R X P 0 BC 2 0 D MI 0 R X P F DI_ R XN 5 B G1 0 F D I _ TX N 5 2 P M_ B A T L OW #
2 D MI _ R X P 1 F D I _ TX N 6 2 R 2 46 8. 2 K _ 0 4 1 1 26
BJ 1 8 D MI 1 R X P F DI_ R XN 6 B G9 1125
2 D MI _ R X P 2 BJ 2 0 D MI 2 R X P F DI_ R XN 7 F D I _ TX N 7 2 S U S _ P W R _A C K
2 D MI _ R X P 3 R 4 83 10 K _ 0 4
D MI 3 R X P B G1 4 SU SB#
AW 2 4 FD I_ RX P 0 B B 14 F D I _ TX P 0 2
2 D MI _ T XN 0 AW 2 0 D MI 0 T XN FD I_ RX P 1 B F 14 F D I _ TX P 1 2 3 . 3V S
S U S C#
2 D MI _ T XN 1 BB1 8 D MI 1 T XN FD I_ RX P 2 B G1 3 F D I _ TX P 2 2
2 D MI _ T XN 2 AV1 8 D MI 2 T XN FD I_ RX P 3 B E 12 F D I _ TX P 3 2 SL P_ S5 # P M_ C L K R U N # R 4 47 8. 2 K _ 0 4
2 D MI _ T XN 3 D MI 3 T XN FD I_ RX P 4 B G1 2 F D I _ TX P 4 2
D MI
FD I
AY 2 4 FD I_ RX P 5 B J1 0 F D I _ TX P 5 2 S L P _ M#
2 DM I _T X P 0 AY 2 0 D MI 0 T XP FD I_ RX P 6 BH9 F D I _ TX P 6 2
2 DM I _T X P 1 AY 1 8 D MI 1 T XP FD I_ RX P 7 F D I _ TX P 7 2
2 DM I _T X P 2 AU 1 8 D MI 2 T XP
S AM E TH E BI O S R O M S I D E
2 DM I _T X P 3 D MI 3 T XP A W 16
F D I _I N T F DI_ INT 2
R 42 3 4 9 . 9_ 1 % _0 4 D MI _ C OMP _ R BJ 2 4 A V 12
1 .0 5 V S D MI _ Z C O MP F D I _F S Y N C 0 F DI_ F SY N C0 2 R T CV CC
BG 2 5 BC1 0
D MI _ I R C OM P F D I _F S Y N C 1 F DI_ F SY N C1 2
R 42 2 7 5 0_ 1 % _0 4 D MI _ 2 R B I A S BH 2 1 A V 14 DS W O DV R E N R4 7 2 33 0 K _ 04
D MI 2 R B I A S F D I _ LS Y N C 0 F D I _ LS Y N C 0 2
B B 10 R4 7 9 *3 30 K _ 0 4
Sheet 15 of 46 F D I _ LS Y N C 1 F D I _ LS Y N C 1 2
A 18 DS W O DV RE N
PCH/ DMI, FDI, 1 1 24

28 S US _ A C K #
S U S_ A CK # R 6 71 * 0_ 0 4 D S W V R ME N
S ys te m Pow er M ana ge me nt
C 12 E 22 DSWODVREN - On Die DSW VR Enable
S U S _ P W R _A C K R 6 70 0 _ 04 S U S _A C K # _R D P W R OK R 2 57 *1 0m i l _0 4 RS M RST #
S U SA CK # D P W R OK
GPIO 3 . 3V S
R4 5 3 1 0 K _ 04 S Y S _R E S E T # K 3
S Y S_ RE S E T # W AKE#
B9 P CIE _ W A K E #
P C I E _ W A K E # 22 , 2 4, 2 7
HI Enabled (DEFAULT)
LOW Disabled
S Y S _P W R OK P1 2 N3 P M_ C L K R U N #
C 5 89 *0 . 1 u_ 1 6V _Y 5V _ 0 4 S Y S_ P W RO K C L K R U N # / GP I O3 2 P M _C L K R U N # 23
R2 7 0 10 K _ 0 4 P M_ P C H _P W R OK _ R L22 G8
2 8 P M_ P C H _P W R OK P W R OK S U S _ S TA T# / GP I O6 1 S 4 _S TA T E # 2 3
1229 D02
R2 1 3 *0 _0 4 P M_ MP W R OK L10
A P W R OK S U S C L K / GP I O6 2
N1 4 S US CL K
S U S C L K 28 0310-J
ME-POWROK
to EC 11 2 4 Add timing Adj VDD 3
B1 3 D1 0 S LP _ S 5 # 3 .3 V _ M
3 P M_ D R A M_ P W R G D D RAM P W RO K S L P _S 5# / GP I O6 3 S L P _ S 5# 2 8
R4 3 3 4 7 0K _ 0 4
32 S LP _M
R S MR S T# C 21 H4 S US C# R 62 2 R6 9 0 1129
28 RS M RS T # R S MR S T# SL P_ S4 # S U S C# 28 , 3 4
R2 6 1 1 0K _ 0 4 *1 0 K _0 4 1 0K _ 0 4
Q5 0
G
S US_ P W R_ AC K K1 6 F4 S US B # C5 9 4 MT N 7 00 2 Z H S 3 U 4 8A
14
2 8 S US _ P W R_ A CK S U S W A R N # / S U S P W R D N A C K / GP I O3 0 SL P_ S3 # SU SB# 6, 2 7 , 2 8, 3 2
7 4 L V C0 8 P W
3 30 0 p_ 5 0 V _X 7 R _ 0 4 S D 1
P W R _B T N # E2 0 G1 0 S L P _ M# 3 P M_ MP W R OK
28 P W R _B T N # P W RB T N# SL P_ A# S L P _ M# 28 , 3 2 2 R 62 3 0_04
H 20 G1 6
t o EC
A C_ P RE S E N T S LP _ S U S # 1 1 24 R 62 4
1 7, 28 A C _ P R E S E N T A C P R E S E N T / GP I O 31 S LP _ S U S # S L P _ S US # 2 8
7
3 5 1. 05 V _ LA N _ P W R G D C5 9 5 1 M_ 0 4
1u _ 6 . 3V _ X 5R _ 04
P M_ B A T LO W # E1 0 A P 14
B A T L OW # / G P I O7 2 P M S Y N CH H _P M _ S Y N C 3
0323-J
S W I# A1 0 K 14 P M_ S L P _L A N # add 0310-J
28 S W I# R I# S LP _ L A N # / GP I O2 9 P M _S L P _ L A N # 2 8, 3 2 , 3 5 Add
C o ug a rP o ni t _ R e v _ 1 p0
U 1 5 _3 . 3 V
U 1 5D 0 1 05 D 02
VD D3 3 .3 V U 1 5_ 3 . 3 V 7 4 L V C0 8 P W
1 12 9
14
R 62 5 * 0_ 0 4 P M _P C H _ P W R OK _ R
R 63 3 *0 _0 4 12
3 6 0 . 85 V S _ P W R GD 3 7 D E LA Y _ P W R G D 11 S Y S _ P W R _O K S Y S _ P W RO K
3 4 D D R 1 . 5 V _P W R GD R 62 7 0 _ 04
R 63 4 0_ 0 4 R6 2 6 0_ 0 4 13
2 8 P M _ P C H _ P W R OK
3, 3 4 1 . 8V S _ P W R GD U 1 5 _3 . 3 V U 1 5_ 3 . 3 V A L L_ S Y S _P W R GD R6 2 8 *0 _0 4 R2 5 3
7
U 15 _ 3. 3 V U 15 C
R 6 93 R 69 4 U 15 B 1228 D02 7 4 LV C 08 P W 1228 D02 10 K _ 0 4
U1 5 A 0_ 0 4 * 0_ 0 4 7 4 L V C 0 8P W
14
0224 74 L V C 0 8 P W
14
R6 9 2 0 _ 04 R 6 29 0 _ 04 9
3, 3 4 1 . 8V S _ P W R GD
14
4 8
1 6 A L L _S Y S _ P W R G D 1 1, 28 , 3 7
R6 9 1 * 0_ 0 4 R 6 30 0 _ 04 1 0
3 4 D D R 1. 5 V _ P W R G D 3 5 1 3, 1 9 , 2 5, 2 6 , 32 3 . 3 V _M
2 9, 1 0 , 34 V T T _M E M
R 54 6 R5 4 5
35 1 . 0 5V _ L A N _ P W R GD 1 3 , 20 R TC V C C
7
*2 K _ 0 4 1 0K _ 0 4 1 3, 1 4 , 1 9, 2 0 , 32 1 . 0 5V S
7
2 , 3, 8 , 1 1 , 13 , 1 7, 19 , 2 0, 2 2 , 2 3, 2 7 , 2 9, 3 1 , 3 2, 3 4 , 36 3 .3 V
7
3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 14 , 1 6 , 17 , 1 8 , 19 , 2 0, 23 , 2 4, 2 5 , 2 6, 2 8 , 2 9, 3 0 , 3 1, 3 2 , 37 3 .3 V S
R6 3 1 *0 _ 0 4 13 , 1 4 , 17 , 1 8, 20 , 2 2, 2 3 , 2 4, 2 5 , 2 8, 3 2 , 3 3, 3 5 , 39 V D D3
R 2 78 *1 0 K _0 4 P M_ MP W R OK
R 55 1
*1 K _ 0 4 1 207
ON R 6 32 0_ 0 4
1. 0 5 V S _ V TT _ E N 3 2 , 35
? ? SUSB# -->? ? 1.05VS_VTT? SUSPEND? ? ? ? ?
B - 16 PCH/ DMI, FDI, GPIO

Schematic Diagrams
PCH/ LVDS, DDI, CRT
CougarPoint -M
(LVDS,DDI,CRT)
U 37D
J47 AP4 3
11 B L ON M 45 L _ BKL TEN S D V O _ TV C L K I N N AP4 5
1 1, 28 NB _ E N A V DD L _ V D D_ E N S D V O _ T V C LK I N P
P4 5 AM 4 2
L _ BKL TC TL S D V O_ S T A L L N AM 4 0
T4 0 S D V O_ S TA LL P
Ver:1.0
11 P _D D C _ C LK K4 7 L _ D DC _ CL K AP3 9
pull up 2.2K 1 1 P _ D D C _ D A TA L _ D DC _ DA T A S D V O _I N T N AP4 0
T4 5 S DV O _ INT P
R1 6 3 1 0K _0 4 L _ C TR L _ C L K
3 .3 VS L _ C TR L _ D A TA P3 9 L _ C TR L _ C L K
R2 1 5 1 0K _0 4
L _ C TR L _ D A TA
R1 7 0 2 . 3 7K _1 % _ 0 4 L V D S _ IB G AF3 7 P3 8
AF3 6 L V D _ IBG S D V O_ C TR L C L K M 39
L VD _ VBG SD VO _ CT R L DAT A
AE4 8
AE4 7 L VD _ VR EF H AT 4 9
L VD _ VR EF L DD P B _ A UX N
D DP B _ A UX P
AT 4 7
AT 4 0 Sheet 16 of 46
Display Port B
AK3 9 DD P B _ H P D
11 L V D S -L C L K N AK4 0 L VD SA_ C L K# AV4 2
LVDS
11 L V D S -L C LK P L VD SA_ C L K DD P B _ 0 N
PCH/ LVDS, DDI,
SDVO
AV4 0
AN 4 8 D D P B _0 P AV4 5
11 L V D S -L 0 N AM 4 7 L VD SA_ D ATA# 0 DD P B _ 1 N AV4 6
Digital Display Interface

CRT
11 L V D S -L 1 N AK4 7 L VD SA_ D ATA# 1 D D P B _1 P AU 4 8
11 L V D S -L 2 N AJ 4 8 L VD SA_ D ATA# 2 DD P B _ 2 N AU 4 7
L VD SA_ D ATA# 3 D D P B _2 P AV4 7
AN 4 7 DD P B _ 3 N AV4 9 R 271 2 .2 K_ 0 4
11 L V D S -L 0 P AM 4 9 L VD SA_ D ATA0 D D P B _3 P 3 .3 VS
R 272 2 .2 K_ 0 4
11 L V D S -L 1 P AK4 9 L VD SA_ D ATA1
11 L V D S -L 2 P AJ 4 7 L VD SA_ D ATA2 P4 6
L VD SA_ D ATA3 D D P C _ C TR L C L K P4 2 H D M I _ C T R L C L K 12
DD P C _ CT R L DA T A H DM I_ CT R L DA T A 1 2
AF4 0
11 L V D S -U C L K N AF3 9 L VD SB_ C L K# AP4 7
Display Port C
11 L V D S -U C L K P L VD SB_ C L K D D P C_ A UX N AP4 9
AH 4 5 DD P C _ A UX P AT 3 8 P C H_ D DP C _ HP D R 153 *1 0 m i l_ 0 4
11 L V D S -U 0 N AH 4 7 L VD SB_ D ATA# 0 D DP C_ H P D P O R T C _H P D 12
11 L V D S -U 1 N AF4 9 L VD SB_ D ATA# 1 AY 4 7 HD M IB _ D2 B N _C C 1 40 0 . 1u _ 1 0 V _ X 7 R _ 0 4
11 L V D S -U 2 N AF4 5 L VD SB_ D ATA# 2 D DP C_ 0 N AY 4 9 HD M IB _ D2 B P _C H DM IB_ D 2B N 12
C 1 41 0 . 1u _ 1 0 V _ X 7 R _ 0 4
L VD SB_ D ATA# 3 D D P C _0 P AY 4 3 HD M IB _ D1 B N _C C 1 24 0 . 1u _ 1 0 V _ X 7 R _ 0 4 H DM IB_ D 2B P 12
AH 4 3 D DP C_ 1 N AY 4 5 H DM IB_ D 1B N 12
HD M IB _ D1 B P _C C 1 25 0 . 1u _ 1 0 V _ X 7 R _ 0 4
11 L V D S -U 0 P AH 4 9 L VD SB_ D ATA0 D D P C _1 P BA4 7 HD M IB _ D0 B N _C H DM IB_ D 1B P 12
C 1 26 0 . 1u _ 1 0 V _ X 7 R _ 0 4
11 L V D S -U 1 P AF4 7 L VD SB_ D ATA1 D DP C_ 2 N BA4 8 HD M IB _ D0 B P _C H DM IB_ D 0B N 12
11 L V D S -U 2 P C 1 27 0 . 1u _ 1 0 V _ X 7 R _ 0 4 H DM IB_ D 0B P 12
AF4 3 L VD SB_ D ATA2 D D P C _2 P BB4 7 HD M IB _ CL K B N_ C C 1 37 0 . 1u _ 1 0 V _ X 7 R _ 0 4
L VD SB_ D ATA3 D DP C_ 3 N BB4 9 H DM IB_ C LK BN 1 2
HD M IB _ CL K B P_ C C 1 38 0 . 1u _ 1 0 V _ X 7 R _ 0 4
D D P C _3 P H DM IB_ C LK BP 1 2
DA C_ B L U E R2 0 0 1 50 _ 1 % _ 0 4 DA C_ B L U E N 48 M 43
12 DAC _ B L U E C RT _ BL U E D D P D _ C TR L C L K
C 196 R1 8 7 1 50 _ 1 % _ 0 4 DA C_ G RE E N P 4 9 M 36
DA C_ G RE E N DA C_ R E D T4 9 C RT _ G RE E N DD P D _ CT R L DA T A
12 D A C _ GR E E N * 3 3p _ 5 0 V _ N P O_ 0 4 R1 9 2 1 50 _ 1 % _ 0 4
C 188 C RT _ R E D
* 3 3p _ 5 0 V _ N P O_ 0 4 DA C_ R E D AT 4 5
Display Port D
12 DAC _ RE D T3 9 D D P D_ A UX N AT 4 3
CRT
C 169
1 2 D A C _D D C A C L K M 40 C RT _ D DC _ CL K DD P D _ A UX P BH 4 1
* 3 3p _ 5 0 V _ N P O_ 0 4 1 2 D A C _D D C A D A T A
EMI NEAR PCH M 47
C R T _ D D C _ D A TA D DP D_ H P D
D DP D_ 0 N
BB4 3
BB4 5
12 DAC _ HS Y N C M 49 C RT _ H S Y NC D D P D _0 P BF 4 4
12 DA C _ V S Y NC C RT _ VS YN C D DP D_ 1 N BE4 4
D D P D _1 P BF 4 2
DA C_ IR E F T4 3 D DP D_ 2 N BE4 2
R 165 1 K_ 1 % _ 0 4
T4 2 D A C _I R E F D D P D _2 P BJ 4 2
C RT _ IR T N D DP D_ 3 N BG 4 2
D D P D _3 P
C o u g arP o in t _ R e v _ 1 p0
Connect to GND
1 1 , 1 2 , 1 9 , 2 0 , 2 6, 30 , 3 1 , 3 2 , 3 7 , 3 8 5 V S
3 , 9 , 1 0 , 1 1 , 1 2 , 1 3, 14 , 1 5 , 1 7 , 1 8 , 1 9 , 20 , 2 3 , 2 4 , 2 5 , 2 6 , 2 8, 29 , 3 0 , 3 1 , 3 2 , 3 7 3 . 3 V S
PCH/ LVDS, DDI, CRT B - 17

Schematic Diagrams
PCH/ PCI, USB, NVRAM
Boot BIOS Strap

BBS_BIT1 BBS_BIT0 Boot BIOS Location
0 0 LPC
CougarPoint -M (PCI,USB,NVRAM)
0 1 Reserved (NAND) U 3 7E
AY7 FOR LAYOUT SWAP
1 0 PCI R SVD 1 AV7
B G2 6 R SVD 2 A U3 R N5 3 .3 V S
1 1 SPI TP1 R SVD 3
BJ 2 6 B G4 1 0 K _ 8P 4R _ 0 4
B H2 5 TP2 R SVD 4 I NT _ P I R QD # 4 5
BJ 1 6 TP3 A T 10 D _ GP U _ P W R _ E N# 3 6
B B S _ B IT 1 B G1 6 TP4 R SVD 5 B C8 S A T A _ OD D_ DA # 2 7
R 2 26 * 1 K _0 4
A H3 8 TP5 R SVD 6 I NT _ P I R QG # 1 8
A H3 7 TP6 A U2
R 4 46 * 1 K _0 4
B B S _B IT0 1 3 AK4 3 TP7 R SVD 7 AT4 R N4
AK4 5 TP8 R SVD 8 AT3 1 0 K _ 8P 4R _ 0 4
TP9 R SVD 9
C1 8 AT1 I N T _P IR Q A # 4 5
N3 0 TP1 0 R SVD 1 0 AY3 D GP U _ HO LD _ R S T # 3 6
H3 TP1 1 R SVD 1 1 AT5 D GP U _ SE L ECT # 2 7
A H1 2 TP1 2 R SVD 1 2 AV3 I N T _P IR Q E # 1 8
AM 4 TP1 3 R SVD 1 3 AV1
Flash Descriptor security override strap AM 5 TP1 4 R SVD 1 4 BB1
Y1 3 TP1 5 R SVD 1 5 BA3 I N T _ P I RQ B # 1 0 K _0 4 R2 2 8
K2 4 TP1 6 R SVD 1 6 BB5 I N T_ P I R QC # 1 0 K _0 4 R2 6 5
LOW = PCI_GNT#3 swap override L24 TP1 7 R SVD 1 7 BB3 I N T_ P I R QH # 1 0 K _0 4 R2 5 1
PCI_GNT#3 AB4 6 TP1 8 R SVD 1 8 BB7 D G P U_ P W M _ S E L E C T#
Sheet 17 of 46 HIGH = Default AB4 5 TP1 9
TP2 0
R SVD 1 9
R SVD 2 0
BE8
B D4
* 1 0K _ 0 4 R2 4 1
R SV D
R SVD 2 1 BF6
PCH/ PCI, USB, R 22 5 * 1K _0 4 P C I _G NT # 3
B2 1
TP2 1
R SVD 2 2
R SVD 2 3
AV5
M2 0 AV1 0
NVRAM A Y1 6
B G4 6
TP2 2
TP2 3
TP2 4
R SVD 2 4
R SVD 2 5
AT8
AY5
R SVD 2 6 BA2
BE2 8 R SVD 2 7
B C3 0 TP2 5 A T 12
R2 4 3 *1 K _ 0 4 IN T_ P IR QE # BE3 2 TP2 6 R SVD 2 8 BF3
BJ 3 2 TP2 7 R SVD 2 9
B C2 8 TP2 8
BE3 0 TP2 9
BF3 2 TP3 0
B G3 2 TP3 1 C2 4
MPC Switch Control AV2 6 TP3 2 U SBP0 N A2 4 U S B _ P N0 27
MPC ON -- 0 BB2 6 TP3 3
TP3 4
U SBP0 P
U SBP1 N
C2 5
U
U
SB_ PP0
S B _ P N1
27
31
USB PORT0 (J_USB3_1; USB3.0)
A U2 8 B2 5
MPC OFF -- 1 DEFAULT A Y3 0 TP3 5 U SBP1 P C2 6 U
U
SB_ PP1
S B _ P N2
31
22
USB PORT1 (J_USB_1)
A U2 6 TP3 6 U SBP2 N A2 6
A Y2 6 TP3 7 U SBP2 P K2 8 U
U
SB_ PP2
S B _ P N3
22
31
WLAN
AV2 8 TP3 8 U SBP3 N H2 8
AW 3 0 TP3 9 U SBP3 P E2 8 U SB_ PP3 31 FINGER PRINTER
TP4 0 U SBP4 N D2 8 U S B _ P N4 23
U SBP4 P C2 8 U SB_ PP4 23 3G
U SBP5 N A2 8 U S B _ P N5 23
3 .3 V
PIN PLT_ RST# to B uffe r
U SBP5 P
U SBP6 N
C2 9 U SB_ PP5 23 CCD
B2 9
C 2 07 *0 . 1 u _1 6 V _ Y 5 V _ 0 4 IN T_ P IR QA # K4 0 U SBP6 P N2 8
K3 8 P IR QA # U SBP7 N M2 8
IN T_ P IR QB #
U 13 IN T_ P IR QC # H3 8 P IR QB # U SBP7 P L3 0
PC I
5
P L T _ RS T # 1 7 4 A HC 1 G0 8 GW IN T_ P IR QD # G3 8 P IR QC # U SBP8 N K3 0
4 P IR QD # U SBP8 P G3 0
B UF _ P L T _R S T # 2 2, 24 , 2 5 , 2 7, 28 U SBP9 N U S B _ P N9 3 1
2 DG P U _H OL D _R S T # C4 6 E3 0 3 .3 V VD D3
DG P U _S E LE CT # C4 4 R E Q1 # / GP I O5 0 U SBP9 P C3 0 U SB_ PP9 3 1 USB PORT2 (AJ_USB1)
U SB
R 24 5 D_ G P U_ P W R_ E N # E4 0 R E Q2 # / GP I O5 2 U SBP1 0 N A3 0
R E Q3 # / GP I O5 4 US B P 10 P L3 2
3
BBS _ BIT 1 D4 7 U SBP1 1 N K3 2 US B _P N1 1 2 9 1126

1 0 0 K _0 4 R6 8 9 R6 8 8
D GP U _ P W M _S E L E CT # E 4 2 G N T 1 # / GP I O 5 1
G N T 2 # / GP I O 5 3
US B P 11 P
U SBP1 2 N
G3 2 U SB_ PP1 1 2 9 BT PORT11
P C I _G N T # 3 F4 6 E3 2 *0 _ 0 4 0 _0 4
G N T 3 # / GP I O 5 5 US B P 12 P C3 2
U SBP1 3 N A3 2
IN T_ P IR QE # G4 2 US B P 13 P
S A T A _ OD D_ D A # G4 0 P IR QE # / G P IO 2 RN 6
2 6 S A T A _ O D D _D A # IN T_ P IR QG # C4 2 P IR QF # / G P IO 3 C3 3 US B _ B I A S R 4 67 2 2. 6 _ 1 % _ 04 1 0 K _ 8P 4R _ 0 4
IN T_ P IR QH # D4 4 P IR QG # / GP IO 4 U S B RB I A S # U S B _ OC # 45 5 4
P IR QH # / GP IO 5 6 3
U S B _ OC # 10 1 1
B3 3 U S B _ OC # 67 7 2
K1 0 US B R B IA S U S B _ OC # 12 1 3 8 1
28 PM E# PM E#
P L T _R S T # C6 A1 4 US B _O C# 0 1 RN 7
1207 3 ,2 3 P L T _R S T # PL T RST # OC 0 # /
OC 1 # /
GP I O 5 9
GP I O 4 0
K2 0
B1 7
US B
US B
_O
_O
C# 2 3
C# 4 5
US B _ O C # 0 1 31
U S B _ OC # 01 5
1 0 K _ 8P 4R _ 0 4
4
H4 9 OC 2 # / GP I O 4 1 C1 6
10/29 6 3
US B _O C# 6 7 U S B _ OC # 14
P C LK _T P M _ P C H H4 3 C LK O UT _ P C I0 OC 3 # / GP I O 4 2 L1 6 US B _O C# 8 9 U S B _ OC # 23 7 2
2 3 P C LK _T P M R 2 14 22_04
R 2 27 22_04 CL K _ P C I _ F B _ R J48 C LK O UT _ P C I1 OC 4 # / GP I O 4 3 A1 6 US B _O C# 1 0 1 1 U S B _ OC # 89 8 1
1 4 C LK _ P C I _ F B K4 2 C LK O UT _ P C I2 OC 5# / G P IO 9 D1 4 US B _O C# 1 2 1 3
R 2 60 22_04 CL K _ P C I _ K B C_ R H4 0 C LK O UT _ P C I3 OC 6 # / GP I O 1 0 C1 4 US B _O C# 1 4
28 P C L K _ K B C C LK O UT _ P C I4 OC 7 # / GP I O 1 4
R2 3 3 * 0_ 0 4 A C _ P RE S E N T 1 5 , 2 8
C o ug a rP o i nt _ R e v _ 1p 0
B - 18 PCH/ PCI, USB, NVRAM

Schematic Diagrams
PCH/ GPIO, VSS_NCTF, RSVD

R1 8 0 1 0K _0 4 B IO S _ RE C
3. 3 V S
R1 8 4 *0 _ 0 4
CougarPoint - M (GPIO,VSS_NCTF,RSVD)
BIOS RECOVERY
U 37F
DISABLE----R349 NO STUFF (DEFAULT)
ENABLE-----R349 STUFF S _ GP I O T7 C 40 S A T A _ OD D _ P W R GT
B M B U S Y # / G P I O0 T A C H 4 / G P I O6 8 S A T A _ O D D _P W R G T 26
S MI # A4 2 B4 1 P C H _ GP I O 5 7 R 46 9 1 . 5 K _ 1 %_ 0 4
28 S MI # T A C H 1 / G P I O1 T A C H 5 / G P I O6 9
D G P U _ H P D _ I N TR # H3 6 C 41 GP I O 7 0 R 47 4 1 . 5 K _ 1 %_ 0 4
GF X _ C R B _ D E T T A C H 2 / G P I O6 T A C H 6 / G P I O7 0 3. 3 V S
3. 3 V S R4 5 1 *1 0 K _ 04
S CI# E3 8 A4 0 GP I O 7 1 R 47 1 1 . 5 K _ 1 %_ 0 4
28 S CI# T A C H 3 / G P I O7 T A C H 7 / G P I O7 1 3. 3 V S
R4 5 0 10 0 K _ 0 4 I C C _E N # C1 0
11/18 G P I O8
P M_ L A N P H Y _ E N R3 1 6 0 _ 04 C4
2 5 P M _ LA N P H Y _ E N L A N _P H Y _P W R _ C TR L / GP I O1 2
R3 1 4 *0 _ 0 4 H O S T _A L E R T # 1 G2 P4
28 O CP P E # G P I O1 5 A 20 G A T E G A2 0 28
R 1 37 *1 0 K _ 0 4
AU 1 6 HP E CI_ R 1. 05 V S _ V T T
Internal GFX: Low (Default) R 1 38 * 0 _0 4
S A T A _ DE T # 4 U2 PEC I H _P E C I 3 ,2 8
S A TA 4 G P / G P I O1 6 P5 K B C _R S T #
External GFX: High R CI N# K B C _ RS T # 2 8
GPIO
D G P U _ P W R OK D4 0 AY 1 1
T A C H 0 / G P I O1 7 P R OC P W R GD H _C P U P W R G D 3
CPU/MISC
B I OS _ R E C T5 AY 1 0 H T H R M TR I P # _ R R 1 25 3 9 0 _ 1% _ 0 6
11/18 H _T H R M T R I P # 3
V DD 3 S C L OC K / G P I O2 2 T H R M TR I P #
H O S T _A L E R T # 2 E8 T14 INIT 3 _ 3 V# R 4 30 2 .2 K_ 0 4
G P I O2 4 / M E M_ L E D I N I T 3_ 3 V # 1 . 8V S
R4 8 4 *1 0 K _ 0 4 E1 6 AY 1 N V _ C LE R 4 29 1 K _ 04
R4 6 5 1 K _ 04 I C C _E N #
28 S LP _M E _ C S W _S E V #
11 S B _ B L ON
R 6 76 * 0 _0 4 P L L_ O D V R _ E N P8
G P I O2 7
G P I O2 8
D F_ TVS
AH 8 R 5 4 7 *1 0 m i _l 0 4 DMI & FDI Termination Voltage

10/28 H _ S N B _I V B # 3
Sheet 18 of 46
K1 TS_ VSS1
PCH/ GPIO,
1124 GP I O 3 4
S T P _ P C I # / GP I O3 4 AK1 1 R 5 4 8
R6 9 9 0_ 0 4 *1 0 m i _l 0 4 Set to Vss when LOW
28 ICP P E # P C H _ MU T E # K4 TS_ VSS2 NV_CLE
1201 G P I O3 5 A H 1 0R 5 4 9 *1 0 m i _l 0 4
Set to Vcc when HIGH
TS_ VSS3
INTEGRATE CLOCK
DISABLE----R465 NO STUFF (DEFAULT)
2 6 S A T A _ OD D _ P R S N T#
S A T A _ OD D _ P R S N T #
F DI_ O V RV L T G
V8
M5
S A TA 2 G P / G P I O3 6
S A TA 3 G P / G P I O3 7
TS_ VSS4
AK1 0 R 5 5 0 *1 0 m i _l 0 4 VSS_NCTF, RSVD
ENABLE-----R465 STUFF R4 4 9 1 0K _ 0 4 MF G _ MO D E N2 P3 7
3 .3 VS S L O A D / GP I O 3 8 N C_ 1
GF X _ C R B _ D E T M3
S D A T A O U T 0 / GP I O3 9
R1 8 1 1 0K _ 0 4 TE S T_ S E T_ U P V1 3 BG 2
3 .3 VS S D A T A O U T 1 / GP I O4 8 V S S _ N C TF _ 1 5
11/18 2 C R I T _ T E MP _ R E P #
R4 3 5 *0 _ 0 4 C R I T_ T E M P _ R E P # _ R V3 BG 4 8
V DD 3 S A TA 5 G P / G P I O4 9 V S S _ N C TF _ 1 6
R2 2 2 1 00 K _ 0 4 T E ST _ DET D6 BH 3
G P I O5 7 V S S _ N C TF _ 1 7
BH 4 7
R4 6 2 1 K_ 0 4 H OS T _ A L E R T# 1 V S S _ N C TF _ 1 8
R2 5 4 1 K_ 0 4 H OS T _ A L E R T# 2 A4 BJ 4
P M _ LA N P H Y _ E N V S S _N C TF _ 1 V S S _ N C TF _ 1 9
R4 6 1 *1 0 K _ 0 4
A4 4 BJ 4 4
V S S _N C TF _ 2 V S S _ N C TF _ 2 0
3 .3 VS R N8 A4 5 BJ 4 5
1 0 K _ 8P 4R _ 04 V S S _N C TF _ 3 V S S _ N C TF _ 2 1
1 8 SC I# A4 6 BJ 4 6
NCTF
2 7 SM I# V S S _N C TF _ 4 V S S _ N C TF _ 2 2
3 6 G A2 0 A5 BJ 5
4 5 K B C _ R S T# V S S _N C TF _ 5 V S S _ N C TF _ 2 3
A6 BJ 6
V S S _N C TF _ 6 V S S _ N C TF _ 2 4
R1 7 9 1 0 K _ 04 S _ GP I O B3 C 2
S A T A _ OD D _ P R S N T # V S S _N C TF _ 7 V S S _ N C TF _ 2 5
R1 6 6 2 0 0K _0 4
R2 6 4 1 0 K _ 04 D G P U _ H P D _ I N TR # B4 7 C 48
R4 7 0 1 K_ 0 4 S A T A _ OD D _ P W R GT V S S _N C TF _ 8 V S S _ N C TF _ 2 6
R4 5 5 *1 K _ 0 4 GP I O 3 4 B D1 D 1
R4 3 6 1 0 K _ 04 C R I T _T E M P _ R E P #_ R V S S _N C TF _ 9 V S S _ N C TF _ 2 7
R4 8 0 *1 0 K _ 0 4 DG P U_ P W RO K B D4 9 D 49
R4 4 2 1 0 K _ 04 SA T A _ DET # 4 V S S _N C TF _ 1 0 V S S _ N C TF _ 2 8
BE1 E1
V S S _N C TF _ 1 1 V S S _ N C TF _ 2 9
R1 9 4 *1 K _ 0 4 P L L _ OD V R _ E N BE4 9 E4 9
V S S _N C TF _ 1 2 V S S _ N C TF _ 3 0
R2 0 1 1 0 0K _0 4 F D I _ OV R V L T G BF 1 F1
V S S _N C TF _ 1 3 V S S _ N C TF _ 3 1
BF4 9 F49
V S S _N C TF _ 1 4 V S S _ N C TF _ 3 2
C o u ga rP o i n t _ R e v _ 1 p0
1 3 , 1 4 , 1 5, 1 7 , 2 0 , 2 2, 2 3 , 2 4 , 2 5, 2 8 , 3 2 , 3 3, 3 5 , 3 9 V D D 3
2 , 3 , 5 , 1 9 , 20 , 3 5 , 3 7 1. 05 V S _ V T T
6, 1 9 , 3 4 1 . 8V S
2 , 3 , 8, 1 1 , 1 3 , 1 5, 1 7 , 1 9 , 2 0, 2 2 , 2 3 , 2 7, 2 9 , 3 1 , 3 2, 3 4 , 3 6 3 . 3V
3 , 9, 10 , 1 1 , 1 2, 13 , 1 4 , 1 5, 1 6 , 1 7 , 1 9, 2 0 , 2 3 , 2 4, 2 5 , 2 6 , 2 8, 2 9 , 3 0 , 3 1, 3 2 , 3 7 3 . 3V S
PCH/ GPIO, VSS_NCTF, RSVD B - 19

Schematic Diagrams
PCH/ POWER1
CougarPoint -M (POWER) L1 7
H C B 1 0 05 K F -1 2 1 T2 0
3 . 3V S
layout? check
5 VS
1 .0 5 VS U3 7 G P OW E R V C CA _ D A C_ 3 .3 V S
All VCCORE = 1.3A 1mA U 39
5 1
AA2 3 U 48 OU T IN
C1 6 8 C 15 8 C 1 78 C1 7 4 AC 2 3 V CC CO RE [1 ] V CC A DA C C4 5 1 C4 5 2 C4 5 3 C5 3 9 C4 5 7 C4 5 9
AD 2 1 V CC CO RE [2 ] 3
R 4 57
CRT
1 0u _ 6 . 3V _X 5 R _ 0 6 1 u _ 6 . 3V _Y 5 V _0 4 1 u_ 6 . 3 V _ Y 5 V _ 0 4 1 u _ 6. 3 V _ Y 5V _ 0 4 AD 2 3 V CC CO RE [3 ] U 47 0. 0 1 u _1 6 V _ X 7R _ 04 0 . 1 u_ 1 0 V _ X5 R _0 4 1 0u _ 6 . 3V _X 5 R _ 0 6 *0 . 1 u_ 1 0 V _ X5 R _0 4 *2 2u _ 6 . 3 V _ X5 R _0 8 * 2 3. 7 K _ 1 % _0 4 S H DN # * 1u _ 6 . 3V _X 5 R _ 0 4
AF 2 1 V CC CO RE [4 ] V S S A DA C 4 2
VCC CORE
AF 2 3 V CC CO RE [5 ] SET G ND
AG 2 1 V CC CO RE [6 ] 3. 3 V S _ V C C A _ L V D *A P L 5 6 03 -3 3 B
AG 2 3 V CC CO RE [7 ]
AG 2 4 V CC CO RE [8 ] A K 36
1mA
R 1 59 *2 0 m il _ 0 4
AG 2 6 V CC CO RE [9 ] V C C A LV D S 3 .3 VS R 4 60
AG 2 7 V CC CO RE [1 0 ] A K 37 C1 5 6
AG 2 9 V CC CO RE [1 1 ] V S S A LV D S
* 1 0K _ 1 % _ 04
AJ 2 3 V CC CO RE [1 2 ] 0 . 1 u_ 1 0 V _ X5 R _0 4 1 . 8 V S _ V C C T X_ L V D L3 4
V CC CO RE [1 3 ] APL5603-33B 6-02-56033-4C0
LVDS
AJ 2 6 AM 3 7 H C B 16 0 8 K F -1 2 1T 2 5
1 .0 5 VS 1 . 0 5 V S _ V C C A P L L _E XP AJ 2 7 V CC CO RE [1 4 ] V C C T X _ LV D S [ 1 ] 60mA G9091-330T11UF 6-02-90913-4C0
AJ 2 9 V CC CO RE [1 5 ] AM 3 8
. 1 .8 VS
AJ 3 1 V CC CO RE [1 6 ] V C C T X _ LV D S [ 2 ] C1 5 3 C1 5 0 C4 3 9
V CC CO RE [1 7 ] A P 36
R 15 2 * 2 0m i l _0 4
V C C T X _ LV D S [ 3 ] 0. 0 1 u _1 6 V _ X 7R _ 04 0 . 0 1u _ 1 6V _X 7 R _ 0 4 2 2u _ 6 . 3V _X 5 R _ 0 8
A P 37
1 . 0 5 V S _ V C C A P L L_ E X P AN 1 9 V C C T X _ LV D S [ 4 ]
L31 V C C I O[ 2 8 ]
Sheet 19 of 46 * H C B 10 0 5 K F -1 2 1T 2 0
. V C C A _ P LL _ E X P BJ 2 2
V C C A P L LE XP
V3 3
266mA
3 . 3V S
PCH/ POWER1 V C C 3 _3 [ 6 ]
HVCMOS
C4 2 4 AN 1 6 C1 7 9
V C C I O[ 1 5 ]
layout? check *1 0 u_ 6 . 3 V _ X5 R _0 6 AN 1 7 0 . 1 u_ 1 0 V _ X5 R _0 4
V C C I O[ 1 6 ] V3 4
V C C 3 _3 [ 7 ]
AN 2 1
1 .0 5 VS V C C I O[ 1 7 ] 1 . 5V S _1 . 8 V S
AN 2 6
All VCCIO = 2.92A V C C I O[ 1 8 ]
AN 2 7 AT1 6
160mA
C 1 47 C 17 1 C 14 9 C1 5 1 C1 5 2 V C C I O[ 1 9 ] V C C V R M[ 3 ]
AP2 1
1 0 u _6 . 3 V _ X 5R _ 06 1 u _6 . 3 V _ Y 5 V _ 0 4 1 u _6 . 3 V _ Y 5 V _ 0 4 1 u_ 6 . 3 V _ Y 5 V _ 0 4 1 u_ 6 . 3 V _ Y 5 V _ 04 V C C I O[ 2 0 ]
AP2 3 AT2 0
42mA
V C C I O[ 2 1 ] V C C D MI [ 1 ] 1. 05 V S _ V T T
AP2 4
DMI
2mA C1 4 6 C 12 8
V C C I O[ 2 2 ]
VCCIO
AP2 6 A B 36 V C C C L K D MI R1 6 4 * 2 0m i l _0 4 1 u _ 6. 3 V _ Y 5 V _ 0 4 1 0 u_ 6 . 3 V _ X5 R _0 6
V C C I O[ 2 3 ] V CC CL K DM I 1 . 05 V S
AT 2 4
V C C I O[ 2 4 ]
AN 3 3
V C C I O[ 2 5 ]
3 . 3V S AN 3 4 AG 1 6
V C C I O[ 2 6 ] V C C D F T E R M[ 1 ] V _ N V RA M _ V CC Q 1. 8 V S 3. 3V S
190mA
266mA BH 2 9 AG 1 7 R1 4 0 *2 0 m il _ 0 4
CougarPoint power supply range
DFT / SPI
V C C 3_ 3 [ 3 ] V C C D F T E R M[ 2 ]
C1 4 4 1 .5 VS_ 1 .8 VS R 14 1 *0 _ 0 4 Min Voltage Max
AJ 1 6 C 16 0
V C C D F T E R M[ 3 ]
0 . 1 u _1 0 V _ X 5R _ 04 160mA 1.00V 1.05V 1.10V
AP1 6 0 . 1 u_ 1 0 V _ X5 R _0 4
1 . 0 5 V S _ V C C A P L L _F D I V CC V RM [2 ] AJ 1 7
V C C D F T E R M[ 4 ] 1.43V 1.5V 1.58V
R4 2 1 *0 _0 4 BG 6 V C C ME 3 . 3 V 3. 3 V S 3 . 3 V
1 .0 5 V S V c cA F D I P L L 1.71V 1.8V 1.89V
11/01 R 43 9 *0 _ 0 4 3.14V 3.3V 3.47V
AP1 7 20mA 11/03
V C C I O[ 2 7 ] V1 R 44 0 *0 _ 0 4 4.75V 5V 5.25V
FDI
VCC S PI
1 . 0 5S _ V C C _ D MI AU 2 0 R 66 6 0 _0 4
V CC DM I[2 ] 3 . 3 V _M
42mA R 14 9 *2 0 m il _ 0 4
1 . 0 5V S _V TT
C o u g arP oi n t _ R e v _ 1 p0 C 44 6
1 u _6 . 3 V _ Y 5 V _ 0 4
13 , 1 5 , 2 5, 2 6 , 3 2 3. 3 V _ M
20 1. 5 V S _ 1 . 8 V S
1 1 , 1 2, 2 0 , 2 6 , 30 , 3 1 , 3 2, 3 7 , 3 8 5V S
1. 05 V S 1 .5 VS 1. 8 V S 1 . 5 V S _ 1 . 8V S 2 , 3 , 8 , 1 1, 1 3 , 1 5 , 17 , 2 0 , 2 2, 2 3 , 2 7 , 29 , 3 1 , 3 2, 3 4 , 3 6 3. 3 V
3 , 9, 10 , 1 1 , 1 2, 1 3 , 1 4, 15 , 1 6 , 1 7, 1 8 , 2 0 , 23 , 2 4 , 2 5, 2 6 , 2 8 , 29 , 3 0 , 3 1, 3 2 , 3 7 3. 3 V S
6, 1 8 , 3 4 1. 8 V S
3 0 ,3 2 1. 5 V S
R1 4 3 *0 _ 04
2, 3, 5 , 1 8 , 2 0, 3 5 , 3 7 1. 0 5 V S _ V T T
R1 4 8 *2 0 mi l _ 04 13 , 1 4 , 1 5, 2 0 , 3 2 1. 0 5 V S
R1 4 7 *0 _ 04
B - 20 PCH/ POWER1
Schematic Diagrams
PCH/ POWER2
CougarPoint power supply range CougarPoint - M (POWER) V ol tag e Ra il V olt ag e S0 Ic cm ax C urr en t (A )

L 36 1 . 0 5 V S _ V C C A _C L K V _C PU_ IO 1.0 5 1 (mA )
Min Voltage Max * H C B 1 00 5 K F -1 2 1T 2 0 V 5R EF 5 1 (mA )
1 . 05 V S
1.00V 1.05V 1.10V V 5R EF_ Su s 5 1 (mA )
V DD 3
R4 5 2 0_04 U3 7 J P OW ER V cc 3_3 3.3 0. 266
1.43V 1.5V 1.58V C1 9 4 A D4 9 N2 6 All VCCIO=2.92A V cc ADA C3 1.0 5 1 (mA )
V CC A CL K V C C I O [ 2 9] 1. 0 5 V S
1.71V 1.8V 1.89V 11/18 0 . 1 u_ 1 0 V _X 5 R _ 0 4 P 26 C1 9 2 V cc ADP LL A 1.0 5 0. 08
3mA T1 6 V C C I O [ 3 0]
3.14V 3.3V 3.47V V CC DS W 3 _ 3 P 28 11/18 V cc ADP LL B 1.0 5 0. 08
1u _ 6 . 3V _Y 5V _0 4
V C C I O [ 3 1]
4.75V 5V 5.25V V cc Cor e 1.0 5 1. 3
C 1 90 *0 . 1 u _1 0 V _ X 5R _0 4 P C H_ V C CDS W V1 2 T2 7
DC P SUSB Y P V C C I O [ 3 2] VD D3 V cc DMI 1.1 0. 042
L 16
H C B 1 0 0 5K F -12 1 T 20 266 mA T2 9 V cc IO 1.0 5 2. 925
V C C3 _ 3 T3 8 V C C I O [ 3 3]
3. 3 V S V C C 3 _3 [ 5 ]
97mA V cc ASW 1.0 5 1. 01
C1 7 6 C 1 87 T2 3 R2 7 4 0 _ 06 0 3
11/01 V C C S U S 3 _ 3[ 7] V cc SPI 3.3 0. 020
B H2 3
V C C A P L LD MI 2 T2 4
1 0u _ 6 . 3 V _X 5 R _ 0 6 1 u _ 6 . 3V _ Y 5V _ 0 4 C1 8 4 C 19 7 V cc DSW 3_ 3 3.3 2 (mA )
L 30 AL 2 9 V C C S U S 3 _ 3[ 8]
* H C B 1 00 5 K F -1 2 1T 2 0
V C C I O[ 1 4 ] V 23 0. 1 u _ 10 V _ X 5 R _ 0 4 0 . 1 u_ 1 0 V _ X5 R _0 4
11/18 V cc DFT ER M 1.8 0. 19
V C C S U S 3 _ 3[ 9]
USB
W243 1117 + V C C A P L L _C P Y _ P C H V cc Sus 3_ 3 3.3 0. 097
1 . 05 V S AL 2 4 V 24
C 1 61 *1 u _ 6. 3 V _ X 5 R _ 04 DC P S US DC P SUS[3 ] V C C S U S 3 _ 3 [ 1 0] V cc Sus HD A 3.3 1 (mA )
1 1/01
1 . 0 5 V _M P 24 R 45 6 *0 _ 04
V C C S U S 3 _ 3[ 6] D1 0 R B 75 1 S -4 0 C 2 3 .3 V V cc VRM 1.5 0. 16
A ll V CC AS W=1 .0 1A
AA1 9 C A R 45 4 0_ 0 4 V cc ClK DM I 1.0 5 0. 02
V CC A S W [1 ] V D D3
Sheet 20 of 46
T2 6 R1 9 6 * 20 m i _l 0 4
AA2 1 V C C I O [ 3 4] 1. 0 5 V S V cc SSC 1.0 5 0. 095
R 24 2 10 _ 0 4
C 4 41 C4 3 8 C 2 00 C1 7 3 C 1 83 V CC A S W [2 ] V D D5
1mA V cc DIF FC LK N 1.0 5 0. 055
AA2 4 M2 6 + V 5 A _ P C H _ V C C 5R E F S U S C 20 3 0. 1 u _ 10 V _ X 5 R _ 0 4
V CC A S W [3 ] V 5R E F _ S U S V cc ALV DS 3.3 1 (mA )
2 2 u _6 . 3 V _ X 5R _ 08 2 2u _ 6 . 3V _X 5 R _ 0 8 1 u _ 6. 3V _ Y 5V _ 0 4 1 u_ 6 . 3 V _ Y 5 V _ 04 1 u _ 6 . 3V _ Y 5V _ 0 4
PCH/ POWER2
Clock and Miscellaneous

AA2 6
V CC A S W [4 ] A N2 3 + V C CA _ US B S US C1 5 4 * 1u _ 6 . 3V _ X 5 R _ 0 4 V cc TX_ LV DS 1.8 0. 06
AA2 7 D C P S U S [ 4]
V CC A S W [5 ] A N2 4
AA2 9 V C C S U S 3 _ 3[ 1] VD D3 11/19
V CC A S W [6 ]
AA3 1 + 5 V _ P C H _V C C 5R E F S U S
V CC A S W [7 ]
1mA D1 1 R B 75 1 S -4 0 C 2
Note: C1289- STUFFED ONLY FOR CPT INTERPOSER; A C2 6
V CC A S W [8 ] V 5 RE F
P 34 C A
3 .3 V S
11/18
UNSTUFF FOR CPT A C2 7 R 26 3 10 _ 0 4
V CC A S W [9 ] N2 0 5 VS V DD 3
PCI/GPIO/LPC
A C2 9 V C C S U S 3 _ 3[ 2] C 20 2 1 u _6 . 3 V _ X 5R _ 04
V CC A S W [1 0 ] N2 2
97mA
A C3 1 V C C S U S 3 _ 3[ 3]
V CC A S W [1 1 ] 11/03
P 20 R2 7 5 0 _ 06 0 3
A D2 9 V C C S U S 3 _ 3[ 4]
V CC A S W [1 2 ] P 22 3 .3 VS C1 8 6
A D3 1 V C C S U S 3 _ 3[ 5]
V CC A S W [1 3 ]
266mA 1u _ 6 . 3 V _Y 5 V _0 4
W21 AA1 6
V CC A S W [1 4 ] V C C 3 _ 3[ 1]
W23 W 16
V CC A S W [1 5 ] V C C 3 _ 3[ 8]
W24 T3 4 C1 8 1 C 19 3 C1 8 0
V CC A S W [1 6 ] V C C 3 _ 3[ 4]
0. 1u _ 1 0V _ X 5 R _ 0 4 0 . 1 u _1 0 V _ X5 R _0 4 0 . 1u _ 1 0V _ X 5 R _ 0 4
W26
V CC A S W [1 7 ]
W29
V CC A S W [1 8 ]
C2 0 1 0 . 1 u _ 10 V _ X 5R _ 04 W31 A J2
V CC A S W [1 9 ] V C C 3 _ 3[ 2] +V 1 . 0 5 S _ S A T A 3 L15
W33 All VCCIO=2.92A H C B 1 6 08 K F -1 2 1 T2 5
V CC A S W [2 0 ]
1 . 0 5V S L 3 2
H C B 1 0 0 5K F -12 1 T 20
1 . 0 5V S _V C C A _ A _ D P L
1. 5 V S _ 1 . 8 V S V C C I O[ 5]
AF1 3 . 1 . 05 V S
+V C C R T C E X T N1 6 C1 6 6 C 15 9
DC P RT C A H1 3
V C C I O [ 1 2]
+C 4 36 C 4 23 C4 2 7 1u _ 6 . 3V _Y 5 V _0 4 * 10 u _ 6. 3 V _ X 5R _ 06
R 4 24
16mA Y4 9 A H1 4
* 2 20 u _ 6. 3 V _ 6 . 3 *4 . 2 2 2 u _6 . 3 V _ X 5R _ 08 1 u_ 6 . 3 V _ Y 5 V _ 04 V CC V RM [4 ] V C C I O [ 1 3]
* 0 _0 4 11/18
AF1 4 L33 3 . 3A _ 1 . 5 A _ H D A _I O
L35 1. 1V S _ V C C A _ B _ D P L
80mA B D4 7 V C C I O[ 6] * H C B 10 0 5 K F -1 21 T 2 0 VDD 3 3 .3 V 1. 5V
SATA
H C B 1 0 0 5K F -12 1 T 20 V CC A DP L L A AK1 1 . 05 V S _ V C C A P L L _ S A TA 3
80mA BF4 7 V C C A P L LS A T A 1 . 0 5V S
R2 5 8 * 0_ 0 6
V CC A DP L L B
C 4 49 C 4 22 C4 2 6 1 . 05 V S AF1 1 R2 5 9 * 0_ 0 6
55mA AF1 7 V C C V R M[ 1] 1 . 5V S _1 . 8 V S
C 1 64 C 1 63
AF3 3 V CC I O[ 7 ]
* 2 2u _ 6 . 3V _ X 5 R _ 0 8 2 2 u _6 . 3 V _ X 5R _ 08 1 u_ 6 . 3 V _ Y 5 V _ 04 R2 7 6 0_06
1 u _ 6. 3V _ Y 5V _ 0 4 1u _ 6 . 3V _ Y 5V _ 0 4 AF3 4 V CC DIF F C L K N[1 ] A C1 6
A G3 4 V CC DIF F C L K N[2 ] V C C I O[ 2] 1 . 0 5V S 11/18
V CC DIF F C L K N[3 ] A C1 7
11/03 V C C I O[ 3]
C1 6 7 1 3 , 1 4 , 15 , 1 7 , 18 , 2 2 , 2 3, 2 4 , 2 5, 2 8 , 3 2, 33 , 3 5 , 39 V D D 3
A G3 3 A D1 7
1 .0 5 VS V CC S S C V C C I O[ 4] 2 7 , 3 2 , 33 , 3 5 V D D 5
1u _ 6 . 3V _Y 5V _0 4 2 5 , 32 , 3 5 1 . 05 V _ L A N _ M
1 . 0 5V _L A N _M
V C CS S T V1 6 32 1 . 05 V _ M
C 15 5 1 3 3 . 3A _ 1 . 5 A _ H D A _I O
R 6 37 * 0 _0 4 + V 1 . 0 5M _V C C S U S C1 9 1 0 . 1 u _ 10 V _ X 5R _ 04 DC P SS T
1 u_ 6 . 3 V _ Y 5V _0 4
+ V 1 . 0 5M _ V C C S U S 19 1 . 5 V S _1 . 8 V S
T1 7 T2 1 1 .01 A 1 3, 1 5 R T C V C C
C1 8 2 * 1 u_ 6 . 3 V _ X5 R _0 4 W243 1117
V1 9 DC P SUS[1 ] V C C A S W [ 2 2] 1 . 05 V _ M 2 3 , 27 , 3 1 , 32 , 3 4 , 3 5, 3 6 5 V
W243 1117 DC P SUS[2 ] 1 1, 1 2 , 1 9 , 26 , 3 0 , 31 , 3 2 , 3 7, 3 8 5 V S
MISC
V 21 2 , 3 , 8 , 11 , 1 3 , 1 5, 1 7 , 1 9, 2 2 , 2 3 , 27 , 2 9 , 31 , 3 2 , 3 4, 3 6 3 . 3 V
1 . 0 5 V S _V TT V C C A S W [ 2 3] 3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4 , 15 , 1 6 , 17 , 1 8 , 1 9, 2 3 , 2 4, 2 5 , 2 6 , 28 , 2 9 , 30 , 3 1 , 3 2, 3 7 3 . 3 V S
1mA 3 , 6 , 8 , 9 , 10 , 2 7 , 3 2, 3 4 1 . 5 V
CPU
C 4 03 C4 1 2 C4 1 3 BJ 8
V _ P RO C_ IO 1 3 , 14 , 1 5 , 1 9, 3 2 1 . 0 5V S
T1 9
V C C A S W [ 2 1] 2 , 3 , 5 , 18 , 1 9 , 3 5, 3 7 1 . 0 5V S _ V T T
4 . 7 u _6 . 3 V _ X 5R _ 06 *0 . 1 u _1 0 V _ X 5R _0 4 *0 . 1 u _1 0 V _ X 5R _ 04
A2 2 P 32
16mA
RTC
RT CV C C V CC RT C V CC S US H DA 3 . 3 A _ 1. 5 A _ H D A _ I O
HDA
C 4 60 C4 6 2 C4 6 1 11/01
C o u g ar P oi n t _ R e v _ 1p 0 C 20 4
1 u _ 6. 3 V _ Y 5V _ 0 4 0 . 1 u_ 1 0 V _X 5 R _ 0 4 0 . 1 u_ 1 0 V _X 5 R _ 0 4
0 . 1 u_ 1 0 V _ X5 R _ 0 4
PCH/ POWER2 B - 21
Schematic Diagrams
PCH/ GND
CougarPoint -M (GND)
U37I
U37H
AY4 H46 H5
AY42 VSS[159] VSS[259] K18 VSS[0]
AY46 VSS[160] VSS[260] K26 AA17 AK38
AY8 VSS[161] VSS[261] K39 AA2 VSS[1] VSS[80] AK4
B11 VSS[162] VSS[262] K46 AA3 VSS[2] VSS[81] AK42
B15 VSS[163] VSS[263] K7 AA33 VSS[3] VSS[82] AK46
B19 VSS[164] VSS[264] L18 AA34 VSS[4] VSS[83] AK8
B23 VSS[165] VSS[265] L2 AB11 VSS[5] VSS[84] AL16
F45 VSS[171] VSS[271] M12 AB7 VSS[11] VSS[90] AL26
BB12 VSS[172] VSS[272] P16 AC19 VSS[12] VSS[91] AL27
BB16 VSS[173] VSS[273] M18 AC2 VSS[13] VSS[92] AL31
BB28 VSS[177] VSS[277] M32 AC34 VSS[17] VSS[96] AM11
BB30 VSS[178] VSS[278] M34 AC48 VSS[18] VSS[97] AM14
BB38 VSS[179] VSS[279] M38 AD10 VSS[19] VSS[98] AM36

BB4 VSS[180] VSS[280] M4 AD11 VSS[20] VSS[99] AM39
BB46 VSS[181] VSS[281] M42 AD12 VSS[21] VSS[ 100] AM43
BC14 VSS[182] VSS[282] M46 AD13 VSS[22] VSS[ 101] AM45
BC18 VSS[183] VSS[283] M8 AD19 VSS[23] VSS[ 102] AM46
Sheet 21 of 46 BC2
BC22
BC26
VSS[184]
VSS[185]
VSS[186]
VSS[284]
VSS[285]
VSS[286]
N18
P30
N47
AD24
AD26
AD27
VSS[24]
VSS[25]
VSS[26]
VSS[ 103]
VSS[ 104]
VSS[ 105]
AM7
AN2
AN29
VSS[187] VSS[287] VSS[27] VSS[ 106]
PCH/ GND BC32
BC34
BC36
BC40
VSS[188]
VSS[189]
VSS[190]
VSS[288]
VSS[289]
VSS[290]
P11
P18
T33
P40
AD33
AD34
AD36
AD37
VSS[28]
VSS[29]
VSS[30]
VSS[ 107]
VSS[ 108]
VSS[ 109]
AN3
AN31
AP12
AP19
BC42 VSS[191] VSS[291] P43 AD38 VSS[31] VSS[ 110] AP28
BC48 VSS[192] VSS[292] P47 AD39 VSS[32] VSS[ 111] AP30
BD46 VSS[193] VSS[293] P7 AD4 VSS[33] VSS[ 112] AP32
BD5 VSS[194] VSS[294] R2 AD40 VSS[34] VSS[ 113] AP38
BE22 VSS[195] VSS[295] R48 AD42 VSS[35] VSS[ 114] AP4
BE26 VSS[196] VSS[296] T12 AD43 VSS[36] VSS[ 115] AP42
BE40 VSS[197] VSS[297] T31 AD45 VSS[37] VSS[ 116] AP46
BF10 VSS[198] VSS[298] T37 AD46 VSS[38] VSS[ 117] AP8
BF12 VSS[199] VSS[299] T4 AD8 VSS[39] VSS[ 118] AR2
BF16 VSS[200] VSS[300] W34 AE2 VSS[40] VSS[ 119] AR48
BF20 VSS[201] VSS[301] T46 AE3 VSS[41] VSS[ 120] AT11
BF22 VSS[202] VSS[302] T47 AF 10 VSS[42] VSS[ 121] AT13
BF24 VSS[203] VSS[303] T8 AF 12 VSS[43] VSS[ 122] AT18
BF26 VSS[204] VSS[304] V11 AD14 VSS[44] VSS[ 123] AT22
BF28 VSS[205] VSS[305] V17 AD16 VSS[45] VSS[ 124] AT26
BD3 VSS[206] VSS[306] V26 AF 16 VSS[46] VSS[ 125] AT28
BF30 VSS[207] VSS[307] V27 AF 19 VSS[47] VSS[ 126] AT30
BG17 VSS[211] VSS[311] V39 AF 29 VSS[51] VSS[ 130] AT42
BG44 VSS[214] VSS[314] W17 AF4 VSS[54] VSS[ 133] AU24
BG8 VSS[215] VSS[315] W19 AF 42 VSS[55] VSS[ 134] AU30
BH11 VSS[216] VSS[316] W2 AF 46 VSS[56] VSS[ 135] AV16
BH15 VSS[217] VSS[317] W27 AF5 VSS[57] VSS[ 136] AV20
BH17 VSS[218] VSS[318] W48 AF7 VSS[58] VSS[ 137] AV24
BH19 VSS[219] VSS[319] Y12 AF8 VSS[59] VSS[ 138] AV30
H10 VSS[220] VSS[320] Y38 AG19 VSS[60] VSS[ 139] AV38
BH27 VSS[221] VSS[321] Y4 AG2 VSS[61] VSS[ 140] AV4
BH35 VSS[224] VSS[324] Y8 AH11 VSS[64] VSS[ 143] AW14
BH39 VSS[225] VSS[325] BG29 AH3 VSS[65] VSS[ 144] AW18
BH43 VSS[226] VSS[328] N24 AH36 VSS[66] VSS[ 145] AW2
BH7 VSS[227] VSS[329] AJ3 AH39 VSS[67] VSS[ 146] AW22
D3 VSS[228] VSS[330] AD47 AH40 VSS[68] VSS[ 147] AW26
D12 VSS[229] VSS[331] B43 AH42 VSS[69] VSS[ 148] AW28
D16 VSS[230] VSS[333] BE10 AH46 VSS[70] VSS[ 149] AW32
D18 VSS[231] VSS[334] BG41 AH7 VSS[71] VSS[ 150] AW34
D22 VSS[232] VSS[335] G14 AJ19 VSS[72] VSS[ 151] AW36
D24 VSS[233] VSS[337] H16 AJ21 VSS[73] VSS[ 152] AW40
D26 VSS[234] VSS[338] T36 AJ24 VSS[74] VSS[ 153] AW48
D30 VSS[235] VSS[340] BG22 AJ33 VSS[75] VSS[ 154] AV11
D32 VSS[236] VSS[342] BG24 AJ34 VSS[76] VSS[ 155] AY12
D34 VSS[237] VSS[343] C22 AK12 VSS[77] VSS[ 156] AY22
D38 VSS[238] VSS[344] AP13 AK3 VSS[78] VSS[ 157] AY28
D42 VSS[239] VSS[345] M14 VSS[79] VSS[ 158]
D8 VSS[240] VSS[346] AP3 CougarPoint_R ev _1p0
E18 VSS[241] VSS[347] AP1
E26 VSS[242] VSS[348] BE16
G18 VSS[243] VSS[349] BC16
G20 VSS[244] VSS[350] BG28
G26 VSS[245] VSS[351] BJ28
G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
CougarPoint_Rev_1p0
B - 22 PCH/ GND
Schematic Diagrams
New Card, Mini PCIE
NEW CARD(Port 3)
Sheet 22 of 46
New Card, Mini
PCIE
10 /2 9
MINI CARD WLAN 20 mil R6 8 5 0 _ 06

V D D 3 3 . 3V
R6 8 6 * 0_ 0 6 1125
C 47 2
1125 0 . 1 u _1 6 V _ Y 5 V _ 04
J _ MI N I 1
R6 0 5 0_ 0 4 1 2
15 , 2 4 , 27 P C I E _ W A K E # 3 W AKE# 3 . 3V A U X _0 6
5 CO E X 1 1 . 5 V _0 8
R 4 90 1 0 K _ 04
11/18 V D D3
R 6 80 * 1 0K _ 0 4 CO E X 2 U I M _P W R 10 R 55 2 * 0_ 0 4 B T _S B D #
V D D3
3 .3 V 7 U I M_ D A T A 12
1 4 W L A N _ C L K R E Q# 11 C L K R E Q# U I M_ C L K 14 8 0 CL K 28
R 49 1 1 0 K _0 4
1 4 CL K _ P CIE _ M INI# 13 REF C L K - U I M_ R E S E T 16
1 4 C L K _ P C I E _M I N I 9 REF C L K + U I M_ V P P 3 IN1 28
15 GN D 0 4
GN D 1 G ND5
W243 1117 ? ? 3.2
KEY
21 18
27 GN D 2 G ND6 26
29 GN D 3 G ND7 34
GN D 4 G ND8 40
35 G ND9 50
28 W L A N _ D E T# GN D 1 1 G N D 10
23
14 P C I E _ R X N 3 _ W L A N 25 PET n 0 20
1 4 P C I E _R XP 3_ W L A N PET p 0 W _ D I S A B LE # W L A N _ E N 2 8, 2 9
31 22
1 4 P C I E _T X N 3 _ W L A N 33 P ERn 0 P E R S E T# 30 B U F _P LT _ R S T # 1 7, 2 4 , 2 5, 2 7 , 2 8
1 4 P C I E _ T XP 3_ W L A N P ERp 0 S MB _ C L K 32
17 S MB _ D A T A 36 U S B _D # B T _ D E T # 2 8, 2 9
R 35 7 *1 0 mi l _0 4 U S B _P N 2 1 7
R4 9 4 *0 _ 04 19 R e s e rv ed 0 U S B_ D- 38 U S B _D R 35 6 *1 0 mi l _0 4
2 8 , 29 B T _E N 37 R e s e rv ed 1 US B_ D+ U S B _P P 2 1 7
R 6 81 0_04 39 GN D 1 2 24 R 48 9 0_ 0 4
V DD 3 3 . 3V A U X _ 3 3 . 3V A U X _1 VD D3
R 6 82 * 0 _0 4 41 28
1125 3 .3 V 43 3 . 3V A U X _ 4 1 . 5 V _1 48
CL _ CL K _ 1 45 GN D 1 3 1 . 5 V _2 52
1125
R199 , R204 , R498 ? ? 0_04 for Vpro 14 C L _C L K 1 R 1 99 * 0 _0 4 R6 8 4 *0 _0 4 3 .3 V
R 2 04 * 0 _0 4 CL _ DAT A _ 1 47 R e s e rv ed 2 3 . 3V A U X _2 42
Wake up on WLAN Function 14 C L _D A T A 1 CL _ RST # _ 1 49 R e s e rv ed 3 LE D _ W W A N # 44
14 C L _R S T #1 R 4 98 * 0 _0 4 W L A N_ L E D # 2 9
R4 9 9 * 1 0K _ 0 4 51 R e s e rv ed 4 L E D_ W L A N# 46
VDD 3 R e s e rv ed 5 LE D _ W P A N #
R5 0 1 0 _0 4 8 8 91 0 -5 20 4 M-0 1
2 8 ,2 9 B T _E N 1228 D02
B T _S B D # R5 5 3 *0 _ 04
14 B T _S B D #
3, 6, 8 , 9 , 1 0, 2 0 , 2 7, 3 2 , 3 4 1. 5 V
1 9, 3 0 , 3 2 1. 5 V S
2, 3 , 8 , 1 1 , 13 , 1 5 , 17 , 1 9 , 20 , 2 3 , 2 7, 2 9 , 3 1, 3 2 , 3 4, 3 6 3 .3 V
3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 17 , 1 8 , 19 , 2 0 , 23 , 2 4 , 25 , 2 6 , 2 8, 2 9 , 3 0, 3 1 , 3 2, 3 7 3 .3 VS
13 , 1 4 , 15 , 1 7 , 18 , 2 0 , 23 , 2 4 , 2 5, 2 8 , 3 2, 3 3 , 3 5, 3 9 V D D3
New Card, Mini PCIE B - 23

Schematic Diagrams
CCD, 3G, TPM

MINI CARD 3G(Port 6) 3G POWER
3. 3 V S 3 .3 V R 5 09 *0 _0 6
3 G_ 3 . 3V
R 51 1 0_06 Q 30 3 G _3 . 3 V
J _ 3 G1 60 mils >48 mil A O3 4 1 5 >48 mil
1 2 R 51 2 * 0 _0 6 3 G_ R S D
3 W AKE# 3. 3V A U X_ 0 6
5 C OE X 1 1 . 5V _ 0 8 U I M_ P W R
C OE X 2 U I M _P W R 10 U I M_ D A TA C2 0 9 C2 8 7 C5 0 0 C 5 07 C 48 3
U I M_ D A T A
G
7 12 U I M_ C LK C2 1 2 + R5 1 5
11 C LK R E Q# U I M_ C L K 14 U I M_ R S T 0 . 1u _ 16 V _ Y 5 V _ 0 4 22 0 u _6 . 3 V _ 6. 3 *6 . 3 *4 . 2 10 u _ 10 V _ Y 5 V _ 0 8 0 . 1 u _1 6 V _ Y 5 V _0 4
13 R EF CL K - UIM _ RE SE T 16 U I M_ V P P 0 . 1u _ 16 V _ Y 5 V _ 0 4 0 . 1 u_ 1 6V _ Y 5V _ 0 4 R5 2 0 1 0 _0 6
9 R EF CL K + U I M_ V P P
15 G ND0 4 1 00 K _ 04
D
G ND1 GN D 5
W243 1117 ? ? 3.2 R 5 19 Q3 3
G MT N 70 0 2Z H S 3
KEY
S
21 18 33 0 K _0 4
27 G ND2 GN D 6 26 Q3 5
29 G ND3 GN D 7 34 G
2 8 3 G _P W R _ E N MT N 7 0 02 Z H S 3
G ND4 GN D 8 40
GN D 9
S
35 50
28 3 G_ D E T # 23 G ND1 1 G ND1 0
PET n 0 From H8 default HI
25 20
31 PET p 0 W _ DIS AB L E # 22 3G _E N 28
33 P E R n0 P ERS ET # 30
P E R p0 S MB _ C L K
S M B _ DAT A
32
SIM CONN
17 36
3 G_ 3 . 3V 19 R es e rv e d0 U S B _D - 38 U S B _ P N4 1 7
37 R es e rv e d1 USB _ D+ U SB_ PP4 1 7
39 G ND1 2 24
41 3 .3 V A UX _ 3 3. 3V A U X_ 1 28 3G _3 . 3 V
43 3 .3 V A UX _ 4 1 . 5V _ 1 48 U I M _P W R R 50 3 *4 . 7 K _0 4 U I M_ D A TA
C2 4 2 C2 6 7 45 G ND1 3 1 . 5V _ 2 52 C2 3 5
R es e rv e d2 3. 3V A U X_ 2 3G _ 3. 3 V
47 42
49 R es e rv e d3 LE D _ W W A N # 44
0 . 1u _ 16 V _ Y 5 V _ 0 4 10 u _ 10 V _ Y 5 V _ 08 0 . 1u _ 16 V _ Y 5 V _ 0 4
R es e rv e d4 L E D_ W L AN#
Sheet 23 of 46 51
R es e rv e d5 LE D _ W P A N #
M P C E C -S 0 0F 1 -T P 0 0
46
+
C2 8 6
2 20 u _ 4V _ V _ A R5 0 4
J _S I M1
L OCK R4 8 8
1228 D02 *1 0 mi l _0 4 ( TO P V IE W) *1 0 mi l _0 4
CCD, 3G, TPM U I M _C L K

U I M _R S T
U I M _P W R
UIM _ C C 3
C 2
C 1
U I M _C LK
U I M _R S T
U I M _P W R
U I M_ D A TA
U I M _V P P
U I M_ G N D
C 7 U I M _D
C6
C5
U I M _D A T A
U I M _V P P
C4 7 0 C4 6 9 C 47 1
OPE N
C 4 8 9 C 1 7 7 06 6 1-1 S I M L OC K *2 2 p_ 5 0V _N P O_ 0 4 *2 2 p_ 5 0V _N P O_ 0 4 * 22 p _5 0 V _ N P O _0 4
*2 2p _ 5 0V _ N P O_ 04
3 . 3V S
TPM 1.2
As se rte d befo re en te ring S3
C5 0 8 C2 8 5 C2 9 4 C3 0 0
L PC r ese t timing :
L PCPD# ina cti ve to L RST# ina ct ive 3 2~96 us
0 . 1u _ 16 V _ Y 5 V _ 0 4 0 . 1u _ 16 V _ Y 5 V _ 0 4 0 . 1u _ 16 V _ Y 5 V _ 0 4 1u _ 1 0V _ Y 5V _ 0 6 CCD
U 28 5V 5 V _ CC D
26 10 U4 1
13 , 2 8 L P C_ A D0 L AD0 VD D1 48 mil
23 19 4 1
13 , 2 8 L P C_ A D1 20 L AD1 VD D2 24 5 V IN V O UT
13 , 2 8 L P C_ A D2 17 L AD2 VD D3 V IN
13 , 2 8 L P C_ A D3 L AD3 MJ_CCD1
C2 R1 1 C 6 C 5 C 4
21 3 2 1
17 P C LK _ T P M L CL K TPM EN G ND
*1 u _ 6. 3 V _ Y 5 V _ 04 *1 0 0K _0 4 0 . 1 u _1 6 V _ Y 5 V _ 04 1 u _ 6. 3 V _ Y 5 V _ 04 1 u _ 6. 3 V _ Y 5 V _ 04
22 5 R6 4 0 *0 _0 4 G5 2 43 A
1 3 , 28 L P C _ F R A ME # L F RAM E # VSB 3 . 3V S
16 5
3 , 17 P L T _R S T # 27 L RE S E T #
1 3 , 28 SE R IRQ C2 8 2 R6 4 1 0_ 0 4 V DD 3
15 S ER IRQ
15 P M _C LK R U N # CL K R UN #
0 . 1u _ 16 V _ Y 5 V _ 0 4 J _C C D 1
R 6 42 * 0_ 0 4 TP M _ LP C P D # 28 6 T P M3 0 0 4
1 5 S 4_ S T A T E # L PCPD # GP I O 2 T P M3 0 0 5 28 C C D _E N 1
W243 1117 17 USB _ P N5
T P M_ B A D D 9 G P I O2 2
T ES T B I/BA DD 17 U S B _P P 5 3
R7 1 9 1 0 K _ 04 13 XTAL I CC D_ DE T #
V DD 3 7 XT A L I 28 C C D _ D E T# 4
TP M _P P
1228 D02 PP X7 5
14 XTAL O 4 1 M C -1 4 6_ 3 2 . 76 8 K H z 8 52 0 5-0 5 0 01
T P M 30 0 1 1 XT AL O 3 2 6 -22 -3 2R7 6- 0B4
HI: ACCESS NC _ 1 From H8 default HI
T P M 30 0 2 3 4 C 3 05 C 30 2
T PM _PP L OW: NORMAL ( Inte rnal PD) T P M 30 0 3 12 NC _ 2 G ND_ 1 11
NC _ 3 G ND_ 2 18
HI: 4E/ 4F H 1 8 p _5 0 V _ N P O_ 0 4 1 8 p _5 0 V _N P O_ 0 4
8 G ND_ 3 25
T PM _BADD L OW: 2E/ 2F H T ESTI G ND_ 4
S L B 9 6 35 T T
R3 4 9 C 2 92 X TA L O
P C LK _ T P M P C LK _ T P M1 13 , 1 4, 15 , 1 7, 1 8 , 2 0, 2 2 , 2 4, 2 5 , 2 8, 3 2 , 33 , 3 5 , 39 V D D 3
2 , 3, 8 , 1 1, 13 , 1 5, 1 7 , 1 9, 2 0 , 2 2, 2 7 , 2 9, 3 1 , 32 , 3 4 , 36 3 . 3 V
X TA L I Co -l ayo ut X 7, X8 3 , 9 , 10 , 1 1 , 12 , 1 3 , 14 , 1 5 , 16 , 1 7, 18 , 1 9, 2 0 , 2 4, 2 5 , 2 6, 2 8 , 2 9, 3 0 , 31 , 3 2 , 37 3 . 3 V S
*3 3_ 0 4 *1 0p _ 5 0V _ N P O_ 06 2 7 , 3 1, 3 2 , 34 , 3 5 , 36 5 V
3 . 3V S
1 4 X8
T P M_ L P C P D # R 6 43 *1 0K _0 4 2 3
*1 T J S 12 5 D J 4 A 42 0 P _ 32 . 7 6 8K H z
T P M_ P P R 3 41 *1 0K _0 4
6- 22 -32 R7 6-0 B2
T P M_ B A D D R 3 48 10 K _ 1 %_ 0 4 6- 22 -32 R7 6-0 BG
R 3 52 *1 0K _1 % _0 4
B - 24 CCD, 3G, TPM

Schematic Diagrams
Card Reader/LAN JMC261C

S D _C L K
JM C2 61 C C 4 54 ne ar P in #41
S witching Regulator
c lose to PIN33
3. 3V _ LA N _C 1124
3. 3V S V D D 3
*1 0p _5 0V _N P O_ 04 DV DD R 4 25 *4. 7K _ 04
SD _ C LK R 4 48 22 _1% _0 4 (>20mil) L3 7 10/29 U 35
R E GLX . DV DD L A N _S C L R 4 26 *4. 7K _ 04 8 7
1 229 D 02 (W 240 HU ) 11 24 (>20mil ) V CC WP MP D R 2 16 10 K_ 04
SD X C _P OW ER S WF 2 520 C F 4- R 7M-M C 17 7 C 44 8 6
3. 3 VS L A N _S D A 5 S CL 1 R 2 17 *4. 7 K_ 04
3 . 3V _L AN _ C
S D X C _P OW ER
S DA A0 2
IS ON _ 25 1C
S D _C L K _C
C 1 65 For JMC251/261 only 10 u_ 6. 3V _ X5R _ 06 0. 1u _1 6V _Y 5 V _04
R 497 *4. 7 K_ 04 S D _C D # C 17 0 P in #3 3 Pi n#3 3 4 A1 3
GN D A2
S D _B S
R E GLX
S D _D 3
S D _D 2
SD _ D 1
SD _ D 0
DV DD
0 1. u_ 16 V_ Y 5V _0 4 2. 2 u_ 6. 3V _X 5R _ 06 C 4 40 0. 1 u_1 6V _ Y 5V _0 4
R 493 10 K_ 04 MS _I N S # *A T2 4C 02 B N
VD D 3
V C C _C A R D
R 158 1K _0 4 S D _W P
47
46
45
44
38
37
36
35
0 104 D02
48
43
42
41
40
39
34
33
U 36
GN D
LX
R 20 7
MD I O1 1
Car d R ead er Pull Hi gh/ Low
V DDIO
V DDO
GN D
LA N _L E D 0
LA N _L E D 1
MD I O5
MD I O4
MD I O3
MD I O2
MD I O1
MD I O0
F B 12
IS ON
*28 mi _l 06
Res ist ors V D D R EG 3. 3V S
(>20mil) (>2 0mil) (>20mil)
49 32 V DDRE G
50 MD I O10 V D D R EG 31 (>20mil)
MD I O8 51 MD I O9 V CC3 V 30 3 . 3V S C 199 C 1 98 C 4 43 C 4 42
R 16 2 *2 0m li _0 4 A V D D 12_ 52 52 MD I O8 P WR C R 29 V C C _ C AR D
DV DD
L AN _ MD I P0 _C 53 V DD TE S T 28 MP D 10u _6 . 3V _X 5R _ 06 0 . 1u _1 6V _Y 5 V_ 04 * 10u _6 . 3V _Y 5 V_ 06 0 . 1u _16 V _Y 5V _ 04
L AN _ MD I N 0_ C 54 V I P_ 1 MPD 27 LA N _ PC I E _W A KE # P in #32 P in #3 2 P in# 31 P in #3 1
DV DD R 15 6 *2 0m li _0 4 A V D D 12_ 55 55 V I N _1 WA K EN 26 LA N _ SC L 3. 3 V_ LA N _ C V DD3
L AN _ MD I P1 _C 56 A V D D 12 L AN _ LE D 2 25 LA N _ SD A
L AN _ MD I N 1_ C 57
58
V I P_ 2
V I N _2
GN D
JMC261 C C R _L ED
R S TN
C P P EN
24
23 C P PE N BU F _ PL T_ R ST # 17 , 22 , 25, 2 7, 2 8 V DD3
R 4 31 *0_ 06
59 22 1 1 /02 112 4
3 .3 V _LA N _ C L AN _ MD I P2 _C 60 A V D D 33 GN D 21 I S ON _2 51 CR 19 1 *20 mil _0 4
V I P_ 3 (LQFP 64) VD D I O 3 . 3V _L A N _C
11 24 L AN _ MD I N 2_ C 61 20 S D _W P 112 4
DV DD R 14 4 *2 0m li _0 4 A V D D 12_ 62 62 V I N _3 MD I O6 19 R 19 0 * 100 K _0 4 3 . 3V _L AN _ C
L AN _ MD I P3 _C 63 A V D D 12 MD IO 1 2 18
64 V I P_ 4 MD IO 1 4 17 S D _C D #
V I N _4 C R _ C D 0N
C R _ C D 1N
R 4 34 10K _ 04
A VD D 3 3
A V D D 12
AV D D 1 2
MD I O13
M D I O7
D1 6
CL K P
RE X T
C LK N
XOU T
RX N
GN D
RX P
T XN
T XP
P C IE _ WA K E# A C L A N _P C I E_ WA K E #
XNI
15 , 22 ,2 7 P C I E_ WA K E # LA N _P C I E _W A KE # 2 8
JMC 2 61 _C PCIe Differential 112 4
12
AV D D 1 2_1 3 1 3
14
15
*R B 75 1S -40 C 2
1
2
3
4
5
6
7
*20 mil _0 4 8
9
10
11
16
Pairs = 100 Ohm
R E XT _C
A V D D 12 _7
C R _ C D 1N
LA N X OU T
Sheet 24 of 46
LA N X I N
MD I O13
M D I O7
R 14 2 4 IN 1 SOCKE T SD/ MMC/MS /MS Pr o
12 K_ 1%_ 04
P1
J_ C A R D -R EV 1
Card Reader/LAN
R 14 5
D VD D R 14 6
SD _ C D #
*20 mi l_ 04
A V D D 12 _7 A V D D 12 _1 3 Card Reader SD _ D 2 P2 CD_ S D
3. 3 V_ LA N _C Power SD _ D 3 P3 D A T 2_S D
C 4 35 C 1 39
1 124
DV DD
R 1 36
R 4 27
*0_ 04
*20 mi l_ 04
MS _I N S #
1 1/0 2 V C C _C A R D
V C C _ C AR D
SD _ B S
SD _ C LK
P4
P5
P6
P7
C D / D A T 3_S D
C MD _ S D
V S S _S D
V D D _ SD
JMC261C
0 . 1u _16 V _Y 5 V_ 04 0 . 1u_ 16 V_ Y 5V _ 04 PC I E _R X P _4_ GLA N C 43 3 0 . 1u_ 10 V _X7 R _0 4 C 4 82 P8 C L K _S D
P in #7 P in #13 PC I E _R X N _4 _GL AN C 43 4 0 . 1u_ 10 V _X7 R _0 4 PC I E _R X P4 _GL A N 1 4 SD _ D 0 P9 V S S _S D
P C IE _ R XN 4 _GLA N 14 0 . 1u_ 16 V_ Y 5V _ 04 SD _ D 1 P 10 D A T 0_S D
SD _ WP P 11 D A T 1_S D
R 7 24 R 72 3 R 49 6 P 12 W P _S D
A V D D 12 _5 2 A V D D 12 _5 5 A V D D 12 _62 A V D D 12 _7 1 50 _0 6 15 0_0 6 *7 5_0 4 P 13 V S S _MS
P C I E _T XN 4 _GLA N 14 V C C _ C AR D SD _ C LK P 14 V C C _ MS
P C I E_ TX P4 _GL A N 1 4 SD _ D 3 P 15 S C L K_ MS
C L K _P C I E_ GLA N 14 C 4 79 D A T 3_M S
MS_ I N S# P 16
C 4 45 C 1 57 C 1 45 C 1 36 LA N XOU T C L K_ PC I E _ GLA N # 14 0 . 1u_ 16 V_ Y 5V _ 04 SD _ D 2 P 17 I N S _MS
SD _ D 0 P 18 D A T 2_M S
0 . 1u _16 V _Y 5 V_ 04 0 . 1u_ 16 V_ Y 5V _ 04 0 .1 u_ 16 V_ Y 5V _0 4 *1 0u _6. 3 V _X5 R _0 6 SD _ D 1 P 19 S D I O/ D A T0 _MS
P in #5 2 P in #55 P in# 62 P in# 7 R 4 28 *1M_ 04 LA N XI N 0 22 4 SD _ B S P 20 D A T 1_M S P2 2
R ese rv ed P 21 B S _MS GN D P2 3
X 10 V S S _MS GN D
2 1 For JMC251 C MD R 01 9-C 0 -104 2
0103 D0 2 R3. 2_1 2_31
3. 3V _ LA N _C 11 24 FS X5 L_ 25 MH Z
X9 11 24
3. 3 V_ LA N _C
3 4
C 1 34 C 1 48 C 45 0 C 1 95 ? ? ? ? P IN 6?
2 1
VD D 3
0 . 1u _16 V _Y 5 V_ 04 0 . 1u_ 16 V_ Y 5V _ 04 C 43 1 *F S X5 L_ 25MH z C 4 32 0. 1u _1 6V _Y 5 V _0 4 *10 u_ 6. 3V _X 5R _ 06
P in #4 3 P in #43
2 2p_ 50 V_ N P O_0 4 2 2p _50 V _N P O_0 4 Pin #2 P in #2 2A
V DD3
P C 1 02 1. 2V
U2 0 1 u_ 10 V_ Y 5V _0 6
5 6 DV DD
3. 3V _ LA N _C 11 24 P C9 9 P R 11 5 9
7
VI N
VI N
V C N TL
4
1A
6-22-25R00-1B4
0_ 04 POK VOU T
0 . 1u _1 6V _Y 5V _ 04
6-22-25R00-1B5 V C C _C A R D V C C _C A R D 3
C 1 33 C 1 35 C 1 89 C 4 37 8 VOU T PR 1 16
EN
1. 6K _1 %_ 04
1 2
P*1in0u#5_69. 3V _X 5R _ 06 0P .in1u_#5916 V_ Y 5V _ 04 P0 in#
.1 u_216 V_ Y 5V _0 4 0P 1.in#u_2116 V_ Y 5V _0 4
C 4 78 C 4 81 C 4 80 GN D VF B
R es er ved PC 9 8
*0 . 1u_ 16 V_ Y 5V _ 04 * 0. 1u _1 6V _Y 5 V_ 04 *0 . 1u _16 V _Y 5 V_ 04 A X 66 1 5E S A
82p _5 0V _N P O_ 04
P la c e all c ap a c ito rs clo s e d to ch ip .
Ne ar Car dre ade r CO NN P R 114
T h e s u b s c rip t in ea c h CA P in cic a te s th e pin G S71 13 2. 4 9K _1 %_0 4
n u mb e r o f JM C2 5 1/ JM C 2 61 th a t s h o u dl b e 6 -02 -07 113 -320
clo s e d t o . A X66 10 12 28 D0 2
6 -02 -06 610 -320
1 3, 1 4, 15 , 17 ,1 8, 2 0, 22 , 23 ,2 5, 2 8, 32 , 33 3, 5, 3 9 V D D 3
3, 9, 1 0, 11 , 12 ,1 3, 1 4, 15 , 16 ,1 7, 1 8, 19 , 20 ,2 3, 2 5, 26 , 28 ,2 9, 3 0, 31 , 32 ,3 7 3 3. V S
3 , 6, 8, 9 1, 0, 2 0, 27 , 32 ,3 4 1 5. V
23 , 27 ,3 1, 3 2, 34 , 35 ,3 6 5 V
Card Reader/LAN JMC261C B - 25

Schematic Diagrams
INTEL LAN 82579

3.3 V_M 3. 3V_M 3. 3V_LAN 1. 05V_LAN_M 1. 0M_LAN
C3 C8 R12 *s ho rt _0 8 R 273 *shor t_08

0.1u_16 V_0 4 0.1 u_1 6V_ 04
0324-J C 10 C3 2 0324-J C590 C 591
change short change short
0 .1u_16V_04 10 u_6. 3V_ X5R _06 0. 1u _16 V_0 4 10u _6.3V_X5R _06
0324-J
add 3. 3VS VDD 3
R6 10 R61 1
*10K_04 10K_04 11/1 9
U 47
48 13 LAN_MD I P0
14 IGLAN _C L KREQ# 36 CL K_R EQ_N MD I_ PLU S0 14 LAN_MD IP0 26
1 7,22, 24 ,27, 28 BUF_PLT_RST# LAN_MD I N0
PE_R ST_ N MD I_MI NU S0 LAN_MD IN 0 2 6
Sheet 25 of 46 14 CL K_PC IE_I GLAN
14 C LK_PCI E_IG LAN #
44
45 PE_C LKP MD I_ PLU S1
17
18
LAN_MD I P1
LAN_MD I N1 LAN_MD IP1 26
PCIE
LAN_MD IN 1 2 6
MDI
PE_C LKN MD I_MI NU S1
INTEL LAN 82579 1 4 PC IE_RXP6_IG LAN C185
C215
0.1u_10 V_X7R _04 PC I E_R XP6 _C _GLAN
0.1u_10 V_X7R _04 PC I E_R XN 6_C_GL AN
38
39 PETp MD I_ PLU S2
20
21
LAN_MD I P2
LAN_MD I N2 LAN_MD IP2 26
14 PCI E_R XN 6_IG LAN PETn MD I_MI NU S2 LAN_MD IN 2 2 6
41 23 LAN_MD I P3
1 4 PC IE_TXP6_ IGL AN 42 PERp MD I_ PLU S3 24 LAN_MD I N3 LAN_MD IP3 26
14 PCI E_TXN 6_ IGL AN PERn MD I_MI NU S3 LAN_MD IN 3 2 6
R 638 0_04 28 6 +VCT_L AN

11/18
SMBUS
14 SML0_C LK 31 SMB_ CLK VC T
R 639 0_04
14 SML0_D ATA SMB_ DATA 1 R 612 4. 7K_04 3. 3V_LAN
R613 10K_04 RSVD _VC C3P3_1 2 R 614 4. 7K_04
VDD 3 RSVD _VC C3P3_2 5
R615 0_04 3 VDD 3P3_I N
1 8 PM_LANPH Y_EN LAN _D ISABL E_N 4 +V3. 3M_LAN _O UT C4 67 1u_ 6. 3V_X5 R_ 06
R616 *1 0K_ 04 VD D3P3_OU T
15
26 VDD 3P3_15 19
27 LED 0 VDD 3P3_19 29
11/18
LED
25 LED 1 VDD 3P3_29 1 .0M_LAN
R 617 1 0K_04 LED 2
3. 3V_ LAN R 618 1 0K_04 47 R 24 *sh ort_ 08
VDD 1P0_47 46
LAN_JTAG_ TD I 32 VDD 1P0_46 37
LAN_JTAG_ TD O 34 JTAG_ TD I VDD 1P0_37
JTA G
LAN_JTAG_ TMS 33 JTAG_ TD O 43
LAN_JTAG_ TC K 35 JTAG_ TMS VDD 1P0_43
JTAG_ TC K 11
VDD 1P0_11 NOTE
R619 0_04 LAN_XTAL_ OU T 9 40 1.0M_LAN Will Work at 0. 95V to 1.15V
LAN_XTAL_ IN 10 XTAL_ OU T VDD 1P0_40 22
XTAL_ IN VDD 1P0_22 16
VDD 1P0_16 8
X16 25MH z LAN _TEST_EN 30 VD D1P0_8 1. 0M_LAN
2 1 TEST_EN R 17 *0_ 06
RES_BIAS 12 7 R 16 *0_ 06
RBI AS CTRL_1 P0
2 7P_50V_NPO_0 4
49
27P_ 50V_N PO_04
C 592 C593 VSS_ EPAD

R 620 R621 8257 9LM/ V
1K_04 3. 01 K_1 %_0 4
13,1 5, 19 ,26, 32 3.3 V_M

13 ,14, 15,1 7, 18,20, 22 , 23,24, 28,3 2, 33 ,35, 39 VD D3
2 0, 32,35 1.05V_LAN_M
3 ,9,1 0, 11 ,12, 13,14,1 5, 16,17, 18 ,19, 20,2 3, 2 4, 26 ,28, 29,3 0, 31,32, 37 3.3 VS
B - 26 INTEL LAN 82579

Schematic Diagrams
LAN (82579), SATA HDD, ODD

1 L25 2
GIGA LAN (82579) 4 3

*W C M 2 01 2 F 2 S -S H O R T
L29 1 L2 6 2
W243 1117 J _ RJ 1
L A N _ MD IP 0 12 13 L MX 1 + 4 3 DL M X1 + 1 GN D 1
3. 3 V _ M 25 L A N_ M DIP 0 L A N _ MD IN0 11 T D4 + M X 4+ 14 L MX 1 - *W C M2 0 12 F 2 S -S H OR T DL M X1 - 2 DA + sh i el d GN D 2
25 L A N_ M DIN0 L A N _ MD IP 1 9 T D4 - M X 4- 16 L MX 2 + DL M X2 + 3 DA - sh i el d
25 L A N_ M DIP 1 L A N _ MD IN1 8 T D3 + M X 3+ 17 L MX 2 - DL M X2 - 6 DB +
25 L A N_ M DIN1 T D3 - MX 3 - 1 L27 2 DB -
GN D
R7 5
L A N _ MD IP 2 6 19 L MX 3 + 4 3 DL M X3 + 4
*0 _ 0 4 25 L A N_ M DIP 2 L A N _ MD IN2 5 T D2 + MX 2 + 20 L MX 3 - *W C M 2 01 2 F 2 S -S H O R T DL M X3 - 5 DC +
25 L A N_ M DIN2 L A N _ MD IP 3 3 T D2 - M X 2- 22 L MX 4 + DL M X4 + 7 DC -
25 L A N_ M DIP 3 T D1 + MX 1 + DD +
L A N _ MD IN3 2 23 L MX 4 - DL M X4 - 8
25 L A N_ M DIN3 T D1 - MX 1 - 1 L2 8 2 DD -
10 15 P J S -0 8 S L 3B
7 T CT 4 MC T4 18 4 3
4 T CT 3 MC T3 21 *W C M2 0 12 F 2 S -S H OR T
1 T CT 2 MC T2 24
W240HU PJS-08SL3B
T CT 1 MC T1 0101D02 W250HU PJS-08SO1B-1
C5 4 C3 4 3 C3 4 2 C3 4 1 G S T 50 0 9 LF
0 . 0 1u _ 1 6V _ X 7 R _ 0 4 *0 . 0 1u _ 1 6V _ X 7 R _ 0 4
*0 . 0 1 u_ 1 6 V _X 7 R _ 0 4 *0 . 0 1u _ 16 V _ X 7 R _ 04 N MC T_ 1 R4 0 2 7 5_ 1 % _0 4 NM CT _ R
N MC T_ 2 R3 9 9 7 5_ 1 % _0 4
N MC T_ 3 R3 9 7 7 5_ 1 % _0 4
N MC T_ 4 R3 9 4 7 5_ 1 % _0 4
C3 3 5
10 0 0 p_ 2 K V _ X 7R _1 2
Sheet 26 of 46
LAN (82579), SATA
HDD, ODD
SATA HDD SATA ODD

Zero Power ODD 5 VS
J _ HD D1
S1 J _ OD D 1
S2 SATA_ T XP0 C4 8 7 0 . 0 1 u_ 1 6 V _X 7 R _ 0 4 S1
S3 S A T A _ T X N0 C4 8 6 0 . 0 1 u_ 1 6 V _X 7 R _ 0 4 S A TA T X P 0 1 3 G ND 1 S2 C4 3 0 0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
S4 S A TA T X N 0 1 3 A+ S3 S A TA T X P 2 1 3
C4 2 8 0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
S5 SA T A_ RXN 0 C4 8 5 0 . 0 1 u_ 1 6 V _X 7 R _ 0 4 A- S4 S A TA T X N 2 1 3
S6 S A TA R X N 0 1 3 G ND 2 S5
SA T A_ RXP0 C4 8 4 0 . 0 1 u_ 1 6 V _X 7 R _ 0 4 C4 2 5 0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
S7 S A TA R X P 0 1 3 B- S6 C4 2 1 0 . 0 1 u_ 1 6 V _X 7 R _ 0 4 S A TA R X N 2 1 3
B+ S7 S A TA R X P 2 1 3
3 . 3V S
G ND 3 ?? ?? ?? ?? ? C5 2 1 C5 2 2
P1 1.5A
P2 0 . 1u _ 1 6V _ Y 5V _ 0 4
P3 P1 5 V S _ OD D *0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
P4 DP P2 S A T A _ OD D _ P R S N T # 18 U4 2
P5 V_ 5 0 P3 S A T A _ OD D _ D A # 1 7 1 4
P6 V _5 0 _ 1 P4 V OU T V IN 5
P7 MD P5 V IN
5V S
P8 G ND 4 P6 C4 1 1 C4 1 0 C 40 8 C4 0 4 +C 3 93
P9 1A G ND 5 2 3
S A TA _O D D _P W R GT 1 8
P1 0 C 18 5 5 3-1 1 3 05 -L * 10 0 u _6 . 3 V _ B 2 G ND EN
P1 1 H D D _N C 0 0 . 1u _ 1 6V _Y 5V _0 4 0 . 1u _ 1 6V _ Y 5V _ 0 4 1 u _6 . 3 V _ Y 5 V _ 04 1 0u _ 1 0V _Y 5V _0 8 G 52 4 3 A
*0 . 1 u _1 6 V _ Y 5 V _0 4
0 . 1u _ 1 6V _ Y 5 V _ 0 4
0 . 1u _ 1 6V _ Y 5 V _ 0 4
1u _ 6 . 3 V _Y 5 V _ 0 4
10 u _ 10 V _ Y 5 V _ 08
P1 2
P1 3 H D D _N C 1 R5 5 5 10 0 K _ 04
P1 4 H D D _N C 2
P1 5 H D D _N C 3
+ C 2 08
A L L T OP -C 16 6 N 5 -1 2 20 5 -L
P IN G ND 1 ~ 2 = G ND *1 00 u _ 6. 3 V _ B _ A
5V S 1 1 , 12 , 1 9 , 2 0, 3 0 , 3 1, 3 2 , 3 7, 3 8
C4 7 6
C4 7 3
C4 7 4
C4 7 5
C2 1 0
3. 3 V _ M 1 3 , 15 , 1 9 , 2 5, 3 2
3. 3 V 2 , 3 , 8 , 11 , 1 3 , 15 , 1 7 , 19 , 2 0 , 22 , 2 3 , 2 7, 2 9 , 3 1, 3 2 , 3 4, 3 6
1. 5 V 3 , 6 , 8 , 9, 1 0 , 2 0, 2 7 , 3 2, 3 4
3. 3 V S 3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 19 , 2 0 , 23 , 2 4 , 25 , 2 8 , 29 , 3 0 , 3 1, 3 2 , 3 7
W240HU ALLTOP-C166N5-12205-L
W250HU 1-162-100561
LAN (82579), SATA HDD, ODD B - 27

Schematic Diagrams
USB3.0 NEC, USB CHARGER

3. 3 V 3. 3 V A 1. 0 5V 3. 3 V A
L 65
. W/O U SB Cha rg er
RE /R F 1 0 /2 9
C 77 4 H C B 1 60 8 KF - 1 21 T 25 C 77 5 C 77 6 C 7 77
0. 1 u_ 1 0V _ X5 R _ 04 G_ D M0 _0 R 55 6 0 _ 04 U S B _P N 1_ A
0 . 1 u_ 10 V _X 5R _0 4 0. 1 u_ 10 V _ X5 R _0 4 C7 7 8 C 7 79
0 . 1 u_ 10 V _X 5 R _0 4 C 78 0 G_ D P 0_ 0 R 55 7 0 _ 04 U S B _P P 1 _A
0 . 1u _1 0 V _X 5R _ 0 4 5p _5 0 V _N P O_ 0 4
0 . 01 u_ 16 V _X 7 R _0 4
C 7 82
C7 8 4
0 . 01 u_ 1 6V _ X7 R _ 04
C 78 6 C7 8 8
C7 9 0
0 . 01 u _1 6V _ X7 R _ 04 3 . 3V A USB C har ger c omp one nt s
0 . 01 u_ 16 V _ X7 R _0 4 0 . 0 1u _1 6V _ X 7R _ 0 4 0 . 01 u _1 6V _ X7 R _ 04 V DD5 V C C _ T PS 2 54 0
17
C 78 3 C 7 89 80 mil U 43 80 mil
0. 0 1u _ 16 V _X 7R _0 4 0. 0 1u _ 16 V _X 7R _0 4 1 12
PPAD
C 78 1 C 78 5 C 78 7 C 7 91 IN O UT
0 . 0 1u _1 6V _ X7 R _ 04 0. 0 1u _ 16 V _X 7R _0 4 0 . 0 1u _1 6V _ X 7R _ 04 0. 0 1 u_ 16 V _X 7 R _0 4 C 79 2 C 79 3 G_D M0_ 0 2 11 U S B _P N 1 _A
D M _O D M_I N
0 . 1 u_ 10 V _X 5 R _0 4 G_D P 0_ 0 3 10 U S B _P P 1_ A
D 10
L14
H1 1
K1 1
K1 2
P1 3
DP_ O D P _I N
F1 3
F 14
G 4
L1 0
L 13
C 8
E 11
E 12
H 4
0 . 01 u _1 6V _ X7 R _ 04
F3
G3
N4
N5
N6
P3
C4
C5
C6
C7
D5
C9
D8
D9
E3
E4
H3
L8
D7
L9
L5
U5 1 4 14 3 . 3V
I L I M_S E L GN D
V DD3 3
V DD3 3
V D D 33
V DD3 3
V DD3 3
V DD3 3
V D D 33
V D D 33
V DD3 3
V DD3 3
V D D 33
V D D 33
V DD3 3
V DD1 0
V D D 10
V D D 10
V DD1 0
V DD1 0
V D D 10
V D D 10
V DD1 0
V DD1 0
V D D 10
V D D 10
V DD1 0
V DD1 0
V DD1 0
V D D 10
V DD1 0
V DD1 0
V DD1 0
U 3A V D D 3 3
U2 A V DD3 3
VD D 33
VD D 10
VD D 10
R 56 0 *10 K _ 04 5 16 R 56 1 *17 . 8K _ 1 %_ 04
P P ON V D D 5 R 58 2 *0_ 0 4
E N/DS C I L I M0
6 15 R 56 3 *40 . 2K _ 0 4 R5 6 2
B2 28 , 32 , 33 D D _ON CT L 1 I L I M1
1 4 C LK _ P C I E _U S B 3 0 B1 P E CL K P B6 7 9
S S TX 2 R 5 64 *1 0K _ 04 1 0K _ 04
14 C L K _P C I E _ U S B 30 # P E CL K N U 3 T XD P 2 V D D5 CT L 2 NC
C 79 4 0 . 1u _1 0 V_ X 7R _ 0 4 D 2 A6 S S TX 2# R 5 65 *1 0K _ 04 A C _ I N 8 13 R 56 6 *0_ 0 4 G_ OC #
14 P C I E _R XP 2 _U S B 3 0 P E T XP U 3 TX D N 2 CT L 3 F A U LT #
1 4 PC I E_ R X N 2 _U S B 3 0 C 79 5 0 . 1u _1 0 V_ X 7R _ 0 4 D 1 P E T XN U 2 D M2
N8 U 2 D M2
D
F2 P8 U2 DP 2 Q37 *TP S 2 54 0
14 P C I E _T X P2 _ U S B 30 F1 P E RX P U 2D P 2 B8 S S RX 2 G *MT N 70 0 2Z H S 3
1 4 PC I E_ T XN 2 _ U S B 30 P E RX N U 3R XD P 2 2 8, 3 9 A C _I N #
M_ PQ FP16
S
3. 3 V A8 S S R X 2#
U 3R X D N 2
11 24 H2
1 7 2, 2 , 24 , 25 , 28 B U F _P L T _R S T #
R7 0 1 0 _0 4 P C I E _W A K E # _R K 1 P E RS T B
CTL 1 CTL 2 CT L3 : 0 X 1-- ---> De dic ate d Cha rg in g Po rt , Aut o-d e tec t
1 5, 2 2, 2 4 P C E I _ W A K E# K2 PEW AKEB G1 4 G_ OC #
1 4 PC I EC LK R Q 2# P E C R EQ B OC 2I B H1 3 CTL 1 CTL 2 CT L3 : 1 1 1- --- -> Ch ar g ing Do wn dtr ea m Por t, BC Spe c 1. 1
C
A U XD E T R 7 25 0_ 0 4 A U X D E T_ R J2 OC 1I B
J1 A UX DE T H1 4 P P ON
D6 3 R 70 3 3 . 3V R 70 2 1 0K _ 04 CTL 1 CTL 2 CT L3 : X 1 0-- ---> Sta nd ar d Dow nstr ea m Por t, USB 2.0 Mo de .
H1 PSEL P P ON 2 J1 4
1 3 U S B 30 _ SM I # S MI B P P ON 1 CL OS E TO C ON N EC TO R
R B 7 51 S - 4 0C 2 3 9 2K _ 1% _0 4
1 1 /0 1 1 0/ 28 St uf f
A
Sheet 27 of 46 C8 0 0
P5
U S B _ SP I _ S C L K M2
P ON R S TB
U 3 T XD P 1
B 10
A 10
S S TX 1
S S TX 1#
C 7 96
C 7 97
0 . 1 u_ 10 V _X 7 R _0 4
0 . 1 u_ 10 V _X 7 R _0 4
T XP 0 _R
T XN 0 _ R
W / US B 3. 0, U SB C ha rg er
R A/ RB , US B 3. 0 c om po ne nt s,
U SB C ha rg er c om p on en ts , RH
1 u_ 6 .3 V _ X5 R _ 04 U S B _ SP I _ C E # N 2 S P IS CK U 3 TX D N 1 N1 0 G_ D M0
USB3.0 NEC, USB U S B _ SP I _ S I

U S B _ SP I _ S O M1
N1 S P ICS B
S P IS I
S P IS O
U 2 D M1
U 2D P 1
U 3R XD P 1
P 10
B 12
G_ D P 0
S S RX 1
W / US B 3. 0, W /o U SB C ha r ge r
R A/ RB , US B 3. 0 c om po ne nt s,
R E/ RF , RG
uPD7 20200 A 12
CHARGER LO W PO WE R R 72 2 =0 _0 4
NO R P OW ER R7 22 = *0 _0 4
K1 3
K1 4
J1 3
G ND
G ND
G ND
U 3R X D N 1
S S R X 1#
W /o U S B3 .0 , US B Ch ar ge r R C/ RD , RE /R F, R G
AU XD E T _R R 7 26 *0 _0 4 R 72 2 0 _0 4 P4
G ND
RRE F
U 2A V S S
P 12 R 7 18
N1 2
1. 6 K _1 % _0 4
USB 3 .0/ PCH U SB 2.0 C o-l ayo ut
01 03 D 0 2 R 3. 2 12 _3 C1 4 N1 1
G ND U 2P V S S 1 0 /2 9
RG
D6
N1 4 U 3A V S S W/ o US B Ch a rg er P ow er U S B 30 V C C
US B V CC R 5 58 0_ 0 6
M1 4 X T1
X T2 C 16 2 0 . 1u _ 16 V _Y 5 V _ 04
RH
P6
C SE L
U GN D W/ U SB C ha r ge r Po we r 100 MIL
+
R 70 4 P 14 R 5 59 *0 _0 6 C 49 5 1 0 0u _6 . 3V _ B _B
G ND P 11 VC C _T P S 25 4 0
1 00 _ 04 G ND P9
A1 G ND P7 J _U S B3 _ 1
X 19 * FS X 8 L_ 24 . 00 0 MH z A2 G ND G ND P2
G ND G ND 12 28 D 02
2 1 A3 P1 TX P 0_ R 9 G ND1
G ND G ND S S T X+ S H I E LD
S tandard -A
A4 N1 3 1 G ND3
A5 G ND G ND N9 TX N 0 _R 8 VBUS S H I E LD
W243 1117 L 64
11 /0 2 A7 G ND G ND N7 U S B_ P N 1 _A 4 3 U S B_ P N 1 _A _ R 2 S S T X-
X 18 2 4. 0 00 MH z / 16 pF / + 30 pp m A9 G ND G ND N3 4 D -
2 1 A1 1 G ND G ND M1 3 U S B_ P P 1_ A 1 2 U S B_ P P 1_ A _R 3 G ND
G ND G ND D +
A1 3
A1 4 G ND G ND
M1 2
M1 1
Diff. trace 90ohm SS R X1 6
7 SSRX+ G ND4
C 7 98 C 79 9 G ND G ND *W C M 20 12 F 2S -S H OR T G ND_ D S H I E LD
B3 M1 0 SS R X1 # 5 G ND2
2 0p _ 50 V _N P O _0 4 2 0p _ 50 V _N P O _0 4 B4 G ND G ND M9 SSRX- S H I E LD
B5 G ND G ND M8
B7 G ND G ND M7 U S B - 09 E C E B -S D 0 01
G ND G ND R A/ RB
B9 M6 P C B F o ot p r i nt = U S B -C 19 00 5
B1 1 G ND G ND M5 G_ D M0
G ND G ND R 1 86 0_ 04
B1 3 M4 W2 4 0H U: 6 -2 1 -B4 A 1 0 -0 0 9
B1 4 G ND G ND M3 G_ D P 0 R 1 93 0_ 04
C1 G ND G ND L1 2 /2 n d: 6 -2 1 -B4 A 0 0 -0 0 9
C2 G ND G ND L1 1 W2 5 0H UQ: 6 - 2 1- B4 A2 0 -0 0 9
G ND G ND R C/ RD
C3 L7
C1 0 G ND G ND L6 G_ D M0 _0
17 U SB _ P N 0 R 1 97 *0_ 0 4
C1 1 G ND G ND
G ND R 2 03 *0_ 0 4 G_ D P 0_ 0
GN D
G ND
G ND
GN D
GN D
G ND
GN D
GN D
G ND
GN D
G ND
GN D
G ND
GN D
G ND
G ND
GN D
G ND
G ND
GN D
GN D
G ND
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
17 U SB _ P P 0
11 19 - 2 PCH U SB2.0
C 12
D1 1
D1 2
D 13
E1 3
E1 4
F1 1
F1 2
G 9
G 11
G1 3
H 8
H 9
J1 1
J 12
E1
E2
F4
F7
F8
F9
J4
J6
J7
J8
K3
K4
L1
C 13
D3
D4
D 14
F6
G1
G2
G6
G7
G8
G12
H6
H7
H 12
J3
J9
L2
L3
L4
USB 2.0 CO -LAYOU T? ? ? ? ? ? ? ?
R 70 8 *1 5 mi _l 0 6 3. 3 V 3. 3 V
NC5
U GN D
*N C _0 4 KBC_SPI_*_R = 0.1"~0.5" R7 1 7
? ? ? ? PIN6? 512Kb it
3 . 3V C8 1 0 0 . 1u _1 6V _ Y 5 V _0 4 4 7K _ 04
5V U5 2
5V 1 .5 V U S B _S P I _ V D D _ 1 8 5 U S B _S P I _ S I _R R 71 3 47 _0 4 U S B _ SP I _ S I
2A C 8 05
VD D SI
2 U S B _S P I _ S O_ R
R 70 5 R 71 4 15 _1 %_ 0 4 U S B _ SP I _ S O
U5 3 1 u_ 6. 3 V _Y 5V _ 04 1. 0 5 V SO
10 K _0 4 R 70 7 5 6 R 7 11 1 K _0 4 U SB _ F LA S H 3 1 U S B _S P I _ C E # _R R 71 5 15 _1 %_ 0 4 U S B _ SP I _ C E #
10 K _0 4
9
7
V IN
V IN
V C N TL
4
3A W P# CE #
6 U S B _S P I _ S C L K_ R R 71 6 47 _0 4 U S B _ SP I _ S C L K
A U XD E T P OK V OU T S CK
3 R 7 12 4 . 7K _ 04 U SB _ H OL D # 7 4
8 V OU T H OLD # V SS
EN C 8 09 MX 25 L5 1 21 E MC -2 0G
D
R 70 6 C 80 2 1 2 R 71 0 75 0_ 1% _ 04 C8 0 7 C 80 8 31 US B V CC
Q52 GN D VF B 20 , 32 , 33 , 3 5 V D D 5
* 0_ 04 3 , 6 , 8, 9 , 10 , 20 , 32 , 3 4 1 . 5V
G C 8 01 1u _6 . 3 V_ Y 5 V _0 4 *1 0 U _1 0 V_ 0 8 1 0 u_ 10 V _Y 5V _ 08 0. 1 u _1 6V _ Y 5 V _0 4
6, 1 5, 2 8 , 32 SU S B# 2 , 3, 8 , 11 , 13 , 15 , 1 7, 1 9, 2 0, 2 2, 2 3 , 29 , 31 , 32 , 34 , 3 6 3 . 3V
*MT N 70 0 2Z H S 3 AX6610 C 80 6 0 . 01 5 u_ 10 V _X 7 R _0 4 2 3 , 31 , 32 , 34 , 35 , 3 6 5 V
S
0 . 1u _1 6 V_ Y 5 V _0 4
C 80 3
(15nF~ 48nF)
C 8 04
1 0u _ 10 V _Y 5 V _ 08 R 70 9
0 .1 u _1 6V _ Y 5 V _0 4
2 . 4 K_ 1 %_ 04
B - 28 USB3.0 NEC, USB CHARGER

Schematic Diagrams
KBC-ITE IT81518
KB C _ A VDD L1 9 VD D3 VDD 3
H C B 10 0 5K F -12 1 T 20 RN 1 1 M OD EL _ID RA RB
VDD 3
. 2 . 2 K _ 8 P 4R _ 04
C 22 2 C 2 66 C2 1 1 C2 6 4 C 25 6 V DD3 SM C_ B AT 4 5 V1 .0 10 K X W 240 HU
C2 3 4 C 23 3 C2 3 2 R 2 99 SM D_ B AT 3 6
0 . 1 u_ 1 6 V _Y 5 V _0 4 1 0 u _1 0 V _ Y 5 V _ 08 0. 1 u _ 16 V _ Y 5 V _ 0 4 0 . 1u _ 1 6V _Y 5V _0 4 0 . 1 u _1 6 V _ Y 5 V _ 04 2 7 W 250 HU Q
0 . 1u _ 1 6V _ Y 5V _ 0 4 * 0. 1 u _ 16 V _ Y 5 V _ 0 4 *0 . 1 u _1 6 V _ Y 5 V _ 04 1 0 0 K _0 4 1 8
X 1 0K W 270 HU Q
K B C _W R E S E T # RN 1 0 V DD 3 V D D3
1 0 K _ 8P 4R _0 4 RA
L21 H C B 1 0 0 5K F -1 2 1 T2 0 E C_ V CC K B C _ A GN D C 2 38 BA T _ DET 4 5 MO D E L _ I D R2 9 2 10 K _ 0 4
3 .3 V S . 3 6
AP_ KEY # R2 9 3 *1 0K _0 4
1 24 3 G_ D E T# 2 7
C2 5 2 J_KB1 0 . 1 u _1 6 V _ Y 5 V _ 04
C C D _D E T # 1 8
RB
114
127
1 21
0. 1 u _ 16 V _ Y 5 V _ 0 4 J _K B 2 J_ K B 1
26
92
74
W 24 0HU /W 27 0HU W2 50H U
11
50
3
U 23 8 5 2 01 -2 4 05 1 *8 5 2 01 -2 4 05 1 11/02
V CC
VST BY
VST BY
VSTB Y
A V CC
VSTBY
VSTBY
VSTBY
10 58 4 4
VBAT
K B -S I 0 K B -S I 0
1 3 ,2 3 L P C_ A D 0 9 L A D0 KS I0 /ST B # 59 K B -S I 1 5 K B -S I 1 5 P C LK _ K B C P CL K _ K B C_ R
1 3 ,2 3 L P C_ A D 1 R 31 2 *1 0 _ 04 C 24 6 *1 0 p_ 5 0V _N P O_ 0 6
8 L A D1 K S I1 /AF D # 60 K B -S I 2 6 K B -S I 2 6
1 3 ,2 3 L P C_ A D 2 7 L A D2 KS I2 /INIT # 61 K B -S I 3 8 K B -S I 3 8
1 3 ,2 3 L P C_ A D 3 13 L A D3 K S I 3/ S LI N # 62 11 11
P CL K _ K B C K B -S I 4 K B -S I 4 B A T _ V OL T C 21 7 1u _ 6 . 3V _ Y 5V _ 0 4
17 P C LK _K B C 6 L P CC L K KSI4 63 K B -S I 5 12 K B -S I 5 12
13 , 2 3 LP C _ F R A M E # 5 L F R A ME # KSI5 64 14 14
LPC K/B MATRIX K B -S I 6 K B -S I 6
1 3 ,2 3 S E RIRQ 22 SE R IRQ KSI6 65 K B -S I 7 15 K B -S I 7 15 A C _I N #
17 , 2 2 , 24 , 2 5 , 27 B U F _ P LT _ R S T # C 25 8 0. 1 u _ 16 V _ Y 5 V _ 0 4
L P C R S T #/ W U I 4 / GP D 2 ( P U ) KSI7
K B C _W R E S E T # 14 36 K B -S O 0 1 K B -S O 0 1
W R ST # K S O 0/ P D 0 37 K B -S O 1 2 K B -S O 1 2
18
11/18
GA 2 0
1 26 K S O 1/ P D 1 38 K B -S O 2 3 K B -S O 2 3
4 G A 20 / G P B 5 K S O 2/ P D 2 39 K B -S O 3 7 K B -S O 3 7
2 7 ,3 9 A C_ IN# 16 K B R S T #/ G P B 6 ( P U ) K S O 3/ P D 3 40 K B -S O 4 9 K B -S O 4 9
29 L E D_ A CIN 20 P W U R E Q # / GP C 7( P U ) K S O 4/ P D 4 41 10 10
0 _0 4 R3 0 0 K B -S O 5 K B -S O 5
1 5 ,1 7 AC _ PRES EN T *0 _ 04 R3 0 3 L 8 0L L A T / GP E 7 ( P U ) K S O 5/ P D 5 42 K B -S O 6 13 K B -S O 6 13
C o- la y SP I RO M
1 5 P M_ P C H _P W R O K 23 K S O 6/ P D 6 43 16 16
K B -S O 7 K B -S O 7 V D D3
18 S MI # 15 E C S C I # / GP D 3 ( P U ) K S O 7/ P D 7 44 K B -S O 8 17 K B -S O 8 17
18 SCI # E C S MI # / GP D 4 ( P U ) K S O8 / A C K # 45 18 18
K B -S O 9 K B -S O 9 U3 1
K S O 9/ B U S Y 46 K B -S O 10 19 K B -S O1 0 19 8 5 K B C _S P I _S I _ R
? EC Pin 78 76
DAC K S O 1 0/ P E 51 K B -S O 11 20 K B -S O1 1 20 V DD S I
2 2 , 2 9 W LA N _ E N 77 G P J0 K S O1 1 / E R R # 52 K B -S O 12 21 K B -S O1 2 21 2 K B C _S P I _S O _ R
? ? ? HI enable 30 K B C_ M UT E # G P J1 K S O1 2 / S LC T SO
78 53 K B -S O 13 22 K B -S O1 3 22
13 ME _ W E 79 D A C 2 / GP J 2 K S O1 3 54 K B -S O 14 23 K B -S O1 4 23 K BC_ F L AS H 3 1 K B C _S P I _C E # _R
1124
31 C P U_ F A N
3 1 W E B _W W W #
15 SUS_ AC K #
80
81
D
D
D
A C 3 / GP J 3
A C 4 / GP J 4
A C 5 / GP J 5
IT8518
K S O1 4
K S O1 5
55 K B -S O 15 24 K B -S O1 5 24 W P# C E#
S CK
6 K B C _S P I _S C L K _R Sheet 28 of 46
0104 D02 K B C _ H OL D # 7 4
39
39
B A T _D E T
B A T _ V OL T
B AT _ DET
B A T _ V OL T
AP_ KEY#
66
67
68
AD
AD
ADC
C 0 / GP I 0
C 1 / GP I 1
FLASH
F L F R A ME # / GP G 2
F L AD0 /SC E #
10 0
10 1
10 2
K B C _S P I _ C E #
K B C _S P I _ S I
3 G_ P W R _E N 2 3
H O LD #
MX 2 5 L3 2 0 6E
VSS
P C B F o o t p rin t = M-S O P 8 B
KBC-ITE IT81518
31 AP_ KEY#
69 AD C 2 / GP I 2 F L A D 1/ S I 10 3 K B C _S P I _ S O
1228 D02
2 TH E R M _ V OL T 70 AD C 3 / GP I 3 F L AD2 /SO 10 4
39 TO T A L_ C U R
3 G_ D E T # 71 AD C 4 / GP I 4 F L A D 3 / GP G 6 10 5 K B C _S P I _ S C LK
1126 POWER W243HWQ 1230 D02
23 3G _ D E T # CC D_ DE T # 72 AD C 5 / GP I 5 F L CL K /S CK 10 6
23 C C D _D E T # 73 AD C 6 / GP I 6 ( P D )F L R S T# / W U I 7 / GP G 0/ T M C CD_ E N 23
MO D E L _ I D
AD C 7 / GP I 7 V D D3
GPIO 56
S M C_ B A T 1 10
SMBUS ( P D )K S O1 6 / GP C 3 57 SU SB# 6 , 15 , 2 7 , 32
C2 8 8 KBC_SPI_*_R = 0.1"~0.5"
1124
39
39
SM C_ B AT
SM D_ B AT
S M D_ B A T 1 11 SM
SM
C L K 0 / GP B 3
D A T 0 / GP B 4
( P D )K S O1 7 / GP C 5 S U S C# 1 5, 3 4
0 . 1 u_ 1 6 V _ Y 5 V _ 04 1M b it
R 67 9 *0 _ 04 1 15 93
1 5 , 32 , 3 5 P M_ S L P _ LA N # 1 16 SM C L K 1 / GP C 1 ( PD )GP H 0/ I D 0 94 S U S _P W R _ A C K 15
R 67 8 *0 _ 04 U3 0
15 , 3 2 S L P _M # 1 17 SM D A T 1 / GP C 2 ( PD )GP H 1/ I D 1 95 BT_ EN 2 2, 2 9 8 5 K BC_ S P I_ S I_ R K B C_ S P I_ S I
3, 1 8 H_ P E C I R 60 6 0_ 0 4 BKL _ EN 11 R3 6 6 4 7 _0 4
1 18 SM C L K 2 / GP F 6 ( P U ) ( PD )GP H 2/ I D 2 96 VDD SI 2 K B C _ S P I _ S O _R R3 5 5 1 5 _1 % _ 04 K B C_ S P I_ S O
2 , 14 S M C _ C P U _ TH E R M SM D A T 2 / GP F 7 ( P U ) ( PD )GP H 3/ I D 3 97 H S P I_ CE # 1 3 SO 1 K B C _ S P I _ C E #_ R K B C_ S P I_ CE #
1124 2 , 14 S M D _ C P U _ TH E R M R 32 8 *0 _ 04 H SP I_ SCL K 1 3 R3 4 2 1 5 _1 % _ 04
R 67 2 *0 _ 04 ( PD )GP H 4/ I D 4 98 R 36 0 1K _ 0 4 C E# 6 K B C _ S P I _ S C LK _R R3 5 9 4 7 _0 4 K B C_ S P I_ S CL K
1 8 S LP _M E _ C S W _ S E V # PWM ( PD )GP H 5/ I D 5 H S P I _ MS O 13 SCK
1124 R 6 73 * 0_ 0 4 L C D _ B R I G H T N E S S 24 99
H S P I _ MS I 1 3
KB C_ F L A SH 3
25 PW M 0 / GP A 0 ( PU ) ( PD )GP H 6/ I D 6 10 7 W P#
30 K B C_ B E E P 28 PW M 1 / GP A 1 ( PU ) ( PD )GP G 1/ I D 7 D D _ ON 2 7, 3 2 , 3 3
2 9 L E D _S C R O L L# 29 PW M 2 / GP A 2 ( PU )
LOW ACTIVE EXT GPIO R6 9 8 0 _0 4 R 34 6 4. 7 K _ 0 4
29 LE D _ N U M# 30 PW M 3 / GP A 3 ( PU ) 82 R6 7 4 *0 _ 0 4 IC PP E# 18 K B C _ H OL D # 7 4 KBC _ S P I _S I C3 0 3 * 33 p _ 50 V _ N P O _ 04
29 LE D _ C A P # 31 PW M 4 / GP A 4 ( PU ) ( P D )E G A D / G P E 1 83 S L P _ S US # 15 H OL D # V S S
R3 0 6 *0 _ 0 4 KBC _ S P I _S O C2 9 0 * 33 p _ 50 V _ N P O _ 04
2 9 L E D_ B A T _ CH G 32 PW M 5 / GP A 5 ( PU ) ( P D )E G C S # / G P E 2 84 R3 1 5 *0 _ 0 4 OC P P E # 18 1201 *P M 2 5L D 0 1 0 C -S C E KBC _ S P I _C E# C2 8 4 * 33 p _ 50 V _ N P O _ 04
HIGH ACTIVE 2 9 L E D _B A T_ F U LL 34 PW M 6 / GP A 6 ( PU ) ( P D )E G C L K / G P E 3 SL P_ S5 # 15
R6 7 5 *0 _ 0 4 KBC _ S P I _S CL K C2 9 7 * 33 p _ 50 V _ N P O _ 04
29 L E D _P W R PW M 7 / GP A 7 ( PU ) S U S CL K 15
WAKE UP 35 6-04-25010-A91
8 0 CL K 85
PS/2 ( P D )W U I 5 / G P E 5 17 R S MR S T# 1 5
22 8 0C L K 86 PS2 C LK 0 / G P F 0( PU ) ( P D )L P C P D # / W U I 6 / G P E 6 K B C _R S T # 18 W243HVQ
22 , 2 9 B T_ D E T# R3 2 0 0_ 0 4 8 0P O R T _ D E T # 87 PS2 D A T0 / G P F 1( PU )
22 3 IN 1 88 PS2 C LK 1 / G P F 2( PU ) PWM/COUNTER 47
3 1 W E B _ E MA I L # 89 PS2 D A T1 / G P F 3( PU ) ( P D )T A C H 0 / GP D 6 48 C P U_ F A NS E N 3 1
31 T P _C L K 90 PS2 C LK 2 / G P F 4( PU ) ( P D )T A C H 1 / GP D 7 H _ P R OC H OT _ E C 3
R3 3 0 0_ 0 4
31 T P _D A T A PS2 D A T2 / G P F 5( PU ) 12 0 P MP C H _ P W R OK _ R R3 3 6 * 0_ 0 4 P M _ P C H _ P W R OK 1 5
( P D )T MR I 0/ W U I 2 / GP C 4 12 4 V C OR E _O N 3 7
1 25
WAKE UP ( P D )T MR I 1/ W U I 3 / GP C 6 A L L _S Y S _ P W R G D 1 1 , 1 5, 3 7
23 3 G_ E N P W R S W / G P E 4( P U )
18
CIR 11 9 R3 2 9 *0 _ 0 4
32 P W R _S W # 21 R I 1# / W U I 0 / GP D 0( P U ) ( P D )C R X / GP C 0 12 3 P ME #_ R
1126 POWER
R3 3 5 *0 _ 0 4
11 , 3 1 L ID_ S W # R I 2# / W U I 1 / GP D 1( P U ) ( P D )C TX / G P B 2 R3 3 1 0 _0 4 PM E# 17
L A N _P C I E _ W A K E # 2 4
33
GP INTERRUPT LPC/WAKE UP 19
15 P W R_ B T N# G I N T / GP D 5 ( P U ) ( P D )L 80 H LA T / G P E 0 SW I# 15
11 2
12 02 1 08 UART
( P D )R I N G # / P W R F A I L # / L P C R S T# / G P B 7 C H G_ R S T 39
* 0_ 0 4 R 6 97 CLOCK
1 09 R XD / GP B 0 ( P U ) 2 CK 3 2 K E
AVSS
22 W LA N _ D E T # R3 2 6 *0 _ 0 4 NB_ ENA VDD 11 , 1 6

VSS
VSS
VSS
VSS
VSS
VSS
VSS
T X D / G P B 1( P U ) C K 3 2K E 12 8 CK 3 2 K V D D3
C K 3 2K
I T 8 5 18 E R3 2 7 *1 0 M_ 0 6 J _ 80 D E B U G 1
1
27
49
91
113
75
12
1 22
R 3 53
X4 *M C -1 4 6_ 3 2 . 76 8 K H z 1 3 IN1
2 1 0 K _ 04
C 25 0 0 . 1 u_ 1 6 V _Y 5 V _0 4 E C _V S S 1 4 8 0 CL K
2 3 3 8 0 DE T # 1228 D02
4
X5 * C M -20 0 S _ 32 . 7 6 8K H z 5
R 33 3 1 4 8 8 26 6 -0 50 0 1
2 3
NC 2 * NC_ 0 4 0 _ 04 C 26 2
C2 6 5 * 15 p _ 50 V _ N P O _ 04
*1 5 p _5 0 V _ N P O _0 4
R 2 88 *1 0 mi l _ 04 L C D _ B R I GH TN E S S
11 B RIG HT NE S S
K B C _A G N D MC-146 & CM200S
C 2 19 * 0. 1 u _ 10 V _ X 5R _ 04
Co-layout 13 , 1 4 , 1 5, 1 7 , 1 8, 2 0 , 2 2, 2 3 , 2 4, 2 5 , 3 2, 3 3 , 3 5, 39 V D D 3
3 , 9 , 10 , 1 1 , 12 , 1 3 , 14 , 1 5 , 16 , 1 7 , 1 8, 1 9 , 2 0, 2 3 , 2 4, 2 5 , 2 6, 2 9 , 3 0, 3 1 , 3 2, 37 3 . 3 V S
KBC-ITE IT81518 B - 29
Schematic Diagrams
LED, MDC, BT
Bluetooth(Port8)
3 V_ BT
J _B T 1
3 . 3V
Port 11 1
2
17 U S B _P N 1 1 3
17 U S B _P P 11 4
2 2 , 28 B T _ DE T # B T_ E N # 5
6
R 3 23
* 8 72 1 2-0 6 G0
* 1 0K _ 0 4
B T _ E N#
D
Q 24 C 25 9
BT_ EN G * MT N 7 0 0 2Z H S 3 3 .3 V 3 V_ BT
R4 7 3
*1 8 0 p_ 5 0 V _N P O_ 0 4
5 0mi l 5 0m il
S
* 2 8m i _l 0 6
C4 6 4
*1 0 u _6 . 3 V _ X5 R _0 6
LE D _ A C I N 28 L E D _ B A T _C H G 28
3 .3 V S 3 .3 V S
Sheet 29 of 46 LED 3 . 3V S 3. 3 V S 3 . 3V S 3 . 3V S L E D _P W R 28 L E D _B A T_ F U LL 2 8
R6 R7
LED, MDC, BT R 3 R4 R 5 2 20 _ 0 4 2 20 _ 0 4
2 2 0_ 0 4 22 0 _0 4 2 2 0 _0 4 POWER ON BAT LED

BT WLAN LED
1 3
3
LED LED
HDD/ODD NUM CAPS SCROLL D 1 D1 4 D1 5
A
R 2 2 4
SG
SG
SG
Y
Y
LED D3 LOCK D4 LOCK D5 LOCK K P B -30 2 5 Y S GC K P B -3 02 5 Y S G C K P B -3 0 25 Y S GC
2 2 0 _0 4
LED LED LED
A
4
R Y -S P 17 0 Y G3 4 -5 M
R 1
R Y -S P 1 7 0 Y G3 4- 5M
R Y -S P 17 0 Y G3 4 -5 M
D2
W L A N _L E D # 2 2
C
R Y -S P 17 0 Y G3 4 -5 M
*1 0 mi l _ 04 R 3 62 R 36 1 R 3 63 R 3 64
B
W L AN_ EN 22 , 2 8
2 2 0 _0 4 2 2 0_ 0 4 22 0 _0 4 2 2 0 _0 4
C
Q 3
*D TC 1 14 E U A
E
LE D _ N U M # 28 LE D _ C A P # 2 8 L E D _ S C R OL L # 28 W240HU ? ?
S A TA _ L E D # 1 3
C
6 -5 2-5 20 01- 02 7 6 -52 -5 200 1- 02 7 6 -5 2- 520 01 -0 27 W250HU ? ? ?
B B T_ E N
B T _E N 2 2 ,2 8
6 -52 -5 200 1- 02 7 Q 1
3 , 6 , 8 , 9, 1 0 , 2 0, 2 7 , 3 2, 3 4 1 . 5V
D TC 11 4 E U A
E
2 , 3 , 8, 1 1 , 1 3, 1 5 , 1 7, 1 9 , 2 0, 2 2 , 2 3, 2 7 , 3 1, 3 2 , 3 4, 3 6 3 . 3V
3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0, 2 3 , 2 4, 2 5 , 2 6, 2 8 , 3 0, 3 1 , 3 2, 3 7 3 . 3V S
H1 5 H2 4 H1 1
M2 M7 M6 M1 M8 2 9 2 9 2 9
M-M A R K 1 M -MA R K 1 M -MA R K 1 M-M A R K 1 M -MA R K 1 3 8 3 8 3 8
H1 2 H 10 4 1 7 4 1 7 4 1 7
H 6 _ 3D 4 _4 H 6_ 3 D 4 _ 4 5 6 5 6 5 6
MT H 3 1 5 D 1 11 MT H 31 5 D 1 1 1 M TH 31 5 D 1 1 1
H 3 H4
C 1 11 D 1 1 1 N C 1 1 1D 11 1 N
M5 M4 M3 H5 H6 H1 3
M -MA R K 1 M-M A R K 1 M -MA R K 1 2 9 2 9 2 9
3 8 3 8 3 J _ T P1
4 1 7 4 1 7 4 1
5 6 5 6 5 6 1 L ED_ PW R
2 L E D_ A CIN
MT H 3 1 5 D 1 11 MT H 31 5 D 1 1 1 M TH 31 5 D 1 1 1 3 L E D_ B A T _ F UL L
4 L E D_ B A T _ CHG
H1 7 H 20 H 18 H 14
H 6 _ 0D 3 _7 S1 H 4_ 7 B 6 _0 D 3 _ 7 H 4 _7 B 6 _ 0D 3_ 7H 6_ 3 D 4 _ 4 5
S MD 80 X 80 6
H9 H7 H2 5
2 9 2 9 2 9 *8 5 2 01 -0 60 5 1
3 8 3 8 3 8
1
4 1 7 4 1 7 4 1 7 GN D
1
5 6 5 6 5 6 ? ? P IN? ?
1124 Del MT H 3 1 5 D 1 11 MT H 31 5 D 1 1 1 M TH 31 5 D 1 1 1
W240HU ? ? ?
W250HU ? ?
H2 3 H8 H 1 H2 H2 1 H 19 H2 2 H1 6
C6 7 D6 7 C6 7 D6 7 C 1 11 D 1 1 1 N C 1 1 1D 11 1 N H 4 _ 0 B 7_ 0 D 3 _ 7 H 4_ 0 B 7 _0 D 3 _ 7 2 9 2 9
3 8 3 8
4 1 7 4 1 7
5 6 5 6
MT H 3 1 5 D 1 11 M TH 31 5 D 1 1 1
B - 30 LED, MDC, BT
Schematic Diagrams
AUDIO CODEC ALC269 VIA1802
7
5
C
o
m
p
o
n
e
n
t
.
A UD IO C OD EC
R 5 27 *0 _ 04
ALC269 VB 1 .5 V S
DV DD _ IO PV D D1 _ 2 5 VS
L ay ou t No te :
VT1802P 3 . 3 V S _A U D
R 5 29 0 _0 4 R 5 10 * 28 m i _l 0 6 V er y clo se t o A ud io C ode c
C5 1 3 C2 9 9 C 49 8 C2 7 1
1 0 u_ 1 0 V _Y 5 V _0 8 0 . 1u _ 1 6V _Y 5V _0 4 1 0 u _1 0 V _ Y 5 V _ 08 0. 1 u _ 16 V _ Y 5 V _ 0 4
3 .3 VS 3 . 3V S _ A U D ALC269 ? ?
VT1802P ? ? ?
R5 6 7 0_04 C4 9 9 C 27 0
* 10 u _ 10 V _ Y 5 V _ 0 8 0. 1 u _ 16 V _ Y 5 V _ 0 4 5 V S _ A UD
C 2 81 C2 8 0 C2 8 3 L4 0 5V S
H C B 1 00 5 K F -1 2 1T 2 0
0 . 1 u _1 6 V _ Y 5 V _ 0 4 10 u _ 10 V _ Y 5 V _ 0 8 0 . 1 u_ 1 6V _Y 5V _0 4 1 2
C 49 7 C 4 96 C5 1 0 C 50 9 C 49 4
5 VS L 39
0 . 1 u_ 1 6 V _Y 5 V _0 4 1 0 u _1 0 V _ Y 5 V _ 08 0 . 1u _ 1 6V _ Y 5V _ 0 4 1 0 u_ 1 0 V _Y 5 V _0 8 1 u _ 6. 3 V _ Y 5 V _ 0 4 *H C B 1 6 08 K F -1 2 1 T2 5
E A P D _ MO D E C
D2 1
A
*R B 7 51 S -4 0 C 2
.
R5 1 8
H D A _ R S T# C A A UDG A UD G C5 0 3 0 . 1u _ 1 6V _ Y 5V _ 0 4
39
25
38
13 H D A _R S T #
46
1
9
D1 8 R B 75 1 S -4 0C 2 10 K _ 0 4 U 29
DV DD1
P VD D1
P V DD2
A V DD 1
A VD D2
D V D D -I O
C A PD # 4 13 SEN SE_ A R3 6 9 20 K _ 1 % _0 4 MI C _S E N S E C5 0 2 0 . 1u _ 1 6V _ Y 5V _ 0 4
2 8 K B C_ M UT E # PD # S e n se A MI C _ S E N S E 3 1
D1 9 R B 75 1 S -4 0C 2
14 L I N E 2 -L R3 6 8 39 . 2 K _ 1 %_ 0 4 HP _ S E N S E
40 L I N E 2- L 15 H P _ S E N S E 31
S P K OU TL + L I N E 2 -R R5 3 3 *2 8 mi l _ 06
S P K OU TL - 41 S P K - L+ LI N E 2 -R
D
S P K - L- 16 M IC2 _ L
G
Q3 2
31 S P K OU T R -
44
45 S P K - R-
MI C 2- L
M I C 2 -R
17 M IC2 _ R 1 20 1
5 VS R5 1 4 * 10 0 K _ 04 *M T N 7 00 2 Z H S 3 ALC269 20K_1%_04 AUD G
31 SPK O UT R+ S P K - R+ 18 S E N S E -B
EMI Require
D
E A P D _ MO D E 47 S e n se -B VT1802P 5.1K_1%_04
Q2 7 S P DIF O 48 S PD IF C2 /E AP D 19 J DR E F R5 2 3 2 0 K _1 % _ 04
G S PD IF O J D RE F 20
H D A _R S T # * B S S 1 38 _ N L
D MI C -D A T 2
G P I O0
MO N O -OU T
M ON O -OU T C 51 2 *1 0 0p _ 50 V _ N P O_ 0 4
Sheet 30 of 46
S
D MI C -C L K 3 21 M I C 1 -L _R C 3 0 6 4 . 7u _ 6 . 3V _ X 5 R _ 0 6 M IC1 _ L A U DG
G P I O1 MI C 1- L 22 M I C 1 -R _ R C 3 0 7 4 . 7u _ 6 . 3V _ X 5 R _ 0 6 M IC1 _ R
M I C 1 -R
5
DIGITAL ANALOG L I N E 1- L
23
24
L I N E 1 -L
L I N E 1 -R C 3 01 0 . 1u _ 1 6V _ Y 5V _0 4
AUDIO CODEC
Clo sed to SB. 1 3 H D A _ S D OU T C 2 91 22 p _ 50 V _ N P O_ 04 S D A T A -OU T LI N E 1 -R
Q 25
1 3 H DA _ B IT CL K
13 H D A _S D I N 0 R3 5 4 3 3 _0 4 A Z _ S D I N 0 _R
6
8
B I T -C LK
S D A T A -I N L DO _ CA P
V RE F
27
28
V R E F -A L C 2 6 9
L D O _C A P
ALC269 2.2u;
C 3 04 2 . 2u _ 6 . 3V _X 5 R _ 0 6
VT1802P 10u ALC269 VIA1802
M TN 7 00 2 Z H S 3 30 M I C 1 -V R E F O-R
D S A Z _ S Y N C_ R 10 MI C 1 -V R E F O -R 29 M I C 2 -V R E F O
13 H DA _ S Y NC C 2 98 1 0u _ 6 . 3V _ X 5 R _ 0 6
S Y NC M I C 2 -V R E F O
HD A _ RS T # 11
R ESET # H P -OU T- L
32
33
H E A D P H ON E -L
HE A DP HO NE - L 3 1
ALC269 2.2u 1 20 7
H E A D P H ON E -R VT1802P NC
3 .3 VS H P -O U T -R HE A DP HO NE - R 3 1
G
BEEP_ R 12
M I C 1-V R E F O-L
AUD G
PC BEEP 35 C B N -A L 2 69 C 27 2 2. 2 u _ 6. 3 V _ X 5 R _ 06
C BN
36 C B P -A L C 2 6 9
P VSS2
DV S S 2
AVS S1
CB P
PVSS1
AVSS2
34 O P V E E -A L C 2 6 9 L24
G ND
D1 3 C 30 9 O PVEE F C M1 0 05 K F -1 2 1 T0 3 J_ S P K L 1
B A T 54 C W GH C2 7 9 S P K OU TL + 1 2 S P K O U T L + _L
1 A 1 u _6 . 3 V _ Y 5 V _ 04 1
28 K B C_ B E E P 2
42
37
31
C 3 BEE P BEEP_ C
43
49
26
R 3 67 4 7 K _ 04 A L C 2 6 9 Q-V B 6 -GR C2 9 3 C 2 95
2 A 2. 2 u _ 6. 3 V _ X 5R _ 06 8 5 20 4 -0 20 0 1
13 H D A _S P K R *1 u _ 6. 3 V _ Y 5 V _ 0 4 * 18 0 p _5 0 V _ N P O _0 4
FOR VOLUMN
R 36 5 C 30 8 M I C 1 -V R E F O-L
ADJUST A U DG S P K OU TL - 17/16 2 S P K O U T L -_ L
4 . 7 K _ 04 1 0 0p _ 5 0V _ N P O_ 0 4 AUD G J_SPKL1
MI C 2-V R E F O R 1 3 0 4 . 7 K _ 04 F C M 10 0 5 K F -1 21 T 0 3 C 2 89 2 1
J _I N T MI C 1 L2 3
I N T _ MI C R1 2 8 1 K _ 04 * 18 0 p _5 0 V _ N P O _0 4
1
C 11 8 2
8 82 6 6 -02 0 0 1
6 8 0p _ 5 0V _ X 7 R _ 0 4 J_INTMIC1
Headphone Anti-Pop Circuit 2 1
3 . 3V S
R5 6 8
R130 C118
H E A D P H O N E -L
H E A D P H O N E -R
*2 2 0 K _0 4 AL269 4.7K_04 AL269 680p
S
E A P D _M OD E G Q3 9 Q4 0 VT1802P 2.2K_04 VT1802P 330p

D
Q3 8 * 2N 7 00 2 W *2 N 7 0 02 W
*A O 3 41 5
3 .3VS _AUD G G MI C 1_ L R 34 3 1 K _ 04
M I C 1 -L 31
D
MI C 1_ R R 35 1 1 K _ 04
M I C 1 -R 31
R5 6 9 R 57 0 R 5 71
5VS *4 . 7 K _ 04 MI C 1-V R E F O- R R 35 0 2 . 2 K _ 04
* 10 K _ 0 4 *1 0K _0 4
20ms A U DG MI C 1-V R E F O- L R 34 5 2 . 2 K _ 04
AZ_ RST# R343 & R351 R345 & R350

C5 3 8
*1 0 u _6 . 3 V _ X5 R _0 6
AL269 1K_04 AL269 2.2K_04
PD# VT1802P 75_04 VT1802P 4.7K_04
A UDG
C 51 1 4. 7 u _ 6. 3 V _ X 5 R _ 06 MI C 2_ L
Spe a ke r w i re le ngt h le ss tha n 80 00 mils , It don't ne ed LC Fil te r. I N T _ MI C R 70 0 1 K _ 04 I N T_ M I C _ R C 51 4 4. 7 u _ 6. 3 V _ X 5 R _ 06 MI C 2_ R
SPKOU TR +, R-, L+ , L- Trac e w idth
1 20 2
C3 9 5 0 . 1 u_ 1 6 V _Y 5 V _0 4
1229 D02(W240HU)
Spe a ke r 4 ohm-- -- --> 40m ils 1 .5 VS 1 9, 3 2
3 .3 VS 3 , 9, 1 0 , 1 1, 1 2 , 1 3, 1 4 , 1 5, 1 6 , 1 7 , 18 , 1 9 , 20 , 2 3 , 24 , 2 5 , 26 , 2 8 , 29 , 3 1 , 3 2, 3 7
AUDIO CODEC ALC269 VIA1802 B - 31

Schematic Diagrams
USB, FAN, TP, MULTI CON

U 38
USB 2.0 FAN CONTROL 5 VS
F ON # 1
2
3
F ON
V IN
GN
GN
D
D
8
7
6
5 VS_ FAN V OU T GN D
4 5
28 C P U_ F A N VSET GN D
AX9 95 B& APE8 87 2 A X 9 95 S A
Co-L ayo ut JFAN

5 VS 5 VS_ FAN 3
80 mil 5 VS_ FAN 5 VS U5 0 J_ F A N 1
US B V C C F O N# 4
1
+
C 4 88
1 0 0 u_ 6 . 3V _B _ B
C 94
0 . 1 u _1 6 V _ Y 5 V _ 04
Port 1 3
1
6
F ON #
V IN
V OU T GN D
2
5
C2 0 5
0. 1 u _ 16 V _ Y 5 V _ 0 4
C 45 6
1
2
3
28 C P U_ F A N VSET GN D 1 0 u_ 6 . 3 V _X 5 R _ 0 6 8 5 20 5 -03 7 0 1
01 0 1 D 0 2 *A X 9 9 5B
1 20 2 2n d Sou rce PN:APE88 74 2 8 C P U_ F A N S E N
J _ US B _ 1
11 1 9 -2 1 R 20 2 4 . 7K _ 0 4
V+ 3. 3 V S
4 L 13 3 A US B _ P N1 _ R 2
17 U S B _ P N1 D A TA _ L
1 2 A US B _ P P 1 _ R 3
17 U SB_ PP1 D A TA _ H
4
CLICK B'd & FP CONN
G ND1
GN D 2
GN D 3
GN D 4
*W C M2 0 12 F 2 S -S H OR T GN D
3 1 7 D E 0 4 P S A 7 A 2C
G ND 1
G ND 3
GN D 2
GN D 4
5 V S _ TP
CO-LAY USB 3.0 J_USB2
R1 3 1 *2 8m i l _0 6
5 VS
R 12 9 R 1 27 C1 1 3
1 0 K _ 04 1 0 K _ 04 1 u _6 . 3 V _ Y 5 V _0 4
W 24 0 H U 3 17 D E 04 P S A7 A 2 C J_ T P 2
W 25 0 H U 1 -2 8 4 -8 0 0 28 1 - 1 1
2 T P_ DAT A 28
Sheet 31 of 46 3
4
5
6
C 11 4 C 1 15
T P_ CL K 28
U S B V CC 4 7 p_ 5 0 V _N P O_ 0 4 4 7 p _5 0 V _ N P O_ 0 4
USB, FAN, TP, 7

8
88 4 86 -0 8 01
3 . 3V S _ F P L5 0
H C B 1 6 08 K F -1 2 1T 2 5
3 . 3V S
L62
MULTI CON G_ U S B V C C
.
H C B 1 6 08 K F -1 2 1 T2 5 US B _ P N 3 1 7
U4 0 100 MIL US B _ P P 3 1 7 C5 9 7
R5 2 4 *0 _0 4 F L G# 5 6
17 U S B _ O C # 01 F L G# V O U T 1 C 5 96 0. 1u _ 16 V _ Y 5 V _ 0 4
2 7 C 49 2 C4 9 3 C 49 1
5V V IN1 V O UT 2 1U _1 0 V _ 06
C5 0 1 0 . 1 u_ 1 6 V _Y 5 V _0 4 3 8 0 . 1 u _1 6 V _Y 5 V _0 4 *0 . 1 u_ 1 6 V _Y 5 V _0 4 1 0 u_ 6 . 3 V _ X5 R _ 0 6
V IN2 V O UT 3
4 1
32 , 3 4 DD_ O N# E N# G ND
R T9 7 15 B G S / S Y 6 2 88 D F A C
1228 D02
If system has AP ON function, uses J_SW1

Audio B'd CONN POWER SWITCH B'd CONN If system has no AP ON function, uses J_SW2
3 .3 V S 3. 3 V
1.1A 60mils CLOSE TO J_SW1
C 22 3 0 . 0 1 u_ 1 6 V _X 7 R _ 0 4 3 . 3V S 3. 3 V
5V
C2 9 C 27 J_ S W 1
J _ A U D I O1 AP_ KEY#
AP_ KEY# 28
2 0m il
1
1 2 M _B T N #
30 M I C 1 -R 0 . 0 1 u_ 1 6 V _X 7 R _ 0 4 0 . 01 u _ 16 V _ X 7R _0 4
2 3 W EB_ W W W #
30 M I C 1 -L 3 4
D
W E B _ E M A I L#
R 33 9 2 2 0 _0 4 H E A D P H ON E -R R 4 J _ SW 2 Q9 5 L ID_ S W #
30 H E A D P H O N E -R
30 H E A D P H O N E -L R 34 0 2 2 0 _0 4 H E A D P H ON E -LL 5 2 0mi l G *M TN 70 0 2 Z H S 3
6
M IC_ S E NS E 6 1 7 AP_ KEY #
S
30 M IC_ S E N S E S P K _H P # 7 2 M _B T N # 8
8 3 M_ B T N # 32
H P _ S E NS E W E B _W W W # 88 4 8 6- 0 8 01
30 HP _ S E N S E 9 4 W E B _E M A I L # W EB_ W W W # 2 8
17 USB_ PN 9 10 5 L ID_ S W # W E B _ E MA I L # 2 8
17 U SB_ PP9 11 6 L ID_ S W # 1 1 ,2 8 C 5 46 C5 4 7
S P K OU T R + 12 7 AP_ O N
* 0 . 1u _ 5 0V _ Y 5 V _ 06
*0 . 1 u_ 1 6 V _Y 5 V _ 0 4
30 S P K OU T R + 13 8 A P _ ON 32
S P K OU T R -
30 S P K OU T R - 14 9
10 V IN
8 72 1 3 - 14 0 0 G
A UD G *5 05 0 0 -01 0 41 -0 0 1L
1229 D02(W240HU)
27 US B V C C
2 , 3 , 8, 1 1 , 1 3, 1 5 , 1 7, 1 9 , 2 0, 2 2 , 23 , 2 7 , 29 , 3 2 , 34 , 3 6 3. 3 V
1 1 , 1 2, 1 9 , 20 , 2 6 , 30 , 3 2 , 37 , 3 8 5V S
23 , 2 7 , 32 , 3 4 , 35 , 3 6 5V
1 1 , 3 2, 3 3 , 34 , 3 5 , 36 , 3 7 , 38 , 3 9 V IN
3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0, 2 3 , 2 4, 2 5 , 26 , 2 8 , 29 , 3 0 , 32 , 3 7 3. 3 V S
B - 32 USB, FAN, TP, MULTI CON

Schematic Diagrams
5VS, 3VS, 1.5V/0.75VS, 1.5VS CPU

S Y S5 V SY S 5V
VI N VA V IN1 S Y S5 V
S Y S 5V
PR 2 24 P R 22 2
P C2 PC 1 10 PC 1 11 O N PR 2 36
D D _ ON " L " T O 10K _ 04 1 0K _0 4 P R 237
0 . 1u_ 50 V_ Y 5V _0 6 0. 1u _5 0V _Y 5V _ 06 0. 1u _5 0V _Y 5 V_ 06 10 K_ 04
" H " F R O M EC D D _ ON # S U SB 10 K_ 04
PU 7 D D _ ON # 31 ,3 4 S U SB 3 , 34 ,3 5
1 8 SL P _M
VA V IN1 S LP _M 15
6 3 PM_ S LP _L AN
D
2 7 R 3 71 10 0K _0 4 D D _ON 0 22 4 D D
D
V IN D D _ON _ LA TC H
PQ6 7A P Q67 B PQ8 5 P C2 9
PR 2 26 1 K _04 3 6 R 60 4 1K _0 4 D D _ ON2 G MTD N 70 02 ZH S 6 R 5 G MT D N 70 02Z H S 6R G MTN 7 002 ZH S 3 0 . 1u _16 V _04 P Q86 PC 7 8
31 M_B T N # M_ BT N # P WR _ SW # P WR _ SW # 28 27, 2 8, 33 D D _ ON S 6, 15 , 27, 2 8 S U SB # S 1 5, 28 S LP _M# G MTN 7 00 2Z H S3 0. 1u _1 6V _0 4
S
PR 2 27 1 K _04 4 5 1 4 15, 2 8, 35 P M_ SL P_ LA N #
ON
S
31 A P _ON I N S TA N T-ON GN D P R 2 21 P R 22 0
ON
P2 80 8B 0 P R 123 10 K_ 04 V DD3
PR 2 34 *10 K_ 04 VN
I 1 1/0 2 1 00 K_ 04 1 00K _ 04
1
10/2 9
D6 1 D 62 *V 15 AV LC 0 40 2 ON O N
5V *V 15 AV LC 0 40 2
2
W243 1117 ? ? 3.2

3 .3 V 3 . 3V S
C 50 4 C 50 5 C 506 C 24 7 C 2 24 C 225
1. 5VS 1. 05V _M 0 308 -J
P DA bu g
S I48 00 BD Y?M E4 41 0AD -G
0. 0 1u_ 16 V_ X7 R _0 4 0. 0 1u _16 V _X7 R _0 4 0. 01 u_1 6V _X 7R _ 04 0. 0 1u_ 16 V_ X7 R _04 0 .0 1u _1 6V _X 7R _0 4 0. 01 u_ 16V _ X7R _ 04 NMOS 1. 5V S
S Y S 15V 1. 5 V S Y S 15 V NMOS
P Q64 A 1 . 05V _ LA N _M 1. 05 V _M
MTN N 2 0N 0 3Q8 P Q91 A
8 2 MT N N 20N 0 3Q8
5V NM OS
5 VS P R 21 8
1 M_0 4
7 1
P R 24 0
8
7
2
1
NM OS P C 21 7 P C2 16 P R 2 19 1 M_0 4
PQ6 5A
3
S Y S1 5V V D D 5 P C 21 8 P C 220 P R 2 41
MTN N 20 N 03 Q8 5V SY S 15 V VD D 5 PQ6 6A 5 VS
3
0 .1 u_ 16 V_ Y 5V _0 4 10 u_6 . 3V _X 5R _ 06 1 00 _0 4
D 1 . 5V S _LO
8 2 MTN N 20 N 03 Q8
D 1 . 05 VM _LO
1. 5 VS _E N 0 . 1u_ 16 V_ Y 5V _0 4 10 u_ 6. 3V _X 5R _ 06 * 100 _0 4
3A 7 1 3A 8 2 1. 0 5V M_E N
P R 22 5 7 1
Powe r Pl ane PR 2 23
Sheet 32 of 46
4
1M_ 04 PQ6 4B
3
4
PR 2 31 1M_ 04 PC 2 19 P R 23 2 MTN N 2 0N 0 3Q8 P Q6 3 PQ9 1B
3
5 V_ EN 1 P C 21 2 MT N 70 02Z H S 3 MTN N 2 0N 0 3Q8 P Q7 2
100 K _04 5V S _E N 1 0. 1u _1 6V _Y 5 V_ 04 *1 00 K_ 04 5 S U SB G P C 21 3 MT N 70 02 ZH S 3
5 SL P _M G
5VS, 3VS, 1.5V/
4
P Q65 B 4 70 p_5 0V _X 7R _ 04
S
4
MT N N 20 N 03Q8 PQ6 6B 4 70 p_5 0V _X 7R _ 04
S
6
P C 2 21 MT N N 20 N 03Q8
6
5 D D _ON # PC 2 22
0.75VS, 1.5VS CPU

47 0p _5 0V _X 7R _0 4 5
SU S B 3 3, 4, 3 5
1
47 0p_ 50 V_ X7 R _0 4
6
1
P J 20
6
P J 19
*4 0mi l ON
2
*4 0mi l ON
2
ON
W243 1117
1. 5VS _C PU
1230 D02
3. 3V 3 .3 VS 1 . 5V 1. 5V S _C P U
NMOS NM OS P J 15
SY S 15 V V D D 3 P Q21 A 3. 3 V S Y S1 5V V DD3 PQ2 0A
3 . 3V S
2
*OPE N _ 5A -S h ort
1 10A 1.05VS
MT N N 20N 0 3Q8 MTN N 2 0N 03 Q8
3A 8 2 3A 8 2 SY S 1 5V PJ15 MUST SHORT
7 1 7 1 P R 72
PR 1 11 P R 10 9 PQ4 8A NMOS 1. 0 5V _L AN _ M 1. 0 5V S
P ower Pla ne
*MTN N 2 0N 03 Q8 *2 20 _04
1M_0 4 PR 2 33 1M_ 04 PC 9 6 P C 94 P R 102 P R 71 8 2 PJ 22
D 1 .5 V S_ C PU _ LO
7 1
3
12 28 D0 2 *OP EN _ 5A
3. 3V _ EN 1 10 0K _0 4 0. 1u _1 6V _Y 5 V_ 04 1 0u _6. 3 V_ X5 R _06 10 0_ 04 V al ue = *1M_ 04 2 1
P C 18 0 PC 1 79
3. 3 VS _L O
4
PQ2 1B 3. 3 VS _ EN 1
3
MTN N 2 0N 0 3Q8 1 . 5V S _C P U EN *0 .1 u_ 10 V_ X7 R _04 *10 u_6 . 3V _X 5R _ 06
PC 9 5
4
5 D D _ON # P Q48 B NMOS
4
220 0p _5 0V _X 7R _0 4 P C 89 P Q20 B MT N N 20 N 03 Q8 P Q11

D
MTN N 20 N 03 Q8 P Q16 P C 46 *MT N 700 2Z H S 3 P Q90

6
47 0p _50 V _X7 R _0 4 MTN 7 00 2Z H S3 5 S US B G S Y S1 5V P 12 03B V

5 SU S B G *22 00 p_ 50V _ X7R _ 04 8 10A
S
7 3
S
6
6 2
6
R 4 43 5 1 C 4 29 C 4 09
R 1 26
*1 0u _10 V_ Y 5V _0 8
1 M_04 *1 00 _04
0 .1 u_ 16 V_ Y5 V _04
4
1 . 05V S _E N
D1 .0 5V S _L O
0 104 D02 ON
ON C 4 55
2 200 p_ 50 V_ X7 R_ 04 3 P Q87 B Q20

D
MT D N 700 2Z H S 6R MT N 70 02Z H S 3
3. 3V _M 5
S
G 1. 05 VS _ EN _ C G
S
4
NM OS 3. 3 V_ M
SY S 15 V P Q9 2A
V DD3 V DD3 R 57 4 *1 0K _0 4
MT N N 20 N 03Q8 P R 24 3
8 2 Pow er P lane 0_ 04
7 1
PR 1 12 1 228 D 02 S US B
6
1M_0 4 P C 97 P C 10 0 PR 1 06 D ON
3
PQ8 8A 2
0 . 1u_ 16 V_ Y 5V _0 4 10 u_ 6. 3V _X 5R _ 06 100 _0 4 G
* MTD N 70 02 ZH S 6R S 1. 0 5V S _V TT _E N 1 5, 35
D 3. 3V M_ LO
3. 3V M_ EN 1 1
S Y S 5V 33 , 35
3 . 3V _M 13 , 15, 1 9, 25 , 26
1 . 05V _L A N _M 20 ,2 5, 3 5
W 24 3 1 11 7
1 . 05V _M 20
4
PC 9 2 P Q92B VA 39
MT N N 20N 0 3Q8 PQ1 7
470 p_ 50 V_ X7 R _04 MTN 70 02 ZH S 3 1 . 5V S_ C PU 3 ,6
5 3. 3V M_ EN G 1 . 5V 3, 6 8, , 9, 10 , 20 ,2 7, 3 4
5V 23 , 27, 3 1, 34 , 35 ,3 6
V IN1 33
S
3 . 3V S 3, 9 ,1 0, 1 1, 12 , 13, 1 4, 15 , 16, 1 7, 18 , 19 ,2 0, 2 3, 24 , 25, 2 6, 28 , 29, 3 0, 31 , 37

6
PR 2 44 0_ 04 P M_S LP _L A N V DD5 20 , 27, 3 3, 35

V DD3 13 , 14, 1 5, 17 , 18 ,2 0, 22 , 23 ,2 4, 2 5, 28 , 33, 3 5, 39
PR 2 45 *0_ 04 S LP _M
1 .0 5V S 13 ,1 4, 1 5, 19 , 20
ON 1 .0 5V S _V TT 2 , 3, 5, 1 8, 19 , 20, 3 5, 37
W243 1117 3 .3 V 2, 3, 8 , 11, 1 3, 15 , 17, 1 9, 20 , 22 ,2 3, 2 7, 29 , 31, 3 4, 36
1 .5 VS 19 ,3 0
5 VS 11 ,1 2, 1 9, 20 , 26, 3 0, 31 , 37, 3 8
V IN 11 ,3 1, 3 3, 34 , 35, 3 6, 37 , 38, 3 9
S Y S1 5V 33 ,3 5
5VS, 3VS, 1.5V/0.75VS, 1.5VS CPU B - 33

Schematic Diagrams
VDD3, VDD5
V RE F
PR1 9 5 *0 _0 4 P R7 7 0_04
PC1 9 5
1 u _ 10 V _ Y 5 V _ 0 6
P R 19 8 PR1 9 7
E N_ 3 V E N_ 5 V
P C2 0 1
1 0 0K _ 0 4 1 00 K _ 0 4 P C1 9 8
10 0 0 p_ 5 0 V _ X7 R _ 0 4 1 00 0 p _5 0 V _ X7 R _0 4
1
P U1 1
V R E G3
EN 2
V RE F
VFB2
T O NS E L
VFB1
E N1
V IN VIN
7 24
P C2 0 0 PC 6 4 VO 2 V O1
P C1 9 9 PR2 0 1 *1 0 K _ 04
4 . 7u _ 2 5V _ X 5 R _ 0 8 4 . 7 u _2 5 V _ X5 R _0 8 8 23
SYS5 V
VDD3 PQ 5 6
P 1 2 0 3B V
1u _ 1 0V _Y 5V _0 6
P C 20 3 9
L D O3 P OK
22
PC2 0 4 0 . 1u _ 1 0V _ X 7 R _ 0 4
P C2 0 6
0 . 1 u_ 5 0 V _ Y 5 V _ 06
P C2 0 5
4. 7 u _ 25 V _ X 5R _ 08
P C 74
4 . 7 u_ 2 5 V _X 5 R _ 0 8 5A
VDD5
B O OT 2 B OO T1
8
7
6
5
5
6
7
8
5A uP6182
0 . 1 u_ 1 0 V _ X7 R _ 0 4 P Q1 3
4 10 21 4 SYS5 V
U GA T E 2 U GA TE 1 P 1 20 3 B V
V DD3 SYS3 V PL 1 0 PL 9 VDD 5
PJ 1 0
3
2
1
1
2
3
PJ 8 4 . 7U H _ 6 . 8 *7 . 3 *3 . 5 0105 D02 1 4. 7 U H _ 6 . 8* 7. 3* 3. 5
2 1 2 1 11 20 2 1 2
PH ASE2 PHASE 1
* 5m m P C 72 PQ 6 0
Ra * 5 mm
C
12 19
8
7
6
5
5
6
7
8
P C6 5 P 1 2 0 3B V P R7 5
GN D P A D
L G A TE 2 L GA TE 1
0. 1 u _ 16 V _ Y 5 V _ 04
PQ 1 2 PD 9 P D2 1 P C6 1
S K IP S E L
Sheet 33 of 46 4 4
22 0 u _6 . 3 V _ 6. 3* 6. 3 * 4. 2
P R7 6 P C6 2 P D 6 P D5 30 K _ 1 %_ 0 6
L DO 5
V CL K
G ND
+
EN 0
P 1 2 0 3B V 1 0 00 p _ 50 V _ X 7R _ 04
C S O D 1 4 0S H
V IN
3
2
1
1
2
3
*S K 3 4 S A
1 3K _ 1 % _ 06 P C 93
1 00 p _ 50 V _ N P O _ 04
C S O D 1 4 0S H
A
A
PD 8 PD 7
Rb
*S K 3 4 S A
VDD3, VDD5
13
14
25
15
16
17
A
A
A C C A
18
V R E G5 V R E G5 * 10 0 0 p_ 5 0 V _X 7 R _ 0 4 P C 63 P C5 8
P R 22 8 P R1 9 6 +
*R B 05 4 0 S 2 PR2 0 9 E N _A L L 0105 D02 2 20 u _ 6. 3V _ 6 . 3 *6 . 3 *4 .02. 1 u _1 6 V _ Y 5 V _ 0 4
P R1 9 4 P C4 4 *R B 0 54 0 S 2 P R 11 3 1 . 5 M_ 0 4 19 . 1 K _ 1% _ 0 6
0105 D02 *6 80 K _ 1 % _0 4 P R 21 3 P R 2 10 P R 2 11
*1 0 00 p _ 50 V _ X 7 R _ 04 M9 90 12 5
2 0K _ 1 % _ 04 P R2 1 2 P D2 2 R B 0 54 0 S 2 * 5. 1 _ 0 6
P R9 3 PR2 1 4 0_ 0 4 *0 _0 4 2 . 2 _0 6 0 _ 0 4 * 0 _0 4 C A
VR EF SY S5 V
0104 D02 EMI P C 2 09 0105 D02
PR2 1 5 *0 _0 4 1124 change 0104 D02 EMI
V R E G5
*5 . 1 _0 6 P D2 3 R B 0 54 0 S 2
1 124 ch an ge fo r Po wer for Power 0 . 0 1 u_ 5 0 V _X 7 R _ 0 4 A C
SYS1 0 V
V IN1 V R E G5
P C6 9
P D 24
D
V RE G 5 P C 20 7 PC2 0 8 P D 2 9 R B 0 54 0 S 2
P Q 73 PR 8 6 *0 _ 04 EN_ 3 V C A 22 0 0 p_ 5 0 V _X 7 R _ 0 4
V IN
E N _ 3 V 5V
G P R9 0 4. 7 u _ 25 V _ X 5R _ 08 1 u_ 1 0 V _ Y 5 V _ 06 C A
39 U S B _ A C_ IN MT N 70 0 2 Z H S 3 R B 0 5 40 S 2 P C 2 10
S
PR 8 2 0_ 0 4 EN_ 5 V
1 0K _ 0 4 P D2 0 R B 0 54 0 S 2
0 . 0 1 u_ 5 0 V _X 7 R _ 0 4 A C
D
SYS1 5 V
P Q1 4 P C6 8
D D _ ON _E N _ V D D G
P Q 18 MT N 7 0 0 2Z H S 3 22 0 0 p_ 5 0 V _X 7 R _ 0 4
D
S
P C 71
P R 84
1
G P J1 1
2 7 , 28 , 3 2 D D _ O N
MT N 7 00 2 Z H S 3
* 4 0m i l
S
0 . 1 u_ 1 0 V _X 5R _0 4
1 0 0K _ 0 4
2
SYS5 V 3 2 ,3 5
SYS3 V 39
VIN 1 1 , 3 1, 32 , 3 4 , 35 , 3 6 , 37 , 3 8 , 3 9
V IN1 32
SYS1 5 V 3 2 ,3 5
V DD 5 2 0 , 2 7, 32 , 3 5
V DD 3 1 3 , 1 4, 15 , 1 7 , 18 , 2 0 , 22 , 2 3 , 2 4, 2 5 , 2 8, 3 2 , 3 5, 3 9
B - 34 VDD3, VDD5
Schematic Diagrams
Power 1.05VS/0.75V, 1.8VS

VIN
P D4
PU 4 A C PC 5 1 P C1 9 2 P C 19 1 PC 1 8 8 P C1 8 6
5V +
5
6
7
8
0. 1 u _ 5 0V _Y 5 V _ 0 6
4 . 7 u_ 2 5 V _ X 5 R _ 0 8
4 . 7 u _2 5 V _ X 5 R _ 0 8
0. 1 u _ 5 0V _Y 5 V _ 0 6
*1 5 u _ 25 V _ 6 . 3 *4 . 4 _ C
u P6 1 6 3 P Q 52
RB 0 5 4 0 S 2 4
MD U 2 6 5 7
VTT_MEM
P C5 6
1.5V
1
2
3
1 0 u _ 10 V _ Y 5V _0 8 V DD Q
PC 6 0 0 . 1 u _ 10 V _ X 7 R _ 0 4
23 22
V L DO IN VB ST
PJ 1 8 P R1 9 2
2 1 24 21
V T T _ ME M
* OP E N _ 2 A
VTT DR V H
3 .3 _ 0 6
PL 7
1. 0 U H _ 1 1 . 5 *1 0 . 2* 3 . 0
V DD Q 30A P J6
1 .5 V
1 20 1 2 1 2
P C1 9 4 P C5 5 PC 5 4 V T T GN D LL
PR8 0 *O P E N _1 2 A
0_ 0 6 2 19
1 0 u_ 1 0 V _ Y 5 V _ 0 8 10 u _ 1 0V _Y 5 V _ 08 * 1 0u _ 1 0V _Y 5 V _ 08 V T T S NS DR V L
5
6
7
8
PD 1 7
P C5 2 P C1 8 4 PC 4 8 P C4 9
C
3 18 PQ 5 1 P C1 6 9
5
6
7
8
G ND P GN D 17 4 +
*1 0 0 0p _ X 7 R _ 0 6
5 6 0u _ 2 . 5 V _ 6. 6* 6 . 6* 5 . 9
0. 1 u _ 1 6V _Y 5V _ 0 4
0 . 1 u _1 6 V _ Y 5 V _ 0 4
V DD Q P R 20 5 0 _0 6 P R8 1 0_ 0 6 P Q5 0
C S _ GN D +
M D U 2 6 544
*5 6 0 u _2 . 5 V _ 6 . 3 *6
1
2
3
P R 20 3 *0 _ 0 6 4 16 PR 8 3 6 . 1 9 K _ 1% _ 0 6 5V
5V M OD E CS
1
2
3
C S O D 1 4 0S H
* MD U 2 6 54 PR 7 3
A
P R 20 2 *0 _ 0 6 PC 7 0 0 . 1 u _ 10 V _ X 7 R _ 0 4 15
5 P V CC 5 14 PR8 9 2. 2 _ 0 4
V T T RE F V CC 5
*5 . 1 _ 0 6
PC 7 6 PC8 0 P R 91
P R2 0 6 0_06 6 13 P GO OD _ 6 16 3
5V C OM P P G OO D 3 .3 V 0 _0 6
1u _ 1 0 V _Y 5V _0 6
1 u _1 0 V _ Y 5 V _ 0 6
8 11
PR2 0 8
V TT _ M E M PR 1 9 3 * 22 _ 0 4 0105 D02
*1 0 0 0 p_ 5 0 V _ X 7 R _ 0 4 V D DQ S NS S5
P C7 5 P R 92
D
9 10 1 00 K _ 0 4
VD DQ SET S3
*1 0 _ 06
P Q5 7
V D D QS E T
SU SB G
Sheet 34 of 46
G ND
D D R 1. 5V _ P W R G D 1 5
*M T N 7 0 02 Z H S 3
NC
NC
S
P C7 9
* 1 00 0 p _5 0 V _ X 7 R _ 0 4
12
25
Power 1.05VS/
P R1 0 1
5V
* 10 K _ 1 % _ 04
5V
P R1 1 8 4 7 K_ 0 4 P R9 8 1 0 K _1 % _ 0 6
0.75V, 1.8VS
PR 9 9 1 0K _1 % _ 0 6
D
P C 84
D
P Q 23
P R1 1 7 1 00 K _ 0 4 G MT N 7 00 2 Z H S 3 P Q2 4 *0 . 1 u _ 16 V _ Y 5V _0 4
G
S
1
P R1 0 3 1 0 0K _ 0 4 VT TEN *M TN 7 0 02 Z H S 3
5V
S
P Q2 2 PJ 1 2
G * 40 m i l
1 5 , 28 S US C #
D
PC8 2 MT N 7 00 2 Z H S 3
3 1, 3 2 D D _ ON #
2
S
PQ 1 9
SU SB G 0. 1 u _ 1 6V _Y 5 V _ 04
M T N 7 0 0 2Z H S 3
S
1 .5V _CTR L1 1. 5_ CTRL0 Volt a ge
1 1 1 .5 5V
1 0 1 .6 0V
0 1 1 .6 5V
0 0 1 .7 0V
3 .3 V ? ? ? ? PIN6?
3 .3 V
5V
P R1 1 0 1 0K _0 4 PC 9 1 1.8VS
2A 5
PU 5
6
1 u _ 10 V _ Y 5V _0 6
V 1. 8 1 .8 V S
1 .8 V S _ P W RG D
9
7
V IN
V IN
V C N TL
4
3A 1
PJ 7
2
3 , 1 5 1 . 8 V S _ P W R GD PO K V O UT
3
1 0 u_ 6 . 3 V _ X 5 R _ 0 6
0 . 1 u _ 16 V _ Y 5 V _ 0 4
*O P E N _ 3 A
10 u _ 6 . 3 V _X 5R _ 06
P R1 0 5 1 0 0 K _0 4 E N1 .8 V S 8 V O UT PR 7 8
5V EN 1 . 2 7 K _1 % _ 0 4
1 2
G ND VFB 6, 1 8 , 1 9 1 . 8V S
1 1, 3 1 , 3 2 , 3 3, 3 5 , 3 6 , 3 7, 3 8 , 3 9 V IN
D
P C 90 PC 6 6
PQ 1 5 2 3, 2 7 , 3 1 , 3 2, 3 5 , 3 6 5V
AX6615ESA 2, 3 , 8 , 1 1 , 1 3, 1 5 , 1 7 , 1 9, 2 0 , 2 2 , 2 3, 2 7 , 2 9 , 3 1, 3 2 , 3 6 3 . 3V
S US B R 69 5 0_ 0 4 G P C8 5 P C8 3
3 , 32 , 3 5 SU SB 1 1/09 3, 6 , 8 , 9 , 1 0 , 2 0, 2 7 , 3 2 1 . 5V
M T N 7 0 02 Z H S 3 8 2 p_ 5 0 V _ N P O _ 0 4
0 . 1 u_ 1 6 V _ Y 5 V _ 04
9 ,1 0 V T T _M E M
S
1 0 u _ 6. 3 V _ X 5 R _0 6
R 69 6 *0 _ 04
0 . 1 u _ 16 V _ Y 5 V _ 0 4
P C5 7
P R 79
P C 67
P C5 9
P C 30 4 GS7113 1 K _ 1% _ 0 4
D
*0 . 1 u _ 16 V _ Y 5 V _ 0 4
PQ 9 9 6-02-07113-320
G
1 5 ,2 8 S U S C# 1129 AX6610
M T N 7 0 0 2Z H S 3
S
6-02-06610-320
Power 1.05VS/0.75V, 1.8VS B - 35

Schematic Diagrams
Power 1.05VS LAN M

V IN
PD4
P U4 A C PC 5 1 PC1 9 2 P C 19 1 PC 1 8 8 P C1 8 6
5V +
5
6
7
8
0. 1 u _ 5 0V _Y 5V _ 0 6
4 . 7 u_ 2 5 V _ X 5 R _ 0 8
4 . 7 u _ 25 V _ X 5 R _ 0 8
0. 1 u _ 5 0V _Y 5V _ 0 6
*1 5 u _ 25 V _ 6 . 3 *4 . 4 _ C
u P6 1 6 3 P Q 52
RB 0 5 4 0 S 2 4
MD U 2 6 5 7
VTT_MEM
PC5 6
1.5V
1
2
3
10 u _ 1 0V _ Y 5 V _ 08 V DD Q
PC 6 0 0. 1 u _ 1 0V _X 7 R _ 0 4
23 22
V L D OI N VB ST
PJ 1 8 P R1 9 2
2 1 24 21
V T T _ ME M
*O P E N _ 2 A
VT T DR V H
3. 3 _ 0 6
PL 7
1. 0U H _ 1 1 . 5 *1 0 . 2* 3 . 0
V DD Q 30A P J6
1 .5 V
1 20 1 2 1 2
P C 19 4 P C5 5 PC 5 4 V T T GN D LL
P R8 0 *O P E N _1 2 A
0_ 0 6 2 19
1 0 u_ 1 0 V _ Y 5 V _ 0 8 1 0u _ 1 0 V _Y 5 V _ 08 * 1 0u _ 1 0 V _ Y 5 V _ 0 8 VT TSN S DR V L
5
6
7
8
P D1 7
P C5 2 P C1 8 4 PC 4 8 P C4 9
C
3 18 PQ 5 1 PC1 6 9
5
6
7
8
G ND P G ND 17 4 +
*1 0 0 0p _ X 7 R _ 0 6
5 6 0u _ 2 . 5 V _ 6. 6* 6 . 6* 5 . 9
0. 1 u _ 1 6V _Y 5V _ 0 4
0 . 1 u _1 6 V _ Y 5 V _ 0 4
VDD Q P R 2 05 0 _0 6 P R 81 0 _0 6 P Q5 0
CS _ G ND +
M D U 2 6 544
*5 6 0 u _2 . 5 V _ 6 . 3 *6
4 16 5V
1
2
3
P R 2 03 *0 _ 0 6 PR 8 3 6 . 1 9 K _ 1% _ 0 6
5V M OD E CS
C S O D 1 4 0S H
1
2
3
* MD U 2 6 54 PR 7 3
A
P R 2 02 *0 _ 0 6 PC 7 0 0. 1 u _ 1 0V _ X 7 R _ 0 4 15
5 P V CC 5 14 PR8 9 2. 2 _ 0 4
V T T RE F V CC 5
*5 . 1 _ 0 6
P C7 6 PC8 0 P R 91
P R 20 6 0_06 6 13 P GO O D _ 6 16 3
5V C OM P P GO OD 3 .3 V 0 _0 6
1u _ 1 0 V _ Y 5 V _0 6
1 u _1 0 V _ Y 5 V _ 0 6
P R2 0 8
P R1 9 3 * 2 2_ 0 4 8 11 0105 D02
V T T_ M E M V D DQ S NS S5
* 10 0 0 p _5 0 V _ X 7 R _ 0 4
P C7 5
P R 92
D
9 10 1 00 K _ 0 4
V D DQ S E T S3
*1 0 _ 06
Sheet 35 of 46
P Q5 7
V D D QS E T
SU SB G
G ND
D D R 1. 5V _P W R G D 1 5
N C
*M T N 7 0 0 2Z H S 3
NC
S
PC7 9
* 1 00 0 p _ 50 V _ X 7 R _0 4
Power 1.05VS LAN
12
25
M 5V
P R1 0 1
* 10 K _ 1 % _ 04
P R1 1 8 4 7 K_ 0 4 P R9 8 1 0 K _ 1% _ 0 6
5V
P R9 9 1 0 K _1 % _ 0 6
D
P C 84
D
P Q 23
P R1 1 7 1 00 K _ 0 4 G MT N 7 00 2 Z H S 3 P Q2 4 *0 . 1 u _ 16 V _ Y 5V _0 4
G
S
1
PR1 0 3 1 0 0K _0 4 VTT EN *M T N 7 0 02 Z H S 3
5V
S
P Q2 2 PJ 1 2
G * 4 0m i l
1 5 ,2 8 SUS C#
D
P C8 2 M TN 7 00 2 Z H S 3
3 1, 32 D D_ O N#
2
S
P Q1 9
S US B G 0. 1u _ 1 6 V _Y 5 V _ 04
MT N 7 0 0 2 Z H S 3
S
1 .5 V_C TR L1 1. 5_ CTRL0 Volt a ge
1 1 1 .5 5V
1 0 1 .6 0V
0 1 1 .6 5V
0 0 1 .7 0V
3 .3 V ? ? ? ? PIN6?
3 .3 V
5V
P R1 1 0 1 0 K _0 4 PC 9 1
1.8VS
2A 5
P U5
6
1 u _ 10 V _ Y 5V _0 6
V1 .8 1 .8 V S
1. 8 V S _P W R G D
9
7
V IN
V IN
V C N TL
4
3A 1
PJ 7
2
3, 1 5 1 . 8 V S _ P W R GD PO K V O UT
3
1 0 u_ 6 . 3 V _ X 5 R _ 0 6
1 0u _ 6 . 3 V _X 5R _ 0 6
0 . 1 u _ 1 6V _ Y 5 V _ 0 4
*O P E N _ 3 A
PR1 0 5 1 0 0 K _ 04 E N1 .8 V S 8 V O UT PR 7 8
5V EN
1 . 2 7 K _ 1% _ 0 4
1 2
G ND VF B 6, 1 8 , 1 9 1 . 8V S
1 1, 3 1 , 3 2 , 3 3, 3 5 , 3 6 , 3 7, 3 8 , 3 9 V IN
D
P C 90 PC 6 6 2 3, 2 7 , 3 1 , 3 2, 3 5 , 3 6 5V
PQ 1 5 AX6615ESA
SUSB G 2, 3 , 8 , 1 1 , 1 3, 1 5 , 1 7 , 1 9, 2 0 , 2 2 , 2 3, 2 7 , 2 9 , 3 1, 3 2 , 3 6 3 . 3V
R 69 5 0_ 0 4 P C8 5 P C8 3 1 1/09
3 , 3 2, 3 5 SU SB M T N 7 0 0 2Z H S 3 8 2 p _5 0 V _ N P O _ 0 4 3, 6, 8 , 9 , 1 0 , 2 0, 2 7 , 3 2 1 . 5V
0 . 1 u_ 1 6 V _ Y 5 V _ 04
S 9 ,1 0 V T T _M E M
1 0 u _ 6. 3 V _ X 5 R _0 6
R 69 6 *0 _ 04
0. 1 u _ 1 6V _Y 5 V _ 0 4
P C5 7
P R 79
P C 67
PC5 9
P C 30 4 GS7113 1 K _ 1% _ 0 4
D
*0 . 1 u _ 16 V _ Y 5 V _ 0 4
PQ 9 9 6-02-07113-320
G
15 , 2 8 S U S C# M T N 7 0 0 2Z H S 3
1129 AX6610
S
6-02-06610-320
B - 36 Power 1.05VS LAN M

Schematic Diagrams
Power 0.85VS
3.3V
PC129
0.022u_16V_X7R_04 PR159
10K_04
0.9V 0.8V 0.725V 0.675V

0. 85VS_PWRGD 15 VIN
VCCSA_VID0 0 0 1 1
PR137 VIN
VCCSA_VID1 0 1 0 1
0_04
4.7u_25V_X5R_08
4.7u_25V_X5R_08
0.1u_50V_Y5V_06
0.1u_50V_Y5V_06
0.1u_50V_Y5V_06
0.1u_50V_Y5V_06
PC173 0. 1u_50V_Y5V_06
5V
PR33 PR147
9. 31K_1%_04 9. 31K_1%_04
A
1 1/0 4 PR34 PR146 PR148 PD1
FOR EMI
PC34
PC155
PC153
PC154
PC197
PC47
100_04 RB0540S2
12K_1%_04 10K_1%_04
PR35 PR145
POK
1
2
10K_1%_04 10K_1%_04
PQ36A
PU9 PC140 PD1503YVS
5
4
3
2
1
PR36 PR144 uP6122
0.1u_16V_Y5V_04
8
Sheet 36 of 46
EAP
BOOT
UG
SS
POK
PL4 6A V0.85 PJ5 0. 85VS
7
15K_1%_04 10K_1%_04 21 1.0UH_6.8*7.3*3.5 *OPEN- 5mm
6
7
8
SET3
SET2
GND
PHASE
LG
20
19
18
1 2 1 2
Power 0.85VS
PR151 9 SET1 VCC 17
EN/ PSM
10 SET0 RT 16 PC40
COMP
FB CSP
PR173
VI D1
PR62 PR64
VI D0
CSN
PC27
1K_1%_04 0_04 0_04 + PC1 68
CSP
5
6
0. 1u_16V_Y5V_04
220U_4V_D2_D
11
12
13
14
15
PR150 PC124 PR157
3
1u_10V_Y5V_06
100_04
33K_1%_04
CSN
PC131 0. 01u_50V_X7R_04
22_04 0. 01u_16V_X7R_04 PQ36B
4
PC25 PD1503YVS PR63 1 1/0 5
12K_1%_04
47p_50V_NPO_04 PC41
PR155 *0_04 PR158
PC42
0.1u_25V_X7R_06
CSP
*0.1u_16V_Y5V_04
100K_1%_04 01 03 D 02 W2 40X
CSN
0.85V_ON 35
PR65 1.3K_1%_04
6 VCCSA_VID0
6 VCCSA_VID1 PR1 49
VCCSA_SENSE 6
0_04
5V 23,27,31, 32,34,35
0.85VS 6
VIN 11,31,32, 33,34,35,37, 38,39
3.3V 2,3,8, 11,13,15,17, 19,20,22,23,27, 29,31,32,34
Power 0.85VS B - 37
Schematic Diagrams
Power V-Core1
PR 2 2 PC1 1
1.0 5VS_VTT
1 0_ 0 4 6 8 0 p _5 0 V _ X 7R _ 0 4
VCORE_1 PR 2 0 P R 1 9 1 . 2 1 K _ 1% _ 0 4
B~ 4 35 0
T R BST
2 4 . 9 K _ 1 %_ 0 4 PUT COLSE
5 4. 9 _ 1 % _0 4
PR1 5 P R 10 P R1 2 P C7
RT 4 TO VCORE
1 3 0 _ 1% _ 0 4 *7 5 _ 04 5 6 0 0p _ 5 0V _X 7 R _0 4 1 2
A_ GN D Phase 1
5 H_ C P U_ S V IDD A T H _C P U _S V I D D A T 1 00 K _ N T C _ 0 6_ B Inductor Q ua d 45 W CPU
5 H _ C P U _ S V I D C LK H _C P U _S V I D C L K P R 1 31 P C1 1 3 PC 1 2
D IFFO UT
5 H _ C P U _ S V I D A L R T# H _C P U _S V I D A L R T# 1 0 0_ 1 % _ 04 10 0 p _ 50 V _ N P O_ 0 4 2 2 p _ 50 V _ N P O_ 0 4 P R1 4 1 1 3 7K _ 1 % _ 0 6
C SP1 38
VI D1 =0 .9 V
PR2 7 7 5 K _ 1 %_ 0 4
FB
PR 1 3 0 1 K _ 04 P R2 1 P C1 3 PR 1 3 3 I cc Max = 9 4A
TSENS E 4 . 02 K _ 1 % _ 0 4 3 3 0 0 P _ 50 V _ X 7 R _ 0 4 16 5 K _ 1 % _0 6 R_ L L= 1. 9m ohm
10/29 P R3 1 1 3 7K _ 1 % _ 0 6
P R1 8 9 1 0 0_ 0 4 P R2 8 1 2. 1 K _ 1 % _ 04 P C 15 1 20 0 P C SP3 38 O CP~ 1 20 A
P R1 2 8 0_04 V S S _ S E N S E _ 61 3 1 P C 14 2 70 p _ 5 0V _X 7 R _0 4
5 V C OR E _ V S S _ S E N S E
PC 5 CSS UM
PC8
P R 18 7
R T3
P R 1 42 1 0 _ 04
C SN1 38
0 . 1 u_ 1 0 V _ X 7 R _ 0 4
1
1 00 0 p _ 50 V _ X 7 R _ 0 4
C SCO M P
P R1 2 4 0_04 VR 1_ C SRE F
B~ 3 96 4 5 V CO RE _ V C C_ S E NS E
TR BST
CO MP
I MO N
CS N 3 38
1 0 0 K _ N T C _ 06 _ B
VCORE P R 1 88 10 0 _ 0 4 PR9 * 15 m i _l 0 6 PR 3 2 1 0 _ 04
8 . 2 5K _ 1 % _ 0 4
IL IM
C SN3 38
V C C_ SE N SE _ 6 1 3 1
PC 2 0 PC 2 2 0. 0 4 7 u _1 0 V _ X 7 R _ 0 4
PUT COLSE 3.3VS A _G ND 1 0 00 p _ 5 0V _X 7 R _0 4
TO VCORE P R4 2 5 . 4 9 K _ 1% _ 0 4
53
52
51
50
48
47
46
45
43
41
40
49
44
42
A_ G ND PU 1 CS P 3 38
A_ GN D
HOT SPOT A_ GN D
EPA D
VS N
F B
N C2
NC 1
I LI M
C SSU M
C OM P
D R O OP
C S C OM P
D I F F OU T
T R BST
IO UT
CSR E F
P R1 6 PR1 1
PR1 5 3 0_ 0 4 CS N 1 38
1 0 K_ 0 4 1 0 K_ 0 4 1 39 C S N 2 _5 V S
5VS
Sheet 37 of 46 3 H _ P R O C H O T# P R2 3 0 0_ 0 4
H _ CPU _ SVID DAT
TSENS E 2
3
4
VSP
TS E N S E
V R H OT #
SDIO
N C P 61 3 1 S
CS N 2
C SP2
CS N 3
C SP3
38
37
36
CS N 3
CS PP 3
PC 2 3 0. 0 4 7 u _1 0 V _ X 7 R _ 0 4
H _ CPU _ SVID CL K 5 35 CSN 1 PR 4 3 5 . 4 9 K _ 1% _ 0 4
Power V-Core1 1 5 D E L A Y _P W R G D
P R8 0_04
H _ CPU _ SVID ALR T#
VR _ RD Y
VR _ RD YA
6
7
8
SCL K
A LE R T #
V R_ RD Y
CS N 1
C SP1
D R ON
34
33
32
CS PP 1
DR ON
D RO N 38
CS P 1 38
V R 1 _P W M1 3 8
VR_ O N V R _ ON _ E N A B LE _6 1 3 1 9 V R_ RD Y A P W M1 / A D D R 31 V R1 _ P W M 3
10 ENA BL E P W M 3 / V B OO T 30 V R 1 _P W M3 3 8
61 31 _ VC C P W M 2_ 6 1 3 1 PR 3 9 0 _0 4
5VS P R1 2 5 2 .2 _ 0 6 P R 14 1 0 K _ 0 4 R OS C 11 VCC P W M2 / I S H E D 29 I MA X _ 6 1 31 5VS PR 1 5 6
VIN P A_G N D 12 RO S C IM A X 28
R1 7 V R MP _V I N VR1_ PWM A
D IF F O UT A
VRM P P W M A /IM A X A V R 1 _P W MA 38
C S C OM P A
1 K _ 1% _ 0 4 T SEN SEA 13 27 V B O OT A P R 41 P R 1 52 1 0 K_ 0 4
5VS
D R OO P A
CSS U M A
TS E N S E A V B OO T A
TR BSTA
* 0 _0 4 P R3 8
CO M P A
IO UT A
VS PA
IL IM A
C SPA
CSN A
TSEN SEA PC 3 P C6 P R4 0 PR 1 5 4 1 0 K_ 0 4
V SNA
F BA
PR 1 8 4 1 . 2 K _ 1 %_ 0 4
1 u _ 6. 3V _X 5 R _ 0 4 0. 0 1 u _ 50 V _ X 7 R _ 0 4 10 K _ 0 4 2 0 . 5 K _ 1% _ 1 / 1 6 W _ 04
* 1 4K _1 % _ 0 4 OPTION: A_ G ND
14
15
16
18
19
20
21
23
25
26
1
17
22
24
DISALBE
1
P J1 4 P R3 7 A_ G ND P J1 3 P R 1 43
V S N A _ 6 1 31
VSPA_ 6 1 3 1
PC 1 1 4 V_GT A_ G ND * 6 m li
* 6 mi l 1 1 3 K _ 1% _ 0 4
RT 1
IC C_MA X_2 1h
2
A_G ND A_G N D 11 3 K _ 1 % _0 4
I MO NA
PR 1 6 9
2
= R*10 uA*25 6A /2 V
0 . 1 u _ 10 V _ X 7 R _0 4
IL IM A
P C2 1 A_G N D 20100805
B~ 39 64 1 00 0 p _ 50 V _ X 7 R _ 0 4
A _G ND
C SNA A_G ND
10 0 K _ N T C _ 0 6 _B
2
IMO NA I MO N C SPPA
8 . 2 5 K _ 1% _ 0 4
PC 1 9
0 . 0 22 u _ 1 6V _ X 7 R _ 0 4 CS N A 38
CSSU M A PR1 3 5
CS P A 38
PR1 4 0 P C 1 17 P R 13 4 PC 1 1 8 CSC OM PA PC 1 6 47 0 p _ 50 V _ X 7 R _ 0 4 11 5 K _ 1 % _0 6 P R 13 9
24 K _ 1 % _ 04 24 . 3 K _ 1 % _ 04 7. 5K _ 1 % _ 0 4 CS P A 38
A_ G ND 0 . 1 u_ 1 0 V _ X 5R _ 04 P R 1 32
0 . 1 u _1 0 V _ X 5R _ 0 4 15 K _ 1 % _ 04
C O MPA PC 1 7 27 0 P _ 5 0 V _ X7 R _0 4
PUT COLSE DIFF OU TA
A_G ND A _G ND
TO V_GT A_ GN D A_ GN D P R2 4 PR 2 6
P C1 0 P R2 5 7 5 K _ 1 % _0 4 1 6 5 K _ 1% _ 0 6
HOT SPOT P R 1 9 1 1 0 0 _ 04 6 8 P _ 50 V _ N P O_ 0 4 1 0 _0 4 RT 2
PR 2 3 1 2 Qua d V CCAX G
P R1 2 7 0 _ 0 4 1 K_ 0 4 VID 1= 1 .15 V
6 V S S _ GT _ S E N S E F BA P C1 1 5 10 0 K _ N TC _ 06 _ B
B~ 4 35 0 Ic cM a x = 26 A
PC 9 1 0 0p _ 5 0 V _ N P O _0 4 R_LL= 3 .9 m ohm
P R1 2 6 0 _ 0 4 1 0 0 0 p_ 5 0 V _ X7 R _ 04
6 V C C _ GT _ S E N S E
P C1 1 6 PUT COLSE OC P~ 31 A
P R 12 9 3 . 0 1 K _ 1% _ 0 4 3 3 00 p _ 5 0V _X 7 R _ 0 4
P R 1 9 0 1 0 0 _ 04 TO V_GT
V_ GT Inductor
PR 6 *1 0 K _ 0 4 V R_ O N
3 .3 V S
1 2
PR3
6
PJ 2 * 6 mi l
*1 0 0K _0 4 D
P Q 6 9A P R5
2
G
S *1 0 K _ 04
3 1
*MT D N 7 0 0 2Z H S 6 R PR 7 *1 0 m li _ 0 4
D V R _O N
1
1 1, 15 , 2 8 A L L _ S Y S _ P W R G D
P Q6 9 B PJ 1
5
28 V CO RE _ O N G * 6m i l
S
4 1 1 , 1 2, 19 , 2 0 , 2 6, 30 , 3 1 , 3 2, 38 5 V S
2
* MT D N 7 0 02 Z H S 6 R
3 , 9 , 1 0 , 1 1, 12 , 1 3 , 1 4, 15 , 1 6 , 1 7, 18 , 1 9 , 2 0 , 23 , 2 4 , 2 5 , 26 , 2 8 , 2 9 , 30 , 3 1 , 3 2 3. 3V S
38 V_ G T
5 , 38 VCO RE
PC 1 13 , 1 4 , 1 5 , 19 , 2 0 , 3 2 1. 05 V S
11 , 3 1 , 3 2 , 33 , 3 4 , 3 5 , 36 , 3 8 , 3 9 V I N
* 0. 1 u _ 1 6V _Y 5 V _ 04 2 , 3, 5 , 1 8 , 1 9 , 20 , 3 5 1 . 0 5 V S _ V T T
B - 38 Power V-Core1
Schematic Diagrams
Power V-Core2 VGFX

VIN
VCORE_2 P C 22 3
+
P C 13 3
+
P C1 5 2 P C 14 9 P C 16 1
*4 . 7 u _2 5 V _ X 5 R _ 0 8
15 u _ 25 V _ 6 . 3* 4 . 4
*4 . 7u _ 2 5V _X 5 R _0 8
0. 1 u _ 50 V _ Y 5 V _ 06
*3 30 u F _ 2 5V
P R1 3 6 P C 11 9
P Q 29 P Q3 9
2. 2 _ 0 6 M DU2 6 5 7 *MD U 2 6 5 7
D
0. 2 2 u _1 0 V _ X 7R _ 06
1125 G G
PU 8 N C P 5 9 11 11/03
P R 16 5 0 _ 06
25A
S
1 8 V R E G_ S W 1 _ H G _ R V R E G _ S W 1 _H G P L6
B ST HG 0. 3 6 u H _ 1 2. 9 * 14 *3 . 8
2 7 V R E G_ S W 1 _ OU T 1 2 VC OR E
37 V R 1 _ P W M1 P WM SW P Q 38 P Q 46 P Q2 8 VCO RE
PR1 3 8 3 M DU2 6 5 4 M DU2 6 5 4 *MD U 2 6 5 4 P C3 6
GN D 6
D
37 D R ON 0224 2 K _ 1 %_ 0 4 EN
C
4 V R E G_ S W 1 _ L G 10 0 0 p_ 5 0 V _X 7 R _ 0 4
5VS VC C LG 5
G G G PD1 5
PAD P R6 9 *1 5 m li _ 0 6
2. 2u _ 6 . 3V _ X 5 R _ 0 6
C SN1 37
S
9 SK3 4 SA
P R5 7
A
5. 1 _ 0 6 P R6 7 *1 5 m li _ 0 6
C SP1 37
P C1 2 5 0104 D02 EMI
P C 13 0 P C 12 0 P C 12 1 P C1 2 2
+
50A
15 u _ 25 V _ 6 . 3* 4 . 4
*4 . 7u _ 2 5V _X 5 R _0 8
*4 . 7u _ 2 5V _X 5 R _0 8
5, 3 7 VCO RE
0. 1 u _ 50 V _ Y 5 V _ 06
P R2 9 P C 18 VIN
P Q4 0 P Q3 0
MD U 2 65 7 *MD U 2 6 5 7
D
2. 2 _ 0 6 0. 2 2 u _1 0 V _ X 7R _ 06 +P C 17 6 +P C 17 2 +P C 17 8 +P C 17 4 +P C 1 7 5 + P C 1 7 0 + P C 1 7 7 + P C 1 7 1
1125 G G
5 60 u _ 2. 5V _ 6 . 6 *6 . 6 *5 . 9
5 60 u _ 2. 5V _ 6 . 6 *6 . 6 *5 . 9
5 60 u _ 2. 5V _ 6 . 6 *6 . 6 *5 . 9
5 60 u _ 2. 5V _ 6 . 6 *6 . 6 *5 . 9
5 60 u _ 2. 5 V _ 6 . 6 *6 . 6 *5 . 9
*3 3 0 U _ 2 . 5V _ D 2
*3 3 0 U _ 2 . 5V _ D 2
*3 3 0 U _ 2 . 5V _ D 2
PU 2 N C P 5 9 11
P R 16 6 0 _ 06
S
1 8 V R E G_ S W 3 _H G_ R V R E G _S W 3_ H G P L5
37 V R 1 _ P W M3 2
B ST
P WM
HG
SW
7 VR EG_ SW3 _ OUT
P Q4 5 P Q 41 P Q3 1
0. 3 6 u H _ 1 2. 9 * 14 *3 . 8
1 2 VC OR E 25A V C OR E
Sheet 38 of 46
Power V-Core2
37 D R ON PR3 0 3 GN D 6 MD U 2 65 4 M DU2 6 5 4 *MD U 2 6 5 4 P C4 3
D
0224 2 K _ 1 %_ 0 4 EN
4 5 VR EG_ SW3 _ L G 10 0 0 p_ 5 0 V _X 7 R _ 0 4
5VS
C
VC C LG G G G
2 . 2 u _6 . 3 V _ X 5R _ 06
PAD P D 11 P R7 0 *1 5 m li _ 0 6 CSN 3 37
VGFX
S
9 P R6 6
S K 3 4S A
A
5. 1 _ 0 6 P R6 8 *1 5 m li _ 0 6 CSP 3 37
P C2 4
0104 D02 EMI
P C1 2 3
+
PC1 2 7 P C1 2 8 P C 12 6
VGFX_CORE
1 5 u_ 2 5 V _6 . 3 *4 . 4
*4 . 7 u _2 5 V _ X 5 R _ 0 8
0 . 1 u_ 5 0 V _Y 5V _ 0 6
*4 . 7 u _ 25 V _ X 5 R _ 0 8
VIN
P R5 2 P C 30 V_GT
P Q3 3
*MD U 2 6 5 7 P Q 32
D
2. 2_ 0 6 0. 2 2 u _1 0 V _ X 7R _ 06 M DU2 6 5 7 PR6 0 *1 5 m li _ 0 6
D
G
PU 3 N C P 5 9 11 G
S
VGFX_CORE
S
1 VR EG_ SWA _H G P L3
HG 8
37 V R 1 _ P W MA
2
B ST
P WM SW
7 VR EG_ SWA
0. 3 6 u H _ 1 0* 10 * 3. 5
1 2 VG FX_ C OR E 25A
P Q4 4 P Q 43
PR5 4 3 *MD U 2 6 5 4 M DU2 6 5 4 PC3 7
P D2
37 D R ON GN D 6
D
0224 2 K _ 1 %_ 0 4 EN + P C1 4 7 +P C 16 4
4 5 VR EG_ SWA _L G 11/09 *1 00 0 p _5 0 V _ X 7R _ 04
5VS VC C LG G G
*3 30 u _ 2. 5 V _ 9 m _6 . 3 *6
3 30 u F _ 2 . 5V _ 9 m _ 6. 3 *6
PAD P R 59 *1 5m i l _0 6
2. 2u _ 6 . 3V _ X 5 R _ 0 6
C S NA 37
S
9 PR6 1
C S O D 1 4 0S H
A
*5 . 1 _0 6
PC 3 8
P R 58 *1 5m i l _0 6
C SPA 37
0105 D02
V C OR E 5 , 3 7
V _ GT 37
V G F X _C OR E 6
1 1 , 31 , 3 2 , 3 3, 3 4 , 3 5, 3 6 , 3 7, 39 V I N
1 1 , 12 , 1 9 , 2 0, 2 6 , 3 0, 3 1 , 3 2, 37 5 V S
Power V-Core2 VGFX B - 39

Schematic Diagrams
AC IN, CHARGER
PR1 6 1 0 _ 04
VA
PR2 5 3 * 47 0 K _0 4
PQ 2
4
01 0 4 D 0 2 EMI V IN ME P 44 3 5 Q8 V _B A T
1 5
2 6
3 7
P C 31 2 P C 31 1 P C3 1 0 8
J_ D C _ JA C K 1
0 . 1 u_ 5 0 V _Y 5 V _0 6 0 . 1 u_ 5 0 V _Y 5V _0 6 0. 1 u _ 50 V _ Y 5 V _ 06
65 W ~ 9 0W / 3 P I N (6-2 0 -B 3 41 0 -0 03 / 6 -2 0-B 3 4 2 0-0 0 3 / 6-2 0 -B 3 43 0 -0 03 / 6 -2 0-B 3 4 2 0-1 0 3) ? ? JBA TT A1
PL 2 VA P Q9 4 8. 2U H_ 7.3 *6 .6* 2. 8MM
H C B 4 5 32 K -8 0 0T 9 0 ME P 44 3 5Q 8 P Q1 A
P C 10 5 8 P R 2 49 P D 1 50 3 Y V S 11 2 9 EMI PL 1 1 0224 PR 4
1 P C 30 5 7 3 0 . 0 2_ 1 %_ 3 2 2 T MP C 06 0 3 H -8 R 2 M-Z 0 1 0. 0 2 _ 1% _ 32
2 6 2 1 7
0 . 1 u_ 5 0 V _Y 5 V _ 0 6
3 5 1
0 . 1 u_ 5 0 V _Y 5 V _ 0 6
4 . 7 u_ 2 5 V _X 5 R _0 8
1 0 _0 6
10 _ 0 6
4 . 7 u _2 5 V _X 5R _0 8
4 . 7 u_ 2 5V _ X 5 R _ 0 8
4 . 7 u _2 5 V _ X 5R _0 8
4. 7 u _ 25 V _ X 5 R _ 0 8
4 . 7 u_ 2 5V _X 5 R _ 0 8
10 _ 0 6
1 0 _0 6
4 . 7 u_ 2 5V _X 5 R _ 0 8
4 . 7 u _2 5 V _ X 5R _ 08
4 . 7u _ 25 V _ X 5 R _ 0 8
4 . 7 u_ 2 5 V _X 5 R _ 0 8
0 . 1 u _5 0 V _ Y 5V _ 0 6
4. 7 u _2 5 V _ X 5R _ 08
G ND 1
5
6
P R 2 82 P C 30 2
G ND 2 1 0 K _ 04
8
* 10 0 0 p_ X 7R _ 06 1 1 30 EM I
PR 2 3
1 0 0K _ 0 4 P R 29 0
W250HU
D02A P Q 1B
4
P R 28 0
P R2 8 3
P C 23 4
P C 2 33
P C2 3 2
P C 23 0
P R2 5 6
P R 2 57
P C 22 5 P D 15 0 3Y V S P C1 3 5 P C 3 0 6 P C 30 7
* 5. 1 _ 0 6 1229 D02 5
1 13 0 EMI
P C 10 8
P C 2 31
P C 23 9
P C 2 38
P C3 0 9
P C 30 8
P C 2 35
0 . 1 u_ 5 0 V _Y 5V _ 0 6
P C 2 28
0 . 1u _ 5 0V _ Y 5 V _ 06
A
0. 0 4 7 u_ 1 0V _X 7 R _ 0 4 4
P D1 4 PR 1 0 . 0 47 u _1 0 V _ X7 R _0 4 3
2
MD L9 1 4S 2 1 5 K _0 4 P C 2 37
0224 0 . 1 u _5 0 V _ Y 5 V _0 6 1
BST_ L L X _C H G 1 4 13 J B A T TA 1
LX H DR
C
*B T D -0 5 T C 1 B
L DR 16 5 IC HP
LD R IC HP
PR2 8 8 0 _0 4 B S T 12 4 IC HM W240HU
P R 2 50 B S TOZ8681 I C H M
VAC 1 11
VAC S DA 5
10 _ 06 C A V D DP 15 10 S M C _ B A T _R
Sheet 39 of 46 P D 2 5 R B 0 5 40 S 2 IA C M 3
V DD P
IA CM
SC L
IAC
7 IA C 1 F C M1 00 5 K F -1 2 1T 0 3
1 2 P L 1 2 B A T _ D E T _R
S M D _ B A T _R
4
3
2
D
IA C P 2 8 C OMP _ O 28 B A T_ D E T 1
AC IN, CHARGER P Q9 6
G 9
IA CP C O MP
6
J B A T TA 2
B ASE
MT N 70 0 2 Z H S 3 AC AV B T D -0 5T I 1 G
A CA V V D DA
F C M1 0 05 K F -1 2 1T 0 3 1 2 P L1 4 S MC _ B A T 2 8
S
PR1 6 3
P U 10 0 _0 4 F C M1 0 05 K F -1 2 1T 0 3 1 2 P L1 3 S MD _ B A T 2 8
17
PR1 6 4
*1 5m i l _s h or t _0 6 PC2 9 9
P R 16 0 P C 13 2 PC2 2 4 P C1 3 6 P C 22 7
*1 u _2 5 V _ 08 *1 u _ 25 V _ 08 1 u _2 5 V _ 08 3 0p _ 50 V _ 0 4
1 00 K _ 0 4
1 00 0 P _5 0 V _ X 7 R _ 04
PC1 3 7 PC3 0 0
PR1 6 2
P C 2 36 1 00 _ 04 P C1 3 8 0 . 47 u _ 10 V _ Y 5 V _ 0 4 3 0p _ 50 V _ 0 4
1 u _ 10 V _ 0 6 1 u_ 1 0 V _0 6 P R2 8 9 1 0 _ 06 TO TA L _ C U R 2 8
PC3 0 1
3 0p _ 50 V _ 0 4
V DD3 P C2 9 8
R es et c ir cu it S MC _B A T
4 7p _ 5 0V _ N P O_ 04
P R 2 55
P R2 5 9
P Q 97 P R 2 87 1 0 K _ 04
1 00 _ 0 4 V_ BAT M TP 3 4 0 3N 3 3 0 0K _1 % _0 4
S D
1229 D02 B A T _ V OL T 28 A C _I N # 27 , 2 8
D
D
P R 24 7 P R2 4 6 P C 2 29 P Q3 7
G
P R2 5 8 1 0 0 K _0 4 P Q9 5 P R 2 51 1M _0 4 G MT N 7 0 0 2Z H S 3
G 1 0 0K _1 % _0 4 6 0. 4 K _ 1 %_ 0 4 0 . 1 u _1 6 V _ Y 5 V _ 04 VA
28 C H G_ R S T
S
MT N 70 0 2Z H S 3
S
P R 25 2
D
2 0 0K _1 % _0 4
G P Q9 8
SY S3 V
PCBLay out no tes MT N 70 0 2 Z H S 3
S
U S B _A C _ I N 3 3
1) All power traces sh ould b e routed on the outer layer s
GNDP, VAD, VSYS, LX, VCHG, VBATT
V D D3
2) Use Kelvin connections f or R3, R4
C
1126 POWER CHANGE
(se perate f orce and measu rement trace s)
S MC _ B A T AC
P D1 6 A
3) R23 and R24 are du mmy r esisto rs, for layout purpo ses only 33 SY S3 V
B A V 9 9 R E CT IF IE R 3 2, 3 3 , 35 S Y S 1 5V
(se rves as single point connection betw een GNDP&GNDA) C
S MD _ B A T AC 32 V A
A 1 3 , 14 , 1 5 , 17 , 1 8 , 20 , 2 2 , 23 , 2 4 , 25 , 2 8, 32 , 3 3, 3 5 V D D 3
P D2 6
4) Fo otprint TO-236 is equivalent to SOT- 23 B A V 9 9 R E CT IF IE R 11 , 3 1 , 32 , 3 3 , 34 , 3 5 , 36 , 3 7 , 38 V I N
C
B A T _ DE T AC
5) Fo otprint SIP/1Pis a single hole axialp ad P D2 7 A
B A V 9 9 R E CT IF IE R
C
6) All resisitors, capac itor s and semiconductor s are SMD AC
B A T _ V OL T
A
7) Po tentio meter s, and test p oints a re axial devices P D1 9
B A V 9 9 R E C TI F I E R
B - 40 AC IN, CHARGER
Schematic Diagrams
CLICK & FINGER BOARD
F
I
N
G
E
R
B
O
A
R
D
C L ED_ A C IN C L E D _ B A T _C H G
CLICK BOARD C L ED_ P W R C L E D _ B A T _F U L L

23
T J_ F P B 1
24
TR E G _O U T T RE F _ O S C
C C1 C C2 C C3 TB D R I V E 1 21 22
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4 *0 . 1 u _1 6 V _ Y 5 V _ 0 4 *0 . 1 u _1 6 V _ Y 5 V _ 0 4 TB D R I V E 2 19 20
17 18 TBEZEL 1 TAVD D
C 5 VS C 5 VS C VD D3
CR 1 C R2 TX I N 15 16 TBEZEL 2
CR 3 C R4 13 14
TX O U T
CG ND CG ND CG ND * 2 20 _ 0 4 * 22 0 _ 0 4 * 22 0 _ 04 *2 2 0 _0 4 11 12 T MI S O
CJ _ T P 1 CJ _ T P 2 CJ _ T P 3 POWER ON TM OS I 9 10 T U S B _ C ON N
1 LED BAT LED TM C L K 7 8 T P D_ RE G
3
1 CT P _ D AT A T3 . 3 V 1 CT P _ CL K 1 CL E D _ P W R C D2 7 C D 26 TM C S 5 6
2 2 2
SG
2 3 4
SG
C T P _ C LK C T P _ D A TA CL E D _ A CIN TN R E S E T T US B_ P N _ R
Y
3 3 C T P B U T TO N _ L 3 C L E D _ B A T _F U L L T3 . 3 V 1 2 T US B_ P P _ R
* K P B -3 0 25 Y S GC *K P B -30 2 5 Y S G C T 3 .3 V
4 4 C T P B U T TO N _ R 4 C L E D _ B A T _C H G
5 5 5
4
TU S B _ P N 10 *C ON 24 A
6 6 6 11/04 11/0 4
TU S B _ P P 1 0 CG ND C GN D
7
8 5 2 01 -0 6 0 51 * 85 2 0 1 -06 0 5 1
8
8 84 8 6 -0 80 1 CG ND CG ND
J_FP1
Pla ce Bott on
CG ND 6-21-91A00-106 6-21-91A00-106 CG ND CG ND C GN D CG ND 23 1
6-21-91A20-106 6-21-91A20-106
6-52-55002-042 6-52-55002-042
6-52-55002-04E 6-52-55002-04E 24 2 2 24
TOP VIEW BOTTON VIEW
W240HU ? ? ?
CSW1~4 W250HU ? ?
2 4
1 3
LIFT
KEY
RIGHT
KEY
LIFT
KEY
RIGHT
KEY
Sheet 40 of 46
1
C SW 1
T J G -53 3 -S -T / R
2 1
C SW 2
T J G-5 3 3 -S -T / R
2 1
CS W 3
*T J G- 53 3 -S -T / R
2 1
CSW 4
*T J G-5 3 3 -S -T / R
2
CLICK & FINGER
3 4 C T P B U T T ON _L 3 4 C T P B U TT O N _ R 3 4 C T PB UT T O N_ L 3 4 C TP B U T T ON _ R
BOARD
5
6
5
6
5
6
5
6
CG ND C GN D C GN D CG ND
6-53-3050B-042 6-53-3050B-042 6-53-3050B-042 6-53-3050B-042

1124 DEL TD1 , TD2
CH 3 CH 1 CH 4 CH 2 CH 5 CH 6
2 9 2 9 2 9 2 9 C9 5 D9 5 H O -1 65 X 9 4_ 5 N P
3 8 3 8 3 8 3 8
4 1 7 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 5 6
M TH 2 37 D 91 M TH 2 37 D 91 M TH 2 37 D 91 M TH 2 37 D 9 1
CG ND C GN D CG ND C GN D CG ND C GN D CG ND C GN D
TBEZEL 1
TU 2 * 3 2m i l _s h o rt
TR 1 1 *4 . 7 K _ 0 4 T X IN T R1 9 4 7 0 _0 4 T XIN_ R T B DR IV E 1 TR 1 4 10 0 _ 1% _ 0 4 1 C GN D T R 1 5 T E S D_ G ND
T 3. 3 V 3
T MI S O TR 1 0 *4 . 7 K _ 0 4 T R1 8 T B DR IV E 2 TR 1 7 10 0 _ 1% _ 0 4 2
T MO S I T GN D 2 1 TBEZEL 2
TR 9 4 . 7 K _ 04 1 M_ 0 4 R C L A M P 0 50 2 B
T X OU T HSX531S+-2 0ppm
3 4 T G ND
T C1 6
CG ND TX1 T E S D _ GN D T 3. 3V
H S X5 3 1 S _ 12 M H Z 3 3 p_ 5 0 V _ N P O _ 04 T U1
T MO S I 5 8
T NR E SE T TR 1 6 4 7 K _ 04 T MI S O 2 S V DD
T 3. 3 V T MC S 1 Q
CG ND
TC 1 5 1 u _6 . 3 V _ X 5 R _ 0 4 TC 1 7 T C1 8 T MC L K 6 CS #
SC K 3 T C1 0
W P#
18 p _ 5 0V _N P O_ 0 4 1 8p _ 5 0 V _N P O _0 4
T RE F _ O S C TC 4 2 7 p_ 5 0 V _ N P O _ 04 0 . 1u _ 1 6 V _Y 5 V _ 04
0224 CG ND CG ND 4 7
VSS HO L D#
CG ND
M 95 1 2 8 W MN 6 TP
T US B _ P N _ R TR 4 2 7 . 4 _1 % _ 0 4 T U S B _P N 1 0 C GN D CG ND
T P D_ RE G TR 5 3 3 0K _0 4 T 3. 3 V 951206
TC 3 1 u _6 . 3 V _ X 5 R _ 0 4 T 3 .3 V T C2
4 7 p_ 5 0 V _ N P O _ 04
TC 8 TC 6 T C1 1
T A V DD CG ND
1 u _ 6 . 3V _X 5 R _ 0 4 1u _ 6 . 3 V _ X5 R _0 4 0 . 1u _ 1 6 V _ Y 5 V _ 0 4
T R E G _O U T TR 13 T U S B _ C ON N TR 2 1 . 5 K _ 1% _ 0 4
TC 13 2 . 2 _1 % _ 0 6 TC 1 2 T C1 4 T US B _ P P _ R TR 3 2 7 . 4 _1 % _ 0 4 T U SB_ PP1 0
CG ND
1 u_ 1 0 V _ 06 1u _ 1 0 V _0 6 0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
T C1
4 7 p_ 5 0 V _ N P O _ 04
CG ND CG ND
CG ND
CLICK & FINGER BOARD B - 41

Schematic Diagrams
AUDIO BOARD/ USB

USB PORT
A _U S B V C C AL 5 A_ USBV C C2
H C B 1 6 0 8K F -12 1 T 25 60 mil
A _U S B V C C
AU 1 AC 1 A C7
A _5 V 5 6 50 mil s +
F L G# V OU T 1 1 0 0u _ 6 . 3V _ B _ A 0 . 1u _ 1 6V _ Y 5V _ 0 4
5 0mi ls 2 7
V I N 1 V OU T 2 A C5 A C6 A J_ U S B 1
A C9 3 8 A R1 0 *1 0 mi l _ 04 1
V I N 2 V OU T 3 0. 1u _ 16 V _ Y 5 V _ 0 4 0 . 1u _ 16 V _ Y 5 V _ 0 4 AL 6 1 A G ND V+
1 0u _ 1 0V _ Y 5V _ 0 8 4 1 A US B _ P N2 4 3 A US B _ P N2 _ R 2
EN # GN D D A TA _ L
R T 97 1 5 B GS / S Y 62 8 8 D F A C AUSB_ PP2 1 2 AUSB_ PP2 _ R 3
A GN D A G ND A G N D A GN D A GN D *A W C M2 0 1 2F 2 S -1 6 1T 0 3 D A TA _ H
G ND 1
G ND 3
4
GN D 2
GN D 4
6-02-09715-920 A R1 1 *1 0 mi l _ 04 G ND
1228 D02
U S 0 4 03 6 B C A 0 8 1
PIN SWAP
GN D 1
GN D 2
GN D 3
GN D 4
6-21-B49C0-104
6-21-B49B0-104
A G ND
TO M/B AUDIO JACK
Sheet 41 of 46 A MI C 1-R
A MI C _ S E N S E
AL 4 F C M1 0 0 5K F -12 1 T 03
5 A J _ MI C 1
4
3 R
AUDIO BOARD/ A MI C 1-L AL 6 F C M1 0 0 5K F -12 1 T 03 2

6
1
L
AC1 0 AC 4 2S J -T 3 51 -S 2 3
USB A_ 5 V A J_ A U D I O1
10 0 p _5 0 V _ N P O_ 0 4 1 0 0p _ 5 0V _ N P O_ 0 4
MIC IN 6-20-B2800-106
A MI C 1 -R 1
A MI C 1 -L 2
3
BLACK
A H E A D P H ON E -R 4 AHP_ S EN SE A _ AUD G
A H E A D P H ON E -L 5
A MI C _ S E N S E 6 A S P K _ HP # 5 A J _ HP 1
A S P K _H P # 7 4
A HP _ S E NS E 8 A H E A D P H O N E -R A R3 6 8_ 0 4 AL 2 F C M 10 0 5K F -12 1 T 03 3 R
A US B _ P N2 9
A US B _ P P 2 10 A H E A D P H O N E -L A R5 6 8_ 0 4 AL 3 F C M 10 0 5K F -12 1 T 03 2
11 6 L
A S P K OU TR + 12 1
A S P K OU TR - 13
AR 9 AR 8 A C3 A C2 2S J -T 3 51 -S 2 3
14
8 7 21 3 -14 0 0 G *1 K _ 1 %_ 0 4 * 1K _ 1 % _0 4 1 00 p _ 50 V _ N P O _ 04 1 00 p _ 50 V _ N P O _0 4
A _A U D G A G N D HEADPHONE
6-20-53A00-114 BLACK 6-20-B2800-106
A _ AUD G
AL 7
AC1 4 0 . 1 u_ 1 6 V _Y 5 V _0 4 F C M1 0 05 K F -1 2 1T 0 3
A S P K O UT R+ 1 2
AC1 5 0 . 1 u_ 1 6 V _Y 5 V _0 4
AC1 3 0 . 1 u_ 1 6 V _Y 5 V _0 4 A L8 A C 11 A J _ S P K R 1 J_SPK1
F C M1 0 05 K F -1 2 1T 0 3 1 0 0 0p _ 50 V _ X 7R _ 04 A S P K O UT R+ _ R
AC1 6 0 . 1 u_ 1 6 V _Y 5 V _0 4 A S P K O UT R- 1 2 A S P K O U T R -_ R 1 2 1
2
85 2 0 4-0 2 00 1
A C8 AC1 7 P C B F o ot p ri n t = 8 5 2 04 -0 2 R
A GN D A _ A UD G 1 80 p _ 50 V _ N P O _0 4 1 80 p _ 50 V _ N P O _ 04
6-20-43150-102
A _ A UD G
6-20-43110-102
A H1 A H3
C 5 9D 59 C5 9 D5 9 AH 2 A H4
2 9 2 9
3 8 3 8
4 1 7 4 1 7
5 6 5 6
M T H 2 76 D 11 1 MT H 2 7 6 D 1 1 1
A GN D A GN D A G N D AG ND
B - 42 AUDIO BOARD/ USB

Schematic Diagrams
Power Switch & LID Board

POWER SW & LED & HOT KEY
S _ 3 . 3V S S _3 . 3 V
POWER
S _ 3 . 3V S S_ 3 .3 V
SWITCH LID SWITCH IC SD2
LED
C
S R2 *B A V 99 R E C T I F I E R
S _ 3. 3 V S S _ 3 . 3V S _ 3 .3 V
SJ _ SW 1 22 0 _ 04
1
2 0mi l S R1 1 0 0 K _1 % _ 04 AC
SJ _ SW 2
2
3
S M _B TN #
1
20 mi l 20 mi l 2 0m il S U1
S W E B _W W W # 1 2 S LI D _ S W #
4 S W E B _E M A I L # 2 S M _B T N # SC6 VC C OU T
5 3
GN D
A
SL ID_ S W # SW EB_ W W W #
A
6 4 S W EB _ E M A IL # *0 . 1 u _1 6 V _ Y 5 V _0 4 SC 2 SC1
7 SAP_ O N S M GN D 5 S L ID_ S W # MH 2 48 -A L F A -E S O
8 6
3
S D3 SD 1 0 . 1 u _1 6 V _ Y 5 V _0 4 /P T3 6 61 G -BB *1 00 p _ 50 V _ N P O _ 04
9 S M GN D 7 SAP_ O N S MG N D
S _ V IN * H T -1 5 0N B -D T S MG N D S M GN D
10 8 H T-1 5 0N B -D T
S M GN D S MG N D
C
* 5 05 0 0-0 1 0 41 -0 0 1L 8 8 48 6 -0 80 1 1228 D02
6-52-56001-023 S MGN D
6-52-56001-028 6-52-56001-023
6-20-94K10-108 6-52-56000-020 6-52-56001-028 SU1, SU2
1 0 pin & 8 pi n co- la y 6-52-56001-022 6-52-56000-020 6-02-00248-LC2
S MG N D S M GN D
6-52-56001-022 6-02-00268-LC1 3
1 2
FOR E5128Q FOR E4120Q/E5120Q

Sheet 42 of 46
Power Switch & LID
6-53-3150B-245 6-53-3150B-245 6-53-3150B-245 S_ VIN 6-53-3150B-245 Board
HOT KEY 6-53-3050B-241
6-53-3050B-240
6-53-3050B-241
6-53-3050B-240
6-53-3050B-241
6-53-3050B-240
6-53-3050B-241
6-53-3050B-240
POWER BUTTON WEB_WWW# WEB_EMAIL# SR 3
AP_KEY#
SPW R _ SW 1 S W W W _S W 1 S MA I L _ S W 1 * 10 0 K _ 1% _ 0 4 S A P _S W 1
T J G-5 3 3-S -T / R T J G-5 3 3-S -T / R 1 1/04 TJ G-5 3 3 -S -T / R T J G-5 3 3 -S -T/ R
1 2 S M_ B T N # 1 2 SW EB_ W W W # 1 2 S W E B _E MA I L # 1 2 S A P _O N
3 4 3 4 3 4 3 4
SC 4 S C3 S C5 SR 5
5
6
5
6
5
6
5
6
PSW1~8 S R4 *4 7K _ 0 4
* 0. 1 u _ 16 V _ Y 5 V _ 0 4 *0 . 1 u_ 1 6V _Y 5V _ 0 4 *0 _ 0 4 *0 . 1u _ 1 6V _ Y 5V _ 0 4
3 1
4 2
S MGN D S M GN D S M GN D S MG N D S MG N D S MG N D S MG N D
S M GN D
S MG N D
FOR E4120Q/E5120Q
POWER BUTTON
SPW R _ SW 2 S M H1 S MH 3 S MH 4
* TJ G- 53 3 -S -T / R S M H2 S MH 5 2 9 2 9 2 9
1 2 S M_ B T N # H 7_ 0 D 2 _ 3 H 7 _0 D 2_ 3 3 8 3 8 3 8
3 4 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6
5
6
PSW1~8 M T H 2 37 D 87 MT H 2 3 7D 87 MT H 2 3 7D 1 18
3 1 S MG N D S M GN D S M GN D S M GN D
4 2
S MGN D
6-53-3150B-245 S M GN D S MGN D
6-53-3050B-240
6-53-3050B-241
FOR E5128Q
Power Switch & LID Board B - 43

Schematic Diagrams
EXTERNAL ODD BOARD

ODD BOARD FOR E5120Q
QJ _OD D 2 QJ_ODD 1
S1 S1
S2 QJ _S ATA_ TXP1 S2
S3 QJ _S ATA_ TXN 1 S3
S4 S4
S5 QJ _S ATA_ R XN 1 S5
S6 QJ _S ATA_ R XP1 S6
S7 S7
QGN D QGND
Sheet 43 of 46 P1
P2
Q_5VS
QJ _OD D_ D ETE CT#
Q_5VS
P1
P2
P3 P3
EXTERNAL ODD P4
P5
P6
QJ _S ATA_ ODD _DA# P4
P5
P6
Board 1-162-1005 62 242001-1
PI N P IN
G N D1~2 =WG ND QGN D QGND GN D 1~3=QGN D
6-21-1 4010-0 13
6-21-1 3A00-0 13 6-21-1 4020-0 13
6-21-1 4030-0 13
Q_5V S
Q C2 QC1
0. 1u_16V_Y5 V_04 *0.1u_16V_Y 5V_04
QGND
QH1 QH 4 QH3 QH2

C 237D91 C 2 37D 91 C 67D 67 C 67D 67
QGN D Q GN D
B - 44 EXTERNAL ODD BOARD

Schematic Diagrams
FINGERPRINT BOARD
F PJ T1
FPU 1 F R EG_OU T 1 2 FR EF _OS C

F BD R I VE1 3 4
B5 FU SB _CON N F BD R I VE2 5 6
U S B_C ON NE C T 7 8 FBE ZEL1 F AVD D
B 11 FB DR I VE 1 F XIN 9 10 FBE ZEL2
B DR I VE 1 F XOU T 11 12
B 10 FB DR I VE 2 13 14 FMI SO
B DR I VE 2 F MO SI 15 16 FU SB _C O N N
A5 FB EZE L1 F MC LK 17 18 FPD _R EG
B7 B EZE L1A F MC S 19 20
NC1 A7
The TES D_GND trace has to be w ide (> 20m il) F N R ESE T 21 22 FU SB _P N
B8 B EZE L1B F3. 3V F 3.3 V 23 24 FU SB _P P
NC2 C5 FB EZE L2
The path be m arked in RED
B9 B EZE L2A
needs to be design to be short and at low impedance. SP N Z-24S 2-VB -017-1-R
NC3 C7 FGN D FGN D
C2 B EZE L2B
NC4 A 10 FR EG _OU T
R EG_ OU T
6-2 1- 41 71 0- 21 2
C 10
AV D D F AVD D
01 03 D 02 ? ? C ha ng e to 6- 21 -4 17 00 -2 12
A3
ESD _G N D 1 F GN D
C3
ESD _G N D 2 F GN D
D VD D 1
A1
F 3.3 V Sheet 44 of 46
D VD D 2
A 11
FINGERPRINT
C9
ESD _G N D 3
A4 FP D_ R EG
F GN D
BOARD
P D _R E G
B2 FMC S
MC S
C6 FMI SO
MIS O
B4 FMOSI
MOS I
B3 FMC L K
MC LK
B1 FU SB _PN
U S B_D N
C1 FU SB _PP
U SB_D P
A2 FN R ES ET FJ1
N R ESE T
1 23 23 1
C4
D GN D 1 F GN D
C 11 FR EF _OS C 2 24 24 2
R EF _O S C BOTTON VIEW TOP VIEW
A8
A GN D F GN D
B6 FXI N
ESD _GN D 4
XTALI N
C8
D GN D 2
FG N D
A6 FXOU T
XTAL OU T
TCS5XF
A9
F G ND
FINGERPRINT BOARD B - 45
Schematic Diagrams
POWER SEQUENCE
W243HVQ/W243HWQ-D01 POWER ON SEQUENCE
DD_ON
858us
5V
1.44ms
3.3V
92.764ms
RS MRST#
(SUSPW RDNACK) 102ms(RSMRST# to SUSPWRDNACK)
SUS_P WR_ACK 102.1ms(RSMRST# to SUSCLK)
S USCLK
102.1ms(RSMRST# to SUS_ACK#)
SUS _ACK#
95.9ms(RSMRST# to SLP_SUS#)
SLP _SUS# 18.5ms(SLP_SUS# to PWRBTN#)
0ms(RSMRST# to ACPRESENT)
ACPR ESENT
80ms(RSMRST# to PWR_BTN#)
206.83ms (RSMRST# to PWR_BTN#)
PWR _BTN# 21.52ms(PWR_BTN# to SLP_A#)
Sheet 45 of 46 103.915ms (RSMRST# to SLP_A# spec:min 5ms)
S LP_A#
POWER
S LP_ME_CS W_DEV#
SEQUENCE 103.915ms(RSMRST# to SLP_LAN#)
SLP _LAN#
102ms(RSMRST# to SLP_S5#)
SL P_S5#
36.9us (SLP_S5# to SUSC# spec:min 30us)
(SLP_S4# )SUSC#
36.9us (SUSC# to SUSB#) (spec:min 30us)
(SLP_S3# )SUSB#
1.645ms(SUSB# to 1.05V_M)
3 .3V_M
2.05ms(SUSB# to APWROK)
(AP WROK)PM_ MPWROK 2.25ms(VCCSPI to APWROK spec:min 1ms)
1.833ms(APWOK to 1.5V);299us(SUSB# to 1.5V)
(VDDQ )1.5V 245us(SUSB# to VCCPLL)
2.05ms(PM_MPWROK to 1.8VS); 3.874ms(1,5V to 1.8VS)
(VCCPLL) 1.8VS
113.54us(1.5V to DDR1.5V_PERGD)
DDR1.5V_ PWRGD
1.51ms(1.8VS to 1.8VS_PWRGD)
1.8VS_ PWRGD
3.9248ms(SUSB# to 1.05VS_VTT_EN)
1.05VS_V TT_EN
1.158ms(1.05VS_VTT_EN to 1.05VS_VTT);2.7ms(SUSB# to 1.05VS_VTT)
(V CCP)1.05 VS_VTT
1.976ms(1.05VS_VTT to 0.85VS);4.6275ms(SUSB# to 0.85VS)
(VCCA)0 .85VS
1.925ms
0.85VS_ PWRGD
3.7ms
VT T_MEM
345.1us
(Vc cCore PC H)1.5VS
603.7us
3.3VS
500us
5VS
1.646ms
1 .05VS
5.536ms
ALL_SYS_ PWRGD
B - 46 POWER SEQUENCE
Schematic Diagrams
POWER SEQUENCE 1
W243HVQ/W243HWQ-D01 POWER ON SEQUENCE
ALL_ SYS_PWRGD
3.4974s
(Vcc AXG)O.85VS
112.83ms
(PWROK) PM_PCH_PWROK
114.11ms
PM_D RAM_PWRGD
114.11ms
VDD PWRGOOD_R
(UN COREPWRGOOD) 115.6ms
3.19ms(spec:min 2ms)
H_ CPUPWRGD
715.65us
VccCore (CPU)VCORE 115.63ms
3.9ms(spec:max 5ms)
IMVP_PW RGD(VR_Ready) Sheet 46 of 46
1.21ms
DE LAY_PWRGD POWER
SYS_PWROK
1.21ms
SEQUENCE 1
1.9ms
PLT_RST#
1.9ms
BUF _CPU_RST#
POWER SEQUENCE 1 B - 47
Schematic Diagrams
B - 48
BIOS Update
Appendix C:Updating the FLASH ROM BIOS 

BIOS Version
To update the FLASH ROM BIOS you must: Make sure you down-
• Download the BIOS update from the web site. load the latest correct
• Unzip the files onto a bootable CD/DVD/USB Flash Drive. version of the BIOS ap-
propriate for the com-
• Reboot your computer from an external CD/DVD/USB Flash Drive. puter model you are
• Use the flash tools to update the flash BIOS using the commands indicated below. working on.
• Restart the computer booting from the HDD and press F2 at startup enter the BIOS.
• Load setup defaults from the BIOS and save the default settings and exit the BIOS to restart the computer. You should only
download BIOS ver-
• After rebooting the computer you may restart the computer again and make anyrequired changes to the default BIOS sions that are
settings.
C:BIOS Update
V1.01.XX or higher as
appropriate for your
Download the BIOS computer model.
1. Go to www.clevo.com.tw and point to E-Services and click E-Channel. Note that BIOS versions
2. Use your user ID and password to access the appropriate download area (BIOS), and download the latest BIOS files are not backward com-
(the BIOS file will be contained in a batch file that may be run directly once unzipped) for your computer model patible and therefore
(see sidebar for important information on BIOS versions). you may not down-
grade your BIOS to an
older version after up-
Unzip the downloaded files to a bootable CD/DVD/ or USB Flash drive grading to a later ver-
1. Insert a bootable CD/DVD/USB flash drive into the CD/DVD drive/USB port of the computer containing the sion (e.g if you upgrade
downloaded files. a BIOS to ver 1.01.05,
you MAY NOT then go
2. Use a tool such as Winzip or Winrar to unzip all the BIOS files and refresh tools to your bootable CD/DVD/USB back and flash the BIOS
flash drive (you may need to create a bootable CD/DVD with the files using a 3rd party software). to ver 1.01.04).
Set the computer to boot from the external drive

1. With the bootable CD/DVD/USB flash drive containing the BIOS files in your CD/DVD drive/USB port, restart the
computer and press F2 (in most cases) to enter the BIOS.
2. Use the arrow keys to highlight the Boot menu.
3. Use the “+” and “-” keys to move boot devices up and down the priority order.
4. Make sure that the CD/DVD drive/USB flash drive is set first in the boot priority of the BIOS.
5. Press F4 to save any changes you have made and exit the BIOS to restart the computer.
C - 1
BIOS Update
Use the flash tools to update the BIOS

1. Make sure you are not loading any memory management programs such as HIMEM by holding the F8 key as you
see the message “Starting MS-DOS”. You will then be prompted to give “Y” or “N” responses to the programs
being loaded by DOS. Choose “N” for any memory management programs.
2. You should now be at the DOS prompt e.g: DISK C:\> (C is the designated drive letter for the CD/DVD drive/USB
flash drive).
3. Type the following command at the DOS prompt:
C:\> Flash.bat
4. The utility will then proceed to flash the BIOS.
5. You should then be prompted to press any key to restart the system or turn the power off, and then on again but
make sure you remove the CD/DVD/USB flash drive from the CD/DVD drive/USB port before the computer
C:BIOS Update
restarts.
Restart the computer (booting from the HDD)

1. With the CD/DVD/USB flash drive removed from the CD/DVD drive/USB port the computer should restart from
the HDD.
2. Press F2 as the computer restarts to enter the BIOS.
3. Use the arrow keys to highlight the Exit menu.
4. Select Load Setup Defaults and select “Yes” to confirm the selection.
5. Press F4 to save any changes you have made and exit the BIOS to restart the computer.
Your computer is now running normally with the updated BIOS

You may now enter the BIOS and make any changes you require to the default settings.
C-2

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W243HVQ Series

About this Manual

The following information is included:

Appendix A, Part Lists

IMPORTANT SAFETY INSTRUCTIONS

This Computer’s Optical Device is a Laser Class 1 Product

Instructions for Care and Operation

Use only approved brands of Unplug the power cord before

The computer has specific power requirements:

User’s Manual on CD/DVD

Power V-Core1 ............................................................................. B-38

Specifications Processor Options Audio

Intel® Core™ i7 Processor High Definition Audio Compliant Interface

“WinKey” keyboard (with embedded numeric keypad)

(Factory Option) One Changeable 12.7mm(h) Optical

Communication Dimensions & Weight

Mini Card Slots

Slot 1 for WLAN Module or Combo WLAN and Bluetooth

Embedded Multi-In-1 Card Reader

6 Cell Smart Lithium-Ion Battery Pack, 48.84WH

Full Range AC/DC Adapter

1 - 4 External Locator - Top View with LCD Panel Open

External Locator - Front & Right Side Views Figure 2

External Locator - Front & Right Side Views 1 - 5

External Locator - Left Side & Rear View

Figure 5 REAR VIEW

1 - 6 External Locator - Left Side & Rear View

External Locator - Bottom View

To prevent your com-

External Locator - Bottom View 1 - 7

Figure 7 Mainboard Overview - Top (Key Parts)

1 - 8 Mainboard Overview - Top (Key Parts)

Mainboard Overview - Bottom (Key Parts) Figure 8

Mainboard Overview - Bottom (Key Parts) 1 - 9

Figure 9 Mainboard Overview - Top (Connectors)

1 - 10 Mainboard Overview - Top (Connectors)

Mainboard Overview - Bottom (Connectors) Figure 10

Mainboard Overview - Bottom (Connectors) 1 - 11

An example of these types of boxes are shown in the sidebar.

To remove the Battery: To remove the 3.75G Module:

1. Remove the battery page 2 - 5

Removing the Battery Figure 1

Removing the Battery 2 - 5

Removing the Hard Disk Drive

a. Locate the HDD bay cover Hard Disk Upgrade Process

New HDD’s are blank. Before you

You have backed up any data

You have all the CD-ROMs and

2 - 6 Removing the Hard Disk Drive

3. Remove the hard disk bay cover 63 (Figure 3b). Figure 3

Removing the Hard Disk Drive 2 - 7

Figure 4 Removing the Optical (CD/DVD) Device

2 - 8 Removing the Optical (CD/DVD) Device

Removing and installing the ODD Bezel Figure 5

Removing and installing the ODD Bezel 2 - 9

Figure 6 Removing the System Memory (RAM)

Be careful not to touch

2 - 10 Removing the System Memory (RAM)

Removing the System Memory (RAM) 2 - 11

Figure 8 Removing and Installing a Processor

2 - 12 Removing and Installing a Processor

c. Turn the release latch to

Removing and Installing a Processor 2 - 13