THE ELECTRONICS & COMPUTER MAGAZINE NOVEMBER 1999

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 WHEN ELECTRONICS WAS YOUNG (9)
In 1895, the German physicist Wilhelm electronics’.
Conrad Röntgen (1845–1923) accidental- Following on Thomson’s work on cathode rays, the German physi-
ly discovered a kind of radiation whose na- cist Karl Ferdinand Braun (1850–1918) modified a cathode ray tube
ture he could not determine, and which he so that its electron beam was deflected by a changing voltage. The re-
therefore called X-rays. He experimented sulting cathode-ray oscilloscope has been of inestimable value in elec-
with burst ionization and used for this pur- tronics and other scientific work and is also the basic component of a
pose a screen covered with a thin film of television receiver.
fluorescent material [BaPt(CN)4]. When As early as 1875, James Maxwell realized the potential possibili-
X-rays were passed through a human onto ties of electromagnetic waves and he predicted wave propagation with
a photographic plate, the bones were seen a finite velocity, which he showed to be the velocity of light. His theo-
as shadowed areas against the lighter flesh, ries in the famous A Treatise on Electricity and Magnetism intrigued
while metal objects, such as a ring, gave many researchers such as Heinrich Rudolf Hertz (1857–94), who in
opaque shadows. Röntgen later suggested 1877 succeeded in producing electromagnetic waves experimentally, thus
Wilhelm Conrad
that X-rays were an electromagnetic radi- Röntgen (1845...1923) confirming Maxwell’s predictions.
ation akin to light but of shorter wave- Guglielmo Marconi (1874–1937), an Italian physicist working in
length, which was proved by von Laue in 1912. Röntgen was awarded England, was interested in Hertz’s experiments and began experiment-
the first Nobel Prize in Physics in 1901 for his discovery of X-rays. Their ing himself in 1895 with a spark induction coil and Branley coherer,
study added much to physics, gave a new technique for use in medicine, and succeeded in sending telegraph messages over a short distance. He
and, after the work of the British physicists Sir William Henry Bragg patented his invention in 1896 and in 1897 formed the Wireless Tele-
(1862–1942) and his son Sir William Lawrence Bragg (1890–1971) graph Company (later the Marconi
in 1915, led to X-ray crystallography. Sadly, Röntgen died in poverty Company) to exploit the patents and to
during the period of high inflation in Germany. set up the manufacture of spark trans-
Edison found in 1884 that in an incandescent lamps in which a mitters and receivers.
metal plate was placed opposite the filament a current flowed only if Marconi continued to improve his
the plate was positive with respect to the filament. Five years later, Sir equipment and succeeded in linking
John Ambrose Fleming (1849–1945) showed that this current consist- England with France by radio in 1899.
ed of negative charges. In 1987, Sir Joseph John Thomson (1856–1940), On on 12 December 1901 he transmit-
while investigating cathode rays (the electrical discharge emitted from ted across the Atlantic from Poldhu in
an electrode under high fields in a gas at low pressure), concluded that Cornwall to a kite-born antenna set up
the rays were made up of particles, which were named shortly after- at St John’s in New Foundland and so
wards ‘electrons’ by the Irish physicist George Johnstone Stoney became a household word overnight at
(1826–1911). Thomson also found that the charge-to-mass ratio (e/m) the age of 27. In 1909, Marconi shared
Guglielmo Marconi
of these particles did not vary from one cathode material to another. the Nobel Prize for physics with Karl (1874...1927)
The discovery of the electron was really the beginning of the ‘age of Ferdinand Braun. (995089)

12 Elektor Electronics 11/99

MICROPROCESSORS
stepper motor control
part 3: construction and software
Having built the PCB and secured it to the front
panel, you should be ready to take the stepper
motor control into use. This is best done in
step-by-step fashion (pun intended), and we
will guide you from adjusting the step-down
voltage regulator right up to operating the PC
terminal program. In the unfortunate case of
the project not working as expected, help is
available in the section ‘Faultfinding’.
Th e step -d ow n voltage con verter is
taken in to u se before fittin g th e in te-
grated circuits and before securing the
SMC board to 80C166 board. When an
in p u t su p p ly voltage of abou t 10 V is
applied to the converter, it should sup-
ply an output voltage of between 4.6 V
an d 5.4 V. Preset P5 is u sed to accu -
rately set a level of 5.0-5.1 V. Th e con -
verter ’s output voltage should remain
stable when the input voltage is raised
to 40 V. Two green LEDs, D11 and D12,
ligh t to in d icate th e p resen ce of th e
supply voltage.
O n ce th e step -d ow n con verter is
know to function properly, the PCB is
plugged on to 80C166 board fitted with
th e SMC firm w are. Circu its IC13 an d
IC14 (74xx123) h ave to be p resen t for
in d icatin g th e clock sign als an d , later,
for the stand-by mode. Additionally, a
PC may be con n ected u p to th e serial
in terface. Th is PC sh ou ld ru n a com -
munication program set to ASCII trans-
fer, 9600 baud, 8 databits, 1 stopbit, and
no parity (9600,8,n,1).
After you switch on the supply volt-
age, the 80C166 board should produce
its version an d in itialisation texts on
Design by K.-.H. Domnick
14
th e PC d isp lay. Wh en th e fin al OK
ap p ears, th e step p er m otor con trol
software is ready for use.
N ext, you h ave to verify th at th e
SMC con trol softw are resp on d s to
p u sh bu tton action , an d su p p lies all
clock an d d irection sign als. O n alter-
n ately p ressin g th e Left an d Right
pushbuttons, the motor direction LEDs
sh ou ld resp on d accord in gly by ligh t-
ing or going out. The Tick (clock pulse)
LED sh ou ld ligh t for th e d u ration of
the motor clock pulse.
O n ce th is w orks as it sh ou ld , th e
su p p ly voltage m ay be rem oved an d
th e GALs an d p ow er d river ICs
in stalled in th eir sockets. N ext, th e
stepper motors are connected up, one
at a tim e, an d each to its ow n p ow er
driver. Install the jumpers for the step-
ping order, current and standby mode,
an d th en p erform th e an alogu e cu r-
rent adjustment with the potentiome-
ters. H avin g d on e th is th e step p er
motors should turn in both d irections
when the relevant control pushbuttons
are p ressed . If th e m otors resp on d
p rop erly to p u sh bu tton con trol it
should also be possible to control them
using the PC.
If step p er m otors are u sed w ith
active zero-search, the motor direction
has to be checked and modified if nec-
essary. To change the direction, simply
swap two wires of a phase winding.
N ext, you m ay en able an d test th e
sen sor in p u ts by fittin g th e op tocou -
plers. Whenever a voltage is applied to
a sen sor in p u t (IN 5-IN 10, IC17 an d
IC18), th e PC d isp lay sh ou ld p rod u ce
the associated report s1 through s6. The
sam e effect m ay also be ach ieved by
sh ort-circu itin g th e op tocou p ler ou t-
puts.
The state of ‘Zero’ (i.e., motor-home)
inputs 1 through 4 (IC16) may be read
in th e sam e w ay as th e sen sor in p u ts.
H ow ever, before th is can be d on e, a
zero (h om e) search com m an d sh ou ld
be issued to the relevant motor. The PC
display will then indicate the associated
reports n1 through n4.
FAU LT F I N D I N G
In all cases, check your soldering work,
as th is is th e com m on cau se of m al-
fu n ction s. Th e same goes basically for
th e com p on en ts m ou n ted on th e
board. Further error sources include:
Motor does not operate at all
➘ Step-down voltage regulator does
not supply 5 V.
➘ 80C166 controller board not con-
nected.
➘ No SMC program in EPRO Ms, or
H and L EPROM interchanged.
➘ Clock signal not available; lost
between SMC board and 80C166
board (boxheader pin bent). Power
driver ICs (IC1-IC8) missing.
➘ GAL (IC9-IC11) missing, not pro-
grammed or incorrectly pro-
grammed.
High-pitch sound heard, jerky move-
ment of motor spindle, or no move-
ment at all.
➘ Clock frequency or lower fre-
quency too high.
➘ Too low current selected on
jumpers JP9-JP20.
➘ With analogue current control,
potentiometers P1-P4 set to wrong
value, or jumpers JP9-JP20 not set
Elektor Electronics 11/99
 186.5

1 168.0
71.0
64.0
31.5

23.5
28.5
33.5
40.0
46.0

51.5
64.5
66.0

69.5
87.5
92.5

112.5
114.0

53.5
68.8
84.0
=3
99.3
114.5
129.8
=9 145.0
160.3
175.5
196.0 990044 - 16

SMC
Stepper Motor Control

Direction Direction
Tick Tick
NULL SEARCH 0, M
TICK FREQUENCY 1, M, 00050-05000 Motor 3 Motor 2
UNDER FREQUENCY 2, M, 00050-05000
OVER FREQUENCY 3, M, 00050-20000 On

Reset
BOOST 4, M, 00005-01000
ACTUAL POSITION 5, M, 00000-50000 Direction
Direction
END POSITION 6, M, 00000-50000 Tick Tick
DURATION MODE 7, M
Motor 4 Motor 1
POSITION MODE 8, M
HALT (ALL MOTORS) 9
Control
On
9

H 1 G H 2 G H 3 G H 4 G
0 1 2 3 4 5 6 7 8

990044 - F

Figure 1. Front panel drilling

for full current. details and suggested lettering. Unable to com-
➘ Too low supply voltage for stepper Motor fails to municate w ith
motor(s). find spindle PC:
home position: ➘ Wrong COM port selected on PC.
Motor runs briefly, then stops: ➘ Wrong direction on stepper motor. ➘ Serial wires RxD and TxD inter-
➘ Missing motor direction signal; ➘ Wrong polarity on home switch or changed.
missing or broken link with sensor (normally-closed instead of ➘ Jumpers for CTS and RTS missing,
80C166 board (boxheader pin normally-open contact). or wrong configuration.
bent). ➘ Missing optocoupler IC16. ➘ Missing SIO component or associ-

Elektor Electronics 11/99 15

 Table 1. Programming Mode
Toggle/ 0 Cntrl/ 9 0...9 H G 0 9
...

Function Pushbutton Motor Value = # sequence Serial

Tick Frequency 1 M1-4 00.050 - 05.000 T 50 - 5.000
Under Frequency 2 M1-4 00.050 - 05.000 U 50 - 5.000
Over Frequency 3 M1-4 00.050 - 20.000 O 50 - 20.000
Boost 4 M1-4 00.005 - 01.000 B 5 - 1.000
Actual Position 5 M1-4 00.000 - 50.000 A -2.147.483,648 - + 2.147.483.648
End Position 6 M1-4 00.000 - 50.000 E -2.147.483.648 - + 2.147.483.648
Duration Mode 7 M1-4 - D1-4
Position-Mode 8 M1-4 - P1-4
Halt (all motors) 9 - - H9
Null search 0 M1-4 - N1–4

Table 1. The pushbuttons on the SMC front panel have

ated tantalum capacitors. different functions in Programming Mode. Values to be
entered into the SMC should include leading zeroes to
Nothing happens… ensure uniform length.
Fu rth er p roblem s m ay be cau sed by
construction errors on the SMC board
or a m issin g, in correctly sp ecified or
even defective part. Check your work Wh en th e p u sh bu tton 1…4 Left is pushbutton down while also pressing
thoroughly, or ask a ‘second opinion’. p ressed , th e m otor w ill tu rn in th e th e Cn trl (Con trol) p u sh bu tton . Th e
op p osite d irection by th e p reviou s yellow LED will start to flash.
number of steps (equals command ‘X To d isable or term in ate Program -
O P E R AT I O N — Repeat Inverse). When the pushbut- m in g Mod e, rep eat th e above
The ten pushbuttons on the SMC front ton 1…4 Right is p ressed , th e m otor sequence. The yellow LED will go out.
p an el allow d irect an d simp le con trol turns in the previously selected direc- Program m in g Mod e is au tom ati-
of the stepper motors, as well as para- tion by th e p reviou s n u m ber of step s cally en d ed after a com p lete or a
m eter en try. Com p lex con trol (equals command Repeat). The effect of w ron g en try. With n u m ber en try, th e
sequ en ces are n ot p ossible u sin g th e N orm al O p eration w ith th e Toggle Toggle p u sh bu tton rep resen ts th e
p u sh bu tton s — in evitably a p erson al switch pressed or not be interchanged value 0, and the Cntrl pushbutton the
computer is then called for. with the aid of DIP switch number 2. valu e 9. In Program m in g Mod e, th e
pushbuttons have different functions.
Normal operation Wh en en terin g valu es in to th e
SMC makes a distinction between Nor- Ha lt Go SMC, lead in g zeroes sh ou ld be
m al O p eration an d Program m in g 1...4 1...4 included to make sure the values con-
Cntrl H Cntrl G
Mode. sist of the same number of digits.
990044 - 3 - 13
S O F T WA R E —
Fine Drive
I N T E R N AL LY
1...4 All clock and direction signals are gen-
H G Figure 4. Normal oper-
ation with Cntrl push- erated in software on the 80C166 con-
990044 - 3 - 11
button pressed. troller board. Each clock is recorded as
a 32-bit number and may be called up
or modified as Actual (current) Position.
Figure 2. Normal oper- Pushbutton 1…4 Left allows the step- After a successful ‘home’ search of the
ation without Toggle p er m otor to be h alted (equ als com - m otor sp in d le, th e relevan t valu e is
pushbutton pressed. m an d Halt). Pu sh bu tton 1…4 Right m ad e 0. Wh en th e com m an d Go is
starts the motor (equals command Go). issued the controller computes a ramp
N ote h ow ever th at a m otor w ill on ly (grad ien t) table from th e p aram eters
Wh en p u sh bu tton s 1…4 Left or 1…4 start if the values representing the cur- Under Frequency (low er frequ en cy),
Right are pressed, the motor will turn rent and end positions are different. Over Frequency (upper frequency) and
in the selected direction at the selected Boost (acceleration rate).
clock frequ en cy, u n til th e relevan t Using these values, clock pulses are
pushbutton is released. Progra mming mode produced until the high-speed phase is
Toggle/ 0 Cntrl/ 9 reached. If the Duration mode (contin-
u ou s op eration ) is en abled , all su bse-
Repea t inverse Repea t qu en t clock p u lses take on th e valu e
990044 - 3 - 14
1...4 1...4 assign ed to Over Frequency. Wh en th e
Toggle H Toggle G
Halt com m an d is issu ed , th e valu es
990044 - 3 - 12 Figure 5. Enable/dis- th at m ake u p th e d eceleration ram p
able Programming (i.e., a look-u p table) are p rocessed
Mode. until the motor stops.
Figure 3. Normal oper- If th e sp in d le p osition in g m od e is
ation with Toggle enabled, the processor also looks at the
pushbutton pressed. Programming Mode table en tries rep resen tin g th e d iffer-
To ch an ge from Normal O p eration to en ce betw een Actual Position an d End
Program m in g Mod e, keep th e Toggle Position, as well as the number of steps

16 Elektor Electronics 11/99

 Table 2. Commands and reports
? Help
A * Actual Position
B * Boost
C Copy Data
D Duration mode
E * End position
E Report
F Fine drive
G Go
H Halt
I Info
J With zeropoint search
K Without zeropoint search
L Left rotate
M Motor actual *
N Null search
n Report
O * Over Frequency
P Position Mode
q Report
R Right rotate
S Status
s Report
T * Tick frequency
U * Under Frequency
V Version.
v Report
W Repeat
X Repeat inverse
Z * Int. position
z Report
Possible values:
for the high-speed phase. If more steps
are required for the two ramps than for
the d ifference between Actual Position
an d End Position, th e m otor w ill be
unable to reach the high-speed phase.
Becau se all requ ired clocks an d
step s h ave been com p u ted after th e
start, all parameters are open to modi-
fications (with the exception of the con-
tinuous or positioning modes).
If you want to stop a running motor
before th e sp in d le reach es th e en d
position, you have to use the Halt com-
m an d . It is p ossible to issu e a N ull
Search command immediately after Go.
On reach in g th e en d p osition th e
m otor w ill th en au tom atically tu rn to
the home position.
An oth er in terestin g com m an d is
Int. Position (in term ed iate p osition ).
Wh en its associated valu e equ als th at
of Actual Position, th e p rogram tran s-
mits a report (z1-z4) via the serial inter-
face. This parameter may be modified
at an y time an d as often as you w an t.
Reports are also transmitted on reach-
ing the end (target) position (e1-e4) or
zero (null) position (n1-n4), on leaving
th e zero (n u ll) p osition (v1-v4) or on
detecting an active sensor input (s1-s8).
Th e com m an d N ull Search (tu rn to
spindle home position) only causes the
m otor to actu ally tu rn to th e h om e
position if a ‘home’ sensor is available
Elektor Electronics 11/99
- Request help
±2.147.483.648 Set/request current position
5 – 1.000 Set/request motor acceleration (clocks per ms)
- Copy data from memory into EEPROM
0/1 – 4/9 Switch on continuous mode (Position mode off)
±2.147.483.648 Set/request end position
1–4 Report “End Position reached”
0/1 – 4/9 Turn slowly using clock frequency in selected direction
0/1 – 4/9 Start motor / turn to end position
0/1 – 4/9 Halt motor
- Request info (status with semicolon preceding)
0/1 – 4/9 Turn to home sensor and then clear current position to 0
0/1 – 4/9 No home sensor, clear current position to 0 immediately
0/1 – 4/9 Turn left using clock frequency (slow)
1-4 Set/request motor no. for subsequent commands
0/1-4/9 Turn to spindle home (zeropoint) using clock frequency
1-4 Report “Zeropoint reached”
50 - 20.000 Hz Set/request upper frequency (fast)
0/1-4/9 Position mode on (Duration mode off)
0-9 Acknowledge (q0) and error reports (q1-q9)
0/1-4/9 Turn right using clock frequency (slow)
-/0/1-4/9 Request status: M1, T500, U1000, O10000, B500, . . . .
1-8 Report “Sensor reached”
50 - 5.000 Hz Set/request clock frequency (slow)
50 - 5.000 Hz Set/request lower frequency (Start/Stop)
- Request program version number
1-4 Report “Leaving zeropoint”
0/1-4/9 Repeat previous no. of steps in previous direction
0/1-4/9 Repeat previous no. of steps in opposite direction
± 2.147.483.648 Set/request intermediate position
1-4 Report “Int. position reached”
0 = current motor (set beforehand using M1 - M4)
1–4 = indicated motor
9 = all motors
and the parameter With zeropoint search Table 3. Error reports
has been enabled. With No home sensor,
on ly th e cu rren t p osition is reset to Q0 OK
zero, an d a rep ort (n1-n4) is tran sm it- Q1 Wrong command
ted. Q2 Wrong motor number
Q3 Wrong value
P C C O M M U N I C AT I O N
Th e SMC an d th e PC com m u n icate Q6 RAM checksum error
th rou gh as serial lin k em p loyin g th e Q7 EEPROM checksum error
following parameters: Q8 EEPROM write error
9600 bits/secon d , 8 d atabits, 1 stop bit,
no parity (9600,8,n,1). Using a terminal
emulation program or general-purpose
com m u n ication softw are for th e PC
(Telix, ProComm, HyperTerminal) you m1, t 500 / M1, T500 /
sh ou ld be able to con trol an d in terro- M1: T500: M2: T800 / Mot or 1,
gate th e Step p er Motor Con trol in Ti ckf r equency 500
plain ASCII. Complex sequences to be
p erform ed by th e step p er m otor w ill After a semicolon (;) comment may be
require a program, however, that sup- inserted up to the end of the line:
plies the relevant commands and eval-
u ates th e variou s rep orts retu rn ed by M1, T500 ; Cl oc k f r equenc y
the SMC. 500 Hz f or Mot or 2 <r et >
SMC w an ts to receive all com -
m an d s eith er as a ch aracter or as a Statu s rep orts are tran sm itted in
com p lete w ord w ith ou t n u m bers or u p p ercase ch aracters, w h ile p osition
sp ecial ch aracters. Th e system is n ot reports appear in lowercase. Informa-
case-sensitive: tion and comment is always preceded
by a semicolon (;). Each line ends with
M1 / m2 / M 3 / m 4 / Mot or 2 a Carriage Retu rn an d a Lin e Feed
(CR-LF sequence).
A lin e m ay con tain m ore th an on e All commands and reports are listed
command provided a comma or colon in Table 2.
(:) is used as a delimiter: (990044-2)
17
MICROPROCESSORS

controller area
network (CAN)
intelligent, decentralized data
communications in practice:
Part 3

The first two parts of

this article dealt with
the history, standard-
ization, basic setup,
and data transmission
protocol of the Con-
troller Area Network.
In this third part, the
attention is shifted to
more practical
aspects. It deals with
a network interface
bus design that can
be connected to any
current microcon-
troller system.

INTRODUCTION • adding the remaining fields;

Cu rren t Con troller Area N etw ork
(CAN ) in terfaces con sist basically of
three chips as shown in the block dia-
gram in Figure 9. All th e m icro-con -
troller is required to do is to write the
data bytes (0–8) to be transmitted into
the CAN protocol IC, fill the identifier
field an d th e DLC field , an d set th e
RTR bit accordingly. The remainder of
the process:
By B vom Berg & P Groppe • computing the CRC check sum;
• accessing the bus;
• transmitting the data;
• detecting and remedying errors
is effected by the CAN controller IC.
The data are applied to the bus via
th e CAN tran sceiver IC th at p rovid es
direct coupling to the bus.
The microcontroller then receives a
m essage con firm in g th e su ccessfu l
tran sm ittin g of th e d ata or an error
m essage, follow in g w h ich requ isite

Elektor Electronics 11/99

20
action can be taken.
More or less th e sam e h ap p en s
w h en d ata.are bein g received . Th e
CAN con troller receives th e CAN
fram es from th e bu s via th e CAN
transceiver IC, rechecks the check sum,
removes all superfluous fields from the
fram e an d p asses eith er th e received
data or an error message to the micro-
controller.
Th e read er w ill alread y h ave
noticed that only a modest amount of
material, hardware as well as software,
is requ ired for a CAN bu s in terface.
Moreover, m icrocon trollers th at con -
tain a CAN controller on the same chip
are alread y com m ercially available.
Su ch a ch ip m akes a tw o-stage CAN
interface possible.
Some more information is given in
the following section before the design
of a p ractical in terface can be d is-
cussed.
ACCE P TAN CE
F I LT E R I N G
We h ave seen in Part 2 th at a Con -
troller Area N etw ork op eratin g w ith
standard frame format (CAN 20A) can
process up to 2048 different identifiers.
It is, of course, not necessary that each
and every station linked to the bus can
receive all d ata/rem ote fram es. For
in stan ce, it m ay w ell be th at for, say,
Station K only frames with the identi-
fiers 129, 1345, and 1999, are of interest
an d th e oth er 2045 are of n o con se-
qu en ce w h atever. To avoid Station K
receiving and processing all identifiers
and passing them on to the microcon-
troller (which has to recheck whether
each an d every id en tifier is to be
accepted or rejected – a time consum-
ing activity), some kind of selection fil-
tering of identifiers to ensure that only
th ose of in terest are p assed to th e
microcontroller is highly desirable.
The selection of identifiers is called
acceptance filtering. It allows the CAN
con troller ch ip to be p rogram m ed so
th at on ly fram es w ith certain id en ti-
fiers are passed to the microcontroller.
All oth er fram es are received an d
checked (incl. error correction), but not
passed on. In this way, the microcon-
troller is freed of m an y su p erflu ou s
com p arison s an d can th erefore m ore
sp eed ily p rocess th e requ ired
data/remote frames.
There are two ICs that can be used
for acceptance filtering.
BasicCAN
This IC has a simple filter that is, say,
eigh t bits w id e, w h ich allow s coarse
pre-selection only. Normally, this con-
sists of passing groups of identifiers, in,
say, th e ran ge 700–707. Selection of a
single identifier is not possible. This IC
therefore requires the microcontroller
to carry ou t a fu rth er selection to
arrive at the wanted identifier.
Elektor Electronics 11/99
9 CAN protocol IC,
CAN protocol,
CAN IC
databus
TxD CAN H
micro- user CAN
controller data transceiver
control bus IC
RxD CAN L
CAN
frames
990066 - 14
Figure 9. Block diagram
of a three-stage Con-
troller Area Network
Rem ote fram es design. (with different identi-
in ten d ed for th e rele- fiers) are n ot p assed
van t station are also on sin ce th e con -
passed by the filter and applied to the troller programme is fixed.
microcontroller. It is only then that the Therefore, if many frames with dif-
microcontroller can generate the rele- feren t id en tifiers are to be received it
van t resp on se d ata an d p ass th ese to makes better sense to use a BasicCAN
the CAN controller. chip. It must be borne in mind , how-
ever, th at in th is case th e m icrocon -
FullCAN troller needs to carry out a substantial
Th e Fu llCAN ch ip allow s th e exact p art of th e selection p rocess an d th is
programming and selecting of a single in tu rn m ean s th at a m ore p ow erfu l
identifier. In other words, it can be set microcontroller is needed.
to accep t a sin gle fram e or a n u m ber A ben eficial p rop erty of th e Fu ll-
of sin gle fram es, for in stan ce, on ly CAN ch ip is th at th e m icrocon troller
those with identifier 798. can program the response to a remote
Th e d raw back of th e IC is, h ow - fram e on to th e CAN con troller IC.
ever, th at a large n u m ber of fram es Wh en th is IC receives a p erm issible
Table 4: Brief parameters of interface
CAN controller IC Type SJA1000 (Philips Semiconductors)
Microcontroller interface can be arranged for Intel or compatible and
Motorola or compatible microcontrollers
Mode of operation 1: pin-, hardware-, and software-compatible with
PCA82C200
CAN 20A and 20B passive
Standard frame format
Data transfer rates up to 1 Mbps
Acceptance filter BasicCAN
Mode of operation 2: Extended and standard frame format
Data transfer rates up to 1 Mbps
CAN 20B capability
Extended acceptance filter with BasicCAN
properties
Transceiver IC Compatible with ISO/DIS11898, high-speed CAN
Data transfer rates up to 1 Mbps
Internal protection against noise specific to motor
vehicles
Internal protection against short-circuits and ther-
mal overload
Non-powered nodes (stations) do not affect the
bus
Allows the design of Controller Area Networks with
up to 110 nodes
21
 5V JP11

10 1
Ub
5V 5V Ub Ub
VIN
IC5 C1
C6
V+
7
5
* JP3
K1
0 0 100n R1 1
NMV
* C7 1 5V
8 Ub

390Ω
0505SA 6
0 2 7 2
C8 AN EN
2 0 R2 7
3
IC2 6
390Ω CA OUT C3 3
JP12 3x 100n
1 6N137 4 8
NC NC
100n
4
22 18 12 0
5 9
0
D7 2 5
AD7 1 2 3 11 3 R8
D6 1 MODE TP
5V AD6

120Ω
7 5 6
D5 28 CLKOUT 5V VREF CANL
AD5 C2
D4 27 13 1 IC4
C9 AD4 IC3 TX0 TXD
D3 26 19 4
JP2
AD3 RX0 R4 100n RXD PCA
10µ 16V D2 25 Ub 82C250
AD2 8

390Ω
8 7
D1 24 14 RS CANH K2
AD1 TX1 7 2
K3 D0 23 20 EN AN
AD0 RX1 IC1 R3 2 1
D7 1 2 6 3 0
SJA1000 OUT CA 390Ω 6
D6 3 4 WR 6 C4
WR 9 5V 4 6N137 1 2
D5 5 6 E/RD 5 XTAL1 NC NC
E/RD 7
D4 7 8 CS 4 X1 22p
CS R5 5 3
D3 9 10 ALE/AS 3 R7 JP4
ALE/AS

R
8
C5

47k
D2 11 12 INT 16
INT 10 4
D1 13 14 RST 17 XTAL2
RST
D0 15 16 1 2 3
16MHz
22p
R6
* zie tekst 9
5
8 21 15
0
* see text 0

* siehe Text 0

* voir texte 990066 - 2 - 11

Figure 10. Circuit diagram of the

CAN bus interface.

remote frame for the relevant station, error test, and respond with
it can sen d th e resp on se d ata fram e and ACK bit or an error frame.
w ith ou t in terven tion by th e m icro- Although the communication is not Controllers with 20B capability
controller. d istu rbed , th e received exten d ed - Th ese con trollers p rocess, store, an d
With the inexorable progress of the frame data are not stored or passed on, p ass on , stan d ard -form at as w ell as
tech n ology, th e d ifferen ces betw een sin ce th e ch ip s are in ten d ed for p ro- extended-format frames.
the BasicCAN and FullCAN chips are cessin g fram es in stan d ard form at When a decision has to be made on
becoming less defined. Also, FullCAN on ly. N everth eless, th ese con trollers th e p u rch ase of a CAN con troller or
chips are becoming more powerful, so are perfectly all right for use in hybrid m icrocon troller w ith on -ch ip CAN
that they can select larger numbers of systems. controller, there is such a wide choice
in d ivid u al id en tifiers an d can store
m ore d ata registers. State-of-th e-art
CAN con troller ch ip s can sw itch
betw een th e tw o mod es of op eration
by means of software.

C O M P AT I B I L I T Y
B E T WE E N 2 0 A AN D 2 0 B
As we have seen during the discussion
of the frame formats (Part 2), there is
a Stand ard Format with 11-bit id enti-
fiers an d an Exten d ed Form at w ith
29-bit id en tifiers. Great care m u st be
taken in ch oosin g a CAN con troller
w h en both formats are u sed in a bu s
system (which is perfectly possible and
permissible).

Controllers with 20A capability

Th ese con troller ch ip s can p rocess
standard frames only and generate an
error m essage w h en an exten d ed
fram e m essage is received . Sin ce th is
cou ld brin g th e w h ole system to a
standstill, these controllers can be used
only in systems that operate with stan-
dard frames.

Controllers with 20A capability and 20B

passive properties
Th ese ch ip s accep t exten d ed fram es
w ith 29-bit id en tifiers, carry ou t an

22 Elektor Electronics 11/99

that it really pays to visit the Internet
Home pages of producers like Hitachi, 11 IC5 K1

JP11

JP12
In tel, Motorola, N SC, Ph ilip s, SGS, JP2

H1
K3 * * IC4
Siemens, and Temic, and Texas Instru- R8
R7
ments to name but a few. C3
JP4
R1

ROTKELE )C(
1-660099
C1 R3
CAN B U S I N TE RFACE C9
After th e len gth y d iscu ssion s on th e- IC2 IC1
ory and basic principles, the practical 1 0
design of a CAN bus interface can now JP3 R2 R4
R5 R6
be described in relatively few words. C2
The circuit diagram of the interface C8 C7
is sh ow n in Figure 9 an d a su itable
printed-circuit board in Figure 10. Brief
IC3 K2
p arameters of th e in terface are given
in Table 4. 990066-1
Th e CAN con troller, IC 3, is a Typ e H2

C4
SJA1000, w h ose in tern al block TP
C5 X1 C6
schematic is shown in Figure 11. This
chip is the successor of the PCA82C200
with which, in operating mode 1, it is
p in -, h ard w are-, an d softw are-com -
patible.
Th e in terface w ith th e m icrocon - Figure 11. Printed-cir-
troller can be arran ged for u se w ith cuit board for the CAN
eith er a Motorola or an In tel ch ip (or bus interface.
compatible types).
The CAN transceiver, IC4, is a Type
PCA82C250.
The microcontroller is linked to the
CAN bus interface by a length of flat-
cable, which should be not longer than Parts list
10 cm (4 in ), term in ated in to 16-p in
header K3. The pin connections of this Resistors:
connector are given in Table 5. R1–R4 = 390 Ω
R5, R6 = see text
Via th is lin k th e m icrocon troller R7 = 47 kΩ
exchanges operating data, control data, R8 = 120 Ω
an d statu s d ata, w ith th e CAN con -
troller. These data are processed by the Capacitors:
controller both in the send and receive C1–C3, C6–C8 = 0.1 µF, ceramic
d irections. The microcontroller there- C4, C5 = 22 pF, ceramic
fore ‘sees’ th e CAN con troller as an C9 = 10 µF, 16 V, radial
exten sion to its m em ory to w h ich it
Integrated circuits:
w rites op eratin g d ata to be tran sm it- IC1, IC2 = 6N137
ted, or from which it extracts received IC3 = SJA1000
operating data. IC4 = PCA82C250
Th e clock frequ en cy, w h ich is IC5 = NMV505SA (Newport/Farnell)
divided in several stages, can be mea-
sured at test pin TP, for example, when Miscellaneous:
it is to be ascertained whether the con- X1 = 16 MHz quartz crystal
K1, K2 = 9-way D connector, right-
troller can be accessed an d p ro- angled, for board mounting
grammed safely. K3 = 16-way header, right-angled, for
The serial output signal at pin 13 of board mounting, with interlock
the controller is applied to pin 1 of the JP2, JP4 = 2-way, 2.54 mm pin strip
(C) ELEKTOR
990066-1

tran sceiver via op toisolator IC 2. Th e and pin jumper (Maplin)

tran sceiver gen erates th e stan d ard
CAN bus signals which are available at
its p in s 6 an d 7. Th ese sign als are
im p ressed u p on u n sh ield ed tw isted -
pair (UTP) copper wires via connectors
K1 and K2.
Th e sign al received from th e bu s
arrives at pin 4 of the transceiver from
where it is applied to pin 19 of the con-
troller via op toisolator IC 1. Th e con -
troller con verts th e received bits an d
processes them in accordance with the
relevan t CAN p rotocol. Th e received
sign al is fin ally fed to th e m icrocon -
troller where it is analysed.
O ptoisolators IC1 and IC2, and 5 V
JP3, JP11, JP12 = 3-way, 2.54 mm pin
strip and pin jumper (Maplin)
PCB Order no 990066-1 (see Read-
ers’ Services section toward the
end of this issue)
DC/DC inverter IC5, effectively isolate It is, of course, possible to build the
the microcontroller and bus sections of interface without the isolating stages,
th e n od e (station ). Th e arran ge-men t so that R1–R4, C1–C2, IC1–IC2, IC5, and
en su res th at an y fau lty or u n certain JP 1–JP 2 can be om itted . Th e su p p ly
sign als on th e UTP w ires, alth ou gh line terminals as well as the send and
applied to the transceiver, cannot dam- receive pins on IC3 and IC4 must then
age the microcontroller section and fol- be interlinked as appropriate. It must
lowing system. be borne in mind, of course, that faulty

Elektor Electronics 11/99 23

 UTP w ires. Sin ce m ore term in atin g
Table 5: Pin connections of header K3 resistors (at other nodes) will be in par-
Pin Designation Function allel w ith th ese tw o, th ey lead to a
red u ction in total term in atin g resis-
1 D7 tance, which results in a higher output
3 D6 cu rren t from th e tran sceiver an d th is
in tu rn can lead to th erm al overload
5 D5
and damage or destruction of the chip.
7 D4
JP3
9 D3
This jumper must be set according to
11 D2 w h ich m icrocon troller in terface is
13 D1 used. The position shown in Figure 10
(pin 11 of IC3 at + 5 V) and marked ‘0’
15 D0 on th e PCB allow s In tel p rocessors/
2 + 5V positive supply line con trollers or com p atible ch ip s to be
used.
4 WR\ Write\ signal
Wh en th e ju m p er is p laced in th e
6 RD\ Read\ signal oth er p osition (p in 11 of IC 3 at 0 V),
Motorola p rocessors/con trollers or
8 CS\ Chip-Select\ signal
compatible chips may be used.
10 ALE Address latch enable signal
12 INT\ Interrupt\ signal JP4
Th is ju m p er, or rath er resistor R7,
14 RST\ Reset\ signal d eterm in es th e slop e of th e ed ges of
16 GND Earth connection the pulses at the CAN bus.
In th e case of h igh d ata tran sfer
rates (u p to 1 Mbp s), steep -slop ed
ed ges are essen tial, bu t th ese lead to
sign als on th e UTP lin es are th en the 0 and + U b terminals. th e risk of a large n oise sp ectru m
ap p lied u n imp ed ed to th e microcon - An altern ative in th e latter case is bein g gen erated by th e CAN p u lses.
troller section. th e p rovision of su p p ly voltage via This noise can only be negated by the
Ju m p ers JP 11, JP 12, an d JP 2–JP 4 tw o lin es in p arallel w ith th e UTP u se of sh ield ed tw isted p air (STP)
must be arranged as follows. w ires an d con n ectin g th ese to p in s 6 w ires. Th e ju m p er m u st be u sed ,
and 9 of K2 and K1 respectively. thereby shorting out resistor R7.
JP11, JP12 If th e ju mp ers are left op en , th ere With low data transfer rates (up to
These jumpers (marked * on the PCB) is electrical isolation, and the bus sec- 125 Kbps) the edges of the pulses need
d etermin e h ow th e su p p ly voltage is tion is then powered via pins 6 and 9 not be steep. This results in a narrow
applied to the interface and the micro- of K2 and K1 respectively. n oise sp ectru m bein g cau sed by th e
controller system. With these jumpers CAN pulses, so that UTP (unshielded
set as shown in Figure 10, electrical iso- JP2 tw isted p air) w ires can be u sed .
lation is provided and the supply volt- When JP 2 is shorted , bus terminating Jumper JP 4 must not be placed.
age to the bus section (IC1, IC2, IC4) is resistor R8 is connected between pins
via IC5. 6 an d 7 of th e tran sceiver. It m u st be
In th e oth er p osition of th e born e in min d th at on ly tw o bu s ter-
jumpers, there is no electrical isolation, m in ators m u st be u sed , on e at th e
and all stages are supplied directly via begin n in g an d on e at th e en d of th e

12 This concludes the description of the

hardware for the CAN bus interface.
A forthcoming article will deal with
the connection of the CAN bus to a
microcontroller system and its
application in an experimental
CAN bus system.

[990066]

Figure 12. Block dia-

gram of the internal
arrangement of the
Type SJA1000 Con-
troller Area Network IC.

24 Elektor Electronics 11/99

TEST & MEASUREMENT

enhanced
TV line monitor
select and check video line contents

The tester presented

here can do more
than just generate an
oscilloscope trigger
pulse for a selected
video raster line. It
also marks the
selected line in the
CVBS signal and dis-
plays it on the TV
screen as an oscillo-
gram.

Design by W. Foede

In ord er to be able to d isp lay a given

Fe a t u r e s :
✓ exact selection of one horizontal line
(1 through 625)
✓ oscilloscope trigger output
✓ selected line marked in the passed-
through video signal
✓ oscillogram of the selected line merged
with the television picture; amplitude and
position adjustable
✓ adjustable blend of original picture and
oscillogram
✓ line content displayed either aligned to
picture or offset with a horizontal sync
pulse
✓ interlaced and non-interlaced operating
modes
lin e of a vid eo im age on an oscillo-
scop e, you n eed a sp ecial trigger gen -
erator th at u ses th e vertical syn ch ro-
nization pulse to detect the start of the
fram e or field (h alf fram e) an d th en
counts horizontal sync pulses until the
d esired lin e is reach ed , w h ereu p on it
gen erates a trigger p u lse for th e oscil-
loscope.
A circu it wh ich d oes th is (an d on ly
this) was published in the October 1994
issu e of Elektor Electronics (‘TV Lin e
Mon itor ’). In th at circu it, a m icrocon -
troller looks after all th e cou n tin g an d
con trol tasks — everyth in g excep t for
sync separation. However, at the cost of
on ly a little more h ard w are, th is basic

Elektor Electronics 11/99

26
 CVB S + VID

1 AMPL
VID
AMP
CVBS
OUT

INV AVL
SHV VID
AVV
&
CVBS LINE
LINE TRIG
1 D Q 16MHz OUT
AMPL
VID SHV RS
AMP AS C Q
C16 ADC
& R
VID
XSHE
AR C
(DAC)
XSHW
D0-D7 XP0-XP7
1 D Q

CVBS IN
RS ACTR 8 BIT
D Q C Q
DFF XSV R +
CVBS LINE LOGIC COMP
C Q
R
10 BIT
XSVE
A0-A9 MEM
A7
&
A9 RD/WR Q D
XSVW
AMPL DC-OFFSET LINED DFF
Q C
R
C16
1 D Q
DFF SYNC MUX
C Q
R

XODD
& HSYNC

XSHE
XSHE LINE

C Q D 1 C

UNITS
H001 XODDW DFF XU0-XU3 U0-U3
PCTR V624 UTH
Q C
+ R CTR
LOGIC +
EPM7064SLC44-12 LOGIC 11 BIT

TENS
MUX AR XT0-XT3 T0-T3
8 BIT XSVE COMP
DOWN AVV

HUNDREDS
AVL
PR312
NIL XH0-XH2 H0-H2
XP0-XP7 11 BIT

990007 - 12

Figure 1. Block diagram of

function can be enhanced with a num-
ber of in terestin g extras (see th e ‘Fea-
tu res’ box). Sin ce th is tester evalu ates
n ot on ly th e syn c p u lses bu t also th e
content of the selected line, a different
approach must be taken.
The video signal follows two differ-
ent paths from the input. The first path
lead s to a vid eo am p lifier bu ilt u sin g
d iscrete com p on en ts, in w h ich th e
syn c p u lses are sep arated from th e
video signal so that they can be used to
trigger th e lin e cou n ter. Th e secon d
p ath is d igital. First th e CVBS (com -
p osite vid eo) sign al is sam p led by an
A/D con verter, an d th e resu ltin g d ata
are stored in a fast RAM. A D/A con -
verter restores the selected line to ana-
logu e form an d m erges it w ith th e
am p lified CVBS sign al in an ou tp u t
buffer amplifier. The enhanced TV line
m on itor also offers a ran ge of op era-
tion al settin gs, an d it p rod u ces th e
external trigger signal that is essential
for m akin g m easu rem en ts w ith an
oscilloscope.
AN AL O G U E AN D
P R O GRAM M AB LE LO GI C
The block diagram of the TV line mon-
itor, shown in Figure 1, is fairly elabo-
rate. The shad ed elements are located
in a p rogram m able EPLD IC (Altera
typ e EPM7064). A sm aller version of
this IC has already been used in several
Elektor Electronics the enhanced TV line moni- be 125 Ω in stead of
p rojects. H ere th is tor. The shaded elements th e u su al 75 Ω, to
IC h as th ree p rin ci- are contained in a ready- provide satisfactory
p al fu n ction s: it programmed EPLD IC. op eration w ith
cou n ts syn c p u lses, in p u t voltages
it controls the input lower than 1 Vpp . If
A/D converter and RAM, and finally it on the other hand the input voltage is
looks after the conversion of the stored too high, overload ing of the amplifier
line back into analogue form. Let’s look can be prevented by adjusting the level
at th e variou s elem en ts of th e block control P4. Sync pulses are clamped by
diagram in more detail. D1 and C2.
Th e block labelled ‘AS’ con tain s a
CVBS LINE low-p ass filter (R9/C8) th at blocks H F
The first item that the input video signal com p on en ts, su ch as th e bu rst an d
en cou n ters is labelled ‘CVBS LIN E’. chrominance signals.
This is actually just a few passive com- T4 gen erates p ositive vertical an d
p on en ts, as can be seen from th e oth - horizontal sync pulses with an ampli-
erw ise n ot p articu larly in form ative tude of 5 Vpp (signal SHV).
schematic diagram shown in Figure 2.
The amplitud e of the input signal can
be ad ju sted w ith P1, w h ile P3 ad d s a C O U N T I N G I N WI N D O WS
d.c. component to the signal. Diode D2 Th e SHV sign al con tain s all th e in for-
an d cap acitor C7 clam p th e syn c m ation th at th e p rogram m ed logic
impulses to a constant d.c. level. After n eed s in ord er to gen erate th e n eces-
this processing, the signal arrives at the sary clock an d reset sign als (XSH E,
A/D converter IC, a National Semicon- XSHV and XODD) for the three coun-
d u ctor ADC1175CIJM. Th is h as an ters p rogram m ed in to th e EPM7064.
input range of + 0.6 V to + 2.6 V. All of th ese sign als, by th e w ay, p ass
through edge detectors which convert
VID AMP and AS them into ‘needle’ pulses.
The two-stage video amplifier (T2 and
T3) is also con n ected to th e in p u t. It Pixel counter
raises the amplitude of the video signal Th e bin ary p ixel cou n ter, labelled
by at m ost a factor of arou n d 2. Th e ‘ACTR’, ad d resses th e RAM for both
input impedance has been modified to read in g an d w ritin g. It is 10 bits w id e

Elektor Electronics 11/99 27

2
Tr1
5V R16
K4 D8 D9 5V

47Ω
IC5
7805

C17 C15 C16 C18 R21

1k
10µ 16V 100n 10µ 16V 100n D11 D10 C22 C27
14 15 18 13 11 C10 C11
D7
6V / 3VA
A A A D D 4x 1N4001 100µ
25V
100n 100n 10µ
16V
3 D0
D0
VIN 19 4 D1
VIN D1
5 D2
IC4 D2
C16 12 6 D3
CLK D3
ADC1175 D4 7 D4
22 CIJM 8 D5 5V
VRBS D5
23 9 D6
VRB D6
10 D7 C5
17 D7
VRT S2 S1
16 1 LINE
VRTS OE 100n HSYNC NON
INTERLACED
C14 C12 A A D D 3 15 23 35
5V
D0 39 11
20 21 2 24
100n 100n D1 38 13
D2 37 R18 R19
C9

10k

10k
D3 36
D4 34
IC3
4x 10k 1 R24 4x 10k 1 R23 100n
D5 33
5V 28
D6 32
D7 31 EPM7064 29 A5 10 26
LC44-12 A0 CS2
S3 2 3 4 5 2 3 4 5 28 A4 9
8 U3 2 A1
27 A6 8
4 U2 44 A2 11 D5
26 A9 7 D0
A3
UNITS

2 U1 1 IC1 12 D3
25 A7 6 D1
1 U0 43 A4 13 D1
21 A0 5 D2
C A5 15 D0
19 A1 4 D3
A6 RAM 16 D2
S4 18 A2 3 D4
A7 12ns
8 T4 8 17 D4
20 A3 25 D5
4 T3 6 A8 6164 18 D6
24 A8 24 D6
A9
TENS

2 T2 5 19 D7
21 D7
1 T1 4 14 HVSYNC A10
23
C 16 VID A11
2 20
17 SHV A12 CS1
S5
8 H2 12 WE OE
27 14 22
HUNDREDS

4 H1 9 40 LINE
LINE
2 H0 7 41
1
2 3 4 5
C D5 D6 D4 10 22 30 42
C16

R20 K3
3x 4x 10k 1 R22 LINE
1k
C16
1N4148
VIN
R15 5V 5V
HVSYNC
VID

SHV
75Ω

C6 R5
R14 R17
8 D3
1k

D2
390Ω
75Ω

2µ2 5V
16V 16MHZ
1N4148 1 IC2 5
OE
R13 P3 C16 R6 1N4148
T1
C7 CW SG531P
100k

75Ω

P1
250Ω 100n 4
CW 5k
K1
BC550

5V
R8 R10
4k7

1k

K2 T3 5V

T4
T2 BC560 C4 R9
C1
1N4148 560Ω
D1 R3 R4 330n
100Ω

100Ω

2µ2 BC560
16V BC550
CW R7 R2 R1 P2 R11 R12 SHV
C2 CW C8
4k7

100k

270Ω

220k

4k7

P4
250Ω 500Ω
100n 220p

990007 - 11

Figure 2. Schematic diagram of the

enhanced TV line monitor. th e in p u t vid eo sign al. In ad d ition ,
PCTR p rovid es th e tw o sign als AVV
an d AVL. AVV m arks th e region in
w h ich th e merged -in lin e oscillogram
and is clocked at 16 MHz. It is reset by w ith in th e XSH W w in d ow p rod u ces can be d isp layed (in lin es 60 th rou gh
the leading edge of the line sync pulse th e XSH E sign al, w h ich resets th e 275 of th e first field an d 372 th rou gh
XSHE. For reliable synchronisation, the ACTR and also clocks the line counter. 587 of th e secon d field ). AVL refers to
ACTR logic gen erates an 0.5-µs tim e line identification (first field = lines 24
window (XSHW) for the leading edge Line counter th rou gh 311, secon d field = lin es 336
of lin e syn c p u lse. Th is (as w ell as th e The line counter, labelled ‘PCTR’, is an th rou gh 623). Th ese region s m u st be
oth er tim e w in d ow s) acts as effective 8-bit binary down counter which pro- defined to avoid upsetting the vertical
interference suppressor. Only the lead- vides the programmed-logic D/A con- syn ch ron isation of th e television set.
ing edge of the SHV signal that occurs verter with the current line number of The PCTR counter is reset by the rising

28 Elektor Electronics 11/99

3

P1

K2

K1
R1
C1

R6
P4
C6
R3

T1
R2 C4
D1
P3

P2
C2 R4

T2
R5

D2

D3
R7

C5
R8
C7

R10 R11

T3

C8
T4
R9
R13 R12

S1
990007-1
IC1

S2
C9
IC4

R14
R17
IC3

R15 C18 R18

C15 R19
C12 R20
R16
D4
C16
C14

R24

S3 R23 S4 R22 S5 D5
D7

C17

D6

K3

C11
IC2
C27

(C) ELEKTOR (C) ELEKTOR

990007-1 990007-1
K4
R21

H1
TR1

C22 IC5
D8
D11
D10
C10

D9

Figure 3. Everything on one board: no internal cabling is needed.

COMPONENTS LIST Capacitors: IC4 = ADC1175-50 CIJM SMD

C1,C6 = 2µF2 16V radial IC5 = 7805
Resistors: C2,C5,C7,C9-C12,C14,C15,
R1 = 270Ω C18 = 100nF, 5mm raster Miscellaneous:
R2,R13 = 100kΩ C4 = 330nF, 5mm raster K1,K2,K3 = cinch socket, PCB mount,
R3,R4 = 100Ω C8 = 220pF angled (Monacor/Monarch T-709)
R5,R10,R20,R21 = 1kΩ C16,C17,C27 = 10µF 16V radial S1,S2 = switch, 1 make contact
R6,R14,R15 = 75Ω C22 = 100µF 25V radial TR1 = mains transformer, 6V 3VA
R7,R8,R12 = 4kΩ7 S3,S4,S5 = hex thumbwheel switch
R9 = 560Ω Semiconductors: (RS-components o/n 199-251,
R11 = 220kΩ D1-D6 = 1N4148 sequence C-1-2-4-8)
R16 = 47Ω D7 = LED, low current K4 = 2-way PCB terminal block, raster
R17 = 390Ω D8-D11 = 1N4001 7.5mm
R18,R19 = 10kΩ T1,T2 = BC550 Enclosure 125x70x40mm
R22...R24 = 4-way 10kΩ SIL array T3,T4 = BC560 (e.g. Donau SD20)
P1 = 250Ω linear potentiometer IC1 = 6164 PCB, order code 990007-1
P2 = 500Ω linear potentiometer IC2 = SG531P 16MHz
P3 = 5kΩ linear potentiometer IC3 = EPM7064LC44-12
P4 = 250Ω preset H (order code 986523-1)

ed ge of th e vertical syn c p u lse XSVE reset by the leading edge of the frame
th at falls w ith in th e tim in g w in d ow syn c p u lse. Dep en d in g on th e settin g
XSVW. of the mode selection switch ‘NIL’, this
is eith er th e XSVE p u lse (n on -in ter-
Line selector laced mode, lines 1 through 312) or the
Th e block labelled ‘UTH CTR’ is a XO DD pulse (interlaced mode, lines 1
th ree-d igit BCD cou n ter th at is also through 625).
clocked by XSH E. Th e on es an d ten s The UTHCTR outputs drive a com-
d igits have four bits each, while three p arator w h ose secon d set of in p u ts is
bits are su fficien t for th e h u n d red s con n ected to th ree th u m bw h eel
d igit, sin ce th e h igh est p ossible lin e switches. When the current line num-
n u m ber is on ly 625. Th is cou n ter is ber m atch es th e n u m ber set in th e
switches, the comparator generates the
LINE signal. This signal passes through
a flip-flop that is clocked by ACTR (and
the 16-MHz clock) such that the line to
be m on itored is d isp layed startin g
eith er at th e begin n in g of th e visible
horizontal line (aligned to the TV pic-
ture) or offset by a visible synchronisa-
tion pulse, d epend ing on the position
of the HSYNC switch. The signal from
the flip-flop, with appropriately modi-
fied timing, is labelled ‘LINED’. It pro-

Elektor Electronics 11/99 29


vid es th e tim in g w in d ow for th e A/D
converter and video line memory.
High-speed D/A converter and video
line memory
The LINED signal ensures that exactly
one raster line, with a duration of 64 µs,
is read, converted and stored in RAM.
Sin ce th e con verter is clocked at
16 MHz, 1024 samples are stored (64 µs
x 16 MHz). In addition, LINED is made
available at the ‘LINE TRIG OUT’ out-
p u t socket to serve as a trigger sign al
for an oscilloscope.
D/A converter
The D/A converter (‘DAC’) is a ‘home-
brew ’ design. The standard polarity of
th e vid eo sign al is + CVBS, w h ich
means that the sync pulses have a low
level and white video has a high level.
The sync pulses are thus stored in the
RAM as sm all bin ary valu es, w h ile
white regions are stored as large binary
valu es. To obtain a correctly orien ted
d isp lay of th e con ten t of th e stored
line, the down counter ACTR must be
u sed (h igh lin e n u m bers at th e top of
the screen and low line numbers at the
bottom). The DAC is started in line 40
w ith a cou n ter state of 255. Th e 8-bit
com p arator (DAC) com p ares th e
cou n ter state for each raster lin e w ith
the values provid ed by the line mem-
ory (MEM), which in turn is driven by
ACTR in a p eriod ic man n er. It assign s
th e state of th e PCTR cou n ter to each
d igitized voltage valu e. For exam p le,
w h en th e cou n ter state is 155 (corre-
sp on d in g to raster lin e 140), every
stored sample with a value of 155 gen-
erates a pixel in the VID signal. If AVV
and AVL are both active, this forces the
video signal to the white level. The line
content diagram thus becomes part of
the output signal.
Output signals
Th e ou tp u t sign al CVBS + VID O UT
con sists of th e com bin ation of th e
rep rod u ced lin e con ten t d iagram, th e
30
Figure 4. The A/D converter
IC is mounted on the bot-
tom (solder side) of the
board.
CVBS sign al (amp lified an d bu ffered ,
w ith ad ju stable am p litu d e) an d th e
combined sync signal SHV. The blend
of th e CVBS an d lin e con ten t sign als
can be continuously adjusted with P3,
startin g w ith a colou r CVBS p ictu re
w ith a fain t oscillogram , p assin g
through monochrome CVBS and end-
in g w ith a d isp lay of th e oscillogram
alon e w ith ou t th e CVBS im age. Th e
selected lin e is sh ow n as a w h ite lin e
w ith in th e AVL region for id en tifica-
tion.
AL L O N O N E B O ARD
After this somewhat roundabout jour-
n ey th rou gh th e logic of th e TV lin e
mon itor, w e can tu rn ou r atten tion to
its construction. As can readily be seen
from Figure 3, all com p on en ts are
mou n ted on on e sin gle-sid ed p rin ted
circu it board , in clu d in g th e p ow er
tran sform er, jacks an d p resets. N ote
h owever th at if you wan t to u se BNC
sockets in stead of th e sp ecified Cin ch
sockets, you w ill h ave to m ake a few
additional short cables.
In stallin g th e com p on en ts on th e
board is som ew h at tricky, d u e in p art
to th e 22 w ire ju mp ers. Sin ce some of
th ese ru n very close to oth er com p o-
n en ts, you sh ou ld u se fin e in su lated
w ire for all of th em . O n ce all th e
ju m p ers h ave been sold ered in p lace,
m ou n t th e SMD IC before an y of th e
other components. After this, continue
in the usual manner with the low-pro-
file com p on en ts su ch as resistors,
d iod es an d cap acitors, an d fin ish off
with the transformer, switches S1 and
S2, the jacks, presets and so on. Mount
the switches elevated above the board,
so th at th eir levers w ill later p rotru d e
con ven ien tly from th e en closu re. By
the way, C15 should be mounted either
flat in sid e th e socket or on th e back
(sold er sid e) of th e board . Th e ICs as
well as the thumbwheel switches may
be m ou n ted in sockets. Wh en sold er-
ing, take care to avoid making any sol-
d er brid ges between the tracks or sol-
der pads, which are very close together
is some places.
Before putting the TV line monitor
in to u se, you sh ou ld carefu lly in sp ect
th e fin ish ed circu it board . O n ce you
have verified that all polarized compo-
n en ts (in clu d in g th e th u m bw h eel
sw itch es!) h ave been correctly
installed , attach the mains cable to K4
an d secu re it w ith a su itable strain
relief. Then attach the circuit board to
th e low er p art of th e en closu re (on e
screw only) and press the upper part of
th e en closu re in to p lace (after first
m akin g th e n ecessary h oles an d cu t-
aw ays!). Th e tw o sw itch es S1 an d S2
can be left free or attached only loosely.
P RACTI CAL AS P E CTS
Let’s review th e in p u ts, ou tp u ts an d
controls of the TV line monitor. It has a
vid eo sign al in p u t (K2, CVBS IN ),
which can accept a signal from a video
record er, PC vid eo card , satellite
receiver or oth er vid eo sou rce. Ad ju st
P4 so that the strongest available video
sign al d oes n ot overd rive th e first
vid eo amplifier stage (T2). P1 controls
the amplitude of the line content oscil-
logram , w h ile P2 con trols its location
on the screen.
The output signal leaves the TV line
m on itor via K2. O n th e con n ected
m on itor (TV), you w ill see th e in p u t
sign al (p ictu re), a w h ite lin e (th e
selected line) and an oscillogram of the
selected line. The relative strengths of
these signal can be adjusted with P3.
If you want to observe the selected
lin e on an oscilloscop e, con n ect th e
CVBS signal to the Y input and the line
monitor K3 output to the external trig-
ger input of the oscilloscope.
Sin ce th e p ictu re con ten ts of ad ja-
cent lines in the first and second fields
are often nearly identical, the number
of sam p led p ixels can be d ou bled by
displaying both lines at once. To do so,
set switch S1 to non-interlaced (2 x 312
lines). This operating mode also allows
non-interlaced television signals to be
p rocessed , su ch as th at p rod u ced by
the Elektor Video Test Chart Generator
(Sep tember an d O ctober 1996 issu es).
If you w ish to observe on ly on e lin e
per frame (1 x 625 lines), S1 must be set
to interlaced mode.
Th e fu n ction of sw itch S2 can best
be d emon strated by tryin g it ou t w ith
th e TV lin e m on itor in op eration : th e
oscillogram in the CVBS output signal
eith er in clu d es a syn c p u lse, or it
d oesn ’t.
(99007-1)
Elektor Electronics 11/99
GENERAL INTEREST

gradient* meter
based on the recently introduced
Type ADXL105 from Analog Devices
An integrated
accelerometer circuit
such as the ADXL105
from Analog Devices,
although intended pri-
marily for measuring
acceleration and
deceleration, may
readily be used for
gauging gradients* . If
the circuit is to be
used out of doors, its
temperature compen-
sation must be
adapted accordingly.

Design by P. Porcelijn

INTRODUCTION suitable temperature compensation. fou n d th at tem p eratu re variation s

Th e Typ e ADXL05 accelerom eter IC
from An alog Devices w as in trod u ced
in a relevan t Ap p lication N ote in th e
Ap ril 1997 issu e of Elektor Electronics.
Ju st over a year later, th e d evice w as
u sed as th e basis of an ‘electron ic
accelerometer ’ (June 1998 issue of EE).
From the properties of the circuit it is
clear th at th e d evice m ay read ily be
u sed for m easu rin g grad ien ts. Wh en
th is is to be d on e w ith some accu racy
in a motor vehicle or on a bicycle, it is,
of course, necessary to maintain a con-
stant speed.
There are two further matters to be
resolved before grad ien ts can be
gau ged w ith an accelerom eter: th e
choice of a suitable display, and adding
Th e qu estion of a d isp lay is rela-
tively easily satisfied . This is achieved
by obtaining a d irect ind ication of the
percentage gradient from the relation-
sh ip betw een th e acceleration of free
fall, g, the gradient, p, in per cent, and
ad ju stin g th e am p lification of th e cir-
cuit accordingly. From the discussion in
th e box ‘Prin cip le of m easu rem en t’ it
will be seen that, within narrow toler-
ances, the output voltage of the sensor
is virtually directly proportional to the
gradient percentage.
Solvin g th e m atter of tem p eratu re
com p en sation is rath er m ore tricky.
Com p en sation is n ecessary becau se
when the device was tested for use as
a grad ien t gau ge on a bicycle it w as
caused such inaccurate measurements
as to render them unusable.
Fortu n ately, An alog Devices
recen tly u p grad ed th e ADXL05 to th e
Type ADXL105, which is provided with
an in tern al tem p eratu re sen sor. Th e
addition of a few simple electronic cir-
cuits to the sensor gives the upgrad ed
device very efficient temperature com-
pensation.
CIRCUIT DESCRIPTION
Th e circu it d iagram is sh ow n in Fig-
ure 1. It w ill be seen at a glan ce th at,
like th e earlier accelerom eter, th e gra-
d ien t m eter is battery op erated . Also,
th e d isp lay is again form ed by a Typ e
DPM951 d igital voltm eter (DVM)

* Also, especially in USA and Canada, grade: a part of a road or railway that slopes upwards or downwards, an incline. It also indicates the measure of such
an incline (normally as a percentage).

Elektor Electronics 11/99

32
 Figure 1. Other than
the accelerometer IC
and the digital volt-
1 K1 5V
P3

100k
5V

meter (DVM) module, 1 IC3 = TLC272

C4 13 14
the electronics is lim- 2
R2
R6
VDD VDD
ited to two operational

220k
3 1µ 1
270k TOUT
4
amplifiers and some R1 UCAOUT
12
5 6 11
passive components. 6
270k
7
R4 VIN
IC2
IC3b 68k 10
7 5 VNIN DVM
R3 ADXL105
8 8
P1 68k AOUT
9 200k 6
ST
10 3 9
VMID
linked to the circuit via box header K1. 11 1 R5
IC3a 5V COM COM
It will also be seen that, whereas the 2

390k
12
4 7
accelerom eter com p rises ju st th e 13
14
ADXL05 ch ip an d th e DVM m od u le,
P2
the gradient meter has two additional
10k
op eration al amp lifiers (op amp s), on e
of which is needed for the temperature
compensation circuit. 5V LP2950CZ5.0
Accord in g to th e m an u factu rer ’s 1 1
INHI D1
2 2 1N4001
sp ecification , th e temp eratu re d rift of 3 3
INLO DVM IC1
th e ADXL105 is abou t 1 mV °C –1, th at 4 4
VDD DMP951
VCC
is, roughly 60 mV over the entire tem- 5 5
COMMON S1
p eratu re ran ge. Sin ce th e error in th e 6 6
BL+
7 7
grad ien t m eter is am p lified ×4, th e 8 8
REFLO

overall d rift w orks ou t at 4 m V °C –1, 9 9

REFHI 8 C3 C2 C1 Bt1
BP IC3
which, as the polarity of the tempera- 10 10
BP 4 100n 10µ 100µ
16V 16V
ture coefficient is not known, will lead 11 11
N.C.
9V
12 12
to unusable results. 13 13
DP3

The integral temperature sensor of 14 14

DP2
DP1 LK4 LK5 LK6
the ADXL105 provides a temperature-
d ep en d en t voltage, U t , at ou tp u t Tou t 990067-11
(pin 1) of

U t = 2.5+ 8×10 –3 ×(t –25)

[V]

w ith a toleran ce of ± 0.1 V (t is th e Figure 2. Printed-circuit board for the gradient meter
ambient temperature). which is, however, not available ready made.
Th e ou tp u t of th e sen sor is m od i-
fied to a usable value with the aid of a
compensating circuit based on op amp
BT1
S1

-
IC3b. This circuit enables the tempera-
2
HO1

HO
D1

tu re coefficien t to be set betw een C1

P2

Parts list
–8 mV °C–1 and + 8 mV °C–1 with P1. In IC1
P3

C2

p rin cip le, a p assive circu it cou ld h ave Resistors:

C4

R5 R6
been used, but that would have made R1, R2 = 270 kΩ R3
the calibration fairly tedious. R3, R4 = 68 kΩ
R4

Unfortunately, the integral potential R5 = 390 kΩ

IC3

R6 = 220 kΩ
divider in the ADXL105 has an output IC2
P1 = 200 kΩ, 10-turn preset
impedance of 10 kΩ. This is rather high P2 = 10 kΩ, 10-turn preset R2
C3
1

for the present application, particularly P3 = 100 kΩ, 10-turn preset R1 990067-1
since the output voltage is also used for
K1
P1

the DVM module. This small problem Capacitors:

HO3

HO2

ROTKELE )C(
DVM

is remedied by a buffer, op amp IC3a . C1 = 100 µF, 16 V, radial 1-760099

-
+

C2 = 10 µF, 16 V, radial
O F F S E T AN D GAI N C3 = 0.1 µF, ceramic
C4 = 1 µF, metallized polyester
The passive components in the circuit
diagram not yet dealt with form part of Semiconductors:
the offset compensation and requisite D1 = 1N4001
amplification circuits.
The offset error of the ADXL is not Integrated circuits:
in sign ifican t: it m ay be as h igh as IC1 = LP2950CZ5.0
± 625 m V. Fortu n ately, com p en satin g IC2 = ADXL105JQC
IC3 = TLC272CP
for this is easily achieved by injecting a
variable direct current into VIN (pin 11) Miscellaneous:
via resistor R5 an d p reset P 2. At u n ity BT1 = 9 V battery with connecting clips
gain , th e ran ge of th is p reset is
1

S1 = slide switch, 1 make contact

± 870 mV. K1 = 14-way box header
Th e in p u t ran ge of th e sp ecified DVM module as appropriate
Enclosure as appropriate (C) ELEKTOR
DVM module is 200 mV. Assuming that 990067-1
th e m axim u m grad ien t (grad e) to be

Elektor Electronics 11/99 33

 p r i n ci p l e o f m e a s u r e m e n t age regulator IC1. Since the accuracy of
the voltmeter is wholly dependent on
th e su p p ly voltage, th e regu lator
Owing to the earth’s gravity, any freely suspended object is subject to an sh ou ld be a typ e w ith very low tem -
acceleration of free fall, g, which, near the earth’s surface, is equivalent to
p eratu re coefficien t: better th an
9.80665 m s–2. If the object is on a gradient of p%, its acceleration, g s is
150 ppm °C–1. The type specified is also
g s = g sinα, [1] a low-drop model which makes it ide-
ally suited for use in battery operated
where α is the gradient, and equipment.
The gradient meter draws a current
sinα= p/100/√ { 1+ (p/100) 2 } [ 2] of abou t 6 m A. Diod e D 1 gu ard s
against incorrect polarity of the supply
If p/100<< 1, this equation simplifies to lines.

sinα≈ p/100. [3] CAL I B R AT I O N

Offset & temperature compensation
When the latter equation is used, a small error occurs : 1. Place th e grad ien t m eter in a level
position (check with a spirit level) in
0.5% when p= 10%
a constant ambient temperature of
2% when p= 20%
20 °C and leave it to settle down for
Since the error remains within acceptable limits, equation [3] is perfectly all about half an hour.
right for practical use. 2. Set P 3 to th e cen tre of its travel.
Combining equations [1] and [3] gives the following relationship between Con n ect a d igital voltmeter (d irect
acceleration and gradient: m illivoltage ran ge) betw een
‘–DVM’ and pin 7 of IC3. Adjust P 1
p= (g s /g)×100% until the meter reading is exactly 0.
3. Turn P 2 until the DVM module also
This equation shows that if a small error is acceptable, the output voltage of reads exactly 0.
the accelerometer IC is directly proportional to the gradient. 4. Heat the gradient meter with, say, a
hair dryer, whereupon the reading
p/100
sin α = on the DVM will probably change.
√ 1 + (p/100) 2 Readjust P 1 until the module again
gs reads exactly 0.
gs = g • sin α 5. Let th e grad ien t m eter cool off for
P/100 about half an hour and, if necessary,
g read ju st P 2 u n til th e DVM mod u le
reads exactly 0.
α 6. Repeat steps 4 and 5 until a satisfac-
α tory tem p eratu re com p en sation is
1 obtained.
990067-12

traversed is 20% (a steep er in clin e is
seldom encountered on normal roads),
th ese tw o qu an tities can be equ ated
very satisfactorily.
Sin ce th e sen sitivity of th e
accelerom eter IC is 0.25 V g–1, its ou t-
p u t voltage in volts is a qu arter of th e
m axim u m grad ien t in p er cen t. Th is
means that all that needs to be done is
to m ake th e ou tp u t voltage of IC 2 in
volts equal to the gradient in per cent.
A sim p le calcu lation sh ow s th at th is
requires an amplification of ×4, which
is set with resistors R3 and R6. Any tol-
eran ces are com p en sated w ith p reset
P 3 in series with resistor R6. Any inter-
feren ce is m in im ized by cap acitor C 4,
w h ose valu e is ch osen su ch th at th e
reaction of th e circu it to varyin g cir-
cumstances is not unduly delayed.
CONSTRUCTION
Bu ild in g th e grad ien t m eter on th e
p rin ted -circu it board in Figure 2 is
straigh tforw ard . N ote, h ow ever, th at
this board is not available ready-made.
Care should be taken to ensure that the
sen sor is sold ered level on th e board ,
sin ce for correct op eration it m u st be
parallel with the board.
Th e voltm eter m od u le is lin ked to
the circuit via box header K1. If a mod-
ule other than specified is used, it may
be p ossible to om it K1 an d sold er th e
module terminals directly to ‘DVM’ on
the board.
Th e com p leted board fits n icely in
th e sp ecified en closu re. Note th at th e
fixin g bosses in th e en closu re are n ot
u sed : th e board is sim p ly screw ed
d irectly to th e bottom . Good care
should be taken because it is a tight fit-
ting.
Before the board is fitted in the case,
d rill th ree h oles in th e top lid so th at
p resets P 1–P 3 are accessible from th e
outside.
P O WE R S U P P LY
The DVM module is powered by a 9 V
d ry or rech argeable battery. Th e bat-
tery voltage is red uced to 5 V by volt-
Amplification
Th e am p lification sh ou ld be set w ith
th e grad ien t m eter on a grad ien t
(grad e). Th e d iscu ssion in th e box
sh ow s th at th e ap p roxim ation
sin α≈ p/100 has an error that increases
in d irect p rop ortion w ith α. For
instance,
at p≈ 0%, the error is 0%,
at p≈ 10%, the error is 1%,
and at p≈ 20%, the error is 2%.
Th e error m ay be m in im ized by cali-
brating at about the centre of the mea-
su rin g ran ge, rath er th an at th e
extrem es. A sim p le calcu lation sh ow s
th at th e m axim u m error can be
brought down to 1% if calibration takes
p lace at a grad ien t of abou t ×1/1.4
(0.712) th e m axim u m . So, if th e m axi-
m u m is taken as 20%, calibration
should take place at a gradient of 14%.
The gradient is readily obtained by
fixin g (ad h esive tap e) th e grad ien t
meter at the centre of a 1 metre (39.3 in)
long strip of straight wood. A gradient
of 14% is obtained by placing one end
of the strip of wood 14 cm higher than
th e oth er en d . Wh en th is is d on e,
adjust P 3 until the DVM module reads
the percentage gradient of 14%.
[990067]

34 Elektor Electronics 11/99

MICROPROCESSORS

BASIC Stamp
programming course (3)
part 3: BASIC programming
In this instalment we’ll Vin
introduce BASIC 13
P15
Stamp branching and

Servo
EEPROM access
VDD
commands used to 10k
VSS
make your BOE-Bot P12
follow a pre-deter-
mined path. A piezo- Piezo
Speaker
speaker will provide a 3300µF
feedback mechanism
VSS
to identify the location Vin
within your program.
We’ll also introduce a P3
Servo

mobile temperature
logger as an optional 10k

project to help you VSS 990050 - 3 - 11

learn synchronous
serial communication.
Attenti on. An i mportant Correcti on
regardi ng the Elektor Electroni cs BOE-
Bot development board appears else-
where in this issue.
By Chuck Schoeffler, Ph. D.,
Ken Gracey and Russ Miller
Figure 13. Basic con-
trol and feedback
schematic.
M O VE M E N T U S I N G
S U B RO U TI N E S AN D
MEMORY
Movem en t is on e of th e m ost d istin c-
tive features of robots, and it is also an
id eal w ay to learn h ow to stru ctu re
an d w rite a sim p le PBASIC p rogram .
This experiment is all about BASIC pro-
gram m in g as it p ertain s to BO E-Bot
m ovem en t w ith ou t sen sor in p u t.
Structuring your program so the BO E-
Bot m oves as you in ten d requ ires an
u n d erstan d in g of h ow to call su brou -
Parts List.
1 Complete BOE-Bot (robot built on
Elektor Electronics Board of
Education)
1 Piezospeaker
1 3300µF capacitor
2 10kΩ resistors (optional in circuit)
tines, read movement patterns from an
EEPRO M, kn ow h ow far to travel
u sin g a for-n ext loop , an d h ow to get
back to your starting point (physically,
an d w ith in you r sou rce cod e). Th e
parts we will be using are listed in the
Parts List. The complete schematic for
programs used in this column is shown
in Figure 13.

Elektor Electronics 11/99

40
R E VI E W OF
S E RVO C O N TR O L 14 5V
Servos are closed loop d evices, an d 20 ms 1500 µs 20 ms 1500 µs 20 ms
th ey are con stan tly com p arin g th eir 0V
commanded position (from the BASIC 990050 - 3 - 12

Stamp ’s pul s out comman d ) to th eir

actu al p osition (p rop ortion al to th e Figure 14. Servo con-
resistance of a potentiometer mechan- trol using pulsewidth
ically lin ked to th e sh aft). If th ere is modulation.
more than a small d ifference between
th e tw o, th e servo’s electron ics w ill
turn the motor to eliminate the error. ‘ Pr ogr am Li st i ng 1
We m od ified th e servo’s p oten - l ef t _ser vo con 15
tiometer shaft until the gears stopped r i ght _ser vo con 3
moving when the BASIC Stamp sent a x var wor d
1500 µs pulse. A pul sout value of 750 pause 2000
is equal to 1500 µs (the command oper- st ar t :
ates in u n its of tw o m icrosecon d s). A f or x = 650 t o 850 ‘ begi n of r out i ne
valu e larger th an 750 w ill tu rn th e pul sout l ef t _ser vo, x ‘ pul se wi dt h of 1500 us
servo clock-wise, and a value less than pul sout r i ght _ser vo, 1500- x ‘ pul se wi dt h of 1500 us
750 w ill tu rn it cou n ter-clockw ise. A pause 20 ‘ pause f or 20 ms
valu e very close to 750, like 760, w ill next
cau se th e servo to tu rn very slow ly.
Figure 14 is a tim in g d iagram of th e
pulsewidth modulation.
A for-n ext loop can be u sed to see ‘ Pr ogr am Li st i ng 2
h ow d ifferen t p u lsew id th s affect th e Hz var wor d
servo’s sp eed . Stan d you r BO E-Bot on f or Hz = 1 t o 4000 st ep 1000
its front or place an object underneath f r eqout 12, 70, Hz, 4000- Hz
it to keep it from rolling away. Down- ‘ gener at e t wo 70 ms t ones on P12
load Program Listing 1 to your BASIC next
Stam p . Figure 15 is a grap h of
p u lsew id th com p ared to revolu tion s
p er m in u te u sin g th e Fu taba S-148
servo.
GOSUB IS A CLOSE gosub r i ght
SOUND F E E D B ACK R E L AT I VE O F G O T O r et ur n
Th e BASIC Stam p ’s f r eqout com - Th e gos ub (Goto Su brou tin e) state-
mand can be used to add sound feed- m en t also cau ses th e p rogram execu - r i ght :
back to your BOE-Bot. Like all PBASIC tion to ju mp somew h ere else, bu t th e f or x=1 t o 18
com m an d s, it h as a p articu lar syn tax line after the gosub is remembered so pul sout l ef t _ser vo, 650
that must be followed to make it work. that the program can automatically go pul sout r i ght _ser vo, 650
To hear the speaker, download the fol- back an d con tin u e w h ere it left off. pause 20
lowing code to your BASIC Stamp: This lets us easily reuse sections of the
program. The following example illus- This example shows the r i ght routine
f r eqout 12, 750, 2000 trates the gosub command. bein g execu ted tw ice w ith a on e-sec-
‘ 750 ms 2000 Hz t one on P12 on d p au se. Th e gos ub com m an d s
gosub r i ght m ay also be n ested u p
For a m ore “robotic” sou n d try th e pause 1000 Figure 15. Pulsewidth to fou r d eep , so th at
example in Program Listing 2. versus RPM using the
This routine begins by declaring Hz Futaba S-148.
as a word variable, a number between
0 and 65,536. The loop executes a total
of fou r tim es ((4000-1)/1000), gen erat- 15 50.0
in g tw o frequ en cies at on ce on P12.
The first frequency is increasing from 1 40.0
to 4000 Hz while the second frequency
is d ecreasin g from 4000 to 1 H z. 30.0
Sou n d s like th is cou ld be ad d ed 20.0
Rotational Speed (RPM)

throughout your program.

10.0

GOTO S TAT E M E N T 0.0

N orm ally, PBASIC p rogram s execu te -10.0
in stru ction s lin e by lin e. Th e got o
command causes the BASIC Stamp to -20.0
ju m p to a n am ed p lace som ew h ere -30.0
else in the program. It can be either for-
-40.0
ward or backward in the program. The
syntax is quite simple. -50.0

got o f or war d ‘ j ump t o t he 400 500 600 700 800 900 1000 1100 1200
f or war d r out i ne Pulse Out Value (µs) 990050 - 3 - 13

Elektor Electronics 11/99 41

16

Figure 16. EEPROM

memory map.
each return takes the program back to
th e in stru ction after th e m ost recen t
gosub.
USING T H E D ATA
S TAT E M E N T AN D
EEPROM TO STORE
M O VE M E N TS
Th e BASIC Stam p h as a 2K EEPRO M
th at is u sed for p rogram storage
(which builds downward from address
2047) an d d ata storage (stores in th e
op p osite d irection — from ad d ress 0
toward 2047). If the d ata collid es with
your program the source code will not
execu te p rop erly. Each location is a
byte. Th is isn ’t en ou gh m em ory to
bu ild a com p lex en viron m en tal d ata
logger, but it’s certainly enough space
to store bytes of information you’d like
to use in a program.
The BASIC Stamp’s EEPROM is differ-
ent from RAM variable storage in sev-
eral aspects:
‘ Pr ogr am Li st i ng 3
‘ Boe- Bot Pr ogr am f or Roami ng, Li ght , and Sound
‘ Def i ne Var i abl es and Const ant s
‘ ————————————————————————————-
x var wor d ‘ l oop count er f or pul sout
posi t i on var wor d ‘ EEPROM addr ess count er
di r ect i on var wor d ‘ val ue st or ed i n EEPROM
Hz var wor d ‘ f r equency var i abl e
r i ght _ser vo con 3 ‘ r i ght ser vo on P3
l ef t _ser vo con 15 ‘ l ef t ser vo on P15
speed con 40 ‘ added or subt r act ed val ue
‘ ————————————————————————————-
‘ Pr ogr ammed Movement Pat t er ns
‘ ————————————————————————————-
dat a ” FRFRFRBBTFE” ‘ st or e movement s
‘ ————————————————————————————-
‘ Mai n Pr ogr am
‘ ————————————————————————————-
posi t i on=0 ‘ st ar t at EEPROM cel l 0
move: ‘ mai n l oop
r ead posi t i on, di r ect i on ‘ r ead di r ect i on command
posi t i on=posi t i on+1 ‘ i ncr ement t o next cel l
i f di r ect i on=” E” t hen qui t ‘ Deci de whi ch act i on t o t ake
i f di r ect i on=” F” t hen f or war d’ by mat chi ng command l et t er
i f di r ect i on=” R” t hen r i ght
i f di r ect i on=” L” t hen l ef t
i f di r ect i on=” B” t hen backwar d
i f di r ect i on=” T” t hen t ur n_ar ound
got o move ‘ r epeat unt i l E i s seen

❯ EEPRO M takes more time to store a ‘ ————————————————————————————-

valu e, sometimes u p to several mil-
liseconds.
❯ EEPROM can accept a finite number
of w rite cycles, arou n d 10 m illion
w rites to be exact (RAM h as u n lim -
ited read/write capabilities).
❯ Primary function of the EEPRO M is
‘ Sound Rout i nes
‘ ————————————————————————————-
f or war d_sound:
f or Hz = 1 t o 4000 st ep 1000
f r eqout 12, 70, Hz, 4000- Hz
next

42 Elektor Electronics 11/99

 Appr ox i ma t i ng d i st a nc e o f t r a v el
It’s easy to approximate distance travel by calculating the circumference of a wheel and estimating the pulsewidth tim-
ing loops executed by your PBASIC code. First determine wheel circumference.

circumference = pi multiplied by wheel diameter

circumference = 3.14159 x 6.67 cm = 21 cm

Knowing the rotational speed of different pulse widths will allow you to determine a specific travel distance. For exam-
ple, a pul sout command of 850 causes the servo to turn at about 50 revolutions per minute (RPM) or 0.83 revolutions/sec.
Therefore the speed of the robot will be about:

21 cm/revolution x 0.83 revolutions/sec = 17.5 cm/s

6.67 cm
To travel 100 cm, the BOE-Bot would have to travel for:

100 cm / 17.5 cm/s = about 5.7 seconds 5 cm

.9
20
Since each servo pulse takes about 1.5 ms and there is a 20 ms pause in
the loop, each loop will take about 23 ms (1.5+ 1.5+ 20), or 0.023 sec-
onds to execute. A total of 247 loops is required to travel 100 cm. You may
have to adjust the for...next loop for your particular servo.

5.7 sec / 0.023 sec/loop = 247 loops

.
.
f or war d:
f or x=1 t o 247
pul sout l ef t _ser vo, 650
pul sout r i ght _ser vo, 850
pause 20
990050 - 3 - 15
next

r et ur n gosub r i ght _sound to store p rogram s; d ata is stored in

leftover space.
back_sound: f or x=1 t o 18
f or Hz = 4000 t o 6000 st ep 1000 pul sout l ef t _ser vo, 750- speed Th ree com m an d s are u sed to access
f r eqout 12, 70, Hz, Hz- 400 pul sout r i ght _ser vo, 750- speed th e EEPRO M: dat a, r ead, an d
next pause 20 wr i t e. Th e d ata stored in EEPRO M
r et ur n next
l ow 0
builds from the upper left-hand corner
r i ght _sound: got o move (p osition 0,0) an d fills d own ward in a
f r eqout 8, 800, 2500 left to right fashion, by row. The source
r et ur n l ef t : code builds from lower right-hand cor-
hi gh 14 n er (p osition 16,128) an d bu ild s
l ef t _sound: gosub l ef t _sound upward by row, right to left. If the two
f r eqout 8, 800, 4500 collide, the BASIC Stamp will not exe-
r et ur n f or x=1 t o 18 cu te th e p rogram p rop erly. Th is is
pul sout l ef t _ser vo, 750+speed shown in Figure 16.
‘ ————————————————————————————- pul sout r i ght _ser vo, 750+speed
Th e EEPRO M m em ory m ap is
‘ Movement s pause 20
‘ ————————————————————————————- next accessed within the BASIC Stamp Win-
f or war d: l ow 14 dows editor under Run/Memory Map.
gosub f or war d_sound got o move The syntax for the r ead command
f or x=1 t o 60 is shown below. The wr i t e command
pul sout l ef t _ser vo, 750- speed t ur n_ar ound: uses the same syntax.
pul sout r i ght _ser vo, 750+speed f or x=1 t o 30
pause 20 pul sout l ef t _ser vo, 850 wr i t e 0, 100
next pul sout r i ght _ser vo, 850 ‘ wr i t e 100 i nt o eepr om byt e 0
got o move pause 20 r ead 0, x
next
‘ r ead eepr om byt e 0 and st or e
backwar d: got o move
gosub back_sound val ue i n x
f or x=1 t o 60 qui t : debug dec ? x
pul sout l ef t _ser vo, 750+speed end ‘ di spl ay val ue on PC scr een
pul sout r i ght _ser vo, 750- speed ‘ ————————————————————————————-
pause 20
next COMBINE
got o move THE CONCEPTS
Program Listing 3 brin gs all of th ese
r i ght :
concepts together: sound, movement,
hi gh 0
an d sp eed . In ord er to make effective
use of the speed, you will need to iden-

Elektor Electronics 11/99 43

Ex t r a To pi c : Sy nc h r o no u s ser i a l c o mmu ni ca t i o n w i t h
t h e DS1620 Di gi t a l Th er mo met er
Sending bytes of data with a BASIC Stamp is handled by the shi f t i n and VDD
shi f t out commands. If you are ready to learn about serial communication, try P14
1k DS1620
this project on your Board of Education.
The following additional parts are required: 1 DQ VDD 8
P13
2 CLK T(hi) 7
One DS1620 Temperature Sensor
One 1 kΩ resistor 3 RST T(lo) 6
P11
One 0.1 µF capacitor 4 GND T(com) 5
100n

x var byt e ‘ def i ne a gener al 990050 - 3 - 16

pur pose var i abl e, byt e

degC var byt e ‘ def i ne a var i abl e t o hol d degr ees Cel si us
‘ not e: DS1620 has been pr epr ogr ammed f or mode 2.
out s=%0000000000000000 ‘ def i ne t he i ni t i al st at e of al l pi ns
‘ f edcba9876543210
di r s=%1111111111111111 ‘ as l ow out put s

f r eqout 0, 20, 3800 ‘ beep t o si gnal t hat i t i s r unni ng

hi gh 11 ‘ sel ect t he DS1620
shi f t out 14, 11, l sbf i r st , [ 238] ‘ send t he ” st ar t conver t i ons” command
l ow 11 ‘ do t he command
l oop: ‘ goi ng t o di spl ay once per second
hi gh 11 ‘ sel ect t he DS1620
shi f t out 14, 13, l sbf i r st , [ 170] ‘ send t he ” get dat a” command
shi f t i n 14, 13, l sbpr e, [ x] ‘ get t he dat a
l ow 11 ‘ end t he command
degC=x/ 2 ‘ conver t t he dat a t o degr ees C
debug ? degC ‘ show t he r esul t on t he PC scr een
pause 1000 ‘ 1 second pause
got o l oop ‘ r ead & di spl ay t emper at ur e

Once the program is working try to use the write command to save temperature readings to the EEPROM, and read to
receive them back and display on a debug terminal.

tify th e exact cen tre p osition of you r

servo. Chances are although we started
with 750 (1500 µs) the servo may have
wandered to a slightly different value.
Program Listing 1 may be run to iden-
tify th ese valu es. At h igh er sp eed s
(sp eed con stan t arou n d 40) th is is n ot
as visible, but at slower speeds the BOE-
Bot w ill slow ly m ove sid ew ays if th e
cen ter p osition is n ot exactly 750.
Ch an ge valu es, m ovem en t p attern s,
and place the sound routines in differ-
ent sections of the program. This pro-
gram is also available from the d own-
loads section in
http://www.stampsinclass.com.
(990050-3)

Elektor Electronics 11/99

BATTERY CHARGERS

battery charge/refresh
station (2)
construction, adjustment
and practical use
Last month’s arti-
cle, which
describes the fea-
tures and circuit
diagram of the
battery
charge/refresh
station, clearly
suggests that
completing such a
project, with peak
charging currents
of up to 8 A, is a
bit more demand-
ing than for a
device with fewer
automatic features
and relatively lower performance. The construction information given
here is thus especially important if you wish to obtain a good result. In
addition to descriptions of the construction and the microprocessor-con-
trolled, menu-driven alignment procedures, you will find many helpful,
practical tips regarding battery charging and maintenance.

Design by N. Bechtloff & G. Brenner
(Conrad Technology Center, CTC)
Before starting, you should understand
that the battery charge/refresh station
is n ot a su itable p roject for begin n ers.
In ad d ition to th e relatively com p lex
electronics and several alignment pro-
cedures, the relatively high output cur-
rent (8 A peak maximum!) of this high-
performance charger can result in sig-
n ifican t d am age in case of a sh ort
circu it. H ow ever, if you h ave alread y
successfully built a high-power ampli-
fier or a laboratory power supply, you
should not have any difficulty with this
p ow er p roject, as lon g as you w ork
carefully.
CONSTRUCTION HINTS
The charge/refresh station is built using
two single-sided printed circuit boards,
as shown in Figures 4 and 5. These are
supplied as a set and thus have a single
ord er n u m ber in th e com p on en ts list.
One disadvantage of using single-sided
board s is a relatively large n u m ber of

Elektor Electronics 11/99

46
 w ire ju m p ers. It is best to begin by If you do not wish to monitor the tem- take care that the cooling air flow is not
in sertin g th ese ju m p ers, an d to care- perature of the heatsink or the battery, obstru cted . Th e m etal p an el th at fits
fu lly ch eck you r resu lts again st th e you can elim in ate n ot on ly th e N TC in to th e rear of th e en closu re sh ou ld
component layout d iagram to be sure sensor but also resistors R54, R56, R80 h ave a su itably-sized op en in g for th e
th at th ere are in fact seven on th e an d R82 (R81 m u st alw ays be u sed ). fan. Additional ventilation slots can be
sm aller board an d eigh t on th e larger Th e N TC sen sor sh ou ld h ave a cold mad e in the enclosure to improve the
on e. Th e p in s for ju mp er JP1 can best resistan ce betw een 500 an d 1000 Ω. cooling.
be p laced on th e sold er sid e of th e The shutoff temperature of the circuit Determining the value of the series
front panel board, so that the jumper is is set by selectin g th e valu e of R80, as fan resistor R72 is d escribed u n d er
accessible after th e LCD m od u le h as described under ‘Alignment’. ‘Alignment’.
been mounted on the component side. Th e u se of a CPU h eatsin k w ith a Th e p h otos sh ow th e fu lly-p op u -
IC4 must be mounted flat on the larger built-in fan instead of a plain heatsink lated board s an d h ow th ey are fitted
board , so th at its case d oes n ot p u sh is an unusual feature. In principle, any in to th e en closu re. Wh en con n ectin g
against the front panel. Pushbutton S3, stan d ard CPU cooler can be u sed . th e tran sform er to th e m ain s cable
switch S1 and LED D6 should be pro- What is important is that the transistors sockets, take p articu lar care th at th e
vision ally con n ected to th e circu it are m ou n ted in su lated from th e insulation is adequate. All components
board to start w ith . After th e u n it h as h eatsin k, p referably u sin g ceram ic that carry mains voltage must be fully
been tested an d align ed , th ey can be insulation washers with heat conduct- insulated against contact with the user.
mounted in their final positions on the in g p aste on both sid es. Th e h oles for Th e tran sform er u su ally h as fou r
fron t p an el an d con n ected to th e cir- th e fixin g screw s sh ou ld be d rilled to secondary leads. The leads for the two
cu it board u sin g ligh t-d u ty flexible 2.5 or 2.7 m m an d tap p ed for an M3 ‘ou ter ’ en d s of th e w in d in g are grey
wire. The socket for the microcontroller thread . For safety, check the assembly an d red , w h ile th e yellow an d blu e
can initially be left empty, and the LCD with an ohmmeter before installing the lead s can be con n ected togeth er to
mod u le n eed n ot be p lu gged in to th e heatsink, to be sure that the transistors form the centre tap.
socket strip s righ t aw ay, sin ce n eith er are tru ly in su lated from th e h eatsin k. Make the ten connections between
of th ese com p on en ts is n ecessary for Sin ce th e tran sform er can d eliver a th e tw o circu it board s u sin g flexible
the first two alignment procedures (fan very h igh cu rren t (n ot to m en tion a low-d u ty w ire, bu t u se h eavier-d u ty
voltage an d tem p era- battery pack), any short wire for the earth connection (around
ture monitoring). Figure 4. The larger circu it cou ld h ave th e sam e d iam eter as u sed for th e
Th e tem p eratu re circuit board with the u n p leasan t con se- m ain s con n ection ). In th e bottom of
m on itorin g circu itry is microcontroller, con- quences. th e en closu re, d rill su itable h oles for
op tion al an d n eed n ot trols and display is When mounting the attaching the smaller circuit board and
necessarily be installed. located behind the boards in the enclosure, fixin g th e rin g-core tran sform er.
front panel.

R77 C11
990070-1a
K2
R79

P3 H5 H8

R46
D6 R78
C30 X1 R45
A R44
C13
R4

R5

R43
B
R42
R74

R58
R26

IC5 S3
R6
R9

T1 C R41
H3

R40
D C29
R39
T7
E R38
C28

R59 R81 C20

R75 R76 R47
+
R73

D7
D13

R82 R48
D4 S2
R49
D12

D11

F H6
JP1 H7
R57 R50
C12
D5
H4

D19
IC6

S1 C16
R62 R65 R55
D9

R70
R61

R63 R64 R69 R67 R54

C17 C14 V
D10 T8 R56 a1-070099
R68

T10 IC4 R80 C10 C9

Z ROTKELE )C(
R60 R51
IC3 C15 R52
C18 P2 R66 D8 C31 R53
O T9 T6

(C) ELEKTOR
990070-1a

Elektor Electronics 11/99 47

 COMPONENTS LIST R70 = NTC, 500Ω * T8 = BF245B or BF 256B
R72 = 27Ω 2W * THR1,THR2 = TIC116A or BT151-500R
Resistors: R73 = 220Ω IC1 = LM324 (DIL14)
R1,R25,R67,R75,R76,R82 = 100kΩ R74 = 10MΩ IC2,IC6 = LM339 (DIL14)
R2,R3,R37 = 0Ω1 5W R80 = 220Ω * IC3 = TL431CLP
R4,R21,R52,R79,R81 = 22kΩ R83 = VDR S10K275 (Siemens) IC4 = 7806
R5,R9,R14,R18,R61,R66,R71 = 10kΩ P1 = 100Ω preset H IC5 = 68HC05C4 (Harris), Conrad
R6,R78 = 47kΩ P2 = 1kΩ preset H Electronics order code 692265
R7 = 33kΩ2 1% P3 = 1kΩ preset V
R8 = 15kΩ4 1% Miscellaneous:
R10 = 750Ω 1% Capacitors: JP1 = jumper
R11 = 1MΩ 1% C1,C8,C12,C17,C20,C21,C23,C24,C25, K1 = mains appliance socket with
R12 = 9kΩ09 1% C28,C31 = 100nF ceramic integral fuse 630 mAT and mains
R13 = 215kΩ 1% C2,C3 = 1µF 16V tantalum bead switch
R15,R16,R33,R34 = 100Ω C4 = 1nF raster 5mm K2 = 14-way pinheader
R17,R53,R56,R77 = 4kΩ7 C5 = 10nF K3 = 3-way PCB terminal block
R19,R20 = 3kΩ3 C6,C10 = 22nF K4,K5 = 2-way PCB terminal block
R22,R64 = 1kΩ C7 = 22nF S1 = on/off rocker switch
R23 = 487kΩ 1% C9 = 1nF S2 = rotary switch, 12 contacts, 1 pole,
R24 = 33kΩ C11 = 1µF 16V PCB mount
R26,R50,R59 = 220kΩ C13,C19 = 47µF 16V S3 = pushbutton, 1 make contact
R27 = 3kΩ83 1% C14,C15 = 10µF 63V radial F1 = POLYFUSE 1A6 (Polyswitch,
R28 = 237Ω 1% C16,C26 = 10µF 63V Conrad Electronics o/n 53 60 83)
R29,R62 = 15kΩ C18,C27 = 220µF 35V radial Tr1 = toroidal transformer 2 x 18V 3.33A
R30,R68 = 2kΩ2 C19 = 47µF 16V radial X1 = 4MHz quartz crystal
R31 = 390Ω C22 = 22µF 35V F2,F3 = 6.3AT with PCB mount holder
R32 = 27kΩ C29,C30 = 22pF and cap
R35,R36 = 0Ω27 5W CPU ventilator
R38-R46 = 20kΩ 1% Semiconductors: Case: Bopla Lab 223 mm x 72 mm x
R47,R48 = 10kΩ 1% D1-D4,D7,D9,D11,D12,D13,D15,D16, 199 mm (Conrad Electronics o/n 52 33
R49 = 3kΩ32 1% D17,D19 = 1N4148 48) with front panels (Conrad
R51 = 178kΩ 1% D5 = BAT85 Electronics 52 33 72)
R54 = 5kΩ11 1% D6 = LED high efficiency LCD-Module 1 line, 16 characters
R55 = 470kΩ D8 = zener diode 6V8, 400mW (Sharp LM16155)
R57 = 5kΩ6 D10 = zener diode 5V6, 400mW 4 off TO220 mica washer with plastic
R58 = 150kΩ D14,D18 = 1N4001 bush
R60 = 1MΩ T1,T3,T10 = BC557B 2 off wander socket dia. 4mm
R63 = 1kΩ8 T2,T9 = BC547B PCB, order code 990070-1 (see
R65 = 1kΩ2 T4,T5 = BUZ11 Readers Services page)
R69 = 470Ω T6,T7 = BC548C * ) see text

b1-070099
A7

A8

Figure 5. The smaller

circuit board with the
power components of T5 R35 T4 THR1 THR2
R34

R33

C25
F1

C1
R36

the charger circuit.

C24

F2

F3

R37
6.3AT
6.3AT

R3
T

C8
R14

R16
R15

~
R2

~
D1

K3
T3

ACCU

-
D14

D17

D16
D15
D18
R71

K5
C26
C22

R72

+
FAN
C27
O

T
C4

K4
R32
R31
R30

R21
P1

R19
F
C3

R20
C2
IC1

C7
R11
A

D3 R7
R29 R8
D

R28 C21 R13

R27

D2 R12
T2

R24
C19

R10
+

R25
C5
C

R17
Z

R22
.

IC2

R23
V

R1
C23
C6
R18
E

A6

A5

990070-1b 990070-1b

48 Elektor Electronics 11/99

Mou n tin g th e larger circu it board at
th e fron t of th e en closu re is relatively
sim p le — ju st slid e it in to th e p rop er
slot in the lower half of the enclosure.

AL I G N M E N T
Th e first task is to m atch R72 to th e
actual CPU cooler used. The controller
need not be installed for this. Connect
the fan to K4 and measure the voltage
across K4. If this differs from the nom-
in al fan op eratin g voltage (u su ally
12 V) by m ore th an 1 V, th e valu e of
R72 m u st be ap p rop riately m od ified .
For testin g, you can briefly u se stan -
dard 1/3-W resistors if you do not have
a suitable stock of 2-W or 5-W resistors.
Th e fastest w ay to d etermin e th e cor-
rect resistan ce is to first sold er in a
resistor with too high a value (such as
47 Ω) an d th en h old a secon d resistor
by hand ‘across’ this resistor (in paral-
lel) while observing the voltage at K4.
Start w ith a relatively h igh valu e for
th e secon d resistor, an d th en try su c-
cessively lower values until the correct
fan voltage is obtained . Next measure
th e effective resistan ce of th e p arallel
resistors, and then solder a 2-W resistor
w ith th is valu e in p lace on th e circu it
board.
The controller is also not needed for
the alignment of the temperature mon-
itoring circuitry. First brin g th e
u n m ou n ted N TC sen sor (w ith a cold Figure 6. Top view of
resistan ce of 500 to 1000 Ω) to th e the prototype.
d esired cu toff temp eratu re, an d mea- com p on en ts m u st be w h ere it w ill m easu re
sure its resistance at this temperature. in stalled , in clu d in g th e th e ou tp u t cu rren t of
Choose a resistor with the same value con troller an d th e LCD m od u le. To th e battery ch arger flow in g th rou gh
for R80, an d m ou n t it on th e board . start th e m icrocon troller-con trolled the meter. Since the current is pulsed ,
Mount the NTC sensor where the tem- align m en t p roced u res, p u t S1 in th e tru e-RMS m eters w ill give som ew h at
perature is to be monitored, such as on ‘NiCd’ position (closed), set S2 to posi- d ifferen t read in gs th an ord in ary
the transformer or the heatsink. If you tion ‘6’, in stall ju mp er JP1 an d sw itch m eters, bu t th e d ifferen ces are sligh t.
w ish to m on itor th e battery tem p era- on the charge/refresh unit. Now adjust Ad ju st th e ch arge an d d isch arge cu r-
ture d uring charging, the NTC sensor P3 (d isp lay con trast) for th e best legi- rents as follows:
must be fastened to the battery (using bility. Th e d isp lay w ill read ‘START
an elastic or sticky tap e, for examp le), SELFTEST’. Remove JP1. 1. Press S3. Th e d isp lay w ill read
an d th e cu toff temp eratu re sh ou ld be A mu ltimeter w ith a cu rren t ran ge ‘CH ARGE = 3 A MAX’. Ad ju st th e
arou n d 45°C. If th e tran sform er or of 3 to 10 A d .c. is n eed ed for th e fol- indicated value of the current to 3 A
heatsink is monitored , the cutoff tem- lowing alignments. Connect it between using P2.
perature can be 60° to 90° C. th e p ositive an d n ega- 2. Press S3 again . Th e
For th e rem ain in g align m en ts, all tive term in als of K5, Figure 7. Front view of d isp lay w ill read
the prototype.

Elektor Electronics 11/99 49

 WRONG 5 6
POLARITY 4 7
3 8

2 9

MODE 1 10
# OF CELLS

BATTERY CHARGE/ REFRESH STATION NiMH NiCd

990070 - F

Figure 8. Suggested
front panel layout
‘CH ARGE = 2 A MID’. Th e in d i- be greater than 1800, (reproduced at 75% of no battery is connected,
cated valu e sh ou ld rem ain at 3 A or th e d isp lay m u st true size). p ressin g S3 h as n o
however. read ‘OVER-VO LT- effect. N ow select th e
3. Press S3 again. The display will read AGE’ (th e d isp layed battery typ e w ith S1
‘CH ARGE = 1 A MIN ’. Th e in d i- values d epend on the no-load volt- an d th e n u m ber of cells w ith S2 (1 to
cated value should be within 10% of age of the transformer). 10), and then connect a battery or bat-
1 A. Disconnect the meter. 6. Next, short the positive and negative tery p ack. As soon as th e m essage
4. Press S3 again. The display will read terminals of K5 together to produce ‘ADJUST: CHARGE’ appears, you have
‘ADJUST 1.800 A’. Con n ect a fully- an intentional short circuit. The dis- five seconds to press S3 to select a dif-
charged battery con tain in g 4 to 8 p layed valu e m u st be less th an 10, feren t p rogram (see th e ‘Program
cells togeth er w ith an am m eter in and the polarity error indicator (LED modes’ box). If S3 is not pressed within
series with the battery (between the D6, ‘w ron g p olarity ’) m u st ligh t. five seconds, the CHARGE program is
positive terminal of K5 and the pos- Remove the short circuit. au tom atically started . If on th e oth er
itive terminal of the battery). Adjust 7. Press S3 again. The charger will now h an d S3 is p ressed , a n ew p rogram is
P1 for a ch argin g cu rren t betw een be in th e n orm al op eratin g m od e, selected each time it is p ressed , in th e
1.78 an d 1.82 A. Discon n ect th e and the display will read ‘NO ACCU sequ en ce CYCLE, ALIVE (= refresh ),
meter and battery. TO SERVE’ (‘accu’ = battery), since CHARGE.…. If S3 is not pressed again
5. Press S3 again. The display will read no battery is connected. w ith in five secon d s after th e last time
‘OVER-VOLTAGE’. Set S2 to position it was pressed , the ind icated program
‘8’ (8 cells). Th e d isp lay w ill read O P E R AT I O N is started and charging is activated, as
‘IN:xxxx EMP:1220’. The value ‘xxxx’ Switch on the charge/refresh unit with in d icated by th e m essage ‘START
must be greater than 1200. Next put n o battery con n ected . It w ill d isp lay CH ARGIN G’. After an ad d ition al 15
S1 in th e ‘N iMH ’ p osition (op en ). ‘N O ACCU TO SERVE’, w h ich in d i- secon d s, th e load ed cap acity is in d i-
Now either the value of ‘xxxx’ must cates that it is read y to use. As long as cated by the message ‘CCAP = xxmAh’
(for example, ‘CCAP = 1.8mAh’, where
‘CCAP ’ stands for ‘charged capacity ’).
A n u m ber of d isp lays can be
Ca p a ci t i e s brou gh t u p d u rin g th e ch argin g
p rocess by p ressin g th e fu n ction bu t-
The measure of the status of a battery is its capacity, which means the total ton. First the selected program mode is
current that can be drawn from it, expressed in ampère-hours (Ah) or mil- d isp layed for abou t tw o secon d s
liampère-hours (mAh). There is a relatively strong dependence between the (‘CHARGE MODE’, ‘CYCLE MODE’ or
capacity and the level of the discharge current. The lower the discharge cur- ‘ALIVE MO DE’), follow in g w h ich th e
rent, the lower the losses during discharging, and thus the higher the capac- d ischarge capacity DCAP is d isplayed
ity. When buying batteries, you should pay attention to the discharge current for abou t five secon d s if ch argin g is
at which the capacity is specified by the manufacturer. In this regard, the con- takin g p lace (for exam p le, ‘DCAP =
cept ‘C-rate’ is often used, in which the current level (in A or mA) is specified 0.0mAh’), and then the charged capac-
as a fraction of the rated capacity (in Ah or mAh). For example, a capacity of 1 Ah ity CCAP is displayed. For discharging,
th e d isp lay sequ en ce after th e p u sh -
at C/10 (0.1 C) means that the capacity was measured at a discharge current
button is pressed is different; after the
of 100 mA. If a different manufacturer specifies the same capacity at a higher
m od e d isp lay, CCAP is d isp layed fol-
C rate (such as C/3 = 0.33 C), the latter battery is in principle better. In this
low ed by DCAP. If n o m easu rem en t
example, if a capacity of 1 Ah is achieved at a discharge current of 333 mA, d ata are available, su ch as for DCAP
you can rest assured that the capacity at 100 mA will be higher. w h en th e battery is bein g ch arged in
You should not overlook the fact that this high-performance charger works with the CHARGE program, the value ‘0.0’
a high discharge current (initially 1.5 A, dropping to 0.5 A). The measured is displayed.
capacity under these conditions applies to high-current loading of the battery Th e ch argin g p rocess en d s w h en
and will thus always be somewhat lower than the value specified by the man- th e battery n o lon ger accep ts an y
ufacturer, except for large and/or very high-performance batteries. charge. In the CYCLE and ALIVE pro-
The amount of current accepted by the battery while it is being charged does gram s, th e d isch arge p rocess starts at
not give any particular indication of the capacity of the battery. It is always this time, as ind icated by the message
higher than the battery capacity, since part of the charging current is lost in ‘START DISCH ARGE’; oth erw ise th e
the form of heat, increasingly as the charging process nears completion. message ‘CHARGER FINISHED’ indi-
cates th at th e battery m ay be d iscon -

50 Elektor Electronics 11/99

n ected . Th e CCAP an d DCAP valu es
can also be called u p for d isp lay by
p ressin g th e fu n ction bu tton after
ch argin g is com p leted , ju st as d u rin g
ch argin g or d isch argin g. Press th e
p u sh bu tton to cycle th rou gh th e d is-
plays.
If th e ch argin g p rocess can n ot be
completed successfully, due to a defec-
tive or unsuitable battery, the message
‘END WITH ERRO R’ will appear.
If th e battery is n ot d iscon n ected
w ith in an h ou r after th e m essage
‘CH ARGER FIN ISH ED’ ap p ears, a
n ew main ten an ce ch argin g p rocess is
au tom atically started , as in d icated by
th e m essage ‘START TRICKLE’. Th e
d isp lay also sh ow s th e valu e of th e
maintenance-charging capacity TCAP
(trickle ch arge cap acity) in stead of
CCAP d u rin g th is p rocess. Sin ce th e
value of TCAP is not stored, the value
of CCAP determined during the prior
ch argin g p rocess can be called u p by
pressing the pushbutton.
If the overtemperature function is trig-
gered during the charging process (via
th e N TC sen sor), th e p rogram is su s-
pended and the display reads ‘OVER-
TEMPERATURE’. Th e p rogram
resu m es after abou t 15 m in u tes, w ith
th e d isp layed m essage ‘CO N TIN UE
PRO GRAM’.
If the program is interrupted due to
a mains power failure or switching off
the charger, all settings and values are
saved . Program execu tion w ill con -
tin u e correctly on ce main s p ower h as
been restored, with the message ‘CON-
TIN UE PRO GRAM’ d isp layed . H ow -
ever, th is is on ly tru e if th e con n ected
battery contains at least four cells and
th e p ow er ou tage lasts at least 20 sec-
onds. If the battery contains fewer than
fou r cells, th e ch arger w ill resp on d to
the power interruption with the mes-
sage ‘ADJUST: CHARGE’, and the pro-
gram w ill h ave to be m an u ally
restarted.
O P E R AT I N G TIPS
If th e red LED (D6, ‘w ron g p olarity ’)
ligh ts u p w h en th e battery is con -
nected, the battery has either been con-
nected with the incorrect polarity or it
is d eep ly d isch arged . With in correct
p olarity th e m essage ‘N O ACCU TO
SERVE’ remains visible, and you must
reverse th e battery con n ection s. If on
th e oth er h an d th e m essage ‘ADJUST:
CH ARGE’ is d isp layed , you can p ro-
ceed with the charging process just as
w ith a battery th at is n ot d eep ly d is-
ch arged (ie, for w h ich th e red LED
does not light).
If the red LED starts to blink when
th e ch argin g p rocess begin s (‘START
CH ARGIN G’), th ere is a p rotection
d iod e bu ilt in to th e battery or battery
p ack. Th e battery m u st be con n ected
d irectly to th e ch arger (w ith ou t th e
diode).
Elektor Electronics 11/99
Pr ogr a m m ode s
CHARGE
The battery is charged once using a standard fast charge process.
CYCLE
The battery is charged, discharged and then recharged.
ALIVE
The battery is charged, discharged, recharged and again discharged. If the
capacity measured during the second discharge is greater than that for the
first discharge, the charge/discharge cycle is repeated. This process ends
with a final charge process after at most six such cycles, or when there is no
difference between successive capacity values.
If the battery has built-in overtemper- being charged, and you should also let
atu re p rotection in th e form of a th e ch arger w arm u p before u se if it
bim etallic con tact, th e ch arge cu rren t has been stored at a low temperature.
will be interrupted if the overtempera- A bit of cau tion is n ecessary w h en
tu re p rotection is activated . Th e charging the smallest-sized cell (AA or
ch arger w ill th en d isp lay ‘N O ACCU m ign on ). In general, the nominal
TO SERVE’. If you d o n oth in g in th is capacity must be greater than
situ ation , th e con tact w ill close on ce 700 mAh. To be on th e safe sid e, you
th e battery h as cooled d ow n , an d th e should check the battery temperature
ch arger w ill con tin u e w ith th e ch arg- d uring the first several minutes when
in g p rocess. In sp ite of th is in terru p - ch argin g th ese sm all batteries for th e
tion, the battery will be fully loaded in first tim e. If th e (d isch arged ) battery
th e CH ARGE p rogram , even if th e quickly becomes hot at the start of the
bimetallic contact is activated multiple p rocess, you sh ou ld stop ch argin g,
times. However, the CCAP display will sin ce it is evid en tly n ot su ited to fast
be reset each tim e ch argin g is in ter- ch argin g d u e to excessive in tern al
ru p ted , so th at th e valu e d isp layed at resistan ce. Su ch a battery sh ou ld id e-
th e en d of th e p rocess w ill sh ow on ly ally be discarded right away, as should
the loaded capacity since the last inter- a battery w h ich th e ch arger rejects
ruption. w ith th e ‘EN D WITH ERRO R’ m es-
The settings for the number of cells sage. However, p lease remember th at
and the battery type must not be cad m iu m is a h igh ly p oison ou s su b-
changed during operation! These set- stance, so that such batteries should be
tin gs m ay fu n d am en tally on ly be p rop erly d isp osed of in an en viron -
changed when no battery is connected mentally safe and responsible manner
to the charger. If the charging process (contact your local council for informa-
is u n in ten tion ally started w ith in cor- tion on battery disposal).
rect battery typ e or cell n u m ber set- (990070-2)
tings, the battery must be immediately
disconnected, an d it m ay be recon -
n ected on ly after th e settin gs h ave
been corrected.
Du e to th e h igh ch argin g cu rren ts,
normal plastic battery hold ers are not
at all su itable — th e typ ical sp iral
sp rin g con tact w ire w ill qu ickly
becom e red h ot. In d ivid u al cells can
on ly be ch arged in sp ecial battery
h old ers d esign ed for h igh cu rren ts
(such as Conrad Electronics part num-
ber 51 28 77-01). With battery packs (10
cells maximum, minimum cell size AA),
th ese con tact p roblem s d o n ot exist,
bu t you sh ou ld be su re to u se sh ort
connecting leads with adequate cross-
sectional area (at least 1 mm 2).
Charging is best performed at nor-
m al room tem p eratu re (20° C), in
which case the maximum battery tem-
p eratu re w ill be 45° C. H igh an d low
tem p eratu res sh ou ld be avoid ed ; th e
absolute limits are 0° C and 40° C. Cold
batteries m u st be w arm ed u p before
51
GENERAL INTEREST
fast internet access by
ADSL technology
via standard (copper)
telephone lines
Since the early 1990s, it has been possible to
interconnect a television receiver with the tele-
phone system to provide a user interactive data
service. A few years later, it was found that
when Asymmetrical Digital Subscriber Line
(ADSL) technology is used, a Video On
Demand (VOD) service can be implemented.
Since then researchers have discovered that
ADSL provides an opportunity of significantly
increasing the speed of access to the Internet.
This article describes the basics of the ADSL
technology and how it may be used to access
the Internet at high speed.
By G. Kleine
52
INTRODUCTION
Un sh ield ed twisted -p air cop p er wires
as used in telephone networks to carry
voice sign als in th e 300–3400 Hz ban d
are cap able of tran sp ortin g m u ch
higher frequencies. This capability has
alread y been u sed for som e tim e in
Local Area N etw orks (LAN s) at d ata
rates exceeding 10 MHz.
Th e lin e atten u ation u p to abou t
6 MH z is of th e ord er of 0.7 d B/kH z
w ith alm ost con stan t grou p d elay.
Because of this, there is very little pulse
distortion to a digital signal and, there-
fore, very few bit errors.
Th ese ch aracteristics allow th e fre-
quency spectrum above the voice band
to be u sed for a low bit rate (u p to
64 kbit/s) for an upstream subscriber ’s
con trol lin k an d a d own stream d igital
data service at rates exceeding 6 Mbit/s.
Filters with high stop-band attenuation
at each end of an ADSL network are, of
cou rse, requ ired to u se both ban d s
Elektor Electronics 11/99
simultaneously.
a
So as to lim it th e ban d w id th 1 256 channels of 4.3125 kHz each
n eed ed , m od ern m od u lation tech -
n iqu es su ch as Carrierless Am p litu d e POTS
P
Ph ase (CAP) m od u lation as u sed for 4.3125 kHz QAM modulated
Grou p 2 fax m ach in es, an d Discrete
Mu lti-Ton e (DMT) m od u lation , are
u sed . Th ese tech n iqu es allow several
bits to be represented by one transmis-
sion sym bol. ADSL is n am ed for th is
asymmetric bit rate allocation. 1 2 3 4 .... 26 27 28 29 ............... 254 255 256

In Carrierless Am p litu d e Ph ase

modulation, the bit stream is first split
in to tw o com p on en ts an d th en sep a-
0.3 4 26 138 1130
rately p assed th rou gh n on -recu rsive
Upstream Downstream
d igital filters th at h ave an im p u lse
response differing in phase by π/2. The f [kHz] 990065 - 11a

ou tp u ts are th en ad d ed , p assed
th rou gh a d igital-to-an alogu e con - b
224 channels of 4.3125 kHz each
verter (DAC), and filtered before being
passed to the transmission network.
P
Discrete Mu lti-Ton e m od u lation is 4,3125 kHz QAM modulated
very similar to Coded Orthogonal Fre-
qu en cy Division Mu ltip lex (CO FDM) ISDN

sin ce th e m ain ch an n el is sp lit in to 160 kbit/s

many sub-channels.
Each serial in p u t sign al is first
encoded into parallel format and then 1 2 ........ 31 32 33 34 35 ........ 222 223 224

p assed th rou gh a Fast Fou rier Tran s-

form (FFT) processor to convert the fre-
qu en cy-d om ain sam p les in to tim e-
0.3 120 140 280 1104
domain values with a sliding time-win- (80)
Upstream Downstream
d ow effect. Th ese valu es are
tran scod ed in to a serial form at an d f [kHz] 990065 - 11b

p assed th rou gh a d igital-to-an alogu e

converter (DAC) before transmission.
The ADSL technology has been laid c
d ow n in AN SI (Am erican N ation al P
POTS
Stan d ard s In stitu te) Stan d ard
T1.413.(1997).

FREQUENCY SPECTRUM
Currently, the most widely modulation
u sed is DMT. As is to be exp ected , an
ADSL-DMT sign al con sists of a great
number of time-domain sub-channels
th at are su p erim p osed on to th e 1 2 3 ...... 25 26 27 28 29 ....... 254 255 256
twisted-pair copper telephone wires. A
d iagram m atic rep resen tation of th e
resu ltin g sp ectru m is sh ow n in Fig-
ure 1a. Th e ADSL Stan d ard p rovid es 0.3 4 26 138 1130
for the frequency range of 0–26 kHz to Downstream & Upstream Downstream
be left free for the analogue telephone
f [kHz] 990065 - 11c
service (PO TS= Plain
Old Telephone Service – Figure 1. Spectrums with the use of ADSL technology:
colloqu ial). Th e (a) analogue telephony 256 channels. However, in
26–1130 kH z ban d (frequency division multiplex—FDM) p ractice, ow in g to attain -
accommod ates 256 su b- (b) ISDN telephony (frequency division multiplex—FDM) able signal-to-noise ratios,
ch an n els each on ly abou t h alf of th is
(c) analogue telephony
4.3125 kH z w id e. Th e capacity can be used.
(operation with echo compensation)
cen tres of th ese su b- Wh en n oise levels
ch an n els are also sep a- are h igh , or con n ection
rated by 4.3125 kHz. relevant channel: (128-QAM, 64-QAM, cables are very long, the signal space is
The individual carriers in the down- 32-Q AM, 16-Q AM, 8-Q AM, Q PSK). red u ced to an exten t w h ere secu re
stream and upstream ranges are quad- The larger the signal-to-noise ratio, the com m u n ication is m ain tain able. Th is
ratu re am p litu d e m od u lated 1) an d larger th e sign al sp ace an d th u s th e m ean s th at th ere m ay be ch an n els
carry betw een 2 bit/s/H z an d n u m ber of bits rep resen tin g a tran s- w h ich , ow in g to p revailin g n oise or
15 bit/s/Hz. The allocation of this rate of mitted symbol. high attenuation, are useless.
information is adaptive, that is, during Clearly, each ch an n el in th e sign al The standard foresees two possible
the initialization process the individual can transmit up to 64.7 kbit/s, which, in m ean s for allocatin g th e ch an n els to
carriers are allocated variou s sign al th eory, gives a m axim u m cap acity of th e d ow n stream or u p stream ban d :
spaces, depending on the noise in the m ore th an 16 Mbit/s in th e case of relatively straigh tforw ard Frequ en cy

Elektor Electronics 11/99 53

 ADSL Stan d ard , th e low er ch an n els
2 are used during the link set-up for test-
0 dB 64.7 kbit/s in g th e lin es by m ean s of test d ata
p ackets, an d for d eterm in in g th e bit
S/N Bitrate rate of each individual channel. Since,
in the case of ISDN, these channels are
n o lon ger available, ch an n els in th e
u p stream ran ge are allocated for test
p u rp oses. All th is is d etailed in
Annex B.
Sin ce th e low er ch an n els are u sed
for link set-up testing, they are never-
th eless u sed in th e d om estic su b-
-50 dB 8.6 kbit/s scriber ’s system . Th ey also en su re a
1 2 3 4 5 ................... 252 253 254 255 256
secu re first lin k betw een th e ADSL
modem and the end of the (telephone)
carrier no. 990065 - 12
trunk system. In the United Kingdom,
most subscribers are within about 3 km
Figure 2. Bit distribution (about 2 miles) of the end of the trunk
Division Multiplexing as a function of the sig- p revailin g sign al-to- system.
(FDM) or Ech o Com - nal-to-noise ratio. n oise ratio) in con -
pensation. ju n ction w ith th e AD S L M O D E M D E S I GN
In FDM, th e fre- ch an n el equ alizer in Th e d esign of a m od em for u se w ith
qu en cy ran ge is sp lit in to tw o ban d s. th e m od em . Figure 2 sh ow s a typ ical ADSL is typically as shown in the sim-
Th e first 26 ch an n els form th e bit distribution as a function of the sig- p lified block d iagram in Figure 3. A
upstream band, while channels 27–256 nal-to-noise ratio. similar mod em is also n ormally avail-
carry th e d ow n stream d ata—see Fig- able at th e telep h on e exch an ge, bu t
ures 1a and 1b. AD S L AN D I S D N there it can usually handle a number of
In Ech o Com p en sation , th e fre- Figure 1b shows the situation when an su bscribers an d is called Digital Su b-
quency range is split into downstream ISDN (Integrated Services Digital Net- scriber Lin e Access Mu ltip lexer
an d u p stream accord in g to th e d irec- work) access lin e is available. Th e sig- (DSLAM).
tion of tran sm ission —see Figure 1c. n al on su ch a lin e (2×64 kbit/s) Th e in com in g d ata (at th e su b-
Th is lead s to a h igh er cap acity for extends in some countries up to 80 kHz scriber ’s en d , th e u p stream d ata, an d
downstream data flow, since the lower an d in oth ers u p to 120 kH z. In ord er at the exchange end , the d ownstream
112 kH z of th e ADSL ran ge con tain s to make use of the ADSL technology, a data) are applied to an encoder, which
the better channels: at higher frequen- way must be found to combine it with allocates them to the n channels of the
cies, th e atten u ation rises. So as to ISDN technology. This could, of course, DMT signal. This is done in accordance
ensure that all functions well, an Echo be d one by a switch to select between w ith a bit load in g table th at h as been
Equalizer is needed, spaced well away th e tw o d ifferen t u sages, bu t th is established during the link set-up. This
from th e rem ain in g d ata flow. Th e w ou ld m ean th at ADSL an d ISDN table shows how many bit/s each chan-
ADSL Stan d ard term s th is m od e of w ou ld n o lon ger be in d ep en d en t of nel can hand le. The encod er also pro-
operation Category 2 ADSL. on e an oth er an d cou ld n ot be u sed vid es Forw ard Error Con trol2) (FEC)
Level d ifferen ces m ay occu r simultaneously. The solution ad opted with a Reed Solomon code (as used in
betw een th e low frequ en cy carriers is for th e DMT sign al to start at digital television).
an d th e h igh -frequ en cy on es. If th ese 140 kH z in stead of at 26 kH z. Th is The parallel digital bit stream from
do not exceed 50 dB, they are compen- means that, given a channel spacing of th e en cod er is ap p lied to an In verse
sated by th e ch an n el equ alizer in th e 4.3125 kHz, there are only 224 channels Fast Fou rier Tran sform (IFFT) p roces-
ADSL m od em . H igh er atten u ation available. This is laid down as Annex B sor. Th is con verts th e n-bit w id e fre-
w ou ld m ake th e carrier in effectu al, of the ADSL Standard. qu en cy-d om ain sam p les in to tim e-
w ere it n ot for th e u se of altern atin g Th e p roblem is cau sed by th e fact domain values (2n bits – real and imag-
lin e cod in g (in accord an ce w ith th e th at, in lin e w ith th e
Figure 3. Block diagram
of a typical modem for
Bit consumer use in ADSL
3 Loading
Table
technology.

N 2N P Cyclic
Data
In Encoder IFFT Prefix DAC
S Add
Tx/Rx-
Echo Signal
Canceller Di-
plexer

Data N 2N P Cyclic
Out Decoder FFT Prefix Equalizer ADC
S Drop

Bit
Loading 990065 - 13
Table

54 Elektor Electronics 11/99

in ary p arts). Th ese valu es are Some abbreviations and acronyms:
transcoded into a serial format, where-
upon a cyclic prefix is added. AAL ATM Adaptation Layer
The echo canceller creates an image ADC Analogue-to-Digital Converter
ADSL Assymmetrical Digital Subscriber’s Line
of the send and receive signals which
ANSI American National Standards Institute
blots u p th e real ech oes w h en th ey
ATM Asynchronous Transfer Mode
com e alon g. It is set u p d u rin g th e ATU ADSL Transceiver Unit
on set of th e lin k w ith th e aid of a test B-ISDN Broadband ISDN
bit packet. CAP Carrierless Amplitude/Phase modulation
Th e ou tp u t of th e ech o can celler is CDSL Consumer Digital Subscriber Line
ap p lied via a d igital-to-an alogu e con - CODEC COder-DECoder
verter (DAC) an d d ip lexer to th e tele- COFDM Coded Orthogonal Frequency Division Multiplex
phone line. CPE Customer (subscriber) Premises Equipment
Th e in com in g sign al is ap p lied via CRC Cyclic Redundancy Check
th e d ip lexer to an an alogu e-to-d igital DAC Digital-to-Analogue Decoder
con verter (ADC) w h ich con verts th e DMT Discrete Multi-Tone modulation
analogue signals on the telephone line DSL Digital Subscriber Line
into a digital data stream. DSLAM Digital Subscriber Line Access Multiplier
Su bsequ en tly, th e sign al is ap p lied DTE Data Terminal Equipment
to th e ech o can celler w h ich p erform s DTMF Dual Tone Multi Frequency
the same function as in the case of the ETSI European Telecommunications Standards Institute
outgoing data stream. FDM Frequency Division Multiplexing
Th e equ alizer, w h ich is set u p n ot FEC Forward Error Control (or Correction)
on ly d u rin g th e lin k set-u p , bu t also FFT Fast Fourier Transform
d uring normal operation by means of IDSL ISDN Digital Subscriber Line
IETF Internet Engineering Task Force
test m essages, p rovid es requ isite fre-
IFFT Inverse Fast Fourier Transform
quency equalization.
IP Internet Protocol
After th e cyclic p refix h as been ISDN Integrated Services Digital Network
rem oved , an d th e sign al h as been ISO International Standardization Organization
tran scod ed in to p arallel form at, it is ITU International Telecommunications Union
ap p lied to th e Fast Fou rier Tran sform LAN Local Area Network
(FFT) p rocessor. Th is stage recon verts MODEM MOdulator-DEModulator
th e n-bit w id e tim e-d om ain sam p les MPEG Motion Picture Expert Group
into frequency-domain values. N-ISDN Narrowband ISDN
Th e d ecod er recon stru cts th e bits NT Network Terminator
contained in the single DMT channels OSI Open Systems Interconnection
into the correct sequence by means of PABX Public Access Branch Exchange
th e Bit Load in g Table w ith w h ich it is PCM Pulse Code Modulation
p rogram m ed . Th e d ecod er also p ro- PDU Protocol Data Unit
vid es FEC w ith a Reed Solomon cod e POT(S) colloquial term for Plain Old Telephone System (or Service)
w h ich en su res th at an y bit errors are PSTN Public Switched Telephone Network
corrected. QAM Quadrature Amplitude Modulation
In tegrated circu it sets an d oth er QPSK Quadrature Phase Shift Keying
com p on en ts for bu ild in g an ADSL SLIC Subscriber Line Interface
mod em are available from many elec- TCP Transmission Control Protocol
tron ics retailers an d m ail ord er firm s. TDM Time Division Multiplexing
UART Universal Asynchronous Receiver/Transmitter
Man u factu rers of th ese p arts are
URL Uniform Resource Locator
Motorola, STMicroelectronics, Alcatel,
USB Universal Serial Bus
Broad com , Globesp an , an d Texas UTP Unshielded Twisted Pair
In stru m en ts. Th e w eb ad d resses of VADSL Very high rate ADSL
several of th ese m an u factu rers are VDT Video Dial Tone: an alternative term to describe ADSL
given in Table 1. VOD Video On Demand
Th e bu ild in g of th e m od em p re- WAN Wide Area Network
sen ts con stru ctors w ith a few ch al-
len ges. For in stan ce, th e DMT sign al
n eed s very h igh gain am p lifiers an d
linear operation of the power d rivers. Some relevant Internet URLs:
Th e crest factor is very h igh , w h ich ADSL Forum home page www.adsl.com
requires lots of reserve power in driver Alcatel www.usa.alcatel.com
circu its. H ow ever, m an u factu rers like ANSI home page www.ansi.org
Burr-Brown and Analog Devices have ATM Forum home page www.atmforum.org
special ICs available for these purposes. Broadcom www.broadcom.com
Th ere are also p roblem s in telep h on e ETSI home page www.etsi.fr
exch an ges, sin ce each ADSL con n ec- Frame Relay Forum home page www.frforum.com
tion to a subscriber requires a power of GlobeSpan www.globespan.net
12 W. Wh en m an y m od em s are con - Internet Engineering Task Force www.ietf.org
tained, heat dissipation may become a ITU home page www.itu.int
problem. Motorola www.mot-sps.com
St Microelectronics www.st.com
AD S L E Q U I P M E N T Texas Instrument www.ti.com.sc
Figure 4 shows in d iagrammatic form Universal Serial Bus home page www.usb.org
w h at an ADSL lin k en tails at th e su b-

Elektor Electronics 11/99 55

 ADSL line ADSL

4 High Speed
termination modem
Downstream
Data Data
Downstream Downstream
Tx Splitter Splitter Rx

highpass highpass
Control Control
Data Data

Upstream Upstream
Rx cable Tx

lowpass lowpass

switchboard
990065 - 14

Figure 4. Simplified diagram

of a typical ADSL system.
scriber ’s en d an d
at th e telep h on e
exchange.
Im m ed iately on en terin g th e su b-
scriber ’s p rem ises an d th e telep h on e
exchange, an ADSL splitter is need ed .
This contains a high-quality, high-pass
filter w ith very steep skirts for th e
ADSL frequency spectrum.
The incoming or outgoing analogue
telep h on e or ISDN sign al, as th e case
m ay be, is p assed th rou gh a low-p ass
filter.
At th e su bscriber ’s en d , an ADSL
modem must, of course, be available to
w h ich th e ou tp u t of th e sp litter is
ap p lied . Th is m od em con tain s a
receiver (Rx) for th e h igh -rate d ow n -
stream signal and a transmitter (Tx) for
its own upstream signal. The upstream
an d d ow n stream sign als con tain n ot
on ly m essage d ata, bu t also m an age-
ment and control data.
At th e telep h on e exch an ge, ADSL
term in ators m u st be ad d ed for each
and every subscriber who wants ADSL
service. These units are the opposite of
a m od em : a d ow n stream sen d er (Tx)
transmits the high-quality digital data
stream via the splitter to the telephone
lin es. Th e u p stream receiver (Rx)
processes data at mod-
erate rates. A Digital
Su bscriber Lin e Access Mu ltip lexer
(DSLAM) makes ADSL channels avail-
able to a number of subscribers.
AD S L S YS TE M
STRUCTURE
Figure 5 shows in d iagrammatic form
w h at equ ip men t oth er th an an ADSL
splitter and a mod em are required . At
the centre are the ADSL splitters in the
telep h on e exch an ge an d at th e su b-
scriber ’s premises.
At th e exch an ge en d , th e ou tp u t
from the splitter is linked to the ADSL
Term in ation an d from th ere to th e
ATM (Asyn ch ron ou s Tran sm ission
Mode) Backbone 3) via the ATM switch.
The transmission rate between the line
term in ation an d ATM sw itch is
155 Mbit/s.
At the subscriber ’s end, the output
of th e sp litter is ap p lied to th e ADSL
modem, which contains an ATM-F25.6
in terface (25.6 Mbit/s) or a (slow er)
LAN (Local Area N etw ork) in terface
Type 10BaseT. The computer must con-
tain a corresponding ATM or LAN card
to be able to work failure-free with the
modem interface.
In case an ISDN line is used, a Net-
work Terminator (NT) must be inserted
between the splitter and the ISDN con-
nection—see Figure 5.
C O N N E C T I O N S E T- U P
O w in g to th e m an y w ays an ADSL
tran smission system may be set u p , it
is essential to study the protocol, spec-
ification, and any other relevant litera-
ture before starting the practical work.
Th e frequ en cy resp on se in both
directions must be measured carefully
and it should be ensured that the two
m od em s u se th e sam e carrier fre-
qu en cy. Su bsequ en tly, th e bit rates of
th e u p stream an d d ow n stream ch an -
n els sh ou ld be d eterm in ed , an d also
which means is to be used for channel
allocation (FDM or ech o com p en sa-
tion) with the aid of test messages. It is
at this point that the maximum bit rate
of individual connections is decided.
ADSL tech n ology is cap able of
w orkin g w ith varyin g sign al-to-n oise
ratios. Its Bit Sw ap p in g facility allow s
bits to be re-allocated to a specific chan-
nel during operation.
Th e start p h ase m ay take from 20
secon d s to on e m in u te. Th is slow
begin n in g en su res, h ow ever, th at th e

Figure 5. Detailed diagram

of a typical ADSL system. PC
5 ATM-F25,6
or
10BaseT
ATM Backbone

ATM ATM ADSL ADSL

Switch Line modem
Termination

cable
155 Mbit/s Splitter Splitter
ISDN
NTBa ISDN

POTS
switchboard

990065 - 15

56 Elektor Electronics 11/99

maximum possible d ata rates for each
and every channel are fixed optimally.
If, for on e reason or an oth er, it is n ec-
essary to fix the bit rates anew, it is not
n ecessary to w ait again for 20–60 sec-
onds before operation can start. There is
a short procedure for this, which takes
on ly a few secon d s. In th at case, it is,
however, necessary for the mod em to
m on itor th e tran sm ission qu ality of
each and every channel.
AD S L LI TE M O D E M
Sh ortly after th e ADSL Stan d ard h ad
been p u blish ed by AN SI in 1997, a
n u m ber of m an u factu rers, in clu d in g
Microsoft, Intel, and Compaq, formed
th e Un iversal ADSL Workin g Grou p
(UAWG). One of the aims of this group
was to get rid of the splitter, since this
would mean a substantial saving at the
exchange on the Subscriber Line Inter-
face (SLIC) and at the subscriber ’s end
on th e ATM Eth ern etw ork card —see
Figure 6. It sh ou ld be born e in m in d
th at th e ADSL sp litter is a costly u n it.
Th e con sequ en t G.Lite or Un iversal
ADSL m od em is stan d ard ized by th e
ITU in the ITU Standard G992.2 – Split-
terless ADSL.
Apart from the introduction of this
m od em , th e n u m ber of ch an n els is
red u ced from 256 to 128, th e n u m ber
of bits per second per Hertz is reduced,
so that the signal space is smaller, the
d ow n stream bit rate is red u ced to
1.5 Mbit/s, although the upstream can
still be sent at 500 kbit/s. Furthermore,
the output level is reduced to such an
exten t th at p ow er con su m p tion an d
th e requ isite lin earity of th e an alogu e
d river stages are m od erated sign ifi-
can tly. As a bon u s, th is also h elp s to
keep th e an alogu e telep h on e traffic
alm ost en tirely free of in terferen ce.
An d last, bu t n ot least, w ith an ADSL
Lite mod em, op eration is in Category
2 of th e AN SI Sp ecification , w h ich
m ean s th at th e u p stream an d d ow n -
stream sections share the lower ADSL
frequ en cy ran ge by m ean s of ech o
com p en sation . Th is gu aran tees good
tran sm ission coefficien ts on th e in d i-
vidual carriers.
It is interesting to note that splitter-
less ADSL tech n ology is m u ch m ore
popular in Anglo Saxon countries than
in continental Europe.
CONCLUS ION
Now the ADSL technology has proved
itself am on g com m ercial u sers, it is
clear that it can lead to better use of the
telep h on e system , p articu larly as
regard s access to th e In tern et, by
d om estic su bscribers Even w h en
downstream rates of only (!) 1.5 Mbit/s
are attain able, th is gives a 27-fold
in crease in d ata rates com p ared w ith
those provided by a 56 kbit modem.
Current modems for domestic sub-
scriber u se are of th e h ybrid typ e,
Elektor Electronics 11/99
Figure 6. Simplified diagram of
6 a splitterless ADSL system.
ATM ADSL
Line
Termination
cable
Splitter
switchboard
w h ich can h an d le th e V.90 an alogu e
standard as well as the ADSL standard.
Most of these modems can be adapted
via firm w are* in case of stan d ard
updates.
AN D TH E F U TU RE ?
Tech n ology d oes n ot stan d still, an d
already there are countries where Very
h igh rate ADSL—VDASL—is bein g
d evelop ed or market-tested . With th e
ad ven t of fibre tech n ology, th e lin e
im p ed an ce is bein g greatly red u ced .
Th is allow s for very m u ch h igh er bit
rate services: currently expected to be
52 Mbit/s d ow n stream an d 3.2 Mbit/s
u p stream (w ith a cop p er tail of, p er-
h ap s, 100 m etres) w ith in a few years’
tim e. Su ch rates w ill m ake MPEG-2
data transmissions possible.
[990065]
Notes:
1) Q u ad ratu re Amp litu d e Mod u lation
(Q AM) d igital is a varian t of Q u ad ra-
tu re Ph ase Sh ift Keyin g (Q PSK). In
Q PSK, qu ad ratu re p h ase sh ift of th e
carrier is u sed to con vey tw o bits of
d ata in th e same ban d w id th as on e
bit. In Q AM d igital, th is is exten d ed
by obtain in g 8, 16, 32, 64, 128, 256
p h asors from th e same carrier fre-
qu en cy to rep resen t 8, 16, 32, 64, 128,
256 u n iqu e bin ary cod e p attern s, each
of 3, 4, 5, 6, 7, 8 bits.
2) Forw ard Error Con trol (or Correction )
is a tech n iqu e in w h ich th e mean s to
d etect bit errors is con tain ed w ith in
th e tran smitted message stream th u s
allow in g th e receiver to correct th e
errors w ith ou t requ irin g retran smis-
sion of th e d ata.
3) It should be noted that echo cancella-
tion is beneficial only whenever the
same frequency is used for bidirec-
tional traffic .When different subchan-
nels are used for different directions,
echo cancellation is superfluous. In
that case, the UTP becomes three
access points: one for speech, one for
upstream data, and one for down-
stream information.
PC
ADSL
Lite
Modem
POTS
990065 - 16
4) Th e backbon e is th e major tran smis-
sion p ath of a Pu blic Data Netw ork
(PDN ).
5) Strictly speaking, firmware is system
software held in read-only memory
(ROM).
References:
ANSI T1.413: Network and Customer
Installation Interfaces – Asymmetric
Digital Subscriber Line Metallic Inter-
face. Issue 1, 1995. Draft Issue 2, Decem-
ber 1998.
RFC 791: Internet Protocol
ITU G992.1 (G.dmt) Asymmetrical Digi-
tal Subscriber Line (ADSL) Transceivers.
ITU G992/2 (G.lite) Splitterless Asym-
metrical Digital Subscriber Line (ADSL)
Transceivers.
DSL Simulation Techniques and Stan-
dards Development for Digital Subscriber
Line Systems, by Walter Y Chen,
MacMillan Technical Publishing, Indi-
anapolis, IN, 1998
ADSL and DSL Technologies, by Walter
Goralski, McGraw-Hill, New York,
1998.
Integrated Services Digital Networks, by
Hermann J Helgert, Addison Wesley
Publishing Company, Reading, Mass.
1991.
ISDN: Concepts, Facilities, and Services,
by Gary C Kessler and Peter V South-
wick, McGraw-Hill, New York, 1998.
ADSL/VDSL Principles, by Dennis
Rauschmayer, Macmillan Technical
Publishing, Indianapolis, IN, 1999.
ADSL: Standards, Implementation and
Architecture, by Charles K Summers,
CRC Press, London & New York,
1999.
57
AUDIO & HI-FI

audio DAC 2000

Part 1
for perfectionists

This brand-new digital-to-analogue converter (DAC) is intended

especially for those audio enthusiasts who wish to have their audio sys-
tem fully up to date at the beginning of the new millennium. The 24-bit
resolution and the top sampling rate of 96 kHz ensure that full advantage
can be taken of the qualities of the latest compact discs (CDs) and digi-
tal video discs (DVDs).

Design by T Giesberts

Elektor Electronics 11/99

58
1
Sampling
Frequency
Display

4 3 L
Coax 24-Bit 24-Bit 24-Bit 26 / 42 kHz
32...96 kHz 8x oversampling Third-order
Digital Reset Digital Sign-Magnitude I/U Lowpass
Audio Interpolation Audio DAC Converter Post Filter
Receiver De-emp. Filter 3
Optical (CS8414) (DF1704) (2x PCM1704) (2x OPA627) (2x OPA627)
R
4 12 3

Hardware Hardware Hardware

Control Control Control

Mute
Reference
Double Bandwidth
Clock

+12V +5V
+5V Analog
Digital Analog (DAC)
Power Supply Power Supply Power Supply
-12V -5V 990059 - 11

Figure 1. The block diagram

INTRODUCTION
O ver th e p ast few years th ere h ave
been quite a few developments in digi-
tal aud io engineering. Although qual-
ity-conscious audio enthusiasts gener-
ally w elcome th ese d evelop men ts,
many of them wonder if there will ever
be an en d to th eir h avin g to u p d ate
and adapt their systems. It is, therefore,
perfectly understandable that the qual-
ity DACs p u blish ed in th is m agazin e
over th e p ast seven years or so h ave
proved very popular. After all, when it
comes to re-evaluating a d igital aud io
sou rce, it is m u ch sim p ler to u p d ate
just the DAC and not the entire system.
Moreover, a stan d -alon e DAC h as th e
ad van tage th at it is u n iversal an d can
be combined with any CD/DVD player
or digital tape recorder.
The Audio DAC 2000 is intended for
the new millennium: it has a 24-bit res-
olu tion an d is su itable for sam p lin g
rates of 32–96 kH z. Th ese p rop erties
m ake it state of th e art as far as tech -
nology is concerned, while the design
of the practical circuit is aimed at qual-
ity without compromise.
Some enthusiasts may wonder why
h igh er sam p lin g rates h ave n ot been
catered for. The answer to this is that it
is qu estion able w h eth er h igh er rates
w ill ever be im p lem en ted . Alth ou gh
th e n ew 192 kH z stan d ard is w ritten ,
pundits reckon that it will take quite a
of the Audio DAC 2000
few years before th e clearly shows the design
hardware and software and what are the most
w ill becom e com m er- important parts of the unit.
cially available.
DESIGN
Th e circu it is con tain ed on fou r in d i-
vid u al p rin ted -circu it board s: on e for
th e ± 12 V an d + 5 V p ow er su p p lies;
one for the digital audio receiver with
d isp lay d river; on e for a 2-d igit LED
d isp lay; an d on e for th e d igital/an a-
logu e circu its, th e d igital filter, th e
DACs an d th e an alogu e ou tp u t stage.
Its block diagram is shown in Figure 1.
Th e p ow er su p p lies com p rise a
+ 5 V section for th e d igital circu its
(receiver and digital filter) and a ± 12 V
section for th e an alogu e ou tp u t sec-
tion , in clu d in g th e associated relays.
Th ere is also a ± 5 V su p p ly, d erived
from the ± 12 V supply for the DACs.
The digital audio receiver is associ-
ated w ith a sam p lin g rate d isp lay,
hardware control, and reference clock.
Th e d isp lay con sists of tw o 7-seg-
men t LED mod u les for in d icatin g th e
sampling rates: 32 kHz, 44 kHz (in real-
ity 44.1 kHz), 48 kHz, 88 kHz (in reality
88.2 kHz), or 96 kHz.
The hardware control is primarily a
circuit for setting the receive mode via
a 4-pole dual-in-line (DIP) switch.
Th e referen ce clock is an accu rate
crystal oscillator op eratin g at
6.144 MH z
which is used by
a com p arator in
th e receiver to
d eterm in e th e
frequ en cy of th e received clock – a
phase-locked loop, PLL.
The data that indicate the sampling
rate, and the most important received
ch an n el-statu s bits (strictly sp eakin g
only the emphasis bit) are multiplexed
by the receiver.
Th e d ata are d em u ltip lexed by a
Gen eric Array Logic – GAL™ – wh ich
also d rives th e d isp lay. As far as th e
multiplexed data is concerned, they are
translated and passed to the outputs of
the registers. This prevents ad d itional
sw itch in g lin es com in g in to bein g: a
m u ltip lexed d isp lay w ou ld d em an d
quite a high current.
In normal operation, the outputs of
th e GAL are static. A n u m ber of lin ks
n eed ed for th e d isp lay are alread y
interconnected so as to keep the num-
ber of requisite outputs to a minimum.
Th e lin k between th e d igital au d io
receiver an d th e d isp lay is m ad e by a
len gth of 10-core flatcable, an d th at
betw een th e receiver an d DAC board
by 16-core flatcable. The 16-core cable
also carries the + 5 V supply and vari-
ou s sign als to an d from th e d igital fil-
ter: serial au d io d ata, p ow er on reset,
de-emphasis, mute, and switching. The

™ GAL is a trademark of National Semiconductor Corporation.

* Sony/Philips Digital Interface Format

Elektor Electronics 11/99 59

sw itch in g sign als alm ost d ou ble th e
S1
bandwidth of the filter when sampling 5
R5

rates of 88.2 kH z or 96 kH z are 5V 4

1 5V
3
detected. 2
Th e m u te sign al is actu ated w h en 5V 4x 10k
K2
L2 1 2
there is no signal at the receiver input 1 2 5 4 9 10 13 12
5V 3 4
IC2 IC4a IC4b IC4c IC4d
or w h en th e PLL can n ot lock. It is 5V
≥1 ≥1 ≥1 ≥1 5 6
3 47µ C13 7 8
taken from th e error ou tp u t (p in 5 – C9
3 6 8 11
9 10
C8
ERF) of IC 1 an d u sed to d e-en ergize 1
100n
R4 L1
RST
47µ 25V

4Ω7
the output relay and to switch the dig- 2 4 5 6
100n
R2
R6
5V

10k
ital filter to the mute mode. 47µ

220Ω
C6 C7 C4 C5 L4
The reset pulse for the receiver and TORX173
d igital filter is gen erated by n etw ork 10µ 63V 47n 10µ 63V 47n 47µ

JP1
R6-C13 and inverted by the GAL. 7 22 C14 C15

Th e d e-em p h asis sign al is u sed by S/PDIF K1 C1

D A
M3
17 47µ 25V 100n
9 18
th e d igital filter to correct th e p re- RXP M2
24
24
10n M1
emp h asis in th e sou rce sign al. Tw elve R1
4
E2
IC1
M0
23 1
CLK OUT1
23

75Ω
5 27 2 22
DIP sw itch es d eterm in e th e variou s 6
E1 F2
2 3
F2
IC5
OUT2
21
C2 E0 F1 F1 OUT3
settin gs of th e filter as regard s th e 10
RXN F0
3 4
F0 OUT4
20
28 25 5 19
input and output formats, the number 10n VERF
CS8414
ERF
16 6
ERF OUT5
18
C3 R3 SEL RST OUT6
of bits, the filter characteristic, and oth- 470Ω
20
FILT CBL
15 7
SEL
GAL
DBW
17
1 19 8 16
ers. 68n
14
C MCK
12 9
MUTE
15 K3 5V
U SCK DEEM
Th e d igital filter d rives tw o DAC 5V 13
FCK FSYNC
11 10
RESET
14 1 2
26 11 22V10 13 3 4
chips: one for the lefthand and one for D
SDATA
A 5 6
L3
the righthand channel. These chips can 8 21 12
7 8
9 10
be set by h ard w are w h ich w ill be 47µ 11 12
reverted to later. IC3 1 8
+5V 22Ω
R7 13 14
R10 15 16
The output of each of the DACs is a OE 5V 22Ω
R9
5 22Ω
pure current source. The type specified C10 C11
OSC C12 14
22Ω
R8

SG531P IC4
was chosen in view of its well-defined 6.144MHz 100n 7 IC4 = 74HCT32
10µ 63V 100n 4
voltage, good linearity, low noise, low
offset voltage an d h igh slew rate. It is
not cheap, but ideally suited to the pre-
sent application.
The analogue filter at the output is C89 C86
K13
n eed ed to rem ove th e resid u e of th e IC17
R58 7805
oversam p lin g p rod u cts an d th e r.f. 9V * B1 1Ω5
5V
R57
noise. It can be switched between two K12
3k9

cut-off frequencies to allow the use of C88 C87 C85 C84 C83 C82

the two highest sampling rates. D7

1000µ 100n 10µ 100n
4x 22n 25V 63V
Each filter section u ses a d ou ble- B80C1500 POWER

pole relay, since a single-pole type for

both channels would not give the req- K11
C81 C78
u isite ch an n el sep aration at h igh fre- 15V IC15
qu en cies. Th is is becau se th e RC sec- R55 7812
B2 3Ω3
tion s of th e filters h ave too h igh an 12V

impedance. 15V
C79
C76 C74 C72 C70 K10
C80
Sin ce th e ou tp u t im p ed an ce p er 1000µ 100n 10µ 100n
40V 63V
channel is only 100 Ω, a single double- 4x 22n

p ole relay is u sed at th e ou tp u t to B80C1500

C77 C75 C73 C71
switch the mute function on/off and to
1000µ 100n 10µ 100n
obviate switch-on noises. R56
40V 63V
12V
3Ω3
7912
CIRCUIT DESCRIPTION IC16
The circuit diagram of the Audio DAC
2000 is shown in Figure 2.
An im p ortan t task of th e circu it is Figure 2. Circuit diagram of
the decoding of the S/PDIF* data flow the Audio DAC 2000. The
in to a serial d ata form at th at can be The output of the IC dashed lines show how the however, possible to
used by the DACs, which is carried out is ap p lied to th e circuit is divided on to the use the coaxial input
by IC1. The circuit associated with this in p u t of IC 1 via four boards. as S/PDIF* ou tp u t.
ch ip is h ou sed on a d iscrete board so p oten tial d ivid er In th is case, th e ou t-
that the coaxial and optical input con- R1-R2, w h ose valu es p u t im p ed an ce an d
nectors can be placed in the most con- are ch osen su ch th at th e sign al across sign al levels are n o lon ger stan d ard ,
venient position on the enclosure. R1 is sligh tly larger (0.6 V) th an th e bu t th e latter m ay be in creased by
Th e in p u t im p ed an ce, w h ich h as stan d ard on e from th e coaxial in p u t sligh tly red u cin g th e valu e of resistor
th e trad ition al valu e of 75 Ω as far as (0.5 V). Th e 0.1 µF cou p lin g cap acitor R2. In fact, the level of the input signal
the coaxial input is concerned, is deter- p reven ts an y d .c. on th e in p u t from across R1 m ay be as h igh as 1 Vp -p
mined by resistor R1. reaching the receiver. without any problems.
Th e op tical in p u t is p rovid ed by Wh en th e op tical in p u t is u sed , The IC uses a number of frequency
IC2, which is a stand ard chip used for ju m p er JP 1 m u st be sh orted , an d th e sensors to ensure that the PLL locks as
this purpose in consumer equipment. coaxial input cannot be used. It is then, rap id ly as p ossible to th e in com in g

60 Elektor Electronics 11/99

 IC13
12V LM317 5VA

R51
K4 LD2 LD1

249Ω
R18 3 8 8 3 R11
1 2 7 a CA CA
820Ω CA CA a 7 820Ω D5
3 4 6 6 C68 C66 C62 C60
820Ω b b 820Ω 12V
5 6 4 4 K9 R52
820Ω c c 820Ω C64
100µ 100n 10µ

750Ω
7 8 2 2 100n 5V6
820Ω d d 820Ω 25V 63V
9 10 1 1 1W3
820Ω e e 820Ω 10µ 63V
10 10
820Ω f f 820Ω
9 9 R54
820Ω g dp dp g 820Ω C65

750Ω
R24 5 5 R17
2x D6
C69 C67 C63 C61
10µ 63V
HDN1075
12V 100µ 100n R53 10µ
25V 63V 100n 5V6
1W3

249Ω
LM337 5VA
12V
IC14
2x C18 C19 C22
5VD 4µ7 R27 R28 R29
63V C25
100µ 3k57 4k12 3k92 12V
5VA 25V 47p
R25 C48
6 11 C27 C28 C29
C16 C17 2k49
+VDD +VCC
2 12 100n
BCLK BPO DC 12V 2n2 4n7 330p
10µ 63V 100n 7
5VD WCLK IC7 C23 C46
5VD 1 19 1 G
DATA REF DC 2 7
R40 K6 L
K5 100n 5
PCM1704 C24 6
22 S3 9 17 C31 IC10 100Ω
2 1 DBW 20BIT SERVO DC 3
10 Re2
4 3 15 19 INVERT 2x 47µ 1 4
MUTE OW0 7 1n5
14 25V 2
6 5 16 20 IOUT R30 R31 R32
DEM OW1 5 15
5
6 OPA627
8 7 14 4 DGND AGND IC9 3k57 3k65 3k32
RST IW0 16 3
10 9 6 IC6 5 AGND C49
XTI IW1 4 C30 C32 R39
12 11 1 3 –VDD –VCC
DIN I2S

1M
14 13 28 17 4 20 OPA627 100n
LRCIN SF0 1n 270p
Re1
16 15 2 18 5VA 12V
BCKIN SF1 C20 C21 C47
9 27 2x
CLKO SRO 4µ7
7 DF1704 21 63V VDBW
XTO 100n
13 26
ML/RESV BCKO C39 C40 C43 12V
12 25 2x
MC/LRIP WCKO 4µ7 R33 R34 R35
11 24 63V C26
MD/CKO DOL 100µ 3k57 4k12 3k92 12V
10 23 5VA 25V 47p
MODE DOR R26 C52
6 11 C33 C34 C35
S2 2k49
+VDD +VCC
8 S4 100n
2 12
BCLK BPO DC 12V 2n2 4n7 330p VMUTE
7
WCLK IC8 C44 C50
1 19 1 D
DATA REF DC 2 7
R42 K6 R
100n 5
PCM1704 C45 6
9 17 C37 IC12 100Ω
20BIT SERVO DC 3
10 Re3
INVERT 2x 47µ 1 4
7 1n5
14 25V 2
IOUT R36 R37 R38
5VA 5 15
5
6 OPA627
DGND AGND IC11 3k57 3k65 3k32
16 3
AGND C53
4 C36 C38 R41
–VDD –VCC
1M

4 20 OPA627 100n
1n 270p
5VA 12V
C41 C42 C51
2x
4µ7
63V VDBW
100n
12V

DBW DBW'
MUTE MUTE'

12V 12V
R43 R46 R47 R50
D1
150k

10Ω

150k

4Ω7

D2 VMUTE D3 VDBW * zie tekst 5VD

1N4001
R44 R48 * see text
5V
1N4148 1N4148
* siehe Text K8
150k

150k

T1 T2
C54 C55 C56 C57
* voir texte C58 C59
D4

47µ 220µ 1µ 470µ

1M

1M

25V BC517 25V 63V BC517 25V 100µ

25V 100n 5V6
R45 R49 JP2 * 1W3 JP3 *

990059 - 12

d ata flow. In th e absen ce of an in p u t rate, Fs, or twice that rate. m od e p in s M 0–M 3. Details of th is can
sign al, th e frequ en cy of th e voltage- Serial clock SCK is needed for clock- be fou n d in th e CS8414 d ata sh eets
controlled oscillator (VCO ) is low. in g th e in d ivid u al bits an d is equ al to elsewhere in this issue.
The digital filter on the DAC board 64Fs. The recommended mode is the I2S
needs four signals, all derived from the MCK, a clock equal to 256Fs,which mod e, since in this the number of bits
in comin g S/PDIF d ata by th e receiver is needed for oversampling and inter- is basically n ot fixed : it m ay be 16-bit
chip: p olation . Resistors R7–R10 lim it an y data or 24-bit. Because of this, the pre-
SDATA con tain s th e serial d ata of ringing caused by the capacitive loads ferred settin g of DIP sw itch S1 is S1–4
both channels. formed by the flatcable and the digital O N (M 1 = 1) an d th e rem ain d er O FF
PSYN C is th e lefth an d /righ th an d filter. (M 0 = M 2 = M 3 = 0). N ote th at on th e
clock to sep arate th e sam p les for th e These four signals can be provided switch M0–M3 are mixed up but on the
two channels. Depending on the mode by the receiver in various standard for- board the relevant names are adjacent
of operation, it is equal to the sampling m ats: w h ich on e is d eterm in ed by to them (as is the level at ON or OFF).
Other formats are often just as they

Elektor Electronics 11/99 61

 9 6 k Hz Di g i t a l A u d i o status output bits (pins 2–6 and 27) by
lin kin g th ese to select p in SEL. Wh en
SEL is low, th e Error Con d ition (n ot
Re ce i v e r Ty p e CS8 4 14 u sed ) an d Frequ en cy Rep ortin g Bits
are ap p lied to th e ou tp u ts, w h ich are
The Type CS8414 is an upgraded version of Digital Audio Receiver Type th en called E0–E2 an d F0–F2 resp ec-
CS8412, which has been used in several past articles published in this mag- tively. When SEL is high, the Channel
azine. It is pin-compatible with its predecessor, but is available in a 28-pin SOIC Statu s is ap p lied to th e relevan t ou t-
(standard SMD) case only. A data sheet of it can be found elsewhere in this puts in the shape of some status chan-
issue. n el bits, w h ereu p on th e ou tp u ts are
called C0 and Ca –Ce. O f these, only Cc
(F0) is used, which is channel status bit
C 3. In fact, th is is th e em p h asis bit of
CS8414 the channel status. It is inverted by the
VD+ DGND VA+ FILT AGND M3 M2 M1 M0
7 8 22 20 21
MCK
19 17 18 24 23
GAL and retained via a register output,
which therefore retains the actual level
and does not follow SEL. The CBL out-
26 SDATA
Audio 12 SCK
p u t is th erefore lin ked to an in p u t of
Serial Port
RXP 9
RS422 11 FSYNC the GAL to demultiplex the data.
Clock and Data De-MUX
RXN 10
Receiver Recovery
1 C
Wh en SEL is low, bits F0–F2 are
Registers 14 U recoded to six register outputs to drive
MUX MUX 28 VERF a 2-digit LED display. Various segments
of the display are already combined so
13 16 6 5 4 3 2 27 25 15 that, without the need of multiplexing,
CS12/ SEL C0/ Ca/ Cb/ Cc/ Cd/ Ce/ ERF CBL
FCK E0 E1 E2 F0 F1 F2 990059 - 13 only six outputs are needed to display
th e five sam p lin g frequ en cies on tw o
7-segment displays (7 mm types). The
The most notable difference between the two devices is that the range of on ly com p rom ise is th at an y valu e
sampling rates available with the CS8414 has been extended to 96 kHz. The fre- after the decimal point (rate in kHz) is
quency indication with 400 ppm accuracy of the CS8412 has been sacrificed omitted.
in favour of the 88.2 kHz and 96 kHz rates in the new device. The six outputs, + 5 V, and earth, are
Clock detection is carried out by a 2nd-order loop filter via a phase-locked lin ked to th e d isp lay board via K2, a
loop (PLL). In the CS8414 the design of the external RO-filter is slightly differ- 10-core flatcable, and a 10-pin connec-
ent than with the CS8412. tor. O w in g to its h eigh t an d location
The input of the CS8414 is an RS422 receiver that can handle differential beh in d th e fron t p an el, a box h ead er
cannot be used on this board.
(symmetric) as well as asymmetric (single-ended) signals. In the Audio
When ERF is active, all display out-
DAC2000 the input is configured for decoding single-ended signals only: input
p u ts are h igh an d on ly tw o d ash es
RXN is therefore bypassed to earth.
(hyphens) light. Both g-segment LEDs
To ensure optimum operation of the phase detector in the internal PLL, the are permanently linked to earth via R17
input is based on a 50 mV Schmitt trigger. an d R24 resp ectively an d th erefore
ligh t p erm an en tly as lon g as th ere is
supply voltage.
The SCK clock (pin 1 of the GAL) is
used to clock all register outputs.
are n am ed , for in stan ce, ‘MSB first require four additional inputs and four The information on the actual sam-
right justified’, whereby the location of outputs. p lin g rate is u sed n ot on ly for d rivin g
th e least sign ifican t bit (LSB) is fixed The IC is reset when all mode pins th e frequ en cy d isp lay, bu t also for
with respect to the L/R clock. The result are made high, which is the reason that switching the cut-off frequency of the
of this is that some most significant bits th e DIP sw itch is lin ked to th e m od e an alogu e ou tp u t filter to a h igh er
(MSBs) m ay be m issin g. In th e I2S in p u t via th e O R gates. Th e reset valu e. Th at is, ou tp u t DBW (d ou ble
mode, the location of the MSB is fixed, p rop er, w h ich is also ap p lied to th e ban d w id th ) goes h igh w h en a rate of
so th at, assu min g th ere are more bits, digital filter on the DAC board via the 88.2 kHz or 96 kHz is detected.
only some LSBs may be 0. Some of the GAL, is provided by network R6-C13. De-em p h asis ou tp u t DEEM is
other formats are fully compatible with Th e referen ce frequ en cy of ap p lied to th e d igital filter on ly. An
the Burr Brown digital filter, but that is 6.144 MHz which the receiver needs to indication of this is purposely not pro-
left to the reader to sort out if he/she so d eterm in e th e sam p lin g rate is p ro- vided since CDs with pre-emphasis are
wishes. vided by crystal oscillator IC3. The out- very rare in d eed . H ow ever, sin ce th e
The various modes have been made put pin of this IC is located very close facility is there, it is used in the Aud io
p resettable on p u rp ose in view of to th e relevan t in p u t (FCK) of IC 1 to DAC 2000 for correctin g an y p re-
future extension/expansion/upgrade or m in im ize th e n oise level of th e clock emphasis, particularly so since there is
oth er ap p lication s. It also en ables th e signal. The supply lines are well decou- now no need for an additional RC net-
receiver board to be u sed w ith oth er pled by network L3-C10-C11. work in the analogue output output fil-
aud io DACs. This board therefore has Th e su p p ly lin es to all ICs are ter (both channels).
an extra + 5 V terminal: the 5 V line is decoupled effectively: those to the ana- [990059]
linked to it from the DAC board via K3. logue and d igital sections of IC1 sepa-
Th e m an u factu rers recom m en d rately. Next month’s instalment describes the
resettin g th e IC im m ed iately after a Ch an n el statu s ou tp u t C, User bit DAC board with particular emphasis on
power up, for which purpose a circuit output U, and Validity and ERror Flag the digital filter and the DACs.
with four OR gates contained in IC4 is VERF are not used.
u sed . Th is circu it can n ot be p rovid ed Th e Ch an n el statu s BLock (CBL)
in th e GAL u sed , sin ce th is w ou ld start is used to demultiplex the channel

62 Elektor Electronics 11/99

electronics on-line
on line
modifying DVD players
how to change region codes
As a kind of sequel to
last month’s edition of
‘electronics on-line’
we have located a
number of websites
covering the ‘hot’
subject of how to
modify the region
code setting of con-
sumer-market DVD
players.

The DVD (digital video disc) seems

poised for a commercial breakthrough,
and sales volumes of consumer DVD
players rise accordingly. Unfortunately,
under considerable pressure of the
almighty film industry, DVD hardware
manufacturers are forced to fit their
products with a restriction that allows
a DVD to be played in a certain region
only.
This has been achieved by dividing
the world into six regions. Europe and
Japan, for example, represent region 2,
while the U S of A are region 1. A DVD
player bought in a European country
will refuse to play a DVD bought in the
USA and having region code 1. This is
particularly bad and disappointing for executed by the processor inside the found at
film fans, because they have to wait for DVD) and tell you which bits have to http://www.dvdutils.com/homedvd.htm
a film to be DVD-released in Europe, be modified. Clear photographs show, for example,
while the American version has been A good starting point with a gener- where to remove resistors from circuit
available for some time already. ous overview is offered by Data Test- boards, or connect extra cables.
Of course, some whiz kids came up lab at There’s even a special website ded-
with solutions to this problem. Most http://www2.datatestlab.com/region- icated to converting Sony players only:
DVD players are designed and built in hacks/regionhacks_players.htm the Sony DVD codefree site at
a way that enables the manufacturer to On this site you will find a series of http://members.xoom.com/sonydvd/
easily adapt each basic version for a brands and types as well as links to If you want more background
particular region code. In most coun- many other sites including Planet information on this subject, take a look
tries companies exist offering so-called DVD at at Eric Smith’s DVD Information
‘region-free’ DVD players, or an http://www.planet-dvd.ch/ pages, they may be found at
upgrade to your existing player for CineHome at http://www.brouhaha.com/~eric/video/dvd/
around 100 pounds. http://www.cinehome.de/ Adapting your DVD player for
The Internet is not only a vast and the French-language Dézonage at compatibility with a certain region
resource for addresses of these compa- http://perso.club-internet.fr/hitcher/ code is not illegal as long it is for pri-
nies, but also for do-it-yourself modifi- dezone.html vate and personal use. Be warned,
cation documents. Some of the most Another site with extensive informa- however, that any modification to the
ingenious hacks consist of modifica- tion on converting certain players goes hardware may void your warranty.
tions to the firmware (i.e., the program by the name of DVD-utils and may be (995086-1)

64 Elektor Electronics 11/99

Elektor Electronics

CS8414 CS8414

Integrated circuits Integrated circuits

Special Function, AF Special Function, AF
D ATA S H E E T 1 1 /9 9 D ATA S H E E T 1 1 /9 9
SEL is high. Channel status information is displayed for the bringing SEL low. A proper clock on FCK must be input for at
CS8414
channel selected by CS12. C0, which is channel status bit 0, least two thirds of a channel status block for these pins to be Normal Audio Port modes (M3 = 0)
96 kHz Digital Audio Receiver
defines professional (C0= 0)or consumer (C0= 1) mode and valid. They are updated three times per block, starting at the
M2 M1 M0 Format
further controls the definition of the Ca-Ce pins. These pins block boundary. These pins are invalid when the PLL is out
Manufacturer
are updated with the rising edge of CBL. of lock. 0 0 0 0 – Out, L/R, 16-24 Bits
CS12 Channel Select, pin 13
0 0 1 1 – In, L/R, 16-24 Bits
This pin is also dual function and is selected by bringing SEL ERF Error Flag, pin 25
11/99

high. CS12 selects sub-frame 1 (when low) or sub-frame 2
(when high) to be displayed by channel status pins C0 and
Ca through Ce
FCK Frequency Clock, pin 13
Frequency clock input that is enabled by bringing SEL low.
FCK is compared to the received clock frequency with the
value displayed on F2 through F0. Nominal input value is
6.144 MHz.
E0, E1, E2 Error Condition, pins 4-6
Encoded error information that is enabled by bringing SEL
low. The error codes are prioritized and latched so that the
error code displayed is the highest level of error since the
last clearing of the error pins. Clearing is accomplished by
bringing SEL high for more than 8 MCK cycles.
F0, F1, F2 Frequency Reporting Bits, pins 2-3, 27
Encoded sample frequency information that is enabled by
65
Signals that an error has occurred while receiving the audio 0 1 0 2 – Out, L/R, I2S Compatible
sample currently being read from the serial port. Three errors
0 1 1 3 – In, L/R, I2S Compatible
cause ERF to go high: a parity or biphase coding violation
Cirrus Logic, Inc., Crystal Semiconductor Division,
during the current sample, or an out of lock PLL receiver. 1 0 0 4 – Out, WSYNC, 16-24 bits
P.O. Box 17847, Austin, Texas 78760, U.S.A.
Tel. (512) 445 7222, fax (512) 445 7581. 1 0 1 5 – Out, L/R, 16 Bits LSBJ
Receiver interface
Internet: http://www.crystal.com
RXP, RXN Differential Line Receivers, pins 9, 10 1 1 0 6 – Out, L/R, 18 Bits LSBJ
RS422 compatible line receivers.
Features 1 1 1 7 – Out, L/R, MSB Last
➧ Sample rates to > 100 kHz
Phase Locked Loop
➧ Low-Jitter, On-Chip Clock recovery
MCK Master Clock, pin 19 bits. The CS8414 does not need a microprocessor to
➧ 256xFs Output clock Provided
Low jitter clock output of 256 times the received sample fre- handle the non-audio data (although a micro may be
➧ Supports: AES/EBU, IEC 958, S/PDIF, & EIAJ
quency. used with the C and U ports). Instead, dedicated pins
➧ CP340/1201 Professional and Consumer Formats
FILT Filter, pin 20 are available for the most important channel status
➧ Extensive Error Reporting
An external 470Ω resistor and 0.068µF capacitor is required bits. The CS8414 is a monolithic CMOS circuit that
➧ Repeat Last Sample on Error Option
from FILT input to analog ground. receives and decodes digital audio data which was
➧ On-Chip RS422 Line Receiver
encoded according to the digital audio interface stan-
➧ Pin Compatible with CS8411 and CS8412
dards. It contains an RS422 line receiver and clock
and data recovery utilizing an on-chip phase-locked
Ordering information
loop. The audio data is output through a configurable
CS8414-CS 0º to 70º C 28-pin plastic SOIC
serial port that supports 14 formats. The channel sta-
tus and user data have their own serial pins and the
Application example
Audio DAC 2000,
Special Audio port Modes (M3= 1)

Elektor Electronics November 1999.

M2 M1 M0 Format

Description 0 0 0 8 – Format 0 – No repeat on error

The CS8414 is a monolithic CMOS device which 0 0 1 9 – Format 1 – No repeat on error
receives and decodes audio data up to 96 kHz
0 1 0 10 – Format 2 – No repeat on error
according to the AES/EBU, IEC958, S/PDIF and EIAJ
CP340/1201 interface standards. The CS8414 0 1 1 11 – Format 0 – Async. SCK input
receives data from a transmission line, recovers the
clock and synchronization signals, and demultiplexes 1 0 0 12 – Received NRZ Data
the audio and digital data. Differential and single- 1 0 1 13 – Received Bi-phase Data
ended inputs can be decoded.
The CS8414 de-multiplexes the channel, user and 1 1 0 14 - Reserved
validity data directly to serial output pins with dedicat- 1 1 1 15 – CS8414 Reset
ed output pins for the most important channel status
CS8414 Block Diagram.
✃
 CS8414 CS8414

11/99
Integrated circuits Integrated circuits
Special Function, AF Special Function, AF
D ATA S H E E T 1 1 /9 9 D ATA S H E E T 1 1 /9 9
validity flag is OR’ed with the ERF flag to provide a mat is based on M0, M1, M2 and M3 pins. Absolute maximum ratings (GND = 0V, all voltages with respect to ground)
single pin, VERF, indicating that the audio data may SDATA Serial Data, pin 26
not be valid. This pin may be used by interpolation fil- Audio data serial input pin Parameters Symbol Min. Max. Unit
ters that provide error correction. M0, M1, M2, M3 Serial Port Mode Select, pins 23, 24, 18, 17
Power Supply Voltage VD+ , VA+ - 6.0 V
Selects the format of FSYNC and the sample edge of SCK

Elektor Electronics
with respect to SDATA. M3 selects between eight normal Input Current, Any Pin Except Supply (Note 1) Iin - ±10 mA
Pin descriptions modes (M3= 0), and six special modes (M3= 1).
Input Voltage, Any Pin Except RXP, RXN VIN –0.3 (VD+ ) + 0.3 mA

Power Supply Connections Control Pins Input Voltage, RXP and RXN VIN –12 12 V
VD+ Positive Digital Power, pin 7 VERF Validity + Error Flag, pin 28
Storage Temperature Tstg –65 150 ºC
Positive supply for the digital section. Nominally + 5 volts. A logical OR’ing of the validity bit from the received data and
VA+ Positive Analog Power, pin 22 the error flag. May be used by interpolation filters to interpo- Notes: 1. Transient currents of up to 100 mA will not cause SCR latch-up
Positive supply for the analog section. Nominally + 5 volts. late through errors.
DGND Digital Ground, pin 18 U User bit, pin 14
Ground for the digital section. DGND should be connected to Received user bit serial output port. FSYNC may be used to Recommended operating conditions (GND = 0V, all voltages with respect to ground)
the same ground as AGND. latch this bit externally. (Except in I2S modes when this pin is
Parameters Symbol Min. Typ. Max. Unit
AGND Analog Ground, pin 21 updated on the active edge of FSYNC).
Ground for the analog section. AGND should be connected to C Channel Status Output, pin 1 Power Supply Voltage VD+ , VA+ 4.75 5.0 5.25 V
the same ground as DGND. Received channel status bit serial output port. FSYNC may
Supply Current VA+ IA - 20 30 mA
be used to latch this bit externally. (Except in I2S modes
Audio Output Interface when this pin is updated on the active edge of FSYNC). Supply Current VD+ ID - 20 30 mA
SCK Serial Clock, pin 12 CBL Channel Status Block Start, pin 15
The channel status block output is high for the first four Ambient Operating Temperature: (note 2) TA 0 25 70 ºC
Serial clock for SDATA pin which can be configured (via the
M0, M1, M2 and M3 pins) as an input or output, and can bytes of channel status and low for the last 20 bytes. Power Consumption PD - 175 315 mW
sample data on the rising and falling edge. As an output, SEL Select, pin 16
Control pin that selects either channel status information Notes: 2. The -CS parts are specified to operate over 0 to 70ºC but are tested at 25ºC only.
SCK will generate 32 clocks for every audio sample. As an
input, 32 SCK periods per audio sample must be provided in (SEL = 1) or error and frequency information (SEL = 0) to
all normal modes. be displayed on six of the following pins.
Digital characteristics (TA = 25ºC; VD+ , VA+ = 5V ±5%)
FSYNC Frame Sync, pin 11 C0, Ca, Cb, Cc, Cd, Ce Channel Status Output Bits,
Delineates the serial data and may indicate the particular pins 2-6, 27 Parameters Symbol Min. Typ. Max. Unit
channel, left or right, and may be an input or output. The for- These pins are dual function with the ‘C’ bits selected when
High-Level Input Voltage, except RXP, RXN VIH 2.0 - - V

Low-Level Input Voltage, except RXP, RXN VIL - - + 0.4 V

66
High-Level Output Voltage (IO = 200µA) VOH (VD+ ) – 1.0 - - V

Low-level Output Voltage (IO = –3.2mA) VOL - - 0.5 V

Input Leakage Current Iin 0 1.0 10 µA

Input Sample frequency (Note 3) FS 28.4 - 100 kHz

Master Clock Frequency (Note 3) MCK 7.28 256xFS 25.6 MHz

MCK Clock Jitter tj - 200 psRMS

MCK Duty Cycle (high time/cycle time) - 50 - %

Notes: 3. FS is defined as the incoming audio sample frequency per channel.

CS8414 Pinout.
✃
The mic rologger presented here is remarkable bec ause this devic e, no bigger
than a matc hbox, is a data logger and voltmeter that c an operate fully on its
own. In addition, it has an RS232 port for c onnec tion to the COM port of a PC.
Commands to be exec uted by the mic rologger’s built-in c ommand proc essor
c an be entered via the keyboard of the PC, and the measurement result is dis-
played on the sc reen of the monitor. After being c onfigured via the PC, the
mic rologger c an be disc onnec ted and used stand-alone. It c an store up to 82
10-bit measurement values
in EEPROM. Stored mea-
surements are saved even
when the power is
switc hed off. After the
mic rologger has again
been c onnec ted to the
PC, the measurement
data c an be uploaded
and c onverted into a
graphic display, using a
spreadsheet program suc h
as KyPlot.

De sig n b y B. Stuurm a n

m i cr o d a t a l o g g e r
f o r u s e w i t h a P C a n d s t a n d -a l o n e
Micrologger specifications
● operates as a standalone data logger and ‘single-stepper’ with data Its sma ll d imensions a nd sta nd -a lone
postproc essing on a PC, as well as a PC voltmeter/datalogger and op era tion c a p a b ility ma ke the
‘single-stepper’ mic rologger an outstanding c hoic e for
● non-volatile memory for 82 3-digit samples
‘remote’ measurements. For example,
it c ould b e used to mea sure the volt-
● sampling delay adjustable from 1 sec ond to 15:59:59 h:m:s
a g e a nd c urrent c onsump tion of the
● maximum measurement session duration approximately 1300 hours
motor of an elec tric ally driven model,
● RS232 interfac e; protoc ol 38400 (19200), 7, n, 2
to a llow the d rive c omp onents to b e
● sc reen update rate 3x per sec ond
op timized . Ama teur meteorolog ists
● range basic ac c urac y c ould c ollec t mea surements over a
0 to 2.49 V ±(0.5%, 1 d) long p eriod of time without ha ving to
2.5 to 9.99 V ±(0.5%, 3 d) b e p ersona lly p resent. Two d a ta log -
10.0 to 99.9 V ±(0.5%, 2 d) g ers c ould b e c a rried a loft b y a
● input impedanc e: approx. 500 kΩ wea ther b a lloon, one to mea sure the
● power supply: 9-V battery temperature and the other to measure
● c urrent c onsumption: 4.6 mA (LEDs on); 2.8 mA (LEDs off) the a ltitud e. In p hysic s exerc ises in
● dimensions (exc lusive of protruding c onnec tor pins): 64×36×15 mm (l × whic h severa l tea ms ta ke mea sure-
w × h) ments, eac h team c ould be provided
● weight without battery: approx. 30 g with a mic rologger to store their data.
The advantage of this approac h is that

2 - 11/99 Elektor Elec tronic s EXTRA ——————————————— PC TOPICS

an expensive c ollec tion of instruments
is not needed to perform the measure-
ments, and at the same time all mea-
surements are registered by team and
c an be subsequently proc essed.
When the mic rologger is c onnec ted to
a PC, the c omma nd ‘volt’ c a uses the
value of the ac tual voltage to be sent
to the PC three times p er sec ond , via
the RS232 interfa c e. The PC sc reen
a c ts a s the d isp la y, a nd if a ‘full-
sc reen’ c harac ter size is used, the dis-
p la y c a n b e rea d a t a d ista nc e of
several metres.
An introduction
Figure 1 shows the c omp lete
sc hema tic of the mic rolog g er. At its
hea rt is a n ST62T60, a p owerful 8-b it
mic roc ontroller from SGS-Thomson. The
following p erip hera l c omp onents a re
connected to the core of the controller
via an internal serial data bus:
• a normal timer,
• a timer with a pulse-width modulated
(PWM) output,
• a watc hdog timer,
• an 8-bit A/D c onverter,
• a seria l interfa c e (Seria l Perip hera l
Interfac e, or SPI),
• 128 b ytes of nonvola tile memory
(EEPROM).
The normal timer is always ac tive and
looks after the timing of several differ-
Figure 1. A m ic roc ontroller, a n op a m p a nd a ha nd ful of c om p onents a re a ll you need to b uild a m ini PC d a ta logger a nd voltm eter.
PC TOPICS ——————————————
ent software processes. This takes place
in the interrup t routine b y mea ns of
timer flags. Sinc e this timer is also used
to g enera te the sec ond s fla g , it is
a lwa ys loa d ed with a fixed va lue tha t
yields a ‘nearly perfec t’ sec onds c loc k
after some further division.
The PWM timer is used to g enera te a
p ulse wa veform sig na l (on the ARTIM
output). The average value of this sig-
nal is used to inc rease the resolution of
the 8-bit A/D c onverter to 10 bits. We’ll
say more about this shortly.
The wa tc hd og timer is used for seria l
I/O timing , to free up the other timers.
This is p ossib le sinc e the wa tc hd og
timer c an be ac tivated under software
c ontrol. Exc ep t for this timer a nd the
SPI, no ha rd wa re is used for the b a sic
I/O func tion.
The 8-bit A/D converter is naturally used
for volta g e mea surements. To b e p re-
cise, the voltage on the analogue input
(Ain) is mea sured 64 times for ea c h
sa mp le, a nd the result is then d ivid ed
by 64. The range of the A/D c onverter
is from 00H to FFH. The first of these val-
ues will be measured if the voltage on
Ain is eq ua l to the volta g e on the Vss
pin (0V), and the sec ond value will be
measured if the voltage on Ain is equal
to volta g e on the Vd d p in (+ 5V). The
a c c ura c y of the mic rolog g er is thus
direc tly related to the ac c urac y of the
sup p ly volta g e (Vd d ). For this rea son,
a n LP2950CZ5.0 ha s b een c hosen for
Elektor Elec tronic s EXTRA
the voltage regulator. Not only is this a
low-d rop reg ula tor, it is a lso rec om-
mend ed a s a referenc e sourc e b y its
manufac turer!
Current sourc ing or sinking b y other
c omp onents in the c irc uit c a n a ffec t
the conversion, due to voltage drops in
the wiring. For this reason, the LEDs are
switc hed off while a mea surement is
being made. This produc es a c harac -
teristic blinking effec t.
The serial interfac e serves for c ommu-
nication with a PC. It allows commands
to be sent to the micrologger, and data
to be sent from the mic rologger to the
PC. The mic rolog g er c onta ins a true
intera c tive c omma nd p roc essor. Of
c ourse, a terminal emulator program,
suc h a s Hyp erTermina l (sup p lied with
Windows), must be present on the PC.
The 128-b yte EEPROM is used to store
various settings, including the sampling
d ela y p a ra meter, a nd it a lso inc lud es
room for 82 11-b it sa mp le va lues (10
d a ta b its a nd a d ec ima l p oint). The
sa mp les a re written in a n enc od ed
form, with two samples stored in every
three b ytes of memory to ma ke the
best use of the available c apac ity.
More details
The RS232 interface
The ability to communicate with a PC via
the RS232 interfac e is vitally important
for this application. However, this creates
3 - 11/99

Figure 2. Using a n op a m p a s a n a d d er
a m p lifier to inc rea se the resolution from
8 to 10 b its.
a problem, sinc e this c ommunic ation
must not be allowed to disturb the nor-
mal operation of the micrologger.
Usua lly, a n RS232 interfa c e is b uilt up
using software, in whic h the baud rate
is d etermined b y d ela y loop s, or with
the a id of timers. However, here the
timers are indispensable for other pur-
p oses, a nd the softwa re a p p roa c h is
only p ossib le for rela tively low b a ud
rates, whic h would not be appropriate
here. The only remaining possibility is to
use the SPI, whic h a fter a ll is a lrea d y
p resent. Ultima tely, it turns out tha t
RS232 c ommunic a tion c a n b e
achieved by using a 7-bit protocol
a nd look-up ta b les. During
normal operation, the SPI is set
up to rec eive d a ta . A sta rt b it
at Sin (see Figure 1) triggers the
SPI, whic h subsequently takes in
Micro-Logger
Figure 3. The c irc uit b oa rd la yout (sc a le 1:1) a nd c om p onent la yout of the m ic rologger (sc a le 2:1).
4 - 11/99 Elektor Elec tronic s EXTRA
the data all on its own. On c ompletion,
the SPI generates an interrupt, whic h is
used to set a flag. This flag is regularly
polled in the main program loop, which
c a n ta ke the nec essa ry a c tions if it is
set. The ha rd wa re for the RS232 inter-
fac e is minimal — two Sc hottky diodes
(for sp eed ) a nd one resistor. The only
thing that is nec essary is that the c on-
nec tion c a b le inc lud es a numb er of
c ross-c onnec tions tha t serve to ‘tric k’
the UART of the PC (see the Ja nua ry
1999 issue of Elektor for more informa-
tion). The maximum speed of the SPI is
very high, but due to the c loc k rate of
8MHz and the available predivider set-
ting s, only 38400 b a ud a nd 19200
b a ud a re a c tua lly p ossib le. The la tter
va lue c a n b e selec ted b y insta lling
jumper JP1.
From 8-bit to 10-bit ADC resolution
Although the resolution of the A/D c on-
verter of the ST62T60 is 8 bits, it is possi-
b le to inc rea se this resolution with a n
op a mp . The b a sic id ea , illustra ted in
Figure 2, comes from an ST application
handbook [1].
The op a mp is wired a s a noninverting
amplifier with negative feedbac k. Due
to the negative feedback and the high
gain of the opamp, the voltage at
the minus input will always
b e the sa me
IC2
P1
S1 C2
+ led 1
R2
C1
+9 V B1
CA3130E
0V
IC1
(in) R1 R3
(+9 V)
IN K1
hole C4
GND S2
P2
——————————————— PC TOPICS
as the voltage at the plus input. When
Vin reac hes a level that c auses the A/D
c onverter to produc e its maximum out-
p ut va lue, PB2 is set hig h. The resistor
va lues a re c hosen so tha t the outp ut
volta g e of the op a mp then g oes to
zero, which allows the voltage on Vin to
c ontinue to inc rease until the A/D c on-
verter again reac hes its maximum out-
put value. When this happens, PB1 is set
high and the opamp’s output voltage
again goes to zero. The measurement
range of the A/D c onverter is thus used
four times over, so that the resolution is
inc reased from 8 to 10 bits.
Now let’s return to Figure 1. The
CA3130 opamp has two spec ial prop-
erties, which are that its inputs can han-
d le volta g es d own to just b elow ea rth
level and that the output voltage range
extend s d own to the ea rth level. This
op a mp is c onnec ted d irec tly to the
+ 9V supply, so that its output has no dif-
fic ulty rea c hing 5V, whic h is the ma xi-
mum inp ut level of the A/D c onverter.
The PWM sig na l (ARTIM out) is c on-
nec ted to the minus inp ut of the
opamp via R5. There are four working
ra ng es: 0%, 25%, 50% a nd 100%. To
simplify the c alc ulations, the switc hing
points have been c hosen to oc c ur
at a value of 251 (FBH). The maxi-
mum value for eac h range is thus
250, and the total range is thus 0
– 1000. The softwa re tests for a
va lue of 1000 a nd , if this is
rea c hed , switc hes in a 10x
divider by setting PA1 low. For
volta g e rea d ing s und er
1000, P1 is c onfigured as a
‘floa ting ’ inp ut. The volt-
meter thus ha s two
RS232
GND
OUT
IN
k R8 R9 R10
K2 D2 C6 R11
C11
+ k + + +
led 2 led 3
R13
D3 JP1 C10
R6
B3
R4 R5 C5
B2 IC3-ST62T60BB6 B4
C3 R7
k
R12 D1
sounder
reggoL-orciM S3 X-tal
+ C9
C8 C7

ranges: 0.00 to 9.99V and 10.0 to
99.9 V.
A p ulse wa veform a t a round 31 kHz
from the ARTIM outp ut is injec ted into
the minus inp ut of the op a mp . Filter
c apac itors C3 and C5 are provided to
extract the average value of this signal.
The inp ut of the mic rolog g er is K1. In
a d d ition to the usua l IN a nd GND
inp uts, a d irec t inp ut (in) a nd the 9 V
sup p ly volta g e a re p resent a t K1. The
opamp c irc uit has a gain of around 9,
a nd a volta g e of a round 2.2 V on the
direc t input results in an output voltage
of 9.99 V. This means that an interfac e
c irc uit c a n b e c onnec ted to K1, for
example for making c urrent or temper-
ature measurements.
The LEDs and S1, S2 and S3
The LEDs ind ic a te the sta tus of the
mic rolog g er. If no sa mp les a re b eing
taken and the data memory is empty,
the g reen LED will b e on (Id le). If the
memory c onta ins sa mp le d a ta b ut is
not full, the yellow LED will be on (Busy).
When the memory is full, the red LED will
b e on (Full). The sta te of the LEDs is
stored in the EEPROM. If the mic rolog -
g er is switc hed on when the memory
already c ontains sample data, this will
COMPONENTS LIST
Resistors:
(All resistors 0.25 or 0.2 W)
R1 = 499kΩ 1%
R2 = 127kΩ 1%
R3 = 10.7kΩ 1%
R4,R5 = 49.9kΩ 1%
R6 = 200kΩ 1%
R7,R13 = 10kΩ
R8,R9,R10 = 1kΩ
R11 = 4.7kΩ
R12 = 100kΩ
P1 = 25kΩ preset, 6 mm, vertical
P2 = 2.5kΩ preset, 6 mm, vertical
Capacitors:
C1 = 47nF, MKT, raster 7.5mm
PC TOPICS ——————————————
on
power
start
INPUT
(clear)
Figure 4. Sa m p le front p a nel for the m ic rologger.
be indic ated by the
Busy or Full LED being
on. In this c ase, it is not possible to start
sampling or to single step the microlog-
ger. The memory must first be c leared.
S1 is the on/off switc h. If S2 is p ressed
while the Idle LED is on, the micrologger
sta rts c ollec ting d a ta a nd no long er
resp ond s to S2 or S3. If S3 is p ressed
while the Idle LED is on, the micrologger
takes a single sample of the actual volt-
a g e, a nd it no long er resp ond s to S2.
S3 ma y b e p ressed up to 82 times in
suc c ession.
If S2 is held pressed while the microlog-
ger is switc hed on with S1, the memory
is c lea red . If S3 is held p ressed while
the mic rologger is switc hed on with S1,
the LEDs are switc hed on or off. Switc h-
ing the LEDs off sub sta ntia lly red uc es
the c urrent c onsump tion of the
mic rolog g er. Althoug h this setting is
a lwa ys sa ved in the EEPROM, there is
one exc ep tion. If the LEDs ha ve b een
switc hed off a nd sa mp les a re c ol-
lec ted, the Full LED will be switc hed on
when the memory is full.
Signals
The mic rolog g er b eep s a fter ea c h
sa mp le ha s b een ta ken, a nd a fter 82
C2,C11 = 4.7µF 15V, tantalum
C3 = 10nF, MKT, raster 7.5mm
C4 = 470pF, polystyrene (Siemens)
C5 = 3.3nF, MKT, raster 7.5mm
C6,C10 = 100nF, raster 0.1”, multilayer
C7,C8 = 22pF, raster 0.1”, ceramic
C9 = 1µF 15V, tantalum
Semiconductors:
IC1 = CA3130E
IC2 = LP2950CZ5.0
IC3 = ST62T60BB6 (programmed, order
code 996518-1)
D1 = 1N4148
D2,D3 = BAT85
Led1 = LED 3 mm, high intensity, red
Led2 = LED 3 mm, high intensity, yellow
Led3 = LED 3 mm, high intensity, green
Elektor Elec tronic s EXTRA
RS232
PC
Micro-Logger
full busy idle
system
single step
(leds)
sounder
samples — that is, when the memory is
full — it beeps six times. If the memory
is partially or c ompletely filled and the
mic rolog g er is switc hed off a nd then
switc hed on a g a in, for exa mp le in
order to read out the sample data to a
PC, it will beep three times if you try to
start sampling or to operate it in single-
step mode (via the PC or using its push-
buttons). The same thing happens if a
‘step ’ c omma nd is issued via the PC
while the mic rolog g er is sa mp ling , or
vic e versa . A new sa mp ling or sing le-
step session c a n b e sta rted only a fter
the memory has been c leared.
If the mic rologger is operated interac -
tively with a PC, it b eep s onc e if it
rec eives a n inva lid inp ut. This c a n b e
a n inc orrec t c omma nd or a n inva lid
parameter.
Building the micrologger
Figure 3 shows the p rinted c irc uit
b oa rd a nd c omp onent la youts. Sta rt
with the four wire jump ers, a nd then
mount the rest of the components. K1 is
a male header with one more pin than
is needed. To prevent inc orrec t mating
of K1 with its ma tc hing c onnec tor,
remove the ‘extra’ pin at the indic ated
Miscellaneous:
S1 = 1-pole slide switch, 11 mm, PCB
mount (Knitter type MFP 120)
S2,S3 = pushbutton, square (D6)
X-tal = quartz crystal 8 MHz, HC-49/S
(height approx. 4 mm)
Snd = piëzo-ceramic buzzer, 14 mm diam.,
raster 7 mm
K1 = angled pinheader, SIL, 5 contacts
K1-contra = straight socket, SIL, 5 contacts
K2 = angled socket, , SIL, 4 contacts
K2-contra = straight pinheader, SIL, 4
contacts
JP1 = straight pinheader, 2 contacts
JP1-contra = jumper (shunt), 2.54 mm
B1-B4 = wire link
20-pin IC socket
Battery clip for 9-V PP3 battery
3.5”-floppy disk, contains project source-
code: order code 996026-1
5 - 11/99

1 see text
6
2 press ‘?’ and then Enter. The mic rolog-
7 g er will resp ond with a list of a ll a va il-
3 Sin
8 Sout
4 The delay time c an be set by entering
9 it following the ‘d ela y’ c omma nd . To
5 gnd
D-9 connector 4-way pinheader
female
992040 - 15
Figure 5. Ca b le for c onnec ting the m ic rologger to the RS232 p ort of a PC. The D-typ e
c onnec tor inc lud es severa l c ross c onnec tions to ‘tric k’ the UART.
loc ation and enlarge the hole using a nec ted either direc tly to the COM port
1.4-mm d rill. Then g lue a p in a t the or via a seria l extension c a b le, with a
sa me loc a tion on the ma tc hing c on- 25-wa y c onnec tor a t the PC end if
nec tor, using a sma ll d rop of c ra zy nec essary.
g lue. Now the c onnec tors c a n never The Hyp erTermina l p rog ra m c a n b e
be mated the wrong way around. used for c ommunic a tion with the PC.
Treat K2 and its matc hing c onnec tor in Start the program and selec t File/Prop-
the same manner. Finish off the leads of erties. Set Connec t to ‘Direc t to COMn’,
the ma tc hing c onnec tors with hea t- where n is numb er of the COM p ort
shrink tub ing to g ive a nea t a p p ea r- used . Now c hoose Config ure a nd
ance. Make sure that the flats of S2 and enter: 38400, 7, none, 2, flow control =
S3 fac e to the right. ‘Hardware’. Select the Settings tab card
Fina lly, you c a n c op y the front p a nel a nd set Emula tion = ‘Auto d etec t’.
layout in Figure 4, c ut it out and glue it Selec t ASCII Setup and make sure that
to a 1-mm thic k p iec e of ABS p la stic . only ‘Wrap lines’ is c hec ked.
After you ha ve ma d e the nec essa ry Sa ve this file on the d esktop a s Log -
openings, you c an attac h this panel to ger.ht, or with any other suitable name
the circuit board using standoffs and 2- (a s long a s it ha s the ‘.ht’ extension).
mm sc rews. Close HyperTerminal and then start it up
again, using the new ic on on the desk-
Software top. Only then will the new settings take
effec t!
Before the mic rolog g er c a n b e c on- If the mic rolog g er is not yet c on-
nec ted to the COM p ort of a PC, a nec ted to the PC, c onnec t it now and
cable must be constructed as shown in switc h it on.
Figure 5. The 9-way plug c an be c on- Tip: use only lower-c ase c harac ters for
Figure 6. The file c onta ining the m ea surem ent d a ta c a n b e loa d ed into KyPlot in ord er
to d irec tly c rea te a gra p hic d isp la y of the d a ta. Here you see a slow sa wtooth wa ve-
form p rod uc ed b y a func tion genera tor.
6 - 11/99 Elektor Elec tronic s EXTRA ——————————————— PC TOPICS
c ommunic ating with the mic rologger!
Press Enter. The mic rolog g er will b eep
a nd resp ond with ‘c omma nd ?’. Now
able c ommands.
see what the c urrent delay time setting
is (and its format), simply type ‘delay’.
The c ommands ‘delim(iter)’ and ‘d(ec i-
ma l)p (oint)’ c ha ng e the forma tting of
the export file.
The rema ining c omma nd s a re self-
exp la na tory, a lthoug h there’s one
ha nd y tip . If the ‘volt’ c omma nd is
ac tive, it c an be switc hed off by press-
ing the Esc a p e key. This c a n a lso b e
used to nullify a ny unintentiona lly
entered c ommand.
The sa mp le d a ta in the memory a re
exp orted in resp onse to ‘^ d ’ (Control
d). Before doing this, you c an prepare
a file to rec eive the data by selec ting
Tra nsfer a nd then ‘Ca p ture text’ in
Hyp erTermina l, a nd g iving the file a
na me with the extension ‘.txt’. The
exported data will then be directly writ-
ten to the specified file. Be sure to close
this file b efore issuing a ny new c om-
mands. Alternatively, the samples c an
b e selec ted on the sc reen a nd tra ns-
ferred via the c lip b oa rd to the
notepad, for example.
The file data c an be read direc tly into
the KyPlot spreadsheet program [2], so
tha t the d a ta c a n b e p resented in
graphic format.
Calibration
Ind ivid ua l exa mp les of the mic roc on-
troller show slight differenc es in behav-
iour which, small as they may be, make
it impossible to spec ify fixed values for
the breakpoints at 25%, 50% and 75%.
A simp le b ut effec tive solution to this
p rob lem is found b y inc lud ing c om-
ma nd s tha t a llow these va lues to b e
adjusted; these are the ‘inc ’ and ‘dec ’
c ommands. You will need a good DVM
and a variable power supply (0 to 15 V)
to perform the c alibration. If you have
ac c ess to an osc illosc ope, it’s a good
idea to c onnec t it to the ARTIM output
(pin 7). Using the oscilloscope, you can
rea d ily see where the b rea kp oints lie,
a nd it is thus ea sier to a d just them for
smooth transitions.
Connec t b oth the DVM a nd the
micrologger to the variable power sup-
ply, and adjust the voltage to approxi-
mately 2.00 V. Start HyperTerminal and
enter the c omma nd ‘volt’. Now a d just
P1 until the reading on the screen is the
same as that displayed by the DVM (tip:
selec t a fa irly la rg e c ha ra c ter size in
HyperTerminal, so it’s easy to read).
Now set the voltage to 4.00 V and use
the c omma nd s ‘d ec 0’ a nd ‘inc 0’ to
a d just the va lue d isp la yed on the
sc reen until it is as c lose as possible to
the DVM va lue. Dec rea se the volta g e
to a round 2.4V, inc rea se it very slowly
to 2.6V a nd then red uc e it a g a in to
2.4V. The c rossover a t the b rea kp oint
should be as smooth as possible.
Repeat this procedure with a voltage of
6.00 V and the commands ‘dec 1’ and
‘inc 1’ (breakpoint 5.0 V), and then with
8.00 V and the commands ‘dec 2’ and
‘inc 2’ (breakpoint 7.5 V).
Now a d just the volta g e so the va lue
d isp la yed on the sc reen jump s
between 9.99 V and some other value.
Ad just P2 so tha t the ‘other va lue’ is
10.0 V (and not 09.9 V).
This c ompletes the c alibration proc ess.
Conclusion
The a c c ura c y of the c loc k should b e
more tha n adequate in most c ases. It
c a n b e c hec ked b y setting the d ela y
time to one hour. Wait until the seconds
ha nd of your wa tc h rea c hes 12, a nd
start the micrologger. It will emit a beep
then, and every hour thereafter, up to
82 times. Each time a beep occurs, the
sec ond s ha nd of your wa tc h will ind i-
c ate the extent to whic h the mic rolog-
ger c loc k runs fast or slow. If nec essary,
the c loc k ra te c a n b e a d justed b y
exp erimenting with the va lues of C7
and C8.
The SPI is used for both rec eption and
transmission. When the ‘volt’ c ommand
is active, it can happen that SPI is trans-
mitting a t exa c tly the sa me time a s a
key is p ressed , in whic h c a se the key
c ode will be lost. If this happens, press
Enter a nd then enter the c omma nd
onc e again.
(990062)
Literature
[1] ST Applic ation Note AN420/0294,
‘Expanding A/D Resolution of the
ST6 A/D c onverter’.
[2] KyPlot http://www.qualest.c o.jp/
Download/KyPlot/kyplot_e.htm
(see Elektor Elec tronic s Marc h
1999 issue).

Anyone who c arries around every type of c onnec tion c able together with a lap-
top c omputer, often finds that the majority of the baggage is c ables instead of
the laptop itself. However, this size of this c able salad c an easily be minimized.
The standard c ables desc ribed here, together with a few gender c hangers, sup-
port all possible c onnec tions.
By H.-J. Bö hling

a ca b l e f o r a l l o cca s i o n s
co r r e ct co n n e ct i o n s f o r y o u r l a p t o p P C
Sub-D 9 Sub-D 25 Sub-D 25 Sub-D 25
You rea lly need a sort of Swiss a rmy
1 DCD 1 knife of the cable world to be prepared 1 1
6 DSR 14 14 14
2 RXD 2
for a ll ima g ina b le seria l a nd p a ra llel 2 2
7 RTS 15 c onnec tions. The set of c a b les a nd 15 15
3 TXD 3
a d a p ters d esc rib ed in this a rtic le will 3 3
8 CTS 16 16 16
4 DTR 4 ha nd le a ll p ossib le c omb ina tions of 4 4
9 RI 17 c onnec tions. The b a sic c a b le is a n 17 17
5 GND 5 5 5
18
extension c a b le for the p rinter p ort. If 18 18
6 you b uy this rea d y-ma d e, ma ke sure 6 6
19
that it inc ludes the full set of 25 leads, 19 19
7 7 7
20 c onnec ted one to one. This c a b le 20 20
8 should be as long as necessary, but no 8 8
21 21 21
9
longer than it has to be. 9 9
22 In addition, you need a set of adapters 22 22
10
that c onvert from 9-pin to 25-pin c on- 10 10
23 23 23
11
nec tors (and the other way around, of 11 11
24 course), and others that convert a plug 24 24
12
25
into a soc ket or a soc ket into a plug — 12 12
25 25
13 the so-c alled gender c hangers. These 13 13

992038 - 11 are c ommerc ially available in the form 992038 - 12

of a d a p ter c onnec tors, whic h to b e
Figure 1. 9-wa y to 25-wa y RS232 sure a re p ra c tic a l a nd lig ht, b ut they
a d a p ter. make for quite awkward and unreliable Figure 2. Null m od em a d a p ter.

PC TOPICS —————————————— Elektor Elec tronic s EXTRA 7 - 11/99

HyperTerminal, so it’s easy to read).
Now set the voltage to 4.00 V and use
the c omma nd s ‘d ec 0’ a nd ‘inc 0’ to
a d just the va lue d isp la yed on the
sc reen until it is as c lose as possible to
the DVM va lue. Dec rea se the volta g e
to a round 2.4V, inc rea se it very slowly
to 2.6V a nd then red uc e it a g a in to
2.4V. The c rossover a t the b rea kp oint
should be as smooth as possible.
Repeat this procedure with a voltage of
6.00 V and the commands ‘dec 1’ and
‘inc 1’ (breakpoint 5.0 V), and then with
8.00 V and the commands ‘dec 2’ and
‘inc 2’ (breakpoint 7.5 V).
Now a d just the volta g e so the va lue
d isp la yed on the sc reen jump s
between 9.99 V and some other value.
Ad just P2 so tha t the ‘other va lue’ is
10.0 V (and not 09.9 V).
This c ompletes the c alibration proc ess.
Conclusion
The a c c ura c y of the c loc k should b e
more tha n adequate in most c ases. It
c a n b e c hec ked b y setting the d ela y
time to one hour. Wait until the seconds
ha nd of your wa tc h rea c hes 12, a nd
start the micrologger. It will emit a beep
then, and every hour thereafter, up to
82 times. Each time a beep occurs, the
sec ond s ha nd of your wa tc h will ind i-
c ate the extent to whic h the mic rolog-
ger c loc k runs fast or slow. If nec essary,
the c loc k ra te c a n b e a d justed b y
exp erimenting with the va lues of C7
and C8.
The SPI is used for both rec eption and
transmission. When the ‘volt’ c ommand
is active, it can happen that SPI is trans-
mitting a t exa c tly the sa me time a s a
key is p ressed , in whic h c a se the key
c ode will be lost. If this happens, press
Enter a nd then enter the c omma nd
onc e again.
(990062)
Literature
[1] ST Applic ation Note AN420/0294,
‘Expanding A/D Resolution of the
ST6 A/D c onverter’.
[2] KyPlot http://www.qualest.c o.jp/
Download/KyPlot/kyplot_e.htm
(see Elektor Elec tronic s Marc h
1999 issue).

Anyone who c arries around every type of c onnec tion c able together with a lap-
top c omputer, often finds that the majority of the baggage is c ables instead of
the laptop itself. However, this size of this c able salad c an easily be minimized.
The standard c ables desc ribed here, together with a few gender c hangers, sup-
port all possible c onnec tions.
By H.-J. Bö hling

a ca b l e f o r a l l o cca s i o n s
co r r e ct co n n e ct i o n s f o r y o u r l a p t o p P C
Sub-D 9 Sub-D 25 Sub-D 25 Sub-D 25
You rea lly need a sort of Swiss a rmy
1 DCD 1 knife of the cable world to be prepared 1 1
6 DSR 14 14 14
2 RXD 2
for a ll ima g ina b le seria l a nd p a ra llel 2 2
7 RTS 15 c onnec tions. The set of c a b les a nd 15 15
3 TXD 3
a d a p ters d esc rib ed in this a rtic le will 3 3
8 CTS 16 16 16
4 DTR 4 ha nd le a ll p ossib le c omb ina tions of 4 4
9 RI 17 c onnec tions. The b a sic c a b le is a n 17 17
5 GND 5 5 5
18
extension c a b le for the p rinter p ort. If 18 18
6 you b uy this rea d y-ma d e, ma ke sure 6 6
19
that it inc ludes the full set of 25 leads, 19 19
7 7 7
20 c onnec ted one to one. This c a b le 20 20
8 should be as long as necessary, but no 8 8
21 21 21
9
longer than it has to be. 9 9
22 In addition, you need a set of adapters 22 22
10
that c onvert from 9-pin to 25-pin c on- 10 10
23 23 23
11
nec tors (and the other way around, of 11 11
24 course), and others that convert a plug 24 24
12
25
into a soc ket or a soc ket into a plug — 12 12
25 25
13 the so-c alled gender c hangers. These 13 13

992038 - 11 are c ommerc ially available in the form 992038 - 12

of a d a p ter c onnec tors, whic h to b e
Figure 1. 9-wa y to 25-wa y RS232 sure a re p ra c tic a l a nd lig ht, b ut they
a d a p ter. make for quite awkward and unreliable Figure 2. Null m od em a d a p ter.

PC TOPICS —————————————— Elektor Elec tronic s EXTRA 7 - 11/99

 Sub-D 25 Centronics ✗ c able, 25-way Sub-D plug to 25- Sub-D 25 Sub-D 25

1 1 19
way Sub-D soc ket, approx. 2 m, 25 1 1

14 leads 1:1; 14 14

2 2 20 ✗ c able, 9-way Sub-D plug to 25-way 2

15
2
15
15
Sub-D soc ket, approx. 20 c m, (Fig- 3 3
3 3 21
16 ure 1); 16 16
4 4
4 4 22 ✗ c able, 9-way Sub-D soc ket to 25- 17 17
17
way Sub-D plug, approx. 20 c m, 5 5
5 5 23 18 18
18
(Figure 1); 6 6
6 6 24 ✗ mini gender c hanger, 25-way Sub- 19 19
19 D soc ket/soc ket 7 7
7 7 25 20 20
20
✗ mini gender c hanger, 25-way Sub- 8 8

8 8 26 D plug/plug; 21 21

21 ✗ mini gender c hanger, 9-way Sub-D 9

22
9
22
9 9 27
22
soc ket/soc ket; 10 10

10 10 28 ✗ mini gender c hanger, 9-way Sub-D 23 23

11 11
23 plug/plug; 24 24
11 11 29
✗ mini gender c hanger, 25-way Sub- 12 12
24
12 12 30 D soc ket/plug, null modem (Figure 25 25
13 13
25 31 2);
992038 - 14
13 13
✗ gender c hanger, 25-way Sub-D
32
14
plug/Centronic s soc ket (Figure 3).
Figure 4. Interlink a d a p ter.
15 33
If you rea lly wa nt to b e p rep a red for
16 34
everything, you can also add a 25-way
sub-D jumper box to this list. Norton Comma nd er (V4.0 a nd V5.0)
17 35 The b est-known interc onnec tion a nd Wind ows 95 Direc t Ca b le Con-
36
18
method for transferring data between nec tion. The data transfer rate ranges
a la p top a nd a d esktop c omp uter is between 144 MB and 252 MB per hour,
992038 - 13 p rob a b ly DOS 6.x Interlink. Althoug h depending on the ac tual ports used. If
Interlink c an be used with a serial c on- you want to learn more on this subjec t,
nec tion, the ma ximum d a ta tra nsfer have a look at the artic le ‘A Simple PC
Figure 3. Centronic s a d a p ter. rate is only around 35 MB per hour. The Network’ in the PC Top ic s Sup p lement
d a ta tra nsfer ra te via a p a ra llel c on- of the Feb rua ry 1998 issue of Elektor
nec tion is sig nific a ntly hig her. If you Elec tronic s. Also, the LPT/COM tester to
c onnec tions when severa l a d a p ters wa nt to b e a b le to enjoy hig h-sp eed b e d esc rib ed in the Dec emb er 1999
have to be plugged together in series. d a ta tra nsfers, you should without fa il issue forms an ideal supplement to the
It is thus b etter to use short c a b les prepare an Interlink adapter as shown c able set, sinc e it allows you to ‘snoop’
(around 20 c m long) for these c onnec - in Figure 4, and fit it into an empty Sub- within the existing c onnec tions.
tions. D adapter housing. This adapter allows (992038-1)
The following is rec ommend ed a s a connections to be made using not only
basic set: Interlink und er DOS, b ut a lso La p link,

8 - 11/99 Elektor Elec tronic s EXTRA ——————————————— PC TOPICS

Having looked last month at the ways in which we
can design FPGAs, and coming down on the side of
VHDL as a design method, we need to see how we
can take our VHDL and turn it into a format we can
user to program a physical device. This involves a
number of steps from entering the design VHDL, turn-
ing it into a format our place and route software can
understand, and then turn that information into a bit-
stream which can be used to program the device.

By Gordon Pocock

Atmel FPGA design

course (2)
It may be useful to follow the design
flow by installing the IDS6.00 software
T ED which will be used to demonstrate the
EE M N
OU
design flow. Although there will not be
FR
R-M - R O room within this article to go through in

CO VE C D detail every step of the process, this is

all covered in the tutorial and docu-
mentation files on the CD-ROM.
To install IDS6.00, simply insert the CD-
ROM into your drive, and it should auto-
matically run the setup program which
will install the software. If the CD-ROM
What is on the CD-ROM? does not autoplay, select Run from the
Start menu, and enter:
The CD-ROM, presented free with this month’s issue of this magazine, has a number of util-
ities and tools for the design of FPGAs. Here is a list of the actual contents of this CD-ROM: D:\setup.exe

HDL Planner is a template generator and text editor for VHDL entry methods. HDL Planner Where D: is the drive letter of your CD
also integrates Atmel’s Macro Generator software and is especially useful to the new- ROM drive. Follow the on-screen
comer to VHDL. prompts to install IDS 6.00. When asked
Macro Generator software which allows the building of functional blocks which are fully which libraries to install, you should des-
specified and can be reused many times in one or several designs. elect the Viewlogic option. The Free
Place And Route routines which take the design files and actually perform the layout of System that you have been supplied
the design as implemented on the silicon. The Place and Route routines can also be
with uses the Everest Design System and
timing driven to improve design performance.
the libraries for this are installed by
Static timing analyser used to check path delays through a design.
Bitstream Generation and Download routines compatible with all configuration modes.
default. To run the Viewlogic system you
Everest VHDL Synthesis tool would need to purchase a license. If
All the items above are installed when you install the IDS6.0 CD. You can also select addi- there are any installation problems, the
tional libraries for other third party tools as listed below. process is covered in the documenta-
Libraries for the following Third Party Design Capture Systems: tion files on the CD-ROM. If you experi-
- Exemplar ence further problems, contact Kanda
- FpgaExpress Systems, details at the end of the arti-
- MTI cle.
- OrCad Assuming you have successfully
- Synplicity installed IDS 6.00, run the program by
- Viewlogic WorkView Office
selecting Atmel IDS 6.00 from the
Doulos Tutorials covering aspects of the VHDL language. Doulos are a training compa-
Start→Programs menu. After a few sec-
ny running public and company based courses on FPGA Design Methodologies and
Techniques, as well as offering computer-based courses on VHDL and Verilog. onds you will see a screen as in Fig-
ure 5. This is the main design environ-
ment, and all the other routines, such

10 - 11/99 Elektor Electronics EXTRA —————————————— PC TOPICS

as the VHDL template generator, HDL
Planner and the VHDL tool EDS are
launched from within this environment.
The tool bar below the menu bar runs
through the design process left to right.
We will look at the icons relevant to the
VHDL designs we will initially be
involved with. A complete description
of all the buttons can be found in the
on-line documentation and in the book
that accompanies this set of articles
(available from Kanda Systems Ltd., see
advert elsewhere in this issue).

This icon invokes the Design

Launcher. This gives access to
a dialogue that allows the
user to set up the environment for a
particular design, by specifying, for
example, the design name and direc-
tory, design capture package and
device type. To make use of the
Figure 5. Main design environment screen.
accompanying development board,
we must always specify the AT40K fam-
ily of FPGAs, although IDS 6.00 allows
the user to design with the AT6000 fam- is probably most useful as a browser to code in ASCII text, and converts this
ily of FPGAs also. see what functions are available as into something known as EDIF. EDIF is a
macros, and which parameters may generic format defined to allow the
be specified. Note that not all of the transfer of electronic designs between
This icon invokes HDL Planner possible functions in the Macro Gener- design packages. The process of trans-
(Figure 6). HDL Planner looks ators dialogue are available via HDL lation from an ASCII text file to (in this
like a simple text editor, but Planner. A typical Macro Generator case) an EDIF output is known as Syn-
the interface belies its power. HDL Plan- screen is shown in Figure 7. thesis. This is because EDS takes in a
ner is an ideal VHDL learning tool in that description of a function at a high level,
it will automatically generate the tem- and synthesises the logic required to
plate for a design. This template con- This icon brings us on to the implement this function in terms of a
tains all of the basic VHDL constructs conversion from VHDL to specific architecture.
that are required for a design. By using AT40K Library elements. Ever- There are several stages to the synthe-
the VHDL pull-down menu, additional, est Design System (EDS) takes in VHDL sis of a design by EDS, as shown in Fig-
more complex construct templates
may be added to the design, again
aiding the user by inserting the com-
plete VHDL syntax for a particular type
of construct.
HDL Planner is also the interface to the
Macro Generator functions. These
macro generators allow the user to
construct fully placed and routed,
parameterised components into their
design at the VHDL coding stage. This
takes away a lot of the task of writing
VHDL for standard functions ranging
from memories, through counters to
multipliers. All of the available macros
may have their parameters set by the
user. For example, a RAM block may
be defined as having a width of x and
a depth of y, whilst a counter would
have its reset parameters and count
width specified.

This icon allows direct access

to the Macro Generators. This
allows the generation of
Figure 6. HDL Planner screen.
macros externally from HDL Planner, but

PC TOPICS —————————————— Elektor Electronics EXTRA 11 - 11/99


Figure 7. Typical Macro Generator screen.
ure 8. First, the design libraries must be
specified to be the AT40K libraries. Use
the Target Technology button and
selecting the at40k.lib option. This will
force the synthesis tool into producing
the most appropriate output for the
AT40K FPGA architecture.
The next task is to input the design,
achieved by using the Input Design
button. This allows you to browse to the
input VHDL file and specify it. If there is
more than one VHDL file in a design,
they may all be entered using the EDS
command line that appears in the log
output window. As well as reading the
design into the EDS environment, this
process performs a syntactical and
semantic check on the VHDL code. This
will highlight any areas of the input files
that have constructs/sections that do
not adhere to the VHDL standard. Mis-
Figure 8. EDS design stages.
12 - 11/99 Elektor Electronics EXTRA
takes that beginners to VHDL often
make are reduced by using HDL Plan-
ner, as this inserts the framework in the
correct syntax automatically.
Once a design has been successfully
read in to EDS, we can synthesise the
design. There are a few options avail-
able from the Synthesise button, see
Figure 9. The first option is Automatic
Pad Insertion. If pads are not inserted,
the design cannot be correctly read
into the place and route routines. Pad
insertion may be achieved manually,
but it requires the user to map each
design to a port library component in
the VHDL files. Automatic pad insertion
simply does this for you. At this point,
the design pinout is not set, just pads
associated with signals. There are sev-
eral kinds of pads, found by looking
within the List Ports window. So for this
example you should set the Auto Pad
Insertion On
Optimisation level simply specifies how
hard the synthesis routines work. The
higher the level of optimisation, the
longer the design takes to synthesis, but
the result will have a higher efficiency
in general. Execute performs the syn-
thesis, which takes five stages to com-
plete.
Finally, we need to output the EDIF for-
mat file generated by the synthesis. This
is achieved by using the Output Design
button, and specifying the output file
name.
Having synthesised our design, we can
now read it into the IDS 6.00 Place and
Route routines.
Open reads in the design
with options. We can
read in the design as a
—————————————— PC TOPICS
Design or a Macro. A macro is a user-
defined hierarchical block that needs
to be written, synthesised, placed and
routed as a stand alone component.
For macros, pads should not be
inserted into the design. Most of the
time we will be dealing with complete
designs. Select the Design button in this
case. As the design is read into IDS
6.00, as with EDS, the design is
checked to see if it meets the required
design rules for the place and route
routines to operate on. With a VHDL
design entry, it is quite rare to get an
error at this stage as getting the design
to synthesise usually has eliminated any
problems. Any errors should be cov-
ered by the on-line documentation, but
any persistent problems should be
dealt with by Kanda Systems. Once the
design has been read in, a window
called the Design Browser will appear.
This lists all of the design instances (i.e.
library components) used to implement
the design.
Mapping is an optional
function designed to
increase the efficiency of
a design. It takes the original design
and tries to map (or convert) it onto the
AT40K architecture in a more efficient
way than by synthesis alone. For
instance, if a design has synthesised to
having 2-input logic functions, these
can be mapped into one AT40K core
cell. The net result is a smaller, and
often faster design. Also, mapping will
remove double inversions and double
buffering where it is not required. How-
ever, if a chain of buffers/inverters has
been used to create an asynchronous
delay, this will be mapped out of the
design to at most one level of inver-
sion/buffering, removing the delay.
Leave Mapping enabled.
To enable/disable mapping, use the
Options menu, and select Options
(alternatively press O). Select Mapping
from the list box, and then the Mapping
Enabled box may be checked or
unchecked. It may be of interest for the
reader to look through all of the items
under the Options dialogue, and they
are all explained fully in the on-line
documentation.
This window allows the
user to choose which
part is to be used to
implement the design. IDS 6.00 sup-
ports devices from 5K to 40K equivalent
FPGA gates, with between 256 and
2304 core cells. This dialogue also
allows the user to add several parts,
 routed design running at full speed with design and produces the final bit-
almost any pinout. Note that global stream we can use to program our
clock signals are best used for clock device with. There are actually 5 stages
type structures, as with the global reset, to the Place and Route process. Fig-
but above this restriction, almost any ure 11 shows a typical fully placed and
pin should be achievable. routed design.
Also within the Edit menu from this win- Firstly, we have Initial Place. This stage
dow is a command called IO Pad takes all of the design instances and
Attributes. In last month’s article we puts them onto the silicon floorplan IDS
mentioned that each pad is individu- 6.00 uses to perform the Place and
ally assignable with pull up/downs, Route operation, displayed in the Com-
Schmitt trigger inputs, slew rate pile window. This is mainly a geometric
adjustable outputs and a number of exercise, keeping related design
other options. This is achieved with a instances within a (IDS 6.00 determined)
VHDL design through this dialogue box. radius. At this point the design instances
All of the design Inputs, Outputs and Bi- are allowed to ‘contend’ with each
directional signals are listed along with other (i.e., overlap). This is a single
their possible attributes. Each one may stage process allowing a first pass of
Figure 9. Options available for the
be specified on a pin by pin basis, so it placing the design.
Synthesis button.
is possible for pins in a to have different Next comes Optimise Place. This stage
sets of pin parameters. Figure 10 shows takes the placement Initial Place made
the Parts window as a Design Input is and tries to remove all of the place-
and the design software to automati- being dragged onto a pin. ment contentions. This must be done
cally place and route the design over The partition button partitions the prior to routing the device, as a single
more than one device (useful for very design over a number of devices as cell can only perform one function in a
large designs), whilst automatically previously mentioned, before we get design at any given time. This is a two-
allowing for the interconnectivity onto the actual Place and Route of our stage process, and in a complex
between the devices. design. design may take a little time. However,
Whilst using this window it is possible to this may be overcome in a known sim-
do several functions. Firstly, we can ple design by using an option in the
define physical pins to the pads we This button runs the Option dialogue called Place and
inserted in our VHDL design. This allows Auto Compile All Route. Within this, there is a parameter
the specification of a part ready for process. If, prior to called Quality. This represents how hard
PCB layout, and for the Development clicking in this button, you select Win- the Place and Route tools work to
Board peripherals to be connected to dow – New Compile Window, the Com- achieve their goal. The greater the
the correct input or output. The actual pile window appears. This will make the number, the harder IDS 6.00 works, and
assigning of pin locks may be done in following explanation clearer, but is not the longer each stage takes. There is a
one of two ways. totally necessary. This button automati- check box called Auto Set Parameters
Firstly, with the Parts window active, cally places and routes the whole which makes IDS 6.00 look at the
there is a command under the Edit
menu known as Assign Pin Locks. This
allows the user to directly specify the
design pad instance to a pin number.
This is very good for instance where the
PCB layout has already been decided,
and the device just needs to be spec-
ified with this pinout, or where the pin
number is explicitly required (again, as
in the Starter Kit).
Secondly, and more suited to circum-
stances where the FPGA design is to be
specified first (usually the case when a
design still has some uncertainty), the
user may simply ‘drag and drop’ an
instance of a pad onto a pin. This
allows buses to be assigned in order for
a port, for example. This is not always
the best design method for high speed
designs as a number of adjacent out-
puts (or inputs) all switching at the same
time may cause crosstalk, but for most
designs should not be a problem.
The ability of a pinout for a design to
be locked prior to the final FPGA design
was mentioned last month. The AT40K
Figure 10. This is what happens to the Parts window when a Design Input is being
family has such a high level of routabil-
dragged on to a pin.
ity it is possible to get a placed and

PC TOPICS —————————————— Elektor Electronics EXTRA 13 - 11/99

Figure 11. All done — a placed and routed design.
design and set the Quality level as
appropriate. The quality level is used for
the first four stages of the place and
route operation.
Once all of the placement contention
has been removed, it is possible to
move onto the Routing of the design.
But what if not all of the contention can
be removed? There are three options
on this. Firstly, a higher Quality setting
may be set, and the Placement rou-
tines run again. Secondly, a larger
device may be required. This will give
more logic resource and so will usually
cure the problem. With all of the avail-
able 40K devices being pin compati-
ble within a specific package, this is
possible across the range of devices
from 5K to 40K equivalent gates. Finally,
and for some most interestingly, we can
manually modify the placement.
Manual placement allows the moving
of a cell or macro around on the
device to remove contention. This is
done by selecting an instance on the
floorplan, and dragging it to its new
position. Once an instance has been
selected, it turns yellow and, for a
macro block, may be rotated or
flipped and then moved to a suitable
area. For a macro, this is possible due
to the symmetrical nature of the array,
and the fact that macro functions are
pre-parameterised for all orientations of
the macro.
Initial Route is a function not dissimilar
to Initial Place, but obviously it works on
the routing structure and resource. This
time the cells and macros are con-
nected together without too much
regard for using the same routing
resource twice. This is a three-stage
14 - 11/99 Elektor Electronics EXTRA
process as there are several aspects of
routing to be considered. As mentioned
previously, the AT40K family of FPGAs
was designed with routeability in mind,
so this process often gives very good
results prior to Optimise Place.
Optimise Route does the same for rout-
ing as Optimise Place does for place-
ment. This is usually a much easier
stage for IDS 6.00 software due to the
routing based architecture, and if a
design can be placed within a device,
there will be very few times the device
cannot be routed. If, however, the
design does not route, what then? Well,
the same applies for routing as for
Placement. Going to a larger device
will usually solve the problem. Setting a
higher quality factor again will most
times get rid of the contention. Finally,
it is possible to manually edit both
Placement (where the placement can
be tweaked to allow sensible data
flow), and Routing Resource. Manually
Routing the device is something best
left until the user becomes very confi-
dent with the devices, as what seem to
be small changes can have timing
impacts on a design!
The final stage for the design is the Bit-
stream generation. This stage gener-
ates the bitstream in several output for-
mats, ready to be downloaded directly
into the FPGA or to program a configu-
ration Serial EEPROM, ready for pro-
gramming on the user’s board.
Next Time — How About
Some Hardware?
We can see that the process of gener-
ating a bitstream from an initial ASCII
—————————————— PC TOPICS
text file comprises a number of steps,
although none of them are too com-
plex, and the whole process does
become second nature after a while.
Now we have seen how to generate a
bitstream from a design, what about
running this design in hardware? Well,
using the Development Board and the
‘Get Going with FPGA’ book accompa-
nying this series we will next month look
at the FPGA from a hardware point of
view, describing peripheral use on the
board, and how to connect up a con-
figuration device for progressing a
design onto a user’s own PCB.
(990063-2)
Note:
The book and Starter Kit mentioned in
this article series are available (at a
special discounted price for Elektor
readers) from Kanda Systems Ltd, Unit
17-18, Glanyrafon Enterprise Park,
Aberystwyth, Ceredigion SY23 3JQ. Tel.
(01970) 621030, fax (01970) 621040,
Email sales@kanda.com
Developments in the c omputing industry progress
rapidly. Last year’s expensive ac quisitions are
already no longer usable for running modern soft-
ware. However, old c omputers, or at least parts of
them, need not always end up as elec tronic
sc rap. Let’s look at the motors found in old hard
disk drives, for example…
By H. Ne um a nn a nd E. Mö ller
r e cy cl i n g h a r d d i s k
d r iv e m o t o r s
Hard disk drives with
1 c apac ities of 20 to
40 MB c an often be
found in discarded com-
puters (in the basement
or at flea markets). The
data stored on these
devic es is surely of no
interest to anyone, but
eac h one c ontains two
motors, for whic h some
useful applications might
still be found. In addition
to the stepper motor,
whic h moves the
read/write heads, the
ac tual drive motor is an
interesting item. In the
case of the drives inves-
tigated by the authors,
this is a d.c . motor with
electronic commutation.
An example is shown in
2 Figure 1. Our objec tive
here is to see how suc h
a motor can be brought
back to life.
Before you c an do any-
thing with the motor, you
must first d isa ssemb le
the d rive. Sta rt b y
removing the enc losure
c over a nd the p rinted
c irc uit b oa rd . The
proper tool for removing
the sc rews is a Torx
screwdriver, but a sturdy
slot-typ e sc rewd river
c a n a lso b e p ressed
into service if necessary.
After the c over and the
b oa rd ha ve b een
removed , you will see
PC TOPICS —————————————— Elektor Elec tronic s EXTRA
the two motors (Figure 2). You c an now
d ismount the hea d d rive motor (Fig-
ure 3) a nd the p la tter a ssemb ly (Fig-
ure 4). Finally, remove the fixing sc rews
for the drive motor (Figure 5), and you
c an extrac t the desired objec t.
The motor has six leads, three of whic h
a re c onnec ted to its wind ing s. These
leads c an be easily identified with the
help of an ohmmeter. The winding resis-
ta nc e will mea sure a round 3 or 6 Ω,
d ep end ing on whether you mea sure
a c ross one or b oth wind ing s. You c a n
thus direc tly figure out whic h leads are
the wind ing lea d s. The three other
lea d s a re c onnec ted to a Ha ll-effec t
sensor IC, a nd the mea sured resis-
tances between these leads will be sig-
nific a ntly hig her. With the test c irc uit
shown in Figure 6, you c an easily sort
out whic h of these leads is c onnec ted
to what. In the worst case, you will have
to c onnec t eac h of the three leads to
ea rth in turn while the other two a re
c onnec ted to + 12 V via series resistors
a nd LEDs. Turn the rotor of the motor
slowly. If the proper lead is c onnec ted
to ea rth, one of the LEDs will b e c on-
stantly on; the assoc iated lead is then
c onnec ted to the power supply termi-
nal of the IC. The other LED will blink as
the rotor is turned ; its lea d is thus the
signal output of the IC.
Now you ha ve c omp leted the nec es-
sary preparations in order to be able to
use the motor. For this, you will need a
c irc uit as shown in Figure 7, whic h c an
be quic kly c onstruc ted on a bit of pro-
totyping board. The Hall sensor built into
the motor ha s a n op en-c ollec tor out-
p ut. If the outp ut tra nsistor is switc hed
on, tra nsistor T1 is c ut off. Resistors R2
and R3 then supply enough c urrent to
15 - 11/99
3 4

switc h on T2. This in turn supplies base

c urrent to T3 via R4, a nd T3 is a lso
switc hed on. A ma g netic field is c re-
ated in coil L1, and this causes the per-
manent-magnet rotor to rotate slightly.
The Ha ll sensor is now exp osed to the
op p osite ma g netic p ola rity, so tha t its
outp ut tra nsistor is switc hed off. The
base of T1 now rec eives c urrent via R1,
and it switches on. Since the voltage at
the c ollec tor of T1 is now very low, the
c urrent flowing throug h R3 is not suffi-
c ient to keep T2 switc hed on. Conse-
q uently, T3 is a lso no long er switc hed
on, and current no longer flows through
L1. However, sinc e T1 is switc hed on, T4
is supplied with a base c urrent via R2,
a nd it switc hes on. L2 thus rec eives a 5
current and produces a magnetic field,
whic h in turn c auses the rotor to rotate Figures 1 through 5. How to ta ke a p a rt a ha rd d isk d rive.
a bit further. This sequence repeats itself
over a nd over a g a in a s long a s a n
a d eq ua te sup p ly volta g e is p resent.
Diod es D1 a nd D2 p rotec t T3 a nd T4 R1 R2 R4 L1 L2
against induc ed voltages. If you want
3k3

180Ω

180Ω

to reverse the motor’s direc tion of rota-

tion, simp ly exc ha ng e the L1 a nd L2
T2
leads. R3
(992039-1) 1k

BC547
T3
D1
12V T1

1N
1k

1k

Hall-effect BD243 4007

BC547 T3
IC D2

1N
BD243 4007

992042 - 11
992042 - 12
Figure 6. This test c irc uit c a n b e used to
d eterm ine the c onnec tion sc hem e of
the m otor. Figure 7. Control c irc uit for a n elec tronic a lly c om m uta ted m otor.

16 - 11/99 Elektor Elec tronic s EXTRA —————————————— PC TOPICS