CFD Analysis of Automatic Test Equipment

Venkat R. Gaurav
Credence Systems Corporation
Hillsboro, Oregon 97124
Phone: (503) 466-7823
Fax: (503) 466-7454
E-mail: venkat_gaurav@credence.com

thermal engineer in devising cooling strategies for its automatic

ABSTRACT
test equipment. One project involved the design of an ATE’s air-
In many cases the goal of CFD modeling is the accurate prediction cooled test head.
of chip junction temperatures within large electronic enclosures
The complex architecture of the test head made it impractical to
that contain numerous boards, flow obstructions, and other
accurately predict board and system level performance discretely.
thermal/fluid modeling challenges. Although, it is often
impractical to develop a single, coherent CFD model that The goal, therefore, was to develop a CFD model that accurately
accurately predicts system and board level performance, many predicts both system and board-level performance concurrently.
electronic enclosures demand such an approach. Automatic test
SYSTEM DESCRIPTION
equipment (ATE) for testing semiconductors easily fits into this
category. Reliable operation of ATE is critically dependent on Figure 1 below shows the complete Automatic Test Equipment
maintaining a stable thermal environment within the test head. The system. Of this system the test head shown in the foreground is of
complex architecture of the test head, containing heavily populated primary thermal concern.
boards arranged in a radial manner, makes it impractical to
accurately predict board and system level performance discretely.
This paper documents a successful methodology to model
complex systems that require simultaneous system and board level
thermal/fluid interactions. First, a CAD model was created
integrating the board and system level geometry. This CAD
model was then used as the basis for the CFD modeling approach.
The CFD software package used was CFDesign 5.0, a finite
element fluid flow and heat transfer solver. CFDesign’s ability to
import geometry using any industry-standard format and quickly
prepare it for simulation was the key to creating a CFD model that
accurately predicts both system and board level thermal
performance concurrently. Employing the above CAD and CFD
tools in concert with experimentally validated assumptions, chip
junction temperatures were accurately predicted as well as their
sensitivities to system level characteristics.

KEY WORDS

CFD, Automatic Test Equipment, FEA, Thermal and Flow

Modeling, Computer Simulation, Board Level Simulation, System
Level Simulation, Airflow and Temperature Measurements, Flow
Resistance, System Impedance. Figure 1 - Credence’s Octet 800 ATE system.
INTRODUCTION

Credence Systems Corp., Hillsboro, Oregon, is a world leader in

the manufacture of automatic test equipment. The company has
found that fluid flow and heat transfer analysis, or computational The test head contains 8 pin modules with electronics and
fluid dynamics (CFD) software could be used to help guide the equipment to distribute and interface power and signals to the
device under test (DUT). the test head enclosure bound the domain. The intent of this model
was to characterize the flow field within a single card slot and to
predict the temperatures of the principal components modeled.

Figure 2

Each of these pin modules contains 8 pin cards and a distribution

card for a total of 72 pin cards. The pin cards are arranged in a
radial manner in 5o intervals around a central exhaust tube as
shown in fig. 2 above.

Several CFD models were analyzed to study various airflow

patterns through the proposed test head architecture. From the
results of these simulations it was determined that the maximum
cooling benefit is obtained when air is drawn through the sides of
the test head, passed over the entire card, and then up through the Figure 4 – Pin Card
center tube to the plenum where it exits out of the test head. This is
also shown in Figure 2. Due to the radial arrangement of the pin
cards this flow pattern creates a Venturi effect between the pin
cards, so the air speeds up over the hottest components and
enhances cooling.

Six fans, three across and two deep, were used to generate the
required airflow and overcome the system impedance.

Figure 4 shows a typical pin card used in the test head. The key
components at risk for lack of cooling were the timing and power
chips located near the card connector. These included eight TQFP
IC’s with an exposed pad (four on each side) dissipating close to
7.0 W each and sixteen timing chips, 208 pin BGA’s (eight on
each side) dissipating 2.5 W each. The target junction temperature
of the IC’s was not to exceed 95o C at the worst-case allowable
ambient air temperature of 30o C.

THE CFD MODEL

Geometry and Mesh

The modeling approach exploited the cyclic symmetry of the card Figure 5- Cyclic symmetric geometry with two pin cards
layout. Fig. 5 shows the geometry of this wedge-shaped domain. embedded within the flow volume. All power generating and flow
Two adjacent cards, the test head centerline, and the outer wall of obstructing chips are represented on the pin cards.
The model shown in fig. 5 was created using a commercially Later, mock-up pin cards were made and a flow bench was used to
available CAD package [1]. This CAD representation was measure actual system impedance, figure 7.
directly imported into the CFD solver [2]. With very few steps,
this model was then converted into a fully meshed finite element
CFD model.
This meshed model would be considered quite coarse by any
normal CFD modeling standards. For example, flow passages
through the domain were meshed with no regard to the number of
elements spanning across the flow channel. In most cases only one
element was used to define the edge-to-edge separation. Normally
CFD theory, with regard to FEA methods, would recommend a
minimum of 5 nodal points (four 4-node tet elements) from edge-
to-edge across the flow channel [3]. The CFD solver used in this
investigation has the unique ability to inflate or enhance the coarse
mesh near walls. Walls, in this context, refer to surfaces of the
FEA model where airflow encounters turbulence. The mesh
inflation creates a multi-layered mesh of six-node wedge elements
using the initial surface mesh as a template. The number of layers
and their thickness’ are user-defined. The end result allows the
user to create and use an incredibly coarse FE mesh (minimizing
computational pre-processing and data storage tasks) and yet Figure 7 - Measuring system impedance using mock-up pin cards
obtain high quality CFD results. and flow bench.
Thermal and Flow Modeling Flow resistances due to the enclosure side panels and fan plenum
were easily computed [5].
Only those chips, which generated over 1.0 W, were modeled in
sufficient detail using manufacturer’s geometry and material EXPERIMENTAL VALIDATION
specifications [4]. The thermal load on each chip was applied as a
volumetric heat generation. For the circuit board a standard 12- Airflow and temperature measurements were made on a fully
layer FR-4 board was assumed and then its thermal conductivity operational test head to validate the results of the CFD simulation.
was modified using the stack-up information.
Airflow Measurements
The air inlets and fan outlets were defined next as shown in Fig. 5.
A zero static pressure boundary condition was applied at the inlet. An array of airflow sensors was designed to fit across a pin
At the fan outlet, measured air velocity values as well as fan curve module (see figure 8) to measure the air velocity entering the card
data were applied in separate simulations. slots. Additionally another airflow sensor was placed between a
pair of pin cards such that it measured the air velocity between the
Determining System Impedance cards.
Static pressure losses through the complex flow channels inside
the test head could not be easily arrived at by calculation. First, an
estimate was made using a CFD model to size the fans, figure 6.

Fig. 8– Quarter-section Model of the Test Head showing the

Figure 6 - System Impedance as determined by CFD simulation locations of the airflow sensors.
Temperature Measurements

Two pin cards were instrumented to measure junction

temperatures of the power IC’s, the case temperatures of the
timing chips as well as other thermally intensive components.
These two cards were placed in different slots within the test head
to determine location specific temperature variations if any.

RESULTS & DISCUSSION

The CFD modeling and simulation process matured over

successive correlation between empirical data and the simulation
results. The thermal simulations predicted that the 100 lead TQFP
with exposed pad would exceed the target junction temperature of
95oC necessitating a heat sink. The heat sink was designed and
optimized using the same CFD model, see figure 9.
Figure 10

CONCLUSIONS

The results proved that in large electronic enclosures with complex

thermal and flow phenomena, a single, coherent model which
combines both system- and board-level characteristics is very
critical to accurately predicting thermal performance.

ACKNOWLEDGEMENTS

The author would like to thank Jeff Monroy, Director of

Engineering, Credence Systems Corporation for his permission to
present this paper and his manager, Scott Withee, for his support
and guidance.

1.
Figure 9 – Heat sink optimized for the 100 lead TQFP chips.
2.
Additionally, the case temperatures of the timing chips as
predicted, ranged from an average of 45oC to 75oC and compared 3.
closely with the measured results.
The airflow tests indicated consistent and uniform air velocities at
all locations in the test head as predicted. The average air 4.
velocity between pin cards past thermally significant
components as predicted by simulation was within 1% of the
actual measured values. Figure 10 is a graph of the measured 5.
values. The average velocity predicted by simulation was 600
ft/min.
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