Exp No.

0
DESIGN AND SIMULATION OF CMOS INVERTER
11.12.2023

AIM:
To design and simulate CMOS inverter using Cadence Virtuoso EDA Tool.

SOFTWARE USED:
Cadence Virtuoso 6.1.8 for design and ADE L tool for analysis.

PROCEDURE:
Cd to the working directory and open terminal.
csh (C-Shell) incorporates syntax similar to the C programming language,

Cd to source /home/cad/cshrc will give permission to run commands in the C-Shell.

virtuoso & command will start the Virtuoso server and then immediately return you to the shell
prompt, while Virtuoso continues to run in the background. Other tasks can be done in the same
shell session without having to open a new terminal or stop the Virtuoso server.

CDS.log (Cadence Design System)

→ File → New Library → Name → Attach to existing technology library

A new library for an existing technology is created to store the cell that will be built.
Select the existing technology to which you must add the new library i.e (gpdk180)

CDS.log (Cadence Design System)

→ File → New File → Cell - inv

A cell corresponds to the fundamental building block of an IC (in the below case it is an inverter)
I (keyboard) – To add instance

To build a new cell (inverter) NMOS and PMOS are required.

NMOS and PMOS are cells present in the library gpdk180.

It is important to note that the cell we create is a part of the library cmos_inv.

gpdk180 and cmos_inv are libraries of the technology gpdk180.

→ I → Library – gpdk180 → Cell - nmos → View – symbol

→ I → Library – gpdk180 → Cell - pmos → View – symbol

P (keyboard) – To add pin

W (keyboard) – To add wire

F (keyboard) – To fit the designed cell to screen

→ P → Pin Name - in → Direction - input → Usage - schematic

→ P → Pin Name - out → Direction - output → Usage - schematic

Add the pins to model the cell as inverter.

→ Create → Cellview → From Cellview → Apply

Generate a symbol for the cell created using NMOS and PMOS transistors by giving the pin
specifications
Remove the 2 bounding boxes and draw a symbol for the inverter check and save. View log file
for errors.

CDS.log (Cadence Design System)

→ File → New File → Cell – inv_tb (in the case given below cmos_inv_tb)

2 cells are created 1st cell for design i.e inv 2nd cell for testing i.e inv_tb
→ I → Library – cmos_inv → Cell - inv → View – symbol

→ I → Library – analogLib → Cell - gnd → View – symbol

→ I → Library – analogLib → Cell - vdc → View – symbol

→ I → Library – analogLib → Cell - vpulse → View – symbol

2 voltages voltage1 and voltage corresponds to logic 0 and logic 1

Fill other specifications of the cell vpulse to generate an input pulse.

Add the pins to test the inverter. i.e vin and vout

Launch → ADE-L (Analog Design Environment - Layout)

TRANSIENT RESPONSE

Analyses → Analysis – trans → Stop Time – 500ns

DC RESPONSE

Analyses → Analysis – dc → Hysteresis sweep → Component Parameter → Select Component

→(control goes to inv_tb) vpulse →

→ sweep range 0 to 1.8 V → sweep type Linear → step size 0.3

→ ADE L → Output → to be plotted → (select pins vin, vout, node vdd)

Run Simulation:

Transient Response
DC Response

RESULT:
Thus CMOS inverter is designed and simulated using Cadence Virtuoso
EDA Tool.