U.S.N.

B. M. S. College of Engineering, Bengaluru - 560019

Autonomous Institute Affiliated to VTU
March - 2021 Semester End Main Examinations
Programme: B.E. Semester : III
Branch : Computer Science and Engineering Duration: 3 hrs.
Course Code: 19CS3PCCOA Max Marks: 100
Course: Computer Organization and Architecture Date: 29.03.2021

Instructions: 1. Answer any FIVE full questions, choosing one full question from each unit.
2. Missing data, if any, may suitably assumed.

UNIT - I
1. a) Convert the Following pairs of decimal numbers to 5-bit 2’s complement 10
numbers, and then perform addition and subtraction on each pair.
Indicate whether or not overflow occurs for each case.
Important Note: Completing your answers, compulsorily draw diagonal cross lines on the remaining blank pages.

(i) 7 and 13
(ii) -12 and 9.

b) Define Assembler Directives. Explain any four with examples. 05

c) Define an Addressing Mode. Explain any four with example. 05

UNIT - II
2. a) List and explain mechanism for handling multiple interrupt driven I/O 10
Revealing of identification, appeal to evaluator will be treated as malpractice.

data transfer.

b) Explain the concept of parameter passing by value and reference with a 10

program of adding two numbers.

OR
3. a) Two decimal digits represented in ASCII code are located in memory 10
locations LOC & LOC+1. Write a assembly program to represent each of
these digits in the 4-bit BCD code and store both of them in a single byte
location PACKED. The result is said to be in packed-BCD format.

b) Explain the Stack Frame created during the execution of subroutine with 10
an example.

UNIT – III
4. a) Demonstrate the translation of Virtual Address to Physical Address with a 10
neat diagram.

b) Design a Memory of Size 4Mx32 using 1024Kx8 memory chips. Show 10

the design with neat and complete diagram.
 OR
5. a) A cache is organised in a direct mapped manner with the following 05
parameter.
Main Memory size is 64 K
Cache Size is 1K
Block size is 128 words.
i. How many bits are there in Main Memory Address?
ii. How many bits are there in each TAG, BLOCK and WORD fields?

b) A computer system uses 32-bit memory addresses. It has a main memory 10

consisting of 1G bytes. It has a 4K-byte cache organized in the block set-
associative manner, with 4 blocks per set and 64 bytes per block.
(i) Calculate the number of bits in each of the Tag, Set, and Word fields of
the memory address.
(ii) Assume that the cache is initially empty. Suppose that the processor
fetches 1088 words of four bytes each from successive word locations
starting at location 0. It then repeats this fetch sequence nine more times.
If the cache is 10 times faster than the memory, estimate the improvement
factor resulting from the use of the cache.

c) Identify the differences between static RAM and dynamic RAM. 05

UNIT - IV
6. a) Explain the IEEE Floating Point Formats, Represent (0.0625)10 in 05
Single Precision and Double Precision Floating point Formats.

b) Multiply (+22) (Multiplicand) with (-6) (Multiplier) using Booth’s 05

Algorithm Method.

c) Multiply 110101 (Multiplicand) with 011011 (Multiplier) using Bit-Pair 05

Recoding Method.

d) Multiply 14 with 12 using sequential circuit binary multiplier. 05

UNIT - V
7. a) Describe the taxonomy of FLYNN’s in parallel architecture. 10

b) Explain with block diagram the basic organization of a Hardwired Control 10

Unit.

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