TSMC Universal Analog IO General Application Note 2

Organization: F13780-College of Engineering Pune (CoE
TSMC Confidential Information 924762 Interuniversitair\ Micro-Elektronica\ Centrum\ \(IMEC\)\ vzw 07/09/2018
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Version 2.00
April 2008
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General Application Note
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Copyright 2005, Taiwan Semiconductor Manufacturing Company, Ltd. All Rights Reserved.
No part of this publication may be reproduced in whole or in part by any means without prior
written consent.
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NOTICE
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Taiwan Semiconductor Manufacturing Company Ltd. reserves the right to make changes in
the contents of this document without notice. No responsibility is assumed by Taiwan
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Semiconductor Manufacturing Company Ltd. for any infringements of patents or other rights
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of the third parties that may result from its use. Taiwan Semiconductor Manufacturing
Company Ltd. assumes no responsibility for any error that appears in this document.
Revision History
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Version Date Special Note

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1. Update page 2 of Chapter 1.

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2. Update “Analog I/O Cell PDBxA / PDBxAC” section and

2.00 2008/04/10 “Analog Ground Pad PVSS3A/AC” section in Chapter 2.
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TS 3. Update “Example 1” and “Example 3” of Chapter 3.

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4. Update the device mapping table in Chapter 5.

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M 1 Update Figure 2.3, “Analog Ground Pad PVSS3A/AC”, and “ESD

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Core-Clamp PCLAMP Cell” sections in Chapter 2.

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2 Insert new sections on “How to Use TPAxxxGV Universal Analog

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I/O with Bond Pad Cell” and “How to Use TPAxxxNV Universal
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Analog I/O with Bond Pad Cell” in Chapter 2.

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1.40 2007/07/05
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3 Re-arrange “Bond Pad Cell” section in Chapter 2.

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Update Figure 3.1 and 3.2.
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5 Update “Tape-Out with Top Two Thick Metals and Top Two
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Large VIAs“ section in Chapter 4.
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6 Update the Device Mapping Table in Chapter 5.

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1. Update the “Power Cut Adapter Cell PRCUTA” section and insert
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1.30 2005/12/04 “ESD Core Clamp PCLAMP Cell” section into Chapter 2.
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Reorganize Chapter 2, 3, 4, 5, and 6.
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1.20 2005/07/04 1. Update Chapter 5, “Library Integration Notes”.

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1. Insert the section on “Tape Out with Top Two Thick Metals and
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Top Two Large VIAs for the mixed-mode process” into Chapter 2.
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1.10 2005/06/15 2.
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Insert the section on “Direct Shrinkage to Half-Node Technology”
into Chapter 2.
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3. Update the section on “The Bond Pad Cell” of Chapter 2.

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1. First release of Universal Analog I/O Library General Application

1.00 2005/01/06
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Note.
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TSMC Universal Analog I/O Library General Application Note – April 2008 iii
Table of Contents
In
Chapter 1 Introduction 1
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Description............................................................................................................................ 1
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Outline .................................................................................................................................. 1
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Chapter 2 Cell Usage 4

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Universal Analog I/O Power Rail ....................................................................................... 4

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Analog I/O Cell PDBxA / PDBxAC.................................................................................... 5

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Condition One: Connect PDBxA / AC Analog Signal Pin to Internal Gate ......... 7
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Condition Two: Connect PDBxA / AC Analog Signal Pin to Internal Drain....... 7

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Analog Power Pad PVDD3A/AC...................................................................................... 11

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Analog Ground Pad PVSS3A/AC .................................................................................... 12
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Filler Cell PFILLERxA Family & Corner Cell PCORNERA....................................... 14
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Power Cut Adapter Cell PRCUTA .................................................................................. 14

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Place PRCUTA between Analog Domain and Digital Domain............................ 15

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Place PRCUTA between Two Analog Domains .................................................... 17
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How To Use TPAxxxGV Universal Analog I/O with Bond Pad Cell............................ 19
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Non-CUP In-Line Wire-Bond ................................................................................. 19
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How To Use TPAxxxNV Universal Analog I/O with Bond Pad Cell ............................ 22
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Non-CUP In-Line Wire-Bond ................................................................................. 23

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CUP In-Line Wire-Bond ......................................................................................... 26

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ESD Core-Clamp PCLAMP Cell ..................................................................................... 29

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Approach A: Place PCLAMP Cell in between Analog Macro and PVDD3AC &
PVSS3AC Cells......................................................................................................... 29
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Approach B: Place PCLAMP Cell in between The Bond Pads of PVDD3AC

and PVSS3AC........................................................................................................... 31
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Chapter 3 Application Examples 33

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Example 1: Using PRCUTA cell to separate digital/analog domains or to

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separate analog/analog domains (with different supplied voltage) ..................... 33

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Exampleby: Vanita
2: Using Agarwal
PRCUTA cell to separate digital/analog domains or to
Organization: F13780-College
separate analog/analog ofI/OEngineering
domains (with the same voltage)..............................Pune
34 (CoE
TSMC Universal Analog I/O Library General Application Note – April 2008 iv
Example 3: Using PRCUTA cell to separate digital/analog domains or to
separate analog/analog domains (with the same core voltage) ............................ 35
In
Chapter 4 Library Integration Notes 36

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Integration of Library Tape-out Layers.......................................................................... 36

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GDSII Number Mapping ........................................................................................ 36

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OD Mask ................................................................................................................. 36
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ESD Mask ................................................................................................................. 36

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Poly Resistor ............................................................................................................. 37
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Non LDD Device....................................................................................................... 37

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GDSII Change to Mask Revision............................................................................ 37
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High-Vt (Threshold Voltage) Implant.................................................................... 37

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Tape-Out with Top Two Thick Metals and Top Two Large VIAs in Non-CUP Wire
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Bond .................................................................................................................................... 38
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Direct Shrinkage to Half-Node Technologies.................................................................. 39
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Chapter 5 Simulation Notes 40

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Chapter 6 Contact Us 42
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TSMC Universal Analog I/O Library General Application Note – April 2008 v
Chapter 1 Introduction
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Description
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The high-speed interface and Radio Frequency (RF/ultra-low-input capacitance)

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applications have become increasingly common nowadays. Therefore, the analog

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I/O implemented with the ultra-low-input capacitance that can safeguard the
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original signal waveform has played a crucial role. This document summarizes
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useful information on what TSMC universal analog I/O comprises and how to
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correctly use it. C

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By using the TSMC IP, TSMC universal analog I/O library is suitable for all kinds
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of power separation applications and Digital/Analog signal interface. Note that
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TSMC can guarantee the ESD robustness based on the testing condition specified
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in the universal analog I/O silicon report.
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Outline lI
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• Chapter 1 provides general information on what to follow and what to avoid.
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•
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Chapter 2 introduces cell usage for analog I/O, power, ground, power-cut,
corner, filler, bond pad, and ESD core clamp cells.
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•
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Chapter 3 provides application examples using universal analog I/O cells.
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• Chapter 4 provides information on the integration of library tape-out, tape-

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out with top two thick metals, and direct-shrinkage to half-node technologies.
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• Chapter 5 provides guidelines for simulation purpose.

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• Chapter 6 guides you whom to contact for technical support.

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TSMC Universal Analog I/O Library General Application Note – April 2008 1
Warnings Attention 1: The analog power-cut adapter cell PRCUTA MUST
be used to bridge between TSMC universal analog I/O and TSMC
universal standard I/O. Note that it is prohibited to use the standard
In
power-cut cell PRCUT available from the universal standard I/O

library for this purpose! For usage instruction on PRCUT cell,
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please refer to Chapter 10 of Universal Standard I/O General

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Application Note.
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Attention 2: TSMC universal analog I/O is only suitable for interface

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of signal swing between the power rail TAVDD/TACVDD (i.e. non-

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overshoot application) and the ground rail VSS (i.e. non-undershoot

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application), such as Low Noise Amplifier for WLAN/Bluetooth, or

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Gbps. Serial Link/SerDes.

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Attention 3: Ensure the inter-connection between the analog macro
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and universal analog I/O as short as possible.

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Attention 4: There is no limitation on the number of power
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domains on the same chip, if and only if customers use TSMC

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universal I/O cells in the entire I/O ring. Note that using any 3rd
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party IP is beyond TSMC’s guarantee.

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Attention 5: Chapter 2 addresses how to bridge between TSMC

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universal analog I/O and TSMC universal standard I/O. For how to
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bridge between TSMC universal standard I/O and TSMC specialty I/O
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cells, please refer to Chapter 7 of TSMC Universal Standard I/O
General Application Note for details.
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Attention 6: To use TSMC universal analog I/O for metal scheme

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that includes top 2 ultra thick metal layers, “Mu”:

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For universal analog I/O: You need to use the GDS under
(target total metal – 1) lm directory under “mt” directory; then
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insert dummy metal into metal top to fulfill the top 2 “Mu”
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requirement. (e.g. To achieve 8lm GDS with top 2 “Mu”, adopt

7lm GDS under “mt” directory, and then insert dummy metal
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as metal 8 for 8lm tapeout)

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For bond pad: TSMC bond pads cannot yet support “Mu”
metal scheme (where u stands for ultra). Therefore, you need
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to modify the bond pad VIA size according to design rule

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(continued on the following page)

It is necessary to change the data type to “Mu” before
streaming out the GDS file. If needed, TSMC can modify it
through customization service. Note that TSMC plans to
provide the ultra-thick metal bond pad in the near future.
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Please refer to the bond pad library release note for guidance
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on bond pad selection.

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TSAttention 7: Universal analog I/O cannot support metal scheme

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that contains “Y” / “R”. Customer can “either modify it and

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request TSMC for review, or request TSMC to modify it through

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customization service”.
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Attention 8: To reflect the N90 process that features triple-gate

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oxide thickness, N90 universal analog I/O cell name comes with
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_33 / _25 / _18 extensions for DRC/LVS purpose.
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Chapter 2 Cell Usage
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This chapter covers the following topics:

•
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Universal analog I/O TAVDD/TACVDD power rails

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• Universal analog I/O PDBxA/PDBxAC cells

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• Universal analog power pad PVDD3A/PVDD3AC

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• Universal analog ground pad PVSS3A/PVSS3AC

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•
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Filler cell PFILLERxA family & Corner cell PCORNERA
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•
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PRCUTA power cut cell

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• How to Use TPAxxxGV Universal Analog I/O with Non-CUP Bond Pad.
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•
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How to Use TPAxxxNV Universal Analog I/O with Non-CUP or CUP Bond Pad.
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PCLAMP ESD core-clamp cell

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Universal Analog I/O Power Rail lI

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To Core or
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TAVDD/TACVDD (Power Rail) io
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ESD Device
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ESD Device
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VSS (Ground Rail)

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To Pad
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Figure 2.1 Universal Analog I/O Power Rail Scheme

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Figure 2.1 indicates that devices in universal analog I/O are powered by the
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TAVDD/TACVDD power rails, where TAVDD is for the domain supplied by I/O
voltage, and TACVDD is for the domain supplied by core voltage.
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To support universal analog I/O with different interface devices, TSMC provides
two types ofto the
of power/ground cells. Please refer Engineering Pune
following sections for details. (CoE
Analog I/O Cell PDBxA / PDBxAC
Figure 2.2 illustrates the structure of PDBxA/AC cells with the ESD protection
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devices shunted on the signal path.

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Power
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To PAD Side on 9 tro 01 To Analog Macro

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Signal Input/Output
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ESD device
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Ground
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Figure 2.2 The PDBxA/AC Structure or
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The naming convention for PDBxA/AC is presented below (taking PDBxAC as an
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example):
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PD-B-x-A-C
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Supplied by Core Voltage

Analog
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X= 1/2/3, provides optimum design

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for different applications

Bi-directional
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I/O Pad
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Table 2.1 provides a list of PDBxA/AC cells. There are three different input-
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capacitance categories with different ESD robustness levels available for options.
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Table 2.1 PDBxA/AC Cell Categories (where x = 1 or 2 or 3)
Domain Analog Estimated Expected ESD EM Application
Features
Type Cell Capacitance Performance Optimization Example
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Optimum design for

~ 100 fF at
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PDB1AC ~ 1KV HBM No ultra-low-input LNA

steady state
capacitance
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For the domain ~ 300 fF at Optimum design for

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PDB2AC > 2KV HBM No LVDS

supplied by core steady state ESD robustness
voltage
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Optimum design for

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~ 600 fF at
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PDB3AC > 2KV HBM Yes
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steady state
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capacity
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~ 100 fF at
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PDB1A ~ 1KV HBM

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steady state
capacitance
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For the domain ~ 300 fF at

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supplied by I/O PDB2A > 2KV HBM No LVDS

steady state ESD robustness
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Optimum design for
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PDB3A
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> 2KV HBM Yes
both ESD robustness DAC
steady state and EM (current) ADC
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Note 1: The capacitance shown in Table 2.1 only considers the ESD protection devices.
For the total input capacitance, we also need to take account of bond pad, and inter-
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connection between I/O and analog macro. Since this information is library
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dependent, please refer to the library release note for details.
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Note 2: For signal integrity, the signal swing cannot exceed the power rail voltage (Core or
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I/O) by 0.3V, a diode turn on voltage. Similarly, the signal swing cannot go under
the ground rail voltage by 0.3V, a diode turn on voltage.
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Note 3: If analog signal cell is connected to the internal gate, it is required to insert the
secondary ESD protection devices as illustrated in Figure 2.3 to ensure optimal
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ESD protection. If analog signal cell is connected to the internal drain, either insert
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the secondary ESD protection devices as illustrated in Figure 2.4, or follow the
ESD guidelines specified in TSMC Design Rule Manual as illustrated in Figure 2.5.
For robust ESD protection, you need to avoid direct path to power or to ground
EC
through one gate oxide as illustrated in Figure 2.6.

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Note 4: For LNA, the “Expected ESD Performance” in Table 2.1 can only be applicable to
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the input path, but not the output.

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Note 5: Whileby: Vanita
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check, you need to insert the top-level signal net name (that
“AIO” pin is connected to) as the bond pad pin text of PDBxA/AC signal cell for
Organization: net nameF13780-College
consistency. of Engineering Pune (CoE
Continued on the following page
Note 6: The design of PDBxA / PDBxAC universal analog signal cells is not optimized for
ESD Machine-Model protection. However, TSMC can provide guidelines on how to
enhance Machine-Model ESD performance based on specific application. Please
contact TSMC if consulting service is needed.
In
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Condition One: Connect PDBxA / AC Analog

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Signal Pin to Internal Gate

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It is required to implement your own secondary ESD protection device (with proper
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channel length) as specified in the ESD guidelines of TSMC Design Rule Manual,
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where a resistor in series with a PMOS protection device to power and an NMOS
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protection device to ground should be used as illustrated below.
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Diode
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PDBxA / PDBxAC
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For internal signal connection, please avoid direct path to power or to ground through one gate oxide.
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Figure 2.3 Secondary ESD Protection Device to Internal Gate

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Condition Two: Connect PDBxA / AC Analog

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Signal Pin to Internal Drain

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It is required to implement your own secondary ESD protection device (with proper
channel length) as specified in the ESD guidelines of TSMC Design Rule Manual,
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where a resistor in series with a PMOS protection device to power and an NMOS
protection device to ground should be used as illustrated in Figure 2.4.
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Parasitic
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Power Diode
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Ground
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PDBxA / PDBxAC M
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Figure 2.4 Secondary ESD Protection Device Connected to The Drain Side of
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Internal Device
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If you cannot implement the secondary ESD protection device, you need to ensure
k
07
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that the internal P & N transistors (as indicated in yellow) closely follow the ESD
guidelines of TSMC Design Rule Manual. or
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2
at For internal signal connection,

Power
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Ground oxide
PDBxA / PDBxAC
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Figure 2.5 Internal P & N Transistor Need to Follow The ESD Guidelines
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Note: P & N transistors with drain side connected to the analog signal pin need to follow
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ESD guidelines, particularly the RPO ones as shown in Figure 2.6. Since P & N transistors
in this case have to be regarded as ESD devices, please waive the associated DRC errors.
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Poly RPO
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0.6
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Source
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RPO to Contact = x
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RPO to Poly= y
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RPO overlap Poly = z
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Figure 2.6 RPO Rules in ESD Guidelines (x, y; z varies, depending on the
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technology)
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Figure 2.7 shows the ESD scheme of PDBxA/AC cells. Note that the analog power
rail name (TACVDD) of PDBxAC is different from that (TAVDD) of PDBxA cells.
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AIO (to Analog / RF macro) AIO (to Analog / RF macro) AIO (to Analog / RF macro)
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TAVDD (power rail) TAVDD (power rail) TAVDD (power rail)

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ESD Device
TS ESD Device ESD Device
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ESD Device C ESD Device

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VSS (ground rail) C VSS (ground rail) VSS (ground rail)

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PDB1A
on 9 tro 01
PDB2A PDB3A
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fid 24 ni 8
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AIO (to Analog / RF macro)

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AIO (to Analog / RF macro) AIO (to Analog / RF macro)
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TACVDD (power rail)
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ESD Device
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ESD Device ESD Device
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VSS (ground rail) VSS (ground rail)
io VSS (ground rail)
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PDB1AC PDB2AC n PDB3AC

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Figure 2.7 The PDBxA/AC Power Scheme

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Analog Power Pad PVDD3A/AC
In
The PVDD3A/AC is the power cell to both analog macro and I/O power rail. Figure
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2.8 presents the simplified power diagram for PVDD3A/AC cells, where PVDD3AC
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is for supplying both analog macro and I/O power rail with the core voltage, while
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PVDD3A is for supplying both analog macro and I/O power rail with the I/O voltage.
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AVDD (to Analog / RF macro) AVDD (to Analog / RF macro)

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Dummy Resistor Dummy Resistor

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TACVDD
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ESD Device
fid 24 ni 8 ESD Device
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VSS tia VSS

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PVDD3AC
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Figure 2.8 The PVDD3A/AC Power Scheme or
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Table 2.2 summarizes PVDD3A/AC cells in detail. io
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Table 2.2 PVDD3A/AC Cell Description

Port Port Power &
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Cell Name Description

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to Core to Pad Ground

Power source for both analog
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macro and analog I/O power

TACVDD,
PVDD3AC AVDD TACVDD rail (voltage is the same as the
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VSS
pre-driver voltage of Digital
I/O)
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Power source for both analog

macro and analog I/O power
TAVDD,
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PVDD3A AVDD TAVDD rail (voltage is the same as the

VSS
post-driver voltage of Digital
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I/O)
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Regarding Vanita Agarwal
of PVDD3A/AC, let’s take PVDD3A as an example:

PVDD-3-A
In
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Analog power supplied by the I/O voltage

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Power pad for both analog macro and I/O power rail
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TS Power Pad
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Note: The maximum analog power (TAVDD / TACVDD) metal bus resistance from
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the “bonded” PVDD3A/PVDD3AC power cell to any PDBxA/AC analog I/O in the
C
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same domain needs to be less than 1 Ohm for N45/N65/N90 process technologies;
on 9 tro 01
less than 3 Ohm for 0.13µm/0.15µm/0.18µm/0.25µm process technologies. Please
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refer to Figure 10.2 of Universal Standard I/O General Application Note for details.
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Analog Ground Pad PVSS3A/AC

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Figure 2.9 presents the simplified power diagram for PVSS3A/AC cells, where
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PVSS3AC is the ground pad for PVDD3AC, and PVSS3A is the ground pad for
2
PVDD3A. at
AVSS (to Analog / RF macro) AVSS
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(to Analog / RF macro)
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TACVDD TAVDD

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VSS VSS
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PVSS3AC PVSS3A
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Figure 2.9 The PVSS3A/AC Power Scheme

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Note1: It is prohibited to implement the entire I/O ring with
PVDD3A/AC, PVSS3A/AC, and PDBxA/AC universal analog
I/O cells. If you must do so, please contact TSMC to have
PVSS3A/AC customized for this purpose.
In
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Note2: As illustrated in Figure 2.9, the VSS bus of PVSS3A/AC

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is floating in the universal analog I/O domain. Therefore, the

ni
VSS bus needs to be supplied by the “bonded” pre-driver ground

cell (PVSS1DGZ/CDG) in the adjacent universal standard I/O
TS
v
domain.
er
M
si
C
For ESD/Latch-Up considerations, it is required to make the VSS
ta
metal bus resistance from any PDBxA/AC cell (in universal

C
ir\
analog I/O domain) to the closest “bonded” PVSS1DGZ/CDG or

on 9 tro 01
PVSS3DGZ/CDG cell (in the adjacent universal standard I/O
M
domain) less than 1 ohm for N45/N65/N90 I/O; less than 3 ohm
fid 24 ni 8
ic
for 0.13µm/0.15µm/0.18µm/0.25µm I/O. Figure 2.10 illustrates

ro
this requirement.
en 762 ca\
-E
tia
In addition to the bonded PVSS1DGZ/CDG cell that needs to be
le
placed in the adjacent universal standard I/O domain, you also

lI
k
need to implement PVDD1DGZ/CDG, PVDD2POC, and

07
nf
PVSS2DGZ /CDG cells, so that the ESD power (VDD,
or
/0
VDDPST) & ground (VSSPST) buses in the adjacent universal

standard I/O domain are not floating either.
9/
m
2
at
Max. 1 Ohm VSS Bus Resistance for N45/N65/N90 I/O & 3 Ohm for 0.13um/0.15um/0.18um/0.25um I/O
io
C
n
en
PRCUTA
PVSS3A/AC
PVSS1DGZ
PVDD3A/AC
PVSS2DGZ
PDBxA/AC
tr
um
\\
(IM
PVDD2POC
PVDD1DGZ
Filler Cell
EC
\)\
vz
Universal Analog I/O Domain Universal Standard I/O Domain

w
Downloaded by:
Figure 2.10 Vanita
The VSS Bus Agarwal
of Universal Analog I/O Cells Is Supplied By
PVSS1DGZ/CDG Pre-Driver Ground Cell in the Adjacent
Universal Standard I/O Domain
Table 2.3 PVSS3A/AC Cell Description
Port Port Power &
Cell Name Description
to Core to Pad Ground
In
TACVDD, Ground provider used with

PVSS3AC AVSS AVSS
te
VSS PVDD3AC power cell

ru
TAVDD, Ground provider used with

PVSS3A AVSS AVSS
VSS PVDD3A power cell
ni
TS
v
The ESD clamping device implemented within the PVDD3A/AC analog power cells
er
can solidify the whole-chip ESD protection. Therefore, in addition to filler cells, you
M
si
can also consider to insert PVDD3A/AC to the empty space in between universal
C
ta
analog I/O cells, with the trade-off in increasing stand-by leakage current.
C
ir\
on 9 tro 01
M
fid 24 ni 8
ic
ro
en 762 ca\
Filler Cell PFILLERxA Family & Corner Cell
-E
tia
PCORNERA
le
lI
k
07
nf
Similar to Digital I/O, Analog I/O library provides filler cells and corner cell. Since
or
/0
these cells are designed for analog domain, you can insert the filler cells or corner cell
(if necessary), and have them abutted with the neighboring Analog I/O.
9/
m
2
at
While inserting filler cell, DO NOT use smaller filler cells to fill large I/O spacing.
For example, use one 20µm pitch filler cell (PFILLER20A) and one 10µm pitch filler
io
C
cell (PFILLER10A) instead of using 6 “5µm pitch” filler cells (PFILLER5A) to fill
n
en
30µm spacing. Doing so is to avoid potential metal slot DRC violation.

tr
Please refer to the library release note or library databook for the available filler cell
um
names.
\\
(IM
Power Cut Adapter Cell PRCUTA

EC
The power-cut adapter cell (PRCUTA) can be used for the following purposes:
\)\
• To bridge the interface between TSMC universal analog I/O domain and TSMC
vz
universal standard I/O domain.

• To bridge the interface between TSMC universal analog I/O domain and another
w

TSMC universal analog I/O domain with different supplied voltage.
• To bridge the interface between TSMC universal analog I/O domain and another
TSMC universal analog I/O domain with the same supplied voltage particularly for
noise isolation purpose.
There is no limitation on the number of power domains separated by PRCUTA on
the same chip, if and only if customers use TSMC universal I/O cells in the entire
I/O ring. Note that using any 3rd party IP is beyond TSMC’s guarantee.
In
te
Place PRCUTA between Analog Domain and

ru
Digital Domain
ni
TS
v
The design principle of the power-cut adapter cell is to short the analog ground rail
er
(VSS) with the digital pre-driver ground rail (VSS), while leaving the power rails
M
si
open. Please refer to Figure 2.11 for illustration.

C
ta
C
ir\
TAVDD/TACVDD (Analog Power Rail) on 9 tro 01 VDD (Pre-driver Power Rail)

M
VSS (Analog Ground Rail) fid 24 ni 8 VSS (Pre-driver Ground Rail)

ic
VDD33 or VDDPST (Post-driver Power Rail)

ro
en 762 ca\
-E
tia
le
lI
k
07
nf VSSPST (Post-driver Ground Rail)

or
/0
Analog Domain Digital Domain

9/
m
Figure 2.11 PRCUTA as an Adapter Cell between Analog and Digital Domain
2
at
io
C
n
en
Attention!!!
tr
um
For short ESD discharge path, you need to place PVDD1DGZ/CDG cell (from TSMC
universal standard I/O library) near the PRCUTA cell on the Digital side.
\\
(IM
What You Should Know When You Bridge

Between TPAxxxGV Universal Analog I/O and
EC
Staggered Universal Standard I/O through

\)\
PRCUTA Adapter Cell

vz
TPAxxxGV universal analog I/O can only support non-CUP wire bond for ultra low-
w

cap purpose. Since the total height of TPAxxxGV universal analog I/O together with
the non-CUP bond pad equals the height of staggered universal standard I/O itself,
we suggest you adopt CUP wire bond in the domain implemented with staggered
universal standard I/O for area-saving concern.
However, to avoid metal short of the CUP Pad top metal and the PRCUTA top
metal , you need to insert enough filler cells from the “mt_2” back-end
directory of the staggered universal standard I/O library, as illustrated in Figure 2.12.
In
te
ru
Universal Analog I/O
PRCUTA Adapter Cell
Universal Standard I/O

ni
CUP WB
TS
v er
M
si
C
ta
C
ir\
on 9 tro 01
M
Filler Cell
CUP WB
Non-CUP WB
fid 24 ni 8
ic
ro
en 762 ca\
-E
tia
le
lI
k
07
nf
From metal 1 to metal top - 2
or
/0
Figure 2.12 Filler Cell Insertion Between PRCUTA Adapter Cell & Staggered
Universal Standard I/O with CUP Bond Pad
9/
m
2
at
io
C
n
en
What You Should Know When You Bridge

tr
Between TPAxxxNV Universal Analog I/O and

um
Linear Universal Standard I/O through

\\
PRCUTA Adapter Cell

(IM
TPAxxxNV universal analog I/O compatible with linear universal standard I/O can
EC
support non-CUP wire bond or CUP wire bond application. Since the height of
TPAxxxNV universal analog I/O without the bond pad is exactly the same as the
\)\
height of linear universal standard I/O without the bond pad, you may consider to
adopt non-CUP wire bond for both TPAxxxNV universal analog I/O and linear
vz
universal standard I/O, or consider to adopt CUP wire bond for both TPAxxxNV
w
universal analog I/O and linear universal standard I/O for area-saving concern.
Though using CUP pad with TPAxxxNV universal analog I/O could save area, CUP
bond pad would impact the total input capacitance, which might be detrimental to RF
application. Therefore, we suggest non-CUP wire bond for RF application.
In
te
Universal Standard I/O

PRCUTA Adapter Cell
Universal Analog I/O
ru
ni
TS
v er
M
si
C
ta
C
ir\
on 9 tro 01
M
fid 24 ni 8
ic
Non-CUP WB
Non-CUP WB
ro
en 762 ca\
-E
tia
le
lI
k
07
nf
TPAxxxNV universal analog I/O can support either
or
/0
non-CUP wire bond or CUP wire bond application.

9/
m
Figure 2.13 Non-CUP Wire Bond with TPAxxxNV Universal Analog I/O &
2
at
Linear Universal Standard I/O io
C
n
en
Place PRCUTA between Two Analog Domains

tr
The PRCUTA adapter cell can be placed between two analog domains under the
um
following conditions:
• Between two analog domains with different supplied voltage
\\
• Between two analog domains with the same supplied voltage for noise concern.
(IM
EC
Two Analog Domains with Different Supplied

Voltage
\)\
vz
The design principle of PRCUTA adapter cell is to short the analog ground rail (VSS)
of one analog domain supplied by one voltage source with that of another analog
w

domain supplied by another voltage source, while leaving the power rails open.
Please refer to Figure 2.14 for illustration.
TACVDD (Core-Voltage Analog Power Rail) TAVDD (I/O Voltage Analog Power Rail)
VSS (Analog Ground Rail) VSS (Analog Ground Rail)
In
te
ru
ni
TS
v er
M
si
Analog Domain A
C Analog Domain B
ta
Figure 2.14 PRCUTA as Adapter Cell between Two Analog Domains with
C
ir\
Different Supplied Voltages (e.g. core voltage versus I/O voltage)

on 9 tro 01
M
fid 24 ni 8
ic
ro
en 762 ca\
-E
Two Analog Domains with the Same Supplied

tia
le
Voltage lI
k
07
nf
For noise concern, you may consider to place PRCUTA adapter cell between two
or
/0
analog domains with the same supplied voltage. Doing so can considerably isolate
9/
the noise effect induced from the other. Please refer to Figure 2.15 for illustration.
m
2
at
io
C
TACVDD (Core-Voltage Analog Power Rail) TACVDD (Core-Voltage Analog Power Rail)
n
en
VSS (Analog Ground Rail) VSS (Analog Ground Rail)

tr
um
\\
(IM
EC
Analog Domain A Analog Domain B

\)\
vz
Figure 2.15 PRCUTA Used for Noise Isolation

w

How To Use TPAxxxGV Universal Analog I/O
with Bond Pad Cell
In
TPAxxxGV (where xxx is technology code) universal analog I/O comes with “gv”
te
suffix in the library name, indicating that this library can be compatible with
ru
universal standard I/O that comes with “gv” suffix through adapter cell. For example,
ni
tpan65lpgv2 universal analog I/O can be compatible with tpzn65lpgv2 universal

standard I/O through PRCUTA adapter cell.
TS
v er
M
si
Non-CUP In-Line Wire-Bond C

ta
C
TPAxxxGV universal analog I/O can only support non-CUP wire-bond with in-line
ir\
on 9 tro 01
style. Users can select PADxA/AM or PADxAR/ARM bond pads based on the target
M
pad pitch and application. Please refer to the following section for usage instruction.
fid 24 ni 8
For the pad pitch bigger than the I/O cell width, you need to insert appropriate
ic
number of filler cells as instructed in “Filler cell PFILLERxA family & Corner cell
ro
PCORNERA” section of Chapter 2.

en 762 ca\
-E
tia
le
PADxA/AM and PADxAR/ARM Bond Pads for lI

k
0.13µm / 0.18µm TPAxxxGV Universal Analog

07
nf
I/O Library
or
/0
9/
m
Two types of bond pad available from TPBxxxGV bond-pad library can be used for
2
at
0.13µm/0.18µm TPAxxxGV universal analog I/O, PADxA/AM and PADxAR/ARM.
Please refer to Table 2.5 for usage instruction.
io
C
n
en
Table 2.5 Bond Pads for 0.13µm/0.18µm TPAxxxGV Universal Analog I/O
tr
Cell Name Metal Layer Description Where to Find

um
Used with
PADxA From Metal 1 to PDB3A/AC, Under the "wb" directory of the
\\
PADxAM Metal Top PVDD3A/AC, corresponding bond pad library

(IM
PVSS3A/AC
EC
Used with
PADxAR From Metal Top-1 Under the "wb" directory of the
PDB1A/AC,
PADxARM to Metal Top corresponding bond pad library
PDB2A/AC
\)\
vz
w

Figure 2.16 shows where to locate the bond pads for 0.13µm/0.18µm TPAxxxGV
universal analog I/O library.
1 thick top metal PADxA
In
(1 large top via) PADxAR

te
wb directory 2 thick top metals

ru
TPBxxxGV (2 large top vias) PADxAM

ni
Bond Pad Library

TS for mixed-mode PADxARM
v
process
er
M
si
C
ta
Figure 2.16 The Non-CUP Bond Pads for 0.13µm/0.18µm TPAxxxGV Universal
C
Analog I/O Library
ir\
on 9 tro 01
M
fid 24 ni 8
ic
Note 1: The “x” of PADxA / PADxAM / PADxAR / PADxARM is the pad pitch. For
ro
en 762 ca\
example, PAD60A comes with “60µm” pad pitch.
-E
tia
Note 2: For 0.13µm/0.18µm application with top two thick metals and top two large
le
VIAs for the mixed-mode process, you need to use the bond pad with suffix “M”. For
lI
k
instance, use PADxAM as the bond pad for PDB3A/AC, PVDD3A/AC, and
07
nf
PVSS3A/AC. Similarly, use PADxARM as the bond pad for PDB1A/AC and
PDB2A/AC.
or
/0
9/
m
Note 3: Please read special notes on page 21 & 22.
2
at
io
C
n
en
tr
PADxA and PADxAR Bond Pads for 90nm/

um
65nm/45nm TPAxxxGV Universal Analog I/O

Library
\\
(IM
For 90nm & other advanced technologies, because of complex metallization options,
you will not find PADxAM & PADxARM bond pads in the bond pad library. Instead,
EC
you can only see PADxA & PADxAR bond pads under each specific back-end
directory that is named by metal scheme. For example, you can find PADxA &
\)\
PADxAR GDS from 9M_6X2Z directory, where 9M indicates 9 metal layer; 6X2Z
indicates 6 metal layers with X metallization and top 2 metal layers with Z metallization.
vz
Please refer to the table of “Metallization Options” in TSMC Design Rule Manual for
w

definition. Also, please refer to Figure 2.17 for illustration, and Table 2.6 for usage
instruction.
Table 2.6 Bond Pads for 90nm/65nm/45nm TPAxxxGV Universal Analog I/O
Used with
In
From Metal 1 to PDB3A/AC, Under the "wb" directory of the

PADxA
te
Metal Top PVDD3A/AC, corresponding bond pad library

PVSS3A/AC
ru
ni
Used with
TS From Metal Top-1 Under the "wb" directory of the
v
PADxAR PDB1A/AC,
to Metal Top corresponding bond pad library
er
M PDB2A/AC
si
C
ta
C
ir\
on 9 tro 01
M
fid 24 ni 8 PADxA
9lm/9M_6X2Z
ic
PADxAR
ro
en 762 ca\
wb directory
PADxA
-E
tia 6lm/6M_3X2Y
TPBxxxGV PADxAR
le
Bond Pad Library lI

k
07
nf
or
/0
9/
m
2
at
Figure 2.17 The Non-CUP Bond Pads for 90nm/65nm/45nm TPAxxxGV
Universal Analog I/O Library
io
C
n
en
tr
um
Special Notes
\\
(IM
Note 1: For low input capacitance purpose, TPAxxxGV universal analog I/O is
designed for the non-CUP wire bond, but not for the CUP application.
EC
Note 2: For the double-pitch cell width, you need to connect “TWO” bond pads as
\)\
illustrated in Figure 2.18. Align the left edge of one bond pad pr-boundary with the left
edge of double-pitch cell pr-boundary, and align the right edge of the other bond pad pr-
vz
boundary with the right edge of double-pitch cell pr-boundary.

w
DownloadedNoteby:
3: WhileVanita
using PDB1A/ACAgarwal
and PDB2A/AC I/O cells, you need to insert the dummy
metal blockage layer to both the I/O cell and the PADxAR/ARM bond pads to ensure the
low input of Engineering
capacitance. However, doing so might Pune
lead to insufficient metal density errors. (CoE
Please contact TSMC Product Engineer for waive-ability.
Note 4: Misuse of PADxAR/ARM to PDB3A/AC, PVDD3A/AC; PVSS3A/AC would
result in open problem!
Note 5: Misuse of PADxA/AM to PDB1A/AC; PDB2A/AC would result in high bond-

In
pad capacitance!
te
ru
ni
TS
v er
M
si
C Double-Pitch Cell
ta
C
ir\
Align Here on 9 tro 01 Align Here

M
fid 24 ni 8
ic
ro
en 762 ca\
-E
tia
Bond Pad Bond Pad
le
lI
k
07
nf
or
/0
9/
m
2
at
Figure 2.18 Two Bond Pads Required for the Double-Pitch Cell
io
C
n
en
tr
um
How To Use TPAxxxNV Universal Analog I/O

\\
with Bond Pad Cell

(IM
EC
TPAxxxNV (where xxx is technology code) universal analog I/O comes with “nv”
suffix in the library name, indicating that this library can be compatible with the linear
\)\
universal standard I/O that comes with “nv” suffix through adapter cell. For example,
tpan90lpnv3 universal analog I/O can be compatible with tpdn90lpnv3 linear universal
vz
standard I/O through PRCUTA adapter cell.

w
Downloaded by: universal

TPAxxxNV VanitaanalogAgarwal
I/O can support non-CUP wire-bond or CUP wire-bond
with in-line style.
Non-CUP In-Line Wire-Bond
For TPAxxxNV universal analog I/O library, you need to access back-end
In
database under “mt” directory.

te
For TPBxxxNV bond pad library, you need to access back-end database under
ru
“wb” directory
ni
Users can select PADxA/AM or PADxAR/ARM bond pads based on the target pad
TS
v
pitch and application. Please refer to the following section for usage instruction. For
er
the pad pitch bigger than the I/O cell width, you need to insert appropriate number of
M
si
filler cells as instructed in “Filler cell PFILLERxA family & Corner cell PCORNERA”
C
section of Chapter 2.
ta
C
ir\
on 9 tro 01
M
fid 24 ni 8
PADxA/AM and PADxAR/ARM Bond Pads for
ic
ro
en 762 ca\
0.13µm / 0.18µm TPAxxxNV Universal Analog I/O
-E
Library
tia
le
lI
Two types of non-CUP bond pads available from TPBxxxNV bond-pad library can be
k
07
nf
used for 0.13µm/0.18µm TPAxxxNV universal analog I/O, PADxA/AM and
PADxAR/ARM. Please refer to Table 2.7 for usage instruction.
or
/0
9/
m
Table 2.7 The Non-CUP Bond Pads for 0.13µm/0.18µm TPAxxxNV Universal
2
Analog I/O at
Cell Name Metal Layer
io
Description Where to Find
C
n
en
Used with
PADxA From Metal 1 to PDB3A/AC, Under the "wb" directory of the
tr
PADxAM Metal Top PVDD3A/AC, corresponding bond pad library

um
PVSS3A/AC
\\
Used with
PADxAR From Metal Top-1 Under the "wb" directory of the
PDB1A/AC,
(IM
PADxARM to Metal Top corresponding bond pad library

PDB2A/AC
EC
\)\
Figure 2.19 shows where to locate the non-CUP bond pads for 0.13µm/0.18µm
vz
TPAxxxNV universal analog I/O library.

w

PADxA
1 thick top metal
(1 large top via) PADxAR
In
wb directory 2 thick top metals

PADxAM
TPBxxxNV (2 large top vias)
te
Bond Pad Library for mixed-mode

ru
PADxARM
process
ni
TS
v er
Figure 2.19 The Non-CUP Bond Pad for 0.13µm/0.18µm TPAxxxNV Universal
M
si
Analog I/O C
ta
Note 1: The “x” of PADxA / PADxAM / PADxAR / PADxARM is the pad pitch. For
C
ir\
example, PAD60A comes with “60µm” pad pitch.

on 9 tro 01
M
Note 2: For 0.13µm/0.18µm application with top two thick metals and top two large
fid 24 ni 8
ic
VIAs for the mixed-mode process, you need to use the bond pad with suffix “M”. For
instance, use PADxAM as the bond pad for PDB3A/AC, PVDD3A/AC, and
ro
en 762 ca\
PVSS3A/AC. Similarly, use PADxARM as the bond pad for PDB1A/AC and
-E
PDB2A/AC.
tia
le
lI
Note 3: Please read special notes on page 25 & 26.
k
07
nf
or
/0
9/
m
PADxA and PADxAR Bond Pad for
2
at
90nm/65nm/45nm TPAxxxNV Universal Analog io
C
I/O Library n
en
tr
you will not find PADxAM & PADxARM bond pads in the bond pad library. Instead,
um
you can only see PADxA & PADxAR bond pads under each specific back-end
directory that is named by metal scheme. For example, you can find PADxA &
\\
PADxAR GDS from 9M_6X2Z directory, where 9M indicates 9 metal layer; 6X2Z
(IM
indicates 6 metal layers with X metallization and top 2 metal layers with Z metallization.
Please refer to Figure 2.20 for illustration, and Table 2.8 for usage instruction.
EC
\)\
vz
w

Table 2.8 Non-CUP Bond Pads for 90nm/65nm/45nm TPAxxxNV Universal
Analog I/O
In
Used with
te
From Metal 1 to PDB3A/AC, Under the "wb" directory of the

PADxA
ru
Metal Top PVDD3A/AC, corresponding bond pad library

PVSS3A/AC
ni
TS
v
Used with
From Metal Top-1 Under the "wb" directory of the
er
PADxAR PDB1A/AC,
Mto Metal Top corresponding bond pad library
PDB2A/AC
si
C
ta
C
ir\
on 9 tro 01
M
fid 24 ni 8
ic
PADxA
9lm/9M_6X2Z
ro
en 762 ca\ PADxAR

-E
wb directory
tia
TPBxxxNV PADxA
le
Bond Pad Library lI 6lm/6M_3X2Y

PADxAR
k
07
nf
or
/0
9/
m
Figure 2.20 The Non-CUP Wire-Bond Bond Pads for 90nm/65nm/45nm
2
at
TPAxxxNV Universal Standard I/O Library io
C
n
en
tr
um
Special Notes
\\
Note 1: For the double-pitch cell width, you can connect “TWO” bond pads by
(IM
aligning the left edge of bond-pad pr-boundary with the left edge of double-pitch cell
pr-boundary, and by aligning the right edge of the other bond-pad pr-boundary with the
EC
right edge of double-pitch-cell pr-boundary as shown in Figure 2.21.

\)\
Note 2: While using PDB1A/AC and PDB2A/AC I/O cells, you need to insert the dummy
metal blockage layer to both the I/O cell and the PADxAR/ARM bond pads to ensure the
vz
low input capacitance. However, doing so might lead to insufficient metal density errors.
Please contact TSMC Product Engineer for waive-ability.
w

Note 3: Misuse of PADxAR/ARM to PDB3A/AC, PVDD3A/AC; PVSS3A/AC would
Organization:
result inF13780-College
open problem! of Engineering Pune (CoE
Note 4: Misuse of PADxA/AM to PDB1A/AC and PDB2A/AC would result in high
bond-pad capacitance!
In
te
ru
ni
TS
v
Double-Pitch Cell
er
M
si
Align Here C Align Here

ta
C
ir\
on 9 tro 01
M
fid 24 ni 8
ic
ro
Bond Paden 762 ca\ Bond Pad

-E
tia
le
lI
k
07
nf
Figure 2.21 Two Bond Pads Required for the Double-Pitch Cell
or
/0
9/
m
2
at
CUP In-Line Wire-Bond io
C
n
en
For TPAxxxNV universal analog I/O library, you need to select back-end database
under “mt_2” directory. Please refer to Figure 2.23 for example.
tr
um
For TPBxxxNV bond pad library, you need to access back-end database under
“cup” directory, and select PADxARU / PADxARMU CUP pad as shown in Table
\\
2.9.
(IM
Table 2.9 CUP Bond Pad for TPAxxxNV Universal Analog I/O
EC

Used with
\)\
PDB1A/AC,
Under the "cup" directory of the
PADxARU PDB2A/AC
vz
Top 2 corresponding TPBxxxNV bond

PADxARMU PDB3A/AC,
pad library
PVDD3A/AC,
w
Downloaded by: Vanita Agarwal PVSS3A/AC

Please refer to the following section for bond pad usage instruction in different
technologies. For the pad pitch bigger than the I/O cell width, it is necessary to insert
the appropriate number of filler cells as instructed in “Filler cell PFILLERxA family &
Corner cell PCORNERA” section of Chapter 2.
In
te
PADxARU / PADxARMU CUP Pad for 0.13µm/

ru
0.18µm TPAxxxNV Universal Analog I/O Library

ni
TS
v er
Note 1: For CUP application, you need to insert the routing

M
si
blockage layers in the top two metals first, and then route the
C
internal signal afterwards.
ta
C
ir\
on 9 tro 01
Note 2: Though using CUP with TPAxxxNV universal analog
M
I/O could save area, CUP bond pad would significantly increase
fid 24 ni 8
ic
the total input capacitance, which might be detrimental to RF

application.
ro
en 762 ca\
-E
tia
Note 3: For the double-pitch cell width, you can connect
le
“TWO” CUP pads by aligning the left edge of CUP pad pr-
lI
boundary with the left edge of double-pitch-cell pr-boundary,
k
07
nf
and by aligning the right edge of the other CUP pad pr-boundary
with the right edge of double-pitch-cell pr-boundary.
or
/0
9/
m
Figure 2.22 shows where to locate the CUP pads for 0.13µm/0.18µm TPAxxxNV
2
universal analog I/O library.

at
io
C
n 1 thick top metal

en
PADxARU
TPBxxxNV (1 large top via)
tr
Bond Pad Library cup directory 2 thick top metals

um
(2 large top vias)

for mixed-mode PADxARMU
\\
process
(IM
Figure 2.22 The CUP Bond Pads for 0.13µm/0.18µm TPAxxxNV Universal
EC
Analog I/O
\)\
vz
Note 1: The “x” of PADxARU / PADxARMU is the pad pitch. For example,
PAD60ARU comes with “60µm” pad pitch.
w

Note 2: For 0.13µm/0.18µm CUP application with top two thick metals and top two
large VIAs for the mixed-mode process, youofneedEngineering
to use PADxARMU CUP pad, Pune
where (CoE
the character “M” indicates that this CUP pad comes with top two thick metals.
For example, to tape out 6 layer metal gds with one top thick metal and one top
large VIA in 0.13µm:
For universal analog I/O cell, use 6lm gds under “mt_2” directory within the gds
In
kit, where 6lm gds contains metal 1 to metal 4, leaving space in metal 5 and 6
empty.
te
For CUP bond pad, use 6lm gds under “cup” directory within the gds kit, where
ru
6lm gds contains metal 5 to metal 6.

ni
TS
v
I/O: 6lm gds Bond Pad: 6lm gds

er
under mt_2 directory

M under cup directory
si
C
ta
C One top thick metal Metal 6

ir\
on 9 tro 01 One top large VIA VIA 56

Metal 5
M
fid 24 ni 8 VIA 45
ic
VIA 45
Metal 4
ro
en 762 ca\ PADxARU CUP Bond Pad

VIA 34
-E
VIA 56 Metal 3
tia
le
VIA 23 lI
k
Metal 2
07
VIA 12
nf
or
/0
Metal 1
9/
TPAxxxNV Universal Analog I/O

m
2
at
Figure 2.23 Illustration of GDS Kit Under “mt_2” and “cup” Directories for
0.18µm/0.13µm CUP Application io
C
n
en
tr
Reminder: If you need top 2 thick metals, all you have to do is replace PADxARU
um
above with PADxARMU CUP pad.

\\
(IM
PADxARU for 90nm/65nm/45nm Universal

EC
Analog I/O Library

\)\
vz
you will not find PADxARMU CUP pad in the bond pad library. Instead, you can only
see PADxARU CUP pad under each specific back-end directory that is named by metal
w

scheme. For example, you can find PADxARU GDS from 9M_6X2Z directory, where
9M indicates 9 metal layer; 6X2Z indicates 6 metal layers with X metallization and top
2 metal layers with Z metallization. Please refer to Figure 2.24 for illustration.

9lm/9M_6X2Z PADxARU
In
TPBxxxNV cup directory

te
Bond Pad Library

6lm/6M_3X2Y PADxARU
ru
ni
TS
v
Figure 2.24 The CUP Bond Pad for 90nm/65nm/45nm TPAxxxNV Universal
er
Analog I/O
M
si
C
ta
C
ir\
on 9 tro 01
M
fid 24 ni 8
ESD Core-Clamp PCLAMP Cell
ic
ro
en 762 ca\
For ESD robustness in the “core-voltage” analog domain implemented with universal
-E
tia
analog I/O cells, you need to place ESD core-clamp “PCLAMP” cell in either of the
le
following two approaches. lI

k
07
nf
Approach A: Place PCLAMP Cell in between or
/0
Analog Macro and PVDD3AC & PVSS3AC Cells

9/
m
2
at
Step 1: Place analog power PVDD3AC and analog ground PVSS3AC cells together.
io
C
Step 2: Place PCLAMP cell in between (the PVDD3AC & PVSS3AC pairs) and
n
en
internal core.
tr
Step 3: Connect from AVDD pin of PVDD3AC analog power cell to VDDESD pin of
um
PCLAMP cell through Metal 3.

\\
Step 4: Connect from AVSS pin of PVSS3AC analog ground cell to VSSESD pin of
PCLAMP cell through Metal 3.
(IM
Step 5: Connect from VDDESD and VSSESD rails of PCLAMP cell to internal power
EC
rail and ground rail respectively, as illustrated in Figure 2.25.

\)\
vz
w

Analog Macro
In
te
To Internal Core Power & Ground

ru
ni
TS
v
PCLAMP
er
VSSESD Pin Box (Metal 3) M VDDESD Pin Box (Metal 3)

si
C
ta
AVSS Pin Box (Metal 1, 2) C AVDD Pin Box (Metal 1, 2)

ir\
on 9 tro 01
M
fid 24 ni 8
ic
PVSS3AC
PVDD3AC
ro
Metal 3
en 762 ca\
-E
tia
le
VIA Mesh lI
k
07
Metal 1, 2
nf
Non-CUP WB
Non-CUP WB
or
/0
9/
m
2
at
io
C
n
en
Figure 2.25 Place PCLAMP Cell in Analog Macro

tr
um
\\
(IM
EC
Attention: If you do not place PCLAMP cell together with PVDD3AC & PVSS3AC
pair, ESD performance would be degraded.
\)\
vz
w

Approach B: Place PCLAMP Cell in between The
Bond Pads of PVDD3AC and PVSS3AC
In
Step 1: Insert enough filler cells between PVDD3AC and PVSS3AC.

te
Step 2: Place PCLAMP cell between the bond pads of PVDD3AC & PVSS3AC, and
ru
have PCLAMP cell “away” from the die edge (i.e. closer to filler-cell region as
ni
illustrated in Figure 2.26.

TS
v
Step 3: Connect to the bond pad of PVDD3AC and the bond pad of PVSS3AC
er
respectively though METAL 3 as illustrated in Figure 2.27.

M
si
C
ta
Step 4: Run DRC to ensure that there will be no rule violation.

C
ir\
on Filler9Cells tro 01
M
fid 24 ni 8
ic
PVSS3AC
PVDD3AC
ro
en 762 ca\
-E
tia
le
lI
k
07
nf Non-CUP WB
or
/0
9/
m
2
at
Non-CUP WB
io
C
PCLAMP n
en
tr
um
\\
Place PCLAMP cell away from the die edge

(IM
Figure 2.26 Place PCLAMP Cell between The Bond Pads of PVDD3AC and
PVSS3AC
EC
Figure 2.26
\)\
METAL 3
vz
w

In
te
ru
ni
TS
v er
M
si
C
ta
C
ir\
on 9 tro 01
M
fid 24 ni 8
ic
ro
en 762 ca\
-E
tia
le
lI
k
07
nf
or
/0
9/
m
2
at
Figure 2.27 Connect from PCLAMP Cell to The Bond Pads of PVDD3AC and
io
PVSS3AC through Metal 3 (in blue)
C
n
en
tr
um
\\
(IM
Attention: If you do not place PCLAMP cell together with PVDD3AC & PVSS3AC
pair, ESD performance would be degraded.
EC
\)\
vz
w

Chapter 3 Application Examples
This chapter illustrates examples for different types of applications. It is crucial to
In
use the right cells for performance achievement and quality concern. Please contact
te
TSMC regional application engineers if you have any other application-related

ru
questions.
ni
Table 3.1 shows the general rule of thumb, depending on the application type.
TS
v er
Table 3.1 Cell Usage Combination

M
si
Analog Analog C Analog ESD

Power Domain
ta
Signal Cell Power Cell

C Ground Cell CORE CLAMP
ir\
PDB1AC on 9 tro 01 The same as the pre-

PDB2AC PVDD3AC PVSS3AC PCLAMP driver voltage of digital
M
PDB3AC
fid 24 ni 8 I/O
ic
PDB1A The same as the post-

ro
PDB2A PVDD3A
en 762 ca\
PVSS3A Not Applicable driver voltage of digital
-E
PDB3A
tia I/O
le
lI
k
Example 1: Using PRCUTA cell to separate

07
nf
digital/analog domains or to separate
or
/0
9/
analog/analog domains (with different supplied

m
2
voltage)
at To Analog macro
io
C
To Analog macro
n
en
PCLAMP
AVDD AIO AVSS
AVDD AVSS AIO
tr
um
VDD TAVDD TACVDD VDD

\\
P P
ESD Device ESD Device ESD Device ESD Device
P R R
(IM

R C C
C U U
U T T
EC
T ESD Device A A
ESD Device ESD Device ESD Device
A
\)\
VSS VSS VSS

VSS
vz
PVDD3A PDBxA PVSS3A PVDD3AC PVSS3AC PDBxAC

w
Downloaded
Digital by: Vanita Agarwal Core-Voltage
I/O Voltage Digital
Domain B Analog Power Domain Analog Power Domain Domain A
Downloaded on:
Figure 09/11/2023
3.1 Application Example 1 Using PRCUTA
DESCRIPTION
Referred to Figure 3.1, PVDD3A is the power supply in I/O-voltage analog power
In
domain and PVDD3AC is the power supply in core-voltage analog power domain.
te
(a). In I/O-voltage analog power domain: PVSS3A and PDBxA are used with
PVDD3A.
ru
(b). In core-voltage analog power domain: PVSS3AC and PDBxAC are used with
ni
PVDD3AC. Besides, PVDD3AC and PVSS3AC need to be connected to PCLAMP

TS
v
cell.
er
(c). The power-cut adapter cell PRCUTA can be used to separate the analog power
M
domains supplied with different voltage.
si
(d). The power-cut adapter cell PRCUTA can also be used to separate the analog
C
ta
domain from the digital domain, as indicated on the left and right sides of Figure 3.1
C
ir\
(e). There is no limitation on the number of power domains.

on 9 tro 01
M
fid 24 ni 8
ic
ro

en 762 ca\
-E

tia
le
analog/analog domains (with the same I/O lI

k
07
voltage)
nf
or
/0
To Analog macro
9/
m To Analog macro
2
AVDD AIO AVSS

at
AVDD AIO AVSS
io
C
VDD
n
en
TAVDD TAVDD VDD

tr
P P
P ESD Device ESD Device R ESD Device ESD Device R
um
R ESD Device C ESD Device C

C U U
U T T
T A A
\\
A ESD Device ESD Device ESD Device ESD Device

(IM
VSS VSS VSS

VSS
EC
PVDD3A PDBxA PVSS3A PVDD3A PDBxA PVSS3A

Digital
\)\
Digital
I/O-Voltage I/O-Voltage Domain A
Domain B
vz
Analog Power Domain Analog Power Domain

w
Downloaded by:
Figure Vanita
3.2 Application Agarwal
Example 2 Using PRCUTA

DESCRIPTION
In
Similar to Example 1, Figure 3.2 illustrates that PRCUTA cell can also be used in
te
between two analog domains with the same I/O voltage just for noise concern.
ru
ni
TS
v

er
M
si
C
ta
analog/analog domains (with the same core

C
ir\
voltage) on 9 tro 01
M
fid 24 ni 8
ic
To Analog macro To Analog macro

ro
en 762 ca\
-E
PCLAMP
tia PCLAMP
le
AVDD AVSS AIO

lI AVDD AVSS AIO
k
07
nf
VDD TACVDD or TACVDD VDD
/0
9/
P ESD Device ESD Device

P
R
m ESD Device ESD Device
P
R
2
R ESD Device C ESD Device

at C
C U U
U T io T
T A
C
A
A ESD Device ESD Device ESD Device ESD Device
n
en
VSS VSS VSS VSS

tr
um
PVDD3AC PVSS3AC PDBxAC PVDD3AC PVSS3AC PDBxAC
Digital Digital
\\
Core-Voltage Core-Voltage Domain A

Domain B
(IM
Analog Power Domain Analog Power Domain

EC
Figure 3.3 Application Example 3 Using PRCUTA

\)\
DESCRIPTION
vz
w

Similar to Example 2, Figure 3.3 illustrates that PRCUTA cell can also be used in
between two analog domains with the same core voltage just for noise concern.
Chapter 4 Library Integration Notes
In
Integration of Library Tape-out Layers

te
ru
To correctly tape out with TSMC I/O library, users must refer to the
corresponding “Masking Layers & Bias” document at TSMC Online for the most
ni
updated mask tooling layers and operation/bias equations. The following include
TS
v
important notes that users must review prior to tape-out.

er
M
si
GDSII Number Mapping

C
ta
C
ir\
For libraries from different vendors, the GDSII numbers defined for each process
on 9 tro 01
layer and dummy layers could be different. Please follow the definition in the
M
fid 24 ni 8
“GDS Layer Usage Description File” of the corresponding technology that is
ic
downloadable from TSMC online.

ro
en 762 ca\
Warning: The mixing or wrong mapping of GDSII layers could
-E
result in a serious mask problem and silicon failure.

tia
le
lI
k
07
nf
OD Mask or
/0
9/
m
According to the “GDS Layer Usage Description File," there are two methods for
2
defining the OD region in GDSII: One method is to use DIFF; another, is to use
at
(PDIFF+NDIFF). Different libraries may have their preferences and users must
io
C
tape out all the GDSII layers related to an OD mask, or the chip may fail. It’s
n
en
suggested to tape out the OD layer with (DIFF or PDIFF or NDIFF) to ensure all
the OD layout styles are included in the OD mask tooling.
tr
um
ESD Mask
\\
(IM
Different GDSII layers are defined for ESD implant: masks (110) and (111).
Though the ESD implant is optional in process steps, taping out the ESD mask
EC
(111) is strongly recommended to improve ESD margins. You need to make sure
all the ESD-related GDSII layers are taped out correctly according to the
\)\
“Masking Layers & Bias” table. Please check the release note for the special
equation.
vz
w

Poly Resistor
To ensure that the poly resistor and SPICE model match, users can tape out
dummy layers (such as DMN2V, DMP2V, RHDMY or RH⊗ ) to ensure/avoid
In
the LDD implant on the poly resistors. Users must check the “Masking Layers &
te
Bias” table to tape out the corresponding dummy layer with the TSMC universal
ru
I/O library.
ni
TS
v
Non LDD Device

er
M
si
To form Non-LDD implant, RHDMY or RH is used in 0.13µm, 90nm, and 65nm,

C
ta
but not in 0.15µm and 0.18µm technologies. For 0.15µm/0.18µm, you need to
C
insert NOT VARDMY into the general-purpose logic equation. Please check the
ir\
on 9 tro 01
0.15µm/0.18µm library release note for the exact logic operation in detail.
M
fid 24 ni 8
ic
GDSII Change to Mask Revision

ro
en 762 ca\
Even minor changes of the GDSII layers may result in a major change of a mask
-E
tia
set, especially in base layers of a process. For example, the modification of the
le
OD2 GDSII layer not only changes the OD2 mask but also other masks, such as
lI
k
LDD, POLY, RPO, ESD, and so on, depending on the technology. Users must
07
nf
review the “Masking Layers & Bias” document to tape out all the masks related
or
/0
to the changing GDSII layers.

9/
m
2
High-Vt (Threshold Voltage) Implant at

io
C
Since the 0.13µm/90nm/65nm advanced process features high-Vt option, the

n
en
0.13µm/90nm/65nm universal standard I/O gds already contains high-Vt implant

layer on core ESD protection devices to substantially reduce the core power
tr
stand-by leakage current. Please refer to the stand-by leakage current comparison
um
table (“with high-Vt layer” versus “without high-Vt layer”) available from the
library release note first; then decide whether to tape out this layer or not.
\\
To tape out the high-Vt layer, select it in the MT form

(IM
If not, discard the high-Vt implant in the tape out MT form or remove it
EC
from the gds.

\)\
vz
w

DMN2V/DMP2V⊗
are used in 0.18um, 0.15um of Engineering
technologies to ensure LDD implant, butPune (CoE
RHDMY/RH is used to avoid the LDD implant in 0.13um/90nm technology.
Tape-Out with Top Two Thick Metals and
Top Two Large VIAs in Non-CUP Wire
In
te
Bond
ru
ni
To tape out with (ultra) thick top metal and top-1 thick metal, customers can use
the top-1 layer gds, and then insert dummy metal as metal top.
TS
v er
For instance, to tape out with ultra thick top metal and top-1 thick metal in 6lm:
M
si
C
ta
For Universal Analog I/O: Customers can use the 5lm gds (where metal 5 is
C
thick and via45 is large) from "mt" directory, and then insert dummy metal
ir\
as metal6 to achieve this purpose.

on 9 tro 01
M
fid 24 ni 8
For 0.13µm/0.18µm bond pad, use 6lm gds under “wb” directory within the
ic
bond pad library back-end kit, and select PADxAM / PADxARM, where
ro
en 762 ca\
suffix “M” in bond pad name indicates that this bond pad comes with top
two thick metals and top two large VIAs.
-E
tia
le
For 90nm & other advanced technologies, because of complex metallization

lI
options, you will not find PADxAM / PADxARM bond pads in the bond
k
07
nf
pad library. Instead, you can only see PADxA / PADxAR bond pads under
each specific back-end directory that is named by metal scheme. For
or
/0
example, you can find PADxA / PADxAR GDS from 6M_3X2Z directory,
9/
m
where 6M indicates 6 metal layer; 3X2Z indicates 3 metal layers with X
2
at
metallization and top 2 metal layers with Z metallization. Similarly, you can
also find PADxA / PADxAR GDS from 6M_3X2Y directory, etc.
io
C
n Bond Pad
en
I/O: 5lm gds under mt directory 6lm gds under wb directory

tr
Dummy Metal Top thick metal

um
Top large VIA VIA 56

\\
Metal 5 Top-1 thick

(IM
Please select PADxAM/

VIA 45 Top-1 large VIA VIA 45
ARM for 0.13µm/0.18µm,
Metal
Metal 44
and VIA
PADA/AR for N90/
EC
VIA 34 34
Metal 3 N65/N45 technologies
VIA 23
\)\
Metal 2
vz
VIA 12 VIA 12
Metal 1
w

Universal Analog I/O Bond Pad

Figure 4.1 Top Two Thick Metals Using Universal Analog I/O in Non-CUP Wire Bond
Direct Shrinkage to Half-Node
Technologies
In
TSMC Universal Analog I/O can be directly shrunk to half-node technologies

te
without any additional work. For example, 0.18µm universal analog I/O can be
ru
directly shrunk to 0.16µm technology, 0.13µm universal analog I/O can be

ni
directly shrunk to 0.11µm technology, 90nm universal analog I/O can be directly
shrunk to 80nm technology, and 65nm universal analog I/O can be directly
TS
v er
shrunk to 55nm technology. However, only a certain type of bond pads can
M
support direct shrinkage to half-node technologies. For details, please refer to the
si
bond pad library release note of each process technology.

C
ta
C
ir\
on 9 tro 01
M
fid 24 ni 8
ic
ro
en 762 ca\
-E
tia
le
lI
k
07
nf
or
/0
9/
m
2
at
io
C
n
en
tr
um
\\
(IM
EC
\)\
vz
w

Chapter 5 Simulation Notes
In
This chapter provides information on device mapping between Spice Model Card
and LVS/LPE Netlist. For 0.13µm, 0.15µm, 0.18µm, and 0.25µm I/O, since
te
device name defined in the spice model card is different from that in the
ru
LVS/LPE netlist, user must modify the spice netlist following the mapping table
below prior to simulation.
ni
TS
v
However, for 90nm and 65nm I/O, device name of the spice model card is
er
consistent with that of the LVS/LPE netlist. So there is no need to take any
M
si
action on this matter, except for those that feature I/O-voltage over-drive.
C
ta
C
ir\
Device Name in the Device Name in the

Technology on 9 tro 01
Spice Model Card LVS/LPE Netlist
M
fid 24 ni 8
The same as LVS/LPE The same as spice
ic
45nm
netlist model card
ro
en 762 ca\
65nm 2.5v I/O
-E
netlisttia model card

NCH_33 NCH_25OD
le
lI
k
65nm 2.5v I/O with PCH_33 PCH_25OD

07
3.3v Over-Drive
nf
NDIO_33 or NDIO_25OD
/0
PDIO_33 PDIO_25OD
9/
m
2
90nm at
netlist model card
0.13µm
io
C
nch N
0.15µm
n
en
pch P
0.18µm
tr
nch_25
um
nch_33 ND
nch3
\\
pch_25
(IM
pch_33 PD
pch3
EC
nch_na33
NN
nanch3
\)\
DIO_esd33
vz
DIO_esd25 DB
w
Downloaded by: Vanita Agarwal ENDIO_3

NDIO_33
NDIO_25 D2
NDIO_3
In
PDIO_33
te
PDIO_25 D1
ru
PDIO_3
ni
Nch N
TS
v
Pch P
er
0.25µm
M nch3 ND
si
C
ta
pch3 PD
C
ir\
ech3
on 9 tro 01 Y
M
fid 24 ni 8
ic
ro
en 762 ca\
-E
tia
le
lI
k
07
nf
or
/0
9/
m
2
at
io
C
n
en
tr
um
\\
(IM
EC
\)\
vz
w

Chapter 6 Contact Us
In
The TSMC universal analog I/O libraries are released under the supervision of the
TSMC standard quality assurance (QA) procedure. If you find any errors or
te
encounter any problems with the library, please first refer to the release notes and
ru
designkit.info (packed as part of the deliverable kits) for the known issues. Also,
make sure to download the most updated technology files from TSMC Online.
ni
For any further issues, please contact your library distributor or TSMC regional
TS
v
application engineer for immediate assistance.

er
M
si
C
ta
C
ir\
on 9 tro 01
M
fid 24 ni 8
ic
ro
en 762 ca\
-E
tia
le
lI
k
07
nf
or
/0
9/
m
2
at
io
C
n
en
tr
um
\\
(IM
EC
\)\
vz
w


TSMC Universal Analog IO General Application Note 2

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Downloaded by: Vanita Agarwal

Downloaded on: 09/11/2023

Downloaded by: Vanita Agarwal

Version Date Special Note

1. Update page 2 of Chapter 1.

2. Update “Analog I/O Cell PDBxA / PDBxAC” section and

TS 3. Update “Example 1” and “Example 3” of Chapter 3.

4. Update the device mapping table in Chapter 5.

M 1 Update Figure 2.3, “Analog Ground Pad PVSS3A/AC”, and “ESD

Core-Clamp PCLAMP Cell” sections in Chapter 2.

2 Insert new sections on “How to Use TPAxxxGV Universal Analog

Analog I/O with Bond Pad Cell” in Chapter 2.

3 Re-arrange “Bond Pad Cell” section in Chapter 2.

6 Update the Device Mapping Table in Chapter 5.

1.20 2005/07/04 1. Update Chapter 5, “Library Integration Notes”.

3. Update the section on “The Bond Pad Cell” of Chapter 2.

1. First release of Universal Analog I/O Library General Application

Downloaded by: Vanita Agarwal

Chapter 2 Cell Usage 4

Universal Analog I/O Power Rail ....................................................................................... 4

Analog I/O Cell PDBxA / PDBxAC.................................................................................... 5

Condition Two: Connect PDBxA / AC Analog Signal Pin to Internal Drain....... 7

Analog Power Pad PVDD3A/AC...................................................................................... 11

Power Cut Adapter Cell PRCUTA .................................................................................. 14

Place PRCUTA between Analog Domain and Digital Domain............................ 15

Non-CUP In-Line Wire-Bond ................................................................................. 23

CUP In-Line Wire-Bond ......................................................................................... 26

ESD Core-Clamp PCLAMP Cell ..................................................................................... 29

Approach B: Place PCLAMP Cell in between The Bond Pads of PVDD3AC

Chapter 3 Application Examples 33

Example 1: Using PRCUTA cell to separate digital/analog domains or to

separate analog/analog domains (with different supplied voltage) ..................... 33

Chapter 4 Library Integration Notes 36

Integration of Library Tape-out Layers.......................................................................... 36

GDSII Number Mapping ........................................................................................ 36

ESD Mask ................................................................................................................. 36

Non LDD Device....................................................................................................... 37

High-Vt (Threshold Voltage) Implant.................................................................... 37

Chapter 5 Simulation Notes 40

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The high-speed interface and Radio Frequency (RF/ultra-low-input capacitance)

applications have become increasingly common nowadays. Therefore, the analog

correctly use it. C

• Chapter 4 provides information on the integration of library tape-out, tape-

• Chapter 5 provides guidelines for simulation purpose.

• Chapter 6 guides you whom to contact for technical support.

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power-cut cell PRCUT available from the universal standard I/O

please refer to Chapter 10 of Universal Standard I/O General

Attention 2: TSMC universal analog I/O is only suitable for interface

of signal swing between the power rail TAVDD/TACVDD (i.e. non-

overshoot application) and the ground rail VSS (i.e. non-undershoot

application), such as Low Noise Amplifier for WLAN/Bluetooth, or

Gbps. Serial Link/SerDes.

and universal analog I/O as short as possible.

domains on the same chip, if and only if customers use TSMC

party IP is beyond TSMC’s guarantee.

Attention 5: Chapter 2 addresses how to bridge between TSMC

Attention 6: To use TSMC universal analog I/O for metal scheme

that includes top 2 ultra thick metal layers, “Mu”:

requirement. (e.g. To achieve 8lm GDS with top 2 “Mu”, adopt

as metal 8 for 8lm tapeout)