TABLE OF CONTENTS

I. INTRODUCTION .............................................................................................................................................................................2
II. FULL ADDER .................................................................................................................................................................................3
III. RESULTS FOR FULL ADDER AFTER SIMULATION ON ISE TESTBENCH .................................................................... 7
IV. FULL SUBTRACTOR ...................................................................................................................................................................9
V. RESULTS FOR FULL SUBTRACTOR AFTER SIMULATION ON ISE TESTBENCH .................................................... 13
VI. CONCLUSION ............................................................................................................................................................................ 14
APPENDIX .........................................................................................................................................................................................15

LIST OF FIGURES
Fig 1: Block diagram of half adder ..............................................................................................................................................3
Fig 3: Block Diagram of Full Adder .............................................................................................................................................5
Fig 4: Logic Diagram of Full Adder .............................................................................................................................................7
Fig 5a: The input parameters and clock definition ....................................................................................................................... 7
Fig 5b: Results of full adder after simulation in the TESTBENCH of ISE 14.7 ..........................................................................8
Fig5c: Simplified diagram showing the input and output signals ................................................................................................ 8
Fig 6: Block diagram of Half Subtractor ...................................................................................................................................... 9
Fig 7: Logic Diagram of Half Subtractor ................................................................................................................................... 10
Fig 8a: Block Diagram of Full subtractor ...................................................................................................................................11
Fig 8b:Logic Diagram of Full Subtractor ................................................................................................................................... 12
Fig 8c:Results of full subtractor after simulation in the TESTBENCH of ISE 14.7 ..................................................................13
Fig 8d: Simplified Diagram showing input and output signals .................................................................................................. 13

LIST OF TABLES
Table 1: Truth table of half adder ................................................................................................................................................. 3
Table 2a: K map for output variable Sum ‘S’ ...............................................................................................................................4
Table 2b: K map for output variable Carry ‘C’ ............................................................................................................................ 4
Table 3: Truth table of Full Adder ................................................................................................................................................6
Table 4a:K map Simplification for output variable Sum ‘S’ ........................................................................................................6
Table 4b: K map Simplification for output variable ‘Cout‘ ......................................................................................................... 6
Table 5a: Truth Table of Half Subtractor ..................................................................................................................................... 9
Table 5b: K map Simplification for output variable ‘D’ .............................................................................................................. 9
Table 5c: K map Simplification for output variable ‘Bout‘ ....................................................................................................... 10
Table 6a:Truth Table of Full Subtractor .....................................................................................................................................11
Table 6b: K map Simplification for output variable ‘D’ ............................................................................................................ 11
Table 6c: K map Simplification for output variable ‘Bout‘ ....................................................................................................... 12

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I. INTRODUCTION

Full adders and full subtractors are important building blocks in digital circuits. They are used to perform
arithmetic operations such as addition and subtraction of binary numbers. In this project, we will explore the
design and implementation of full adders and full subtractors using logic gates.
A full adder is a combinational circuit that adds three binary digits: A, B, and C-in (carry-in) and produces
two outputs: S (sum) and C-out (carry-out). The sum output represents the least significant bit of the
addition, while the carry-out represents the most significant bit. Full adders are used in multi-bit addition
operations, where the carry-out from one full adder is fed as the carry-in to the next full adder.
A full subtractor is a combinational circuit that subtracts three binary digits: A, B, and B-in (borrow-in) and
produces two outputs: D (difference) and B-out (borrow-out). The difference output represents the result of
the subtraction, while the borrow-out represents whether a borrow is required from the next lower significant
bit. Full subtractors are used in multi-bit subtraction operations, where the borrow-out from one full
subtractor is fed as the borrow-in to the next full subtractor.
In this project, we will design and simulate full adders and full subtractors using logic gates such as AND,
OR, and XOR gates. Finally, we will test our circuits using the FPGA (Field Programmable Gate Array)
programmable logic device.
Full adders and full subtractors are commonly used in digital electronics for arithmetic operations. In
everyday life, these circuits can be found in calculators, computers, and other electronic devices that perform
mathematical calculations. They are also used in security systems, where they can be used to encrypt and
decrypt data. Additionally, full adders and full subtractors can be used in control systems to perform
operations such as counting and timing.

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II. FULL ADDER

A binary adder is a logic circuit that adds two binary numbers together. It takes two inputs, the binary
numbers to be added, and produces a sum output. The simplest form of a binary adder is the half adder,
which can only add two single-bit binary numbers.
A half adder has two inputs, A and B, and two outputs, sum (S) and carry (C). Inputs are called Augend and
Added bits and Outputs are called Sum and Carry.

Fig 1: Block diagram of half adder

Let us observe the addition of single bits,

0+0=0
0+1=1
1+0=1
1+1=10

Since 1+1=10, the result must be two bit output. So, Above can be rewritten as,

0+0=00
0+1=01
1+0=01
1+1=10

The result of 1+1 is 10, where ‘1’ is carry-output (Cout) and ‘0’ is Sum-output (Normal Output)

INPUTS OUTPUTS
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Table 1: Truth table of half adder

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Next Step is to draw the Logic Diagram. To draw Logic Diagram, We need Boolean Expression, which can
be obtained using K-map (Karnaugh map). Since there are two output variables ‘S’ and ‘C’, we need to
define K-map for each output variable.

Table 2a: K map for output variable Sum ‘S’

The equation obtained is : S = AB' + A'B which can logically be written as S = A or B.

Table 2b: K map for output variable Carry ‘C’

The equation obtained from the K-map is C = AB.

Using the Boolean, we can draw the logic diagram as follows:

Fig 2: Logic Diagram for Half Adder

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Though half adders can perform binary addition , half adders have certain limitations that make them
unsuitable for certain applications. Firstly, they can only add two single-digit binary numbers and cannot
handle carry-over from previous additions. Secondly, they do not have the ability to subtract or perform any
other arithmetic operations. Thirdly, they cannot handle multi-bit numbers, which means that they cannot be
used for complex calculations. Finally, they are not capable of performing logical operations such as AND,
OR, and NOT. These limitations make half adders less versatile than other types of adders and limit their use
to simple applications.

To overcome the above limitation faced with Half adders, Full Adders are implemented.

Fig 3: Block Diagram of Full Adder

It is a arithmetic combinational logic circuit that performs addition of three single bits.It contains three
inputs (A, B, Cin) and produces two outputs (Sum and Cout).Where, Cin stands for Carry In and Cout for Carry
Out. A full adder is made up two half adders

INPUTS OUTPUTS
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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 Table 3: Truth table of Full Adder

Table 4a:K map Simplification for output variable Sum ‘S’

The equation obtained is,

S = A'B'Cin + AB'Cin' + ABC + A'BCin'

The equation can be simplified as,

S = B'(A'Cin+ACin') + B(AC + A'Cin')

S = B'(A xor Cin) + B (A xor Cin)'
S = A xor B xor Cin

Table 4b: K map Simplification for output variable ‘Cout‘

The equation obtained is,

Cout = BCin + AB + ACin

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 Fig 4: Logic Diagram of Full Adder

III. RESULTS FOR FULL ADDER AFTER SIMULATION ON ISE TESTBENCH

To simulate the full adder, we used the software ISE 14.7 using its test-bench.

Fig 5a: The input parameters and clock definition

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Fig 5b: Results of full adder after simulation in the TESTBENCH of ISE 14.7

Fig5c: Simplified diagram showing the input and output signals

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IV. FULL SUBTRACTOR

A binary subtractor is a logic circuit that subtracts one binary number from another. It takes two inputs, the
binary numbers to be subtracted, and produces a difference output. The simplest form of a binary subtractor
is the half subtractor, which can only subtract two single-bit binary numbers. A half subtractor has two
inputs, A and B, and two outputs, difference (D) and borrow (B). The truth table for a half subtractor is as
follows:

Fig 6: Block diagram of Half Subtractor

INPUTS OUTPUTS
A B D Bo
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Table 5a: Truth Table of Half Subtractor

Table 5b: K map Simplification for output variable ‘D’

The equation obtained is,

D = A'B + AB'

which can be logically written as,

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D = A xor B

Table 5c: K map Simplification for output variable ‘Bout‘

The equation obtained from above K-map is,Bout = A'B

Fig 7: Logic Diagram of Half Subtractor

A half subtractor is a combinational circuit that is used to subtract two single-bit binary numbers.
However, it has certain limitations. Firstly, it can only subtract two single-bit binary numbers and cannot
perform subtraction of multi-bit binary numbers. Secondly, it cannot handle borrow operations, which
means that if the second number is greater than the first number, it cannot perform the subtraction operation.
Lastly, it can only perform subtraction of binary numbers in 2's complement form, which means that it
cannot perform subtraction of signed binary numbers in other forms such as signed magnitude or excess-3
code.

To overcome the above limitation faced with Half subtractors, Full subtractors are implemented.

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 Fig 8a: Block Diagram of Full subtractor

It is a Combinational logic circuit designed to perform subtraction of three single bits.It contains three
inputs(A, B, Bin) and produces two outputs (D, Bout).Where, A and B are called Minuend and
Subtrahend bits. And, Bin -> Borrow-In and Bout -> Borrow-Out

INPUTS OUTPUTS
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Table 6a:Truth Table of Full Subtractor

Table 6b: K map Simplification for output variable ‘D’

The equation obtained from above K-map is,

D = A'B'Bin + AB'Bin' + ABBin + A'BBin'

which can be simplified as,

D = B'(A'Bin + ABin') + B(ABin + A'Bin')

D = B'(A xor Bin) + B(A xor Bin)'
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D = A xor B xor Bin

Table 6c: K map Simplification for output variable ‘Bout‘

The equation obtained is,Bout = BBin + A'B + A'Bin

Fig 8b:Logic Diagram of Full Subtractor

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V. RESULTS FOR FULL SUBTRACTOR AFTER SIMULATION ON ISE

TESTBENCH

Fig 8c:Results of full subtractor after simulation in the TESTBENCH of ISE 14.7

Fig 8d: Simplified Diagram showing input and output signals

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VI. CONCLUSION

In conclusion, the implementation of full adders and full subtractors in VHDL programming language was
successfully achieved. The design was tested on the test-bench of ISE 14.7, and the results were consistent
with the expected output that was shown on the truth tables. The use of VHDL programming language
provided a flexible and efficient way to design and simulate digital circuits. This project demonstrated the
importance of careful planning and testing to ensure the accuracy and reliability of the design. Overall, this
project was a valuable learning experience in digital circuit design and VHDL programming

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APPENDIX

1. VHDL codes used for the full adder.

CODE VHDL MODULE:This code was typed in a VHDL Module

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulladder is port
(a,b,c: in bit;sum,carry:out bit);
end fulladder;

architecture data of fulladder is

begin
sum<= a xor b xor c;
carry<=(a and b) or (b and c) or (a and c);
end data;

CODE TESTBENCH: This code was typed in a TESTBENCH module

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY fulladdersim IS

END fulladdersim;

ARCHITECTURE behavior OF fulladdersim IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fulladdervhdl
PORT(
a : IN std_logic;
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 b : IN std_logic;
c : IN std_logic;
sum : OUT std_logic;
carry : OUT std_logic
);
END COMPONENT;

--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic := '0';

--Outputs
signal sum : std_logic;
signal carry : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

constant <clock>_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: fulladdervhdl PORT MAP (
a => a,
b => b,
c => c,
sum => sum,
carry=> carry
);

-- Clock process definitions

<clock>_process :process
begin
<clock> <= '0';
wait for <clock>_period/2;
<clock> <= '1';
wait for <clock>_period/2;
end process;
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 -- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

wait for <clock>_period*10;

-- insert stimulus here

wait;
end process;

END;
END ARCHITECTURE;

2. VHDL codes used for the full subtractor.

CODE VHDL MODULE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fullsubtractorvhdl is
Port ( A,B,C : in STD_LOGIC;
D,Bout : out STD_LOGIC);
end fullsubtractorvhdl;

architecture Behavioral of fullsubtractorvhdl is

begin
D<=A XOR B XOR C;
Bout<= ((NOT A) AND B) OR ((NOT A) AND C) OR (B AND C);

end Behavioral;

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CODE TESTBENCH:

-- Create Date: 15:12:43 01/19/2024

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY fullsubtractorsim IS
END fullsubtractorsim;

ARCHITECTURE behavior OF fullsubtractorsim IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fullsubtractorvhdl
PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
D : OUT std_logic;
Bout : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
--Outputs
signal D : std_logic;
signal Bout : std_logic;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fullsubtractorvhdl PORT MAP (
A => A,
B => B,
C => C,
D => D,
Bout => Bout
);

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 -- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A<='0';B<='0';C<='1';
wait for 100 ns;
A<='0';B<='1';C<='0';
wait for 100 ns;
A<='0';B<='1';C<='1';
wait for 100 ns;
A<='1';B<='0';C<='0';
wait for 100 ns;
A<='1';B<='0';C<='1';
wait for 100 ns;
A<='1';B<='1';C<='0';
wait for 100 ns;
A<='1';B<='1';C<='1';

-- insert stimulus here

wait;
end process;

END;

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