ELEC4410

Lab 5: Layout Versus Schematic (LVS)

OBJECTIVES
▪ Perform LVS to check for inconsistencies between the inverter’s layout and its
schematic view.
▪ Create the layout view of NAND2 cell and perform DRC and LVS checks.
▪ Create layout view of a large inverter with a single finger as well as one with multiple
fingers and perform respective DRC and LVS checks.

I. Layout versus Schematic Check (LVS Check)

You are ready to carry out the Layout versus Schematic Check (LVS). It is an important step
because the layout drawing is based on its schematic. The device dimensions and connections
in the layout should be consistent with those on the schematic. To ensure the layout design
matches the schematic, the layout versus schematic check (LVS) must be performed.

The layout view represents the circuit topology but consists of layers of rectangles only. How
can the system recognise devices and their connectivity in the layout view? While LVS is
running, Cadence will look for the technology file which contains the electrical rules. These
rules define structures, for example the overlapping of Poly layer, Nimp layer and Oxide layer
will be taken as a NMOS transistor. Therefore, gates and electrical connections are traced out
and identified from their layout view. Only then the layout and schematic views can be
compared.

To start LVS, open the layout view of the inverter that you have designed in previous lab. Click
Calibre → Run nmLVS. The window shown on the left in Fig. 1 will appear.

Figure 1: Calibre Interactive.

Click File → Load Runset. The “Load Runset File window” (shown on the right in Fig. 1) will
appear. Browse to elec4410 directory under your home directory and select Runset_LVS file.
Then click “Run LVS” on the Calibre interactive window.

ELEC4410-Lab5 Dept. of ECE, HKUST Page 1 of 6

A "Progress" window will pop up when the LVS check has finished. If the schematic view
matches the "layout view", the message “Schematic and Layout Match” would show,
otherwise, mismatches would be listed.

The screenshot in the Fig. 2 shows an example where the layout does not match the schematic.
You will have to resolve these errors step-by-step. Click on the plus sign against the design
name (INVXX in Fig. 2) under Layout Cell /Type. Then click on the discrepancies. In Fig. 2,
two discrepancies can be seen, namely, “Incorrect ports” and “Property Errors.” If you click on
incorrect ports, the errors related to these discrepancies will appear at the bottom in the Calibre-
RVE.

Figure 2: Calibre RVE showing discrepancies in LVS check.

Fig. 3 show the errors corresponding to Incorrect Ports. We are told that a certain net on the
source (i.e., schematic) named OUT is missing on the layout. Your job would then be to find
this net on the layout view and place a pin named “OUT” to resolve the discrepancy.

Fig. 4 shows the errors corresponding to Property. Again, we are told that the width of the
NMOS on the schematic is 0.5µm whereas it is 0.45µm on the layout. Click on the coordinates
under the layout name. The layout view will zoom to that location. Increase the width of the
NMOS to 0.5µm.

Run the LVS check again. If there are no more discrepancies, the Calibre RVE result will look
like Fig. 5.

ELEC4410-Lab5 Dept. of ECE, HKUST Page 2 of 6

 Figure 3: Calibre RVE showing Incorrect Ports in LVS check.

Figure 4: Calibre RVE showing Property Errors in LVS check.

ELEC4410-Lab5 Dept. of ECE, HKUST Page 3 of 6

 Figure 5: Calibre RVE showing LVS pass.

II. Creating layout of the 2-input NAND gate

You have already built the schematic view of the NAND2 cell in Lab 3. Now you can proceed
to draw the layout of NAND2. The NAND2 layout may look like the one shown in Fig. 6 (for
reference only).

Hint: Since you have finished a DRC passed inverter layout, you may want to copy and modify
that layout as a starting point for the NAND2 layout.

Figure 6: NAND2 schematic and layout view.

ELEC4410-Lab5 Dept. of ECE, HKUST Page 4 of 6

Once the layout is complete, perform the DRC and LVS checks. Correct any mismatches that
appear. The NAND2’s layout must match its schematic view. Ask for help if necessary. Show
the LVS pass results to the TA.

III. Multi-Finger Inverter Layout

You will design two inverters with following specifications. Draw schematic, symbol, and
layout of both designs.

Inverter 1:

INV10XS: A large inverter with single finger transistors

PMOS: Total Width: 10µm, Number of Fingers: 1, Length: 0.18µm
NMOS: Total Width: 5µm, Number of Fingers: 1, Length: 0.18µm
Inverter 2:

INV10XM: An inverter having same total width and length as above but with multi-fingers.
PMOS: Total Width: 10µm, Number of Fingers: 5, Length: 0.18µm
NMOS: Total Width: 5µm, Number of Fingers: 5, Length: 0.18µm

Hint: You don’t need to draw layout of the PMOS / NMOS. You can use parametric cells in
tsmc18 library. Similar to schematic drawing, follow the same steps to get instance of PMOS
and NMOS. Fig 7 shows layout of the PMOS and NMOS with five fingers. Fig. 8 shows layout
of inverter INV10XM.

Figure 7: Multi-finger PMOS and NMOS.

ELEC4410-Lab5 Dept. of ECE, HKUST Page 5 of 6

 Figure 8: Multi-finger Inverter Layout.

Once you have layout of Inverter 1 and Inverter 2, perform the DRC and LVS check and
show the results of both inverters to the TA.

End of Lab-5

ELEC4410-Lab5 Dept. of ECE, HKUST Page 6 of 6