Diode Clipping Circuits

Lecture Three - Page 1 of 8

Diode Clipping Circuits

Basic Definition:
There are a variety of diode circuits called clippers (limiters or selectors) that have the
ability to "clip" off a portion of the input signal above (positive) or below (negative)
certain level without distorting the remaining part of the alternating waveform.
Depending on the orientation of the diode, the positive or negative region of the input
signal is "clipped" off.
There are two general categories of clippers: series and parallel. The series
configuration is dined as one where the diode is in series with the load. While the
parallel variety has the diode in a branch parallel to the load (see Fig. 3-1).
vi D vo
V
+ +
T T/2 T
vi R vo t
0 T/2 t − −
0
−V −V
Simple Series (Positive) Clipper
vi R vo
V V
+ +
T D vo
vi
0 T/2 t − − 0 T/2 T t
−V
Simple Parallel (Negative) Clipper

Fig. 3-1

Example 3-1:

Biased Series (Negative) Clipper, see Fig. 3-2.

vi

E D
vi vo
0 5.2V Si
T/2 T t R

-9

Fig. 3-2
 Diode Clipping Circuits
Lecture Three - Page 2 of 8

E − VT Vi D Vi
vi vo
4.5V Ideal 13.5
R

4.5
For t = 0 → t1 and t2 → T; D ON, T/2 t1 t2 T
and vo = vi + 4.5 V. 0
t
For t = t1 → t2; D OFF, - 4.5
and vo = 0 V.

vo vo

13.5 13.5

4.5 4.5

-9 - 4.5 0 9 vi 0
t

Fig. 3-2 (cont.)

Example 3-2:

Biased Parallel (Positive) Clipper, see Fig. 3-3.

vi

10
R
vi vo
D Si
0 T/2 T t
E 5.7V

- 10

Fig. 3-3
 Diode Clipping Circuits
Lecture Three - Page 3 of 8

R
vo
vi
+ id = 0
Vtransition D Si
10
− E 5.7V

t1 t2
Vtransition – id R – Vd + E = 0; 0 T/2 T
t
Vtransition = 0.7 – 5.7 = – 5 V. -5 Vtransition
For t = 0 → t1 and t2 → T; D ON,
and vo = – 5 V. - 10

For t = t1 → t2; D OFF,

and vo = vi.
vo vo
- 10 -5 10
0 vi 0
t
-5
-5

- 10 - 10

Fig. 3-3 (cont.)

Summary:

A variety of series and parallel clippers with the resulting output for the sinusoidal
input are provided in Fig. 3-4.

Fig. 3-4
 Diode Clipping Circuits
Lecture Three - Page 4 of 8

Fig. 3-4 (cont.)

Example 3-3:

Double Diode Series Clipper, see Fig. 3-5.

vi
E1 D1
12

3.3V Si
vi vo
E2 D2
0 T/2 T t R
7.7V Ge
-12

D1
E1 + VT1 Vi1

4V Ideal
vi D2 vo
E2 + VT2 Vi2
R
8V Ideal

Fig. 3-5
 Diode Clipping Circuits
Lecture Three - Page 5 of 8

vi
For t = 0 → t1, t2 → t3, and t4 → T; 20
Vi2
both D1 and D2 will be OFF,
and vo = 0 V.
For t = t1 → t2; D1 ON while D2 OFF, 8
T/2 T

and vo = Vi1 = vi – 4 V. t1 t2 t3 t4
For t = t3 → t4; D1 OFF while D2 ON, 0 t
-4
and vo = Vi2 = vi + 8 V.

vo - 16

8
Vi1
vo
- 12 -8 8
0 4 12 vi
-4 0
-4 t

Fig. 3-5 (cont.)

Example 3-4:

Double Diode Parallel Clipper, see Fig. 3-6.

vi
9
R
vi vo
T D1 Si D2 Si
0 T/2 t
E1 2.3V E 2 5.3V
-9

R R
vo vo
+ id1 = 0D Si
+ id 2 = 0D Si
Vtr1 1 Vtr2 2

− E1 2.3V − E2 5.3V

Vtr1 – id1 R – Vd – E1 = 0; Vtr2 + id2 R + Vd + E2 = 0;

Vtr1 = 0.7 + 2.3 = 3 V. Vtr2 = – 0.7 – 5.3 = – 6 V.

Fig. 3-6
 Diode Clipping Circuits
Lecture Three - Page 6 of 8

For t = 0 → t1, t2 → t3, and t4 → T; vi

both D1 and D2 will be OFF, 9
and vo = vi.
For t = t1 → t2; D1 ON while D2 OFF, 3
t1 t2 t3 t4 T
Vtr1
and vo = 3 V. 0 T/2 t
For t = t3 → t4; D1 OFF while D2 ON, -6 Vtr2
and vo = – 6 V. -9

vo vo
3 3
-9 -6
0 3 9 vi 0 t
-6 -6

Fig. 3-6 (cont.)

Example 3-5:

Special Type Clipper: A Comparator, see Fig. 3-7.

vi

10

D
vi vo
Idial
0 T/2 T t R
E 5V
- 10

Fig. 3-7
 Diode Clipping Circuits
Lecture Three - Page 7 of 8

vi

10

5 E
For t = 0 → t1 and t2 → T; D OFF,
and vo = E = 5 V. t1 t2 T/2 T
0
For t = t1 → t2; D ON, t
and vo = vi.
- 10

vo

10 vi
5
10

5
- 10 0 5 10 vi
0 t

Fig. 3-7 (cont.)

Exercises:

1. Design biased parallel clippers (with silicon diodes) to perform the functions
indicated in the transfer characteristics of Fig. 3-8.

vo vo

12 12

- 12 -6
- 12 0 6 12 vi 0 12 vi
-6

(a) (b)

Fig. 3.8
 Diode Clipping Circuits
Lecture Three - Page 8 of 8

2. Sketch the output voltage (vo) and the transfer characteristics (vo against vi) for each
circuit of Fig. 3-9 for the input (vi) shown.

vi
8 D
vi vo
Ideal R (a)
T/2 T
0 t
E 4V
-8

vi
E1
R
10 vi vo
4V
D Si
(b)
E2 2.3V
0 T t

vi
9
R
vi vo
T/2 T D1 D2
Ge Si (c)
0 t
E1 3.3V E 2 5.3V
-9

vi
D1 D2
150 vi vo
Ideal Ideal
R1 100kΩ R2 200kΩ (d)
E1 25V E 2 100V
0 T t

Fig. 3-9
 Diode Clamping Circuits
Lecture Four - Page 1 of 4

Diode Clamping Circuits

Basic Definition:
The clamping circuit (clamper) is one will "clamp" a signal to a different dc level.
The circuit must have a capacitor, a diode, and a resistive element, but it can also
employ an independent dc supply to introduce an additional shift. The magnitude of
R and C must be chosen such that the time constant τ = RC is large enough to ensure
that the voltage across the capacitor does not discharge significantly during the interval
(T/2) the diode is nonconducting. Throughout the analysis we will assume that for all
practical purposes the capacitor will fully charge or discharge in five time constants.
Therefore, the condition required for the capacitor to hold its voltage during the
discharge period between pulses of the input signal is

T 1
5τ = 5 RC >> = [4.1]
2 2f

Example 4-1:

Determine the output (vo) for the circuit of Fig. 4-1 for the input (vi) shown.
vi
C
10 f = 1kHz vi vo
0.1μF
D Si
-5
0 T/2 T 3T/2 2T t R 50kΩ
E 5V

- 20

Fig. 4-1

Solution:

The analysis of clamping circuits are started by considering that the part of the input
signal that will forward bias the diode. For the circuit of Fig. 4-1, the diode is forward
bias ("on" state) during the negative half period of the input signal (vi) and the capacitor
will charge up instantaneously to a voltage level determined by the circuit of Fig. 4-2.
_ VC
+
_ _ +
0.7V
20V + 50kΩ vo
+ 5V _

Fig. 4-2
 Diode Clamping Circuits
Lecture Four - Page 2 of 4

For the input section KVL will result in

– 20 + VC + 0.7 – 5 = 0 => VC = 24.3 V.
The output voltage (vo) can be determined by KVL in the output section
+ 5 – 0.7 – vo = 0 => vo = 4.3 V.

Now check that the capacitor will hold on or not its establish voltage level during
the period (positive half period in case of Example 4-1) when the diode is in the
"off" state (reverse bias). The total time constant 5τ of the discharging circuit of
Fig. 4-3 is determined by the product 5RC and has the magnitude
5τ = 5RC = 5 (50×103) (0.1×10-6) = 25 ms.
The frequency ( f ) is 1 kHz, resulting in a period of 1 ms and an interval of 0.5 ms
between levels, that is
T/2 = 1/( 2f ) = 1/(2 × 1×103) = 0.5 ms.
We find that
5 τ >> T/2 ( 25ms / 0.5ms = 50 times).
So that, it is certainly a good approximation that the capacitor will hold its voltage
(24.3 V) during the discharge period between pulses of the input signal.

_24.3V
+
+ +
10V 50kΩ vo
_ 5V _

Fig. 4-3

The open-circuit equivalent for the diode will remove the 5-V battery from having any
effect on vo, and applying KVL around the outside loop of circuit will result in
+ 10 + 24.3 – vo = 0 => vo = 34.3 V.

The resulting output appears in Fig. 4-4, where the input and the output swing
are the same.
vo

34.3

19.3

4.3
0 T/2 T 3T/2 2T 5T/2 t

Fig. 4-4
 Diode Clamping Circuits
Lecture Four - Page 3 of 4

Example 4-2:

Using silicon diode, design a clamper circuit that will produce output vo = 10Sinωt–5 V
when the input is vi = 10Sinωt+5 V. Draw the circuit diagram and the input and output
signals.

Solution:

From the input (vi) and output (vo) signals, we have a negative biased clamper.
Therefore, the diode is forward bias ("on" state) during the positive half period of the
input signal (vi). The output voltage (vo) at this positive period can be determined by
KVL in the output section of the circuit shown in Fig. 4-5.
E + 0.7 – vo = 0 => E = 5 – 0.7 = 4.3 V.
For the input section KVL will result in VC _
+
15 – VC – 5 = 0 => VC = 10 V.
+ + +
0_.7V
Fig. 4-5 vi = 15V R vo = 5V
_ E _

The circuit diagram and the input and output signals are shown in Fig. 4-6.
vi

15

C
vi vo
5
D Si
T/2 T 3T/2 2T R
0 t E 4.3V
-5

vo

0 T/2 T 3T/2 2T t
-5

-15

Fig. 4-6
 Diode Clamping Circuits
Lecture Four - Page 4 of 4

Summary:
A number of clamping circuits and their effect on the square-wave input signal are
shown in Fig. 4-7.

Negative Clampers Positive Clampers

Clampers with ideal diodes and 5τ = 5RC >> T/2

Fig. 4-7

Exercise:

Sketch the output (vo) for the circuit of Fig. 4-8 for the input (vi) shown. Assume ideal
diodes.
vi
E0 R1 C
15

+ 3V D1 D2 +
T
vi R2 vo
0 T/2 t − E1 7V E 2 10V −

-15

Fig. 4-8