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CE-221 Lab Manual (New)
CE-221 Lab Manual (New)
Table of contents
Instructions for Students ………………………………………………………. 2
2. The introductory lab provides working guidelines for the entire course of lab. Students
are advised to study it thoroughly before coming to the lab. Actual experiments which
will be graded start from lab 1, “Introduction to Digital Experiments”.
3. All labs have a section named Summary of Theory which provides necessary theory
related to the experiments. Since the purpose of a lab manual is to compliment a text
book, students should not rely completely on this manual.
4. Almost every lab is divided into two main parts, with each section having its own set of
review questions. Labs will be graded on performance in these review questions.
5. Labs will be graded in double entry fashion; one entry in an assessment sheet given at
the end of every lab and another entry in the instructor’s record. This system of keeping
records will keep students aware of their performance throughout the lab.
7. The assessment sheet at the end of every lab looks like this:
Lab Rubrics
3 2 1 0
Can independently Can setup, and Can setup, and Cannot setup or
Apparatus setup, operate and handle the apparatus handle the handle the
Handling handle the apparatus with minimal help apparatus with apparatus
some help
Assembly/ Can assemble Can assemble Can assemble but Cannot assemble
Apparatus according to the design according to design inaccurately
design within least time
Date: ______________________
Lab-1
Introduction to the Lab
This is an introductory lab which provides working guidelines for all the labs. This part of
the lab contains instructions on building a digital circuit.
1.1 Overview:
This section describes the procedure for wiring logic circuits with any general-purpose
white prototype board for your breadboard. One of these is contained in each lab kit.
2. Every time you add a wire or component to the physical circuit, mark off the
corresponding part of the wiring diagram with a colored pencil or marker. This makes it
easy to see what parts of the circuit have been built so far. If you make any circuit
changes, draw these on your wiring diagram.
3. Insert IC packages into the appropriate breadboard area before inserting any wires. You
will usually need to bend the IC leads (pins) slightly inward so that the spacing closely
matches the spacing of sockets on the breadboard. Be careful to check that all IC leads
actually make it into the correct sockets.
4. To remove an IC, use an extraction tool, screwdriver, pliers or tweezers to avoid bending
or breaking IC leads, or personal injury.
5. Use only solid-conductor wire in the size range of AWG 20 to AWG 26. Wire with larger
diameter may damage the socket spring clips of the breadboard. Wire strippers should
be used to cut wires to appropriate lengths and to check wires that are suspected of
having a larger diameter than permitted. Trim and re-strip the end of any jumper wire
that appears badly nicked or overly flexed.
6. It is possible to insert most wires by hand. In tight places, using the forceps from the tool
kit can make the job much easier. In either case, wires are easier to insert if they have
been cut at an angle of approximately 45 degrees with respect to the axis of the wire.
7. When removing wires, be sure to pull at a right angle to the socket to avoid damage.
8. Route wires around IC packages, not over them. Occasionally an IC turns out to be
defective. If wires have been placed over the IC, you will have to remove them so that
the IC can be replaced. It is best to wire a circuit in stages, beginning with power and
ground connections. Add wires with the power switch OFF. Before turning power ON,
remove all hand jewelry and make sure that no foreign metal objects are near the circuit.
Check every IC to make sure it is not overheating. If any IC is too hot to touch immediately
shut the power off and check all leads. (Be careful because shorted ICs can become very
hot and leave a brand on your finger!) Also make sure that no IC has been inserted
backwards.
9. IC devices can be damaged if the power level exceeds 5.5V. Damage may also occur if
the supply voltage connection is removed from the IC pin while power is still being
applied to the circuit.
10. To debug a circuit, use a Oscilloscope to check logic levels. Start at a position in the circuit
where the logic level is known to be correct and work outward from there. If an IC does
not appear to produce the correct signal, check that power and ground are correctly
connected to the IC; also check all inputs to the component. Finally, check that the
output of the IC is not incorrectly connected to some other signal.
11. If you cannot get your circuit to work, bring it and a current circuit diagram or schematic
to Engineer for help.
• Old wire can break inside the insulation, causing incorrect circuit behavior that is
difficult to troubleshoot.
• Old wire should be recycled; place old wires in the wire recycling box next to the
new wire box in Lab.
2. Strip for breadboard squares worth of insulation off the ends of a wire when using it
in the breadboard. This is approximately 5/16 inch or 8 mm.
• If you strip too much, the wires in adjacent breadboard columns can touch, causing
a short circuit and most likely incorrect behavior.
• If you don’t strip enough, the insulation can prevent the spring clips in the
breadboard holes from closing properly around the non-insulated part of the wire
that is inserted into the hole.
3. Create power and ground busses at the top and bottom of your breadboard.
• The connection pattern used in the breadboard is shown in figure (to follow shortly).
• The top and bottom rows can be used to distribute +5VDC and ground to the ICs,
• Note that the top and bottom “bus” rows have a break in the very middle! If you
want a power or ground bus to run the length of the breadboard, you must insert
a jumper in the middle of the row to join the two half rows together. This makes
your wiring less crowded, and makes it easy to see power and ground connections.
4. The top and bottom rows can be used to distribute +5VDC and ground to the ICs. Run
all power signals in red wire and all ground signals in black wire.
• Do not use red or black wire for any other signals. This makes it easy to tell which
wires are power and ground wires, and which are actual signal wires.
• Use a single power or ground wire from the bus to the chip. Do not daisy chain power
or ground connections. Think parallel, not serial.
• You may wire from the bus to the breadboard hole next to the chip. This makes it easy
to see that the power and ground wires are connected to the correct pin.
• You may wire from the bus to the breadboard column that connects to the chip. This
allows more room for signal wires, without covering the power and ground wires.
5. Color codes your wiring in some way. Here are some suggestions that are meant to
make it easier to trace your wiring:
• Use the same color for all the wires of a signal that runs to multiple gates.
6. Wires should be routed no more than ½” (12 mm) above the breadboard.
• If the wires are too high, it will be difficult to trace signals through your circuit.
• If the wires are low, be sure the stripped wire ends are seated firmly in the
breadboard. Careful routing is essential for efficient troubleshooting. Tight wiring
can create sharp bends, which can cause trouble.
7. Avoid sharp bends in the wires. Sharp bends in the wire can cause the wire to break
inside the insulation.
• Your chips may be defective or be damaged while in use, and it is much easier to
remove chips for testing/replacement if you do not have to remove your wiring in
order to remove your chips.
• When possible, leave 2 or 3 rows of the breadboard between chips, to allow signals
to pass from one side of the IC to the other.
10. Wire from a complete schematic diagram. The chip’s pin numbers should match the
pin numbers in the diagram.
Description:
Features:
• Bread Board Based
• Power Supplies Included
• Basic Measuring Instruments Included
• Flexibility to Perform Custom Experiments
• Output Devices like LEDs and 7-Segment Included
• Input Devices like Push Switches, Toggle Switches Included
• Standard Function Generator Included
• Passive Components Included
• Protection Circuits Included
Technical Features:
Supplies:
• Fixed DC: +5V, -5V, +12V, -12V
• Dual DC Power Supply: 0 ~ +15V and 0 ~ -15V adjustable
• FIX Supply AC: 2V-0-2V, 12V-0-12V, 15V-0-15V
Function Generator:
• Output Waveform: Sine, Square, Triangle and TTL
• Output Frequency: up to 100KHz in five steps
Data Switch:
• 16-bit switch with TTL Output
Push Switch
• Two independent Switches
• Each with Q, Q’ output
• De-Bounce Switch
Logic Indicator
• 24 independent LEDs indicate high and low logic state
Digital Display
• 3 independent 7-segment LED display with BCD to 7-segment decoder/driver input
with 8-4-2-1 code
Potentiometer:
• Carbon Track 1K and 100K
Interface Connectors
• 2X BNC Connectors interfaced to 2mm gold plated pins
• 1X Banana Connector interfaced to 2mm gold plated pin
• DB-9 Connector with all pins interfaced to 2mm gold plated pins
• DB-25 Connector with all pins interfaced to 2mm gold plated pins
Solderless Breadboard:
• 2 Terminal Strips, Tie-point 1680
• 4 Distribution Strips, Tie-point 400
Audio Output
• 0.5W Speaker with Audio Amplifier and Volume Control
Accessories:
• 2mm-1mm patch cords, Power Cord, User Manual
A digital multimeter is a test tool used to measure two or more electrical values—
principally voltage (volts), current (amps) and resistance (ohms). It is a standard diagnostic
tool for technicians in the electrical/electronic industries.
Digital Multimeter
Specification:
Special Functions:
• Diode
• Continuity buzzer
• Data Hold
• Icon display
• Sleep mode
General Characteristics:
Specification UTD2102CEX
Channels 2
Bandwidth 100MHz
Waveform Acquisition
≥2000wfms/s
Rate
Storage Setup,Wave,Bitmap
General Characteristic
Standard Individual
Gift Box, English Manual
Packing
Standard Carton
450mm× 420mm × 280mm
Measurement (L×W×H)
Lab-2
Logic Gates & Truth Table
function. All the logic gates have two inputs except the NOT gate, which has only one
input.
When drawing a truth table, the binary values 0 and 1 are used. Every possible
combination depends on the number of inputs. If you don’t know about the logic gates
and their truth tables and need guidance on them, please go through the following
infographic that gives an overview of logic gates with their symbols and truth tables.
IC Circuit Diagram:
74266 IC 4077 IC
0 0 0 1 0 1 0 1
0 1 0 1 1 0 1 0
1 0 0 1 1 0 1 0
1 1 1 0 1 0 0 1
2.4 Procedure:
1. Get the ICs and other required apparatus/equipment from the lab staff.
2. Plug in the IC in the breadboard of the Trainer board and while doing so; try to avoid
touching the IC pins for safety reason.
4. The IC used has four gates each having two inputs (quad 2- in). Pin number 1 and 2
are inputs whereas pin 3 is output of the gate. Similarly, input pair for other gates are
(4, 5) & (8, 9) & (10, 11) and the output is obtained from pin number 6, 10 and 13
respectively.
5. Once you have wired the circuit, check it with your instructor. If approved, power up
your circuit.
6. The output should be connected to the LED on the Logic Trainer for monitoring
purpose.
7. Apply different input combinations at the input and note down the corresponding
output and fill in the following truth table.
A B A.B
A B A+B
A B (A.B)’
A B (A+B)’
A B (A ⊕ B)
A B (A ⊕ B)’
A A’
Lab Rubrics
3 2 1 0
Can independently Can setup, and Can setup, and Cannot setup or
Apparatus setup, operate and handle the apparatus handle the handle the
Handling handle the apparatus with minimal help apparatus with apparatus
some help
Assembly/ Can assemble Can assemble Can assemble but Cannot assemble
Apparatus according to the design according to design inaccurately
design within least time
Date: ______________________
Lab-3
Boolean Algebra & Demorgan’s Law
➢ Trainer Board
➢ Connecting wires / Jumper wires
➢ 14 pin ICs
• NOT (7404)
• AND (7408)
• OR (7432/4071)
➢ Power supply
As well as the logic symbols “0” and “1” being used to represent a digital input or output,
we can also use them as constants for a permanently “Open” or “Closed” circuit or contact
respectively.
A set of rules or Laws of Boolean Algebra expressions have been invented to help reduce
the number of logic gates needed to perform a particular logic operation resulting in a list
of functions or theorems known commonly as the Laws of Boolean Algebra.
Boolean Algebra is the mathematics we use to analyze digital gates and circuits. We can
use these “Laws of Boolean” to both reduce and simplify a complex Boolean expression
in an attempt to reduce the number of logic gates required. Boolean Algebra is therefore
a system of mathematics based on logic that has its own set of rules or laws which are
used to define and reduce Boolean expressions.
The variables used in Boolean Algebra only have one of two possible values, a logic “0”
and a logic “1” but an expression can have an infinite number of variables all labelled
individually to represent inputs to the expression, For example, variables A, B, C etc.,
giving us a logical expression of A + B = C, but each variable can ONLY be a 0 or a 1.
Examples of these individual laws of Boolean, rules and theorems for Boolean Algebra are
given in the following table.
A in parallel with
Annulment
A+1=1 closed = “CLOSED”
A in parallel with
A+0=A Identity
open = “A”
A in series with
A.1=A Identity
closed = “A”
A in series with
A.0=0 Annulment
open = “OPEN”
A in parallel with
A+A=A Idempotent
A = “A”
A in series with
A.A=A Idempotent
A = “A”
NOT NOT A
NOT A’ = A Double Negation
(double negative) = “A”
A in parallel with
A + A’ = 1 Complement
NOT A = “CLOSED”
A in series with
A . A’ = 0 Complement
NOT A = “OPEN”
A in parallel with B =
A+B = B+A Commutative
B in parallel with A
A in series with B =
A.B = B.A Commutative
B in series with A
A brief description of the various Laws of Boolean are given below with A representing a
variable input.
A term AND´ed with a “0” equals 0 or OR´ed with a “1” will equal 1.
• Identity Law –
A term OR´ed with a “0” or AND´ed with a “1” will always equal that term.
• Idempotent Law –
• Complement Law –
A term AND´ed with its complement equals “0” and a term OR´ed with its complement
equals “1”.
• Commutative Law –
❖ Task-1:
Consider an example for the following Boolean function: F1 = x+y’z
✓ Design a circuit for the given Function (i.e., F1 = x+y’z) on the Trainer Board.
✓ Verify the given Truth table.
X Y Z Y’ Y’Z F1
0 0 0 1 0 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 1 0 0 0
1 0 0 1 0 1
1 0 1 1 1 1
1 1 0 0 0 1
1 1 1 0 0 1
❖ Task-2:
Consider the following equation: F2 = x’y + y’z
✓ Design a circuit for the given equation (i.e., F2 = x’y + y’z) on the Trainer Board.
✓ Complete and Verify the given Truth table.
X X’ Y Y’ Z X’Y Y’Z F2
❖ Task-3:
✓ Design a circuit on the trainer board for DeMorgan’s first theorem.
✓ Verify the given Truth table
A B A.B (A.B)’ A’ B’ A’ + B’
0 0 0 1 1 1 1
0 1 0 1 1 0 1
1 0 0 1 0 1 1
1 1 1 0 0 0 0
❖ Task-4:
✓ Design a circuit on the trainer board for DeMorgan’s second theorem.
✓ Complete and Verify the given Truth table.
✓ Draw a logic diagram for DeMorgan’s second theorem.
Inputs Outputs
A B A+B (A+B)’ A’ B’ A’ . B’
Lab Rubrics
3 2 1 0
Can independently Can setup, and Can setup, and Cannot setup or
Apparatus setup, operate and handle the apparatus handle the handle the
Handling handle the apparatus with minimal help apparatus with apparatus
some help
Assembly/ Can assemble Can assemble Can assemble but Cannot assemble
Apparatus according to the design according to design inaccurately
design within least time
Date: ______________________
Lab-4
Combinational Logic Circuits (CLC)
Adders, Subtractors & Comparator
In the combinational circuits, different logic gates are used to design encoder,
multiplexer, decoder & de-multiplexer. These circuits have some characteristics like the
output of this circuit mainly depends on the levels which are there at input terminals at
any time. This circuit doesn’t include any memory. The earlier state of the input doesn’t
have any influence on the current state of this circuit. The inputs and outputs of a
combinational circuit are ‘n’ no. of inputs & ‘m’ no. of outputs. Some of the combinational
circuits are half adder and full adder, subtractor, encoder, decoder, multiplexer, and
demultiplexer.
Unlike Sequential Logic Circuits whose outputs are dependent on both their present
inputs and their previous output state giving them some form of Memory. The outputs
of Combinational Logic Circuits are only determined by the logical function of their
current input state, logic “0” or logic “1”, at any given instant in time.
The result is that combinational logic circuits have no feedback, and any changes to the
signals being applied to their inputs will immediately have an effect at the output. In other
words, in a Combinational Logic Circuit, the output is dependent at all times on the
combination of its inputs. Thus, a combinational circuit is memoryless.
So, if one of its inputs condition changes state, from 0-1 or 1-0, so too will the resulting
output as by default combinational logic circuits have “no memory”, “timing” or
“feedback loops” within their design.
Combinational Logic Circuits are made up from basic logic NAND, NOR or NOT gates that
are “combined” or connected together to produce more complicated switching circuits.
These logic gates are the building blocks of combinational logic circuits. An example of a
combinational circuit is a decoder, which converts the binary code data present at its
input into a number of different output lines, one at a time producing an equivalent
decimal code at its output.
❖ Task-1:
✓ Design a combinational logic circuit that performs arithmetic operation for adding two
bits.
• Truth Table:
• Boolean Expression:
Sum = S = A’B+AB’ = A ⊕ B
Carry = C = A.B
• Logic Diagram:
❖ Task-2:
✓ Design a combinational logic circuit that performs arithmetic operation for adding
three bits.
✓ Complete and verify the given truth table and Boolean expressions.
✓ Draw the Logic Diagram for Full Adder circuit.
• Truth Table:
Total number of inputs = n = 3
Total number of outputs = 2^n = 2^3 = 8
Inputs Outputs
• Boolean Expression:
• Logic Diagram:
❖ Task-3:
✓ Design a combinational logic circuit that performs arithmetic operation for subtracting
two bits.
✓ Verify the given Truth table and Boolean expressions.
1 0 1 0
1 1 0 0
• Boolean Expression:
Difference = D = X’Y+XY’ = X ⊕ Y
Borrow = B = X’.Y
• Logic Diagram:
❖ Task-4:
✓ Design a combinational logic circuit that performs arithmetic operation for
subtracting three bits.
✓ Complete and verify the given Truth table and Boolean expressions.
✓ Draw the Logic diagram for Full Subtractor circuit.
• Truth Table:
Total number of inputs = n = 3
Input Output
• Boolean Expression:
Difference = D = (X’.Y’.BIN) + (X’.Y.B’IN) + (X.Y’.B’IN) + (X.Y.BIN)
= X ⊕ Y ⊕ BIN
• Logic Diagram:
numbers A, B, and determines their relative magnitudes. The outcome of the comparison
is specified my three binary variables that indicate whether A>B, A=B, or A<B.
Digital or Binary Comparators are made up from standard AND, NOR and NOT gates that
compare the digital signals present at their input terminals and produce an output
depending upon the condition of those inputs.
There are two main types of Digital Comparator available, and these are.
1. Identity Comparator – an Identity Comparator is a digital comparator with only
one output terminal for when A = B, either A = B = 1 (HIGH) or A = B = 0 (LOW)
❖ Task-5:
✓ Design a combinational Logic Circuit that compares TWO 1-bit numbers (A and B).
✓ Verify the given Truth table and Boolean expressions.
• Logic Diagram:
Input Output
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
• Boolean Expression:
Lab Rubrics
3 2 1 0
Can independently Can setup, and Can setup, and Cannot setup or
Apparatus setup, operate and handle the apparatus handle the handle the
Handling handle the apparatus with minimal help apparatus with apparatus
some help
Assembly/ Can assemble Can assemble Can assemble but Cannot assemble
Apparatus according to the design according to design inaccurately
design within least time
Date: ______________________
Lab # 05
Combinational Logic Circuits (CLC)
Encoders & Decoders
5.2 Decoders:
The name “Decoder” means to translate or decode coded information from one format
into another, so a binary decoder transforms “n” binary input signals into an equivalent
code using 2n outputs.
Binary Decoders are another type of digital logic device that has inputs of 2-bit, 3-bit or
4-bit codes depending upon the number of data input lines, so a decoder that has a set
of two or more bits will be defined as having an n-bit code, and therefore it will be possible
to represent 2n possible values. Thus, a decoder generally decodes a binary value into a
non-binary one by setting exactly one of its n outputs to logic “1”.
If a binary decoder receives n inputs (usually grouped as a single Binary or Boolean
number) it activates one and only one of its 2n outputs based on that input with all other
outputs deactivated.
A Binary Decoder converts coded inputs into coded outputs, where the input and output
codes are different, and decoders are available to “decode” either a Binary or BCD (8421
code) input pattern to typically a Decimal output code. Commonly available BCD-to-
Decimal decoders include the TTL 7442 or the CMOS 4028. Generally, a decoders output
code normally has more bits than its input code and practical “binary decoder” circuits
include, 2-to-4, 3-to-8 and 4-to-16 line configurations.
❖ Task-1:
✓ Design a circuit for 2-to-4 Line DECODER with E=1 (i.e., enable is HIGH) on the trainer
board.
✓ Verify the given truth table and the Boolean expression.
✓ Draw the Logic Diagram for 2-to-4 line decoder circuit.
• Truth Table:
Enable Inputs Outputs
E A1 A0 Y3 Y2 Y1 Y0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
• Boolean Expression:
Y0 = E.A1’.A0’
Y1 = E.A1’.A0
Y2 = E.A1.A0’
Y3 = E.A1.A0
• Logic Diagram:
❖ Task-2:
✓ Design a circuit for 3-to-8 Line DECODER with E=1 (i.e., enable is HIGH) on the trainer
board.
✓ Complete and verify the given truth table.
✓ Write down the Boolean expression for the Output terms.
✓ Draw the Logic Diagram for 3-to-8 line decoder circuit.
• Truth Table:
Enable Inputs Outputs
E A2 A1 A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
• Boolean Expression:
Y0 = _________________________________
Y1 = _________________________________
Y2 = _________________________________
Y3 = _________________________________
Y4 = _________________________________
Y5 = _________________________________
Y6 = _________________________________
Y7 = _________________________________
• Logic Diagram:
5.3 Encoders:
An Encoder is a combinational circuit that performs the reverse operation of Decoder. It
has maximum of 2n input lines and ‘n’ output lines. It will produce a binary code
equivalent to the input, which is active High. Therefore, the encoder encodes 2 n input
lines with ‘n’ bits. It is optional to represent the enable signal in encoders.
Digital Encoder more commonly called a Binary Encoder takes ALL its data inputs one at
a time and then converts them into a single encoded output. So we can say that a binary
encoder, is a multi-input combinational logic circuit that converts the logic level “1” data
at its inputs into an equivalent binary code at its output.
Generally, digital encoders produce outputs of 2-bit, 3-bit or 4-bit codes depending upon
the number of data input lines. An “n-bit” binary encoder has 2n input lines and n-
bit output lines with common types that include 4-to-2, 8-to-3 and 16-to-4 line
configurations.
The output lines of a digital encoder generate the binary equivalent of the input line
whose value is equal to “1” and are available to encode either a decimal or hexadecimal
input pattern to typically a binary or “B.C.D” (binary coded decimal) output code.
❖ Task-3:
✓ Design a circuit for 4-to-2 Line ENCODER on the trainer board.
✓ Verify the given truth table and the Boolean expression.
✓ Draw the Logic Diagram for 4-to-2 Line decoder circuit.
• Truth Table:
Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
• Boolean Expression:
A1 = Y3 + Y2 ; A0 = Y3 + Y1
• Logic Diagram:
❖ Task-4:
✓ Design a circuit 8-to-3 Line ENCODER on the trainer board.
✓ Complete and verify the given truth table.
✓ Write down the Boolean expression for the Output terms.
✓ Draw the Logic Diagram for 8-to-3 Line ENCODER circuit.
• Truth Table:
Inputs Outputs
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0
• Boolean Expression:
A2 = ______________________________ ; A0 = _________________________
A1 = ______________________________
• Logic Diagram:
❖ Task-5:
✓ Design a circuit for Decimal to BCD Encoder on the trainer board.
✓ Complete and verify the given truth table.
✓ Write down the Boolean expression for the Output terms.
✓ Draw the Logic Diagram for Decimal to BCD ENCODER circuit.
• Truth Table:
No. Inputs Outputs
I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 1 0
2 0 0 0 0 0 0 0 1 0 0
3 0 0 0 0 0 0 1 0 0 0
4 0 0 0 0 0 1 0 0 0 0
5 0 0 0 0 1 0 0 0 0 0
6 0 0 0 1 0 0 0 0 0 0
7 0 0 1 0 0 0 0 0 0 0
8 0 1 0 0 0 0 0 0 0 0
9 1 0 0 0 0 0 0 0 0 0
• Boolean Expression:
A3 = _________________________________
A2 = _________________________________
A1 = _________________________________
A0 = _________________________________
• Logic Diagram:
Lab Rubrics
3 2 1 0
Can independently Can setup, and Can setup, and Cannot setup or
Apparatus setup, operate and handle the apparatus handle the handle the
Handling handle the apparatus with minimal help apparatus with apparatus
some help
Assembly/ Can assemble Can assemble Can assemble but Cannot assemble
Apparatus according to the design according to design inaccurately
design within least time
Date: ______________________
Lab # 06
Combinational Logic Circuits (CLC)
Multiplexers & Demultiplexers
The most basic type of multiplexer device is that of a one-way rotary switch as shown.
4 x 1 Multiplexer
❖ Task-1:
✓ Design a circuit for 4x1 MUX on the trainer board.
✓ Verify the given truth table and the Boolean expression.
✓ Draw the Logic Diagram for 4x1 MUX circuit.
• Truth Table:
• Boolean Expression:
Y = I0 + I1 + I2 + I3
Y = S1’.S0’.I0 + S1’.S0.I1 + S1’.S0.I2 + S1.S0.I3
• Logic Diagram:
In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1 Multiplexer.
We know that 4x1 Multiplexer has 4 data inputs, 2 selection lines and one output. Whereas
8x1 Multiplexer has 8 data inputs, 3 selection lines and one output.
So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs. Since,
each 4x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by
considering the outputs of first stage as inputs and to produce the final output.
Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection lines s2, s1 & s0 and one
output Y. The block diagram of 4x1 Multiplexer is shown in the following figure.
8 x 1 Multiplexer
The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data inputs of
upper 4x1 Multiplexer are I7 to I4 and the data inputs of lower 4x1 Multiplexer are I3 to I0.
Therefore, each 4x1 Multiplexer produces an output based on the values of selection lines,
s1 & s0.
The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is
present in second stage. The other selection line, s2 is applied to 2x1 Multiplexer.
• If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I3 to I0 based
on the values of selection lines s1 & s0.
• If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I7 to I4 based
on the values of selection lines s1 & s0.
Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer performs
as one 8x1 Multiplexer.
Similarly, we can implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1 Multiplexer.
We know that 8x1 Multiplexer has 8 data inputs, 3 selection lines and one output. Whereas,
16x1 Multiplexer has 16 data inputs, 4 selection lines and one output.
So, we require two 8x1 Multiplexers in first stage in order to get the 16 data inputs. Since,
each 8x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by
considering the outputs of first stage as inputs and to produce the final output.
❖ Task-2:
✓ Design a circuit for 8x1 MUX on the trainer board.
✓ Complete and verify the given truth table.
✓ Write down the Boolean expression for the Output terms.
✓ Draw the Logic Diagram for 8x1 MUX circuit.
• Truth Table:
Inputs Select Lines Output
I7 I6 I5 I4 I3 I2 I1 I0 S2 S1 S0 Y
• Boolean Expression:
Y = _____________________________
Y = __________________________________________________
• Logic Diagram:
1 x 4 De-Multiplexer
❖ Task-3:
✓ Design a circuit for 1x4 De-Mux on the trainer board.
✓ Verify the given truth table and the Boolean expression.
✓ Draw the Logic Diagram for 1x4 De-Mux circuit.
• Truth Table:
I/p S1 S0 Y3 Y2 Y1 Y0
I 0 0 0 0 0 I
I 0 1 0 0 I 0
I 1 0 0 I 0 0
I 1 1 I 0 0 0
• Boolean Expression:
Y3 = S1.S0.I
Y2 = S1.S0’.I
Y1 = S1’.S0.I
Y0 = S1’.S0’.I
• Logic Diagram:
1 x 8 De-Multiplexer
The common selection lines, s1 & s0 are applied to both 1x4 De-Multiplexers. The outputs of
upper 1x4 De-Multiplexer are Y7 to Y4 and the outputs of lower 1x4 De-Multiplexer are Y3 to
Y 0.
The other selection line, s2 is applied to 1x2 De-Multiplexer. If s2 is zero, then one of the four
outputs of lower 1x4 De-Multiplexer will be equal to input, I based on the values of selection
lines s1 & s0. Similarly, if s2 is one, then one of the four outputs of upper 1x4 De-Multiplexer
will be equal to input, I based on the values of selection lines s1 & s0.
Similarly, we can implement 1x16 De-Multiplexer using 1x8 De-Multiplexers and 1x2 De-
Multiplexer. We know that 1x8 De-Multiplexer has single input, three selection lines and
eight outputs. Whereas, 1x16 De-Multiplexer has single input, four selection lines and sixteen
outputs.
So, we require two 1x8 De-Multiplexers in second stage in order to get the final sixteen
outputs. Since, the number of inputs in second stage is two, we require 1x2 De-Multiplexer in
first stage so that the outputs of first stage will be the inputs of second stage. Input of this
1x2 De-Multiplexer will be the overall input of 1x16 De-Multiplexer.
❖ Task-4:
✓ Design a circuit for 1x8 De-Mux on the trainer board.
✓ Complete and verify the given truth table.
✓ Write down the Boolean expression for the Output terms.
✓ Draw the Logic Diagram for 1x8 De-Mux circuit.
• Truth Table:
Input Select Lines Outputs
I/p S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
I
• Boolean Expression:
Y7 = _____________________________________ ; Y3 = ________________________________
Y6 = _____________________________________ ; Y2 = ________________________________
Y5 =______________________________________ ; Y1 = ________________________________
Y4 = _____________________________________ ; Y0 = ________________________________
• Logic Diagram:
Lab Rubrics
3 2 1 0
Can independently Can setup, and Can setup, and Cannot setup or
Apparatus setup, operate and handle the apparatus handle the handle the
Handling handle the apparatus with minimal help apparatus with apparatus
some help
Assembly/ Can assemble Can assemble Can assemble but Cannot assemble
Apparatus according to the design according to design inaccurately
design within least time
Date: ______________________
Lab-7
Sequential Logic Circuits (SLC)
Flip Flops (SR & D)
This sequential circuit contains a set of inputs and outputs. The outputs of sequential
circuit depends not only on the combination of present inputs but also on the previous
outputs. Previous output is nothing but the present state. Therefore, sequential circuits
contain combinational circuits along with memory storage elements. Some sequential
circuits may not contain combinational circuits, but only memory elements.
Following table shows the differences between combinational circuits and sequential
circuits.
In the above figure, square wave is considered as clock signal. This signal stays at logic
High 5V for some time and stays at logic Low 0V for equal amount of time. This pattern
repeats with some time period. In this case, the time period will be equal to either twice
of ON time or twice of OFF time.
The reciprocal of the time period of clock signal is known as the frequency of the clock
signal. All sequential circuits are operated with clock signal. So, the frequency at which
the sequential circuits can be operated accordingly the clock signal frequency has to be
chosen.
Triggering:
While applying the clock pulse to the flip flop, it gets triggered by two ways, Level
triggering and edge triggering.
Level Triggering:
In this, the flip flop is triggered only during the high-level or the low level of the clock
pulse. In other words, the output changes its state, when active low or high level is
maintained at the clock signal. Based on the level of triggering, it is of two types:-
• Positive Level Triggering — If the sequential circuit is operated with the clock
signal when it is in Logic High, then that type of triggering is known as Positive
level triggering. It is highlighted in below figure.
• Negative Level Triggering — If the sequential circuit is operated with the clock
signal when it is in Logic Low, then that type of triggering is known as Negative
level triggering. It is highlighted in the following figure.
Edge Triggering:
In edge triggering, the flip flop changes its state during the positive edge or negative edge
of the clock pulse. There are two types of edge triggering.
• Positive Edge Triggering — If the sequential circuit is operated with the clock
signal that is transitioning from Logic Low to Logic High, then that type of
triggering is known as Positive edge triggering. It is also called as rising edge
triggering. It is shown in the following figure.
• Negative Edge Triggering — If the sequential circuit is operated with the clock
signal that is transitioning from Logic High to Logic Low, then that type of
triggering is known as Negative edge triggering. It is also called as falling edge
triggering. It is shown in the following figure.
7.4 Latches:
There are two types of memory elements based on the type of triggering that is suitable
to operate it.
• Latches
• Flip-flops
Latches operate with enable signal, which is level sensitive. Whereas flip-flops are edge
sensitive. Let us discuss about SR Latch & D Latch one by one.
SR Latch:
SR Latch is also called as Set Reset Latch. This latch affects the outputs as long as the
enable, E is maintained at ‘1’. The circuit diagram of SR Latch is shown in the following
figure.
This circuit has two inputs S & R and two outputs Q(t) & Q(t)’. The upper NOR gate has
two inputs R & complement of present state, Q(t)’ and produces next state, Q(t+1)
when enable, E is ‘1’.
Similarly, the lower NOR gate has two inputs S & present state, Q t and produces
complement of next state, Qt+1t+1’ when enable, E is ‘1’.
We know that a 2-input NOR gate produces an output, which is the complement of
another input when one of the input is ‘0’. Similarly, it produces ‘0’ output, when one of
the input is ‘1’.
• If S = 1, then next state Q(t+1) will be equal to ‘1’ irrespective of present state,
Q(t) values.
• If R = 1, then next state Q(t+1) will be equal to ‘0’ irrespective of present state,
Q(t) values.
At any time, only of those two inputs should be ‘1’. If both inputs are ‘1’, then the next
state Q(t+1) value is undefined.
The following table shows the state table of SR latch.
S R Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 -
Therefore, SR Latch performs three types of functions such as Hold, Set & Reset based
on the input conditions.
D Latch:
There is one drawback of SR Latch. That is the next state value can’t be predicted when
both the inputs S & R are one. So, we can overcome this difficulty by D Latch. It is also
called as Data Latch. The circuit diagram of D Latch is shown in the following figure.
This circuit has single input D and two outputs Q(t) & Q(t)’. D Latch is obtained from SR
Latch by placing an inverter between S and R inputs and connect D input to S. That
means we eliminated the combinations of S & R are of same value.
• If D = 0 → S = 0 & R = 1, then next state Q(t+1) will be equal to ‘0’ irrespective of
present state, Q(t) values. This is corresponding to the second row of SR Latch
state table.
• If D = 1 → S = 1 & R = 0, then next state Q(t+1) will be equal to ‘1’ irrespective of
present state, Q(t) values. This is corresponding to the third row of SR Latch state
table.
The following table shows the state table of D latch.
D Q(t+1)
0 0
1 1
Therefore, D Latch Hold the information that is available on data input, D. That means
the output of D Latch is sensitive to the changes in the input, D as long as the enable is
High.
In this chapter, we implemented various Latches by providing the cross coupling
between NOR gates. Similarly, you can implement these Latches using NAND gates.
SR Flip-Flop:
SR flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas SR latch operates with enable signal. The block diagram of SR flip-flop is shown
in the following figure.
The simplest way to make any basic single bit set-reset SR flip-flop is to connect together
a pair of cross-coupled 2-input NAND gates as shown, to form a Set-Reset Bistable also
known as an active LOW SR NAND Gate Latch, so that there is feedback from each output
to one of the other NAND gate inputs. This device consists of two inputs, one called
the Set, S and the other called the Reset, R with two corresponding outputs Q and its
inverse or complement Q (not-Q). The circuit diagram of SR flip-flop is shown below:
This circuit has two inputs S & R and two outputs Q(t) & Q(t)’. The operation of SR
flipflop is similar to SR Latch. But, this flip-flop affects the outputs only when positive
transition of the clock signal is applied instead of active enable.
❖ Task-1:
✓ Design a circuit for SR Flip-Flop (using NAND Gates only) on the trainer board.
✓ Verify the given State & Characteristics table.
• State Table:
The following table shows the state table of SR flip-flop.
S R Q(t+1)
0 0 Q(t) No Change/
Present State
0 1 0 Reset
1 0 1 Set
1 1 - Undetermined
Here, Q(t) & Q(t+1) are present state & next state respectively. So, SR flip-flop can be used
for one of these three functions such as Hold, Reset & Set based on the input conditions,
when positive transition of clock signal is applied. The following table shows
the characteristic table of SR flip-flop.
S R Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 x
1 1 1 x
D Flip-Flop:
D flip-flop is a better alternative that is very popular with digital electronics. They are
commonly used for counters and shift-registers and input synchronization. The logic
symbol of D flip-flop is shown in the following figure.
D flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas D latch operates with enable signal. That means, the output of D flip-flop is
insensitive to the changes in the input, D except for active transition of the clock signal.
The circuit diagram of D flip-flop is shown below:
❖ Task-2:
✓ Design a circuit for D Flip-Flop (using NAND Gates only) on the trainer board.
✓ Verify the given State table.
• State Table:
The following table shows the state table of D flip-flop.
D Q(t + 1)
0 0
1 1
Lab Rubrics
3 2 1 0
Can independently Can setup, and Can setup, and Cannot setup or
Apparatus setup, operate and handle the apparatus handle the handle the
Handling handle the apparatus with minimal help apparatus with apparatus
some help
Assembly/ Can assemble Can assemble Can assemble but Cannot assemble
Apparatus according to the design according to design inaccurately
design within least time
Date: ______________________
Lab-8
Sequential Logic Circuits (SLC)
Flip Flops (JK & T)
A gated S R flip flop with the addition of a clock input circuitry is basically the J k flip flop.
This circuit prevents the invalid output condition which occurs when both inputs are high.
The new addition here gives us four possible outputs of the flip flop. The output may be
– No Change, Logic 0, Logic 1 & Toggle. The circuit diagram of JK flip-flop is shown in the
following figure.
The input condition of J=K=1, gives an output inverting the output state. However, the
outputs are the same when one tests the circuit practically.
In simple words, If J and K data input are different (i.e. high and low) then the output Q
takes the value of J at the next clock edge. If J and K are both low then no change occurs.
If J and K are both high at the clock edge then the output will toggle from one state to the
other. JK Flip-Flops can function as Set or Reset Flip-flops.
❖ Task-1:
✓ Design a circuit for JK Flip-Flop (using NAND Gates only) on the trainer board.
✓ Verify the given State & Characteristics table.
• State Table:
The following table shows the state table of JK flip-flop.
J K Q(t+1)
0 1 0 0
1 0 1 1
1 1 Q(t)' Q(t)’
Here, Q(t) & Q(t+1) are present state & next state respectively. So, JK flip-flop can be used
for one of these four functions such as Hold, Reset, Set & Complement of present state
based on the input conditions, when positive transition of clock signal is applied. The
following table shows the characteristic table of JK flip-flop.
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
T Flip-Flop:
T flip-flop is the simplified version of JK flip-flop. It is obtained by connecting the same
input ‘T’ to both inputs of JK flip-flop. It operates with only positive clock transitions or
negative clock transitions. The logic symbol of T flip-flop is shown in the following figure.
A T flip-flop is like a JK flip-flop. These are basically a single input version of JK flip-flops.
This modified form of JK flip-flop is obtained by connecting both inputs J and K together.
It has only one input along with the clock input.
This circuit has single input T and two outputs Q(t) & Qt()’. The operation of T flip-flop is
same as that of JK flip-flop. Here, we considered the inputs of JK flip-flop as J = T and K =
T in order to utilize the modified JK flip-flop for 2 combinations of inputs. So, we
eliminated the other two combinations of J & K, for which those two values are
complement to each other in T flip-flop.
❖ Task-2:
✓ Design a circuit for T Flip-Flop (using NAND Gates only) on the trainer board.
✓ Verify the given State table.
• State Table:
The following table shows the state table of T flip-flop.
D Q(t+1)
0 Q(t)
1 Q(t)’
Here, Q(t) & Q(t+1) are present state & next state respectively. So, T flip-flop can be used
for one of these two functions such as Hold, & Complement of present state based on the
input conditions, when positive transition of clock signal is applied. The following table
shows the characteristic table of T flip-flop.
T Q(t) Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0
The output of T flip-flop always toggles for every positive transition of the clock signal
when input T remains at logic High 1. Hence, T flip-flop can be used in counters.
Lab Rubrics
3 2 1 0
Can independently Can setup, and Can setup, and Cannot setup or
Apparatus setup, operate and handle the apparatus handle the handle the
Handling handle the apparatus with minimal help apparatus with apparatus
some help
Assembly/ Can assemble Can assemble Can assemble but Cannot assemble
Apparatus according to the design according to design inaccurately
design within least time
Date: ______________________
Lab-9
Sequential Logic Circuits (SLC)
Counters & Shift Registers
• Asynchronous counters
• Synchronous counters
Asynchronous Counters:
If the flip-flops do not receive the same clock signal, then that counter is called
as Asynchronous counter. The output of system clock is applied as clock signal only to
first flip-flop. The remaining flip-flops receive the clock signal from output of its previous
stage flip-flop. Hence, the outputs of all flip-flops do not change affect at the same time.
The 3-bit Asynchronous binary up counter contains three T flip-flops and the T-input of all
the flip-flops are connected to ‘1’. All these flip-flops are negative edge triggered but the
outputs change asynchronously. The clock signal is directly applied to the first T flip-flop.
So, the output of first T flip-flop toggles for every negative edge of clock signal.
The output of first T flip-flop is applied as clock signal for second T flip-flop. So, the output
of second T flip-flop toggles for every negative edge of output of first T flip-flop. Similarly,
the output of third T flip-flop toggles for every negative edge of output of second T flip-
flop, since the output of second T flip-flop acts as the clock signal for third T flip-flop.
Assume the initial status of T flip-flops from rightmost to leftmost is Q2Q1Q0 = 000.
Here, Q2 & Q0 are MSB & LSB respectively. We can understand the working of 3-bit
asynchronous binary counter from the following table.
0 0 0 0
1 1 0 0
2 0 1 0
3 1 1 0
4 0 0 1
5 1 0 1
6 0 1 1
7 1 1 1
Here Q0 toggled for every negative edge of clock signal. Q1 toggled for every Q0 that
goes from 0 to 1, otherwise remained in the previous state. Similarly, Q2 toggled for
every Q1 that goes from 0 to 1, otherwise remained in the previous state.
The initial status of the T flip-flops in the absence of clock signal is Q2Q1Q0=000. This is
decremented by one for every negative edge of clock signal and reaches to the same value
at 8th negative edge of clock signal. This pattern repeats when further negative edges of
clock signal are applied.
The block diagram of 3-bit Asynchronous binary down counter is similar to the block
diagram of 3-bit Asynchronous binary up counter. But, the only difference is that instead
of connecting the normal outputs of one stage flip-flop as clock signal for next stage flip-
flop, connect the complemented outputs of one stage flip-flop as clock signal for next
stage flip-flop. Complemented output goes from 1 to 0 is same as the normal output goes
from 0 to 1.
Assume the initial status of T flip-flops from rightmost to leftmost is Q2Q1Q0=0000.
Here, Q2 & Q0 are MSB & LSB respectively. We can understand the working of 3-bit
asynchronous binary down counter from the following table.
No of negative Q0 Q1 Q2
edge of Clock LSB MSB
0 0 0 0
1 1 1 1
2 0 1 1
3 1 0 1
4 0 0 1
5 1 1 0
6 0 1 0
7 1 0 0
Here Q0 toggled for every negative edge of clock signal. Q1 toggled for every Q0 that
goes from 0 to 1, otherwise remained in the previous state. Similarly, Q2 toggled for
every Q1 that goes from 0 to 1, otherwise remained in the previous state.
The initial status of the T flip-flops in the absence of clock signal is Q2Q1Q0 = 000. This is
decremented by one for every negative edge of clock signal and reaches to the same value
at 8th negative edge of clock signal. This pattern repeats when further negative edges of
clock signal are applied.
Synchronous Counters:
If all the flip-flops receive the same clock signal, then that counter is called
as Synchronous counter. Hence, the outputs of all flip-flops change affect at the same
time.
The 3-bit Synchronous binary up counter contains three T flip-flops & one 2-input AND
gate. All these flip-flops are negative edge triggered and the outputs of flip-flops
change affect synchronously. The T inputs of first, second and third flip-flops are 1, Q0
& Q1Q0 respectively.
The output of first T flip-flop toggles for every negative edge of clock signal. The output
of second T flip-flop toggles for every negative edge of clock signal if Q0 is 1. The output
of third T flip-flop toggles for every negative edge of clock signal if both Q0 & Q1 are 1.
The 3-bit Synchronous binary down counter contains three T flip-flops & one 2-input AND
gate. All these flip-flops are negative edge triggered and the outputs of flip-flops
change affect synchronously. The T inputs of first, second and third flip-flops are 1, Q0’
& Q1′ Q0′ respectively.
The output of first T flip-flop toggles for every negative edge of clock signal. The output
of second T flip-flop toggles for every negative edge of clock signal if Q0′ is 1. The output
of third T flip-flop toggles for every negative edge of clock signal if both Q1′ & ′Q0′ are 1.
❖ Task-1:
✓ Design a circuit for 2-bit UP/DOWN Counter on the Trainer Board such that:
• When UP/DOWN = 0, the counter counts down &
• Circuit Diagram:
• State Diagram:
❖ Task-2:
✓ Design a circuit for 2-bit Shift Register on the Trainer Board such that:
• At the first clock signal, the value Data is stored and displayed at Q1.
• At the second clock signal, the value of Q1 is stored at the second flip-flop and
displayed at Q0. At the same time a new value Data is stored and displayed at Q1.
By doing this, you have "shifted" the stored value by one flip-flop to the right.
• Circuit Diagram:
Lab Rubrics
3 2 1 0
Can independently Can setup, and Can setup, and Cannot setup or
Apparatus setup, operate and handle the apparatus handle the handle the
Handling handle the apparatus with minimal help apparatus with apparatus
some help
Assembly/ Can assemble Can assemble Can assemble but Cannot assemble
Apparatus according to the design according to design inaccurately
design within least time
Date: ______________________
Lab-10
Introduction to Verilog HDL
Gate Level Modeling
10.1 Why Use Verilog HDL:
• Verilog HDL is a general-purpose hardware description language that is easy to learn
and easy to use. It is similar in syntax to the C programming language.
• Verilog HDL allows different levels of abstraction to be mixed in the same model. Thus,
a designer can define a hardware model in terms of switches, gates, RTL, or behavioral
code. Also, a designer needs to learn only one language for stimulus and hierarchical
design.
• By describing designs in HDLs, functional verification of the design can be done early
in the design cycle. Since designers work at the RTL level, they can optimize and modify
the RTL description until it meets the desired functionality. Most design bugs are
eliminated at this point. This cuts down design cycle time significantly because the
probability of hitting a functional bug at a later time in the gate-level netlist or physical
layout is minimized.
• The Programming Language Interface (PLI) is a powerful feature that allows the user
to write custom C code to interact with the internal data structures of Verilog.
Designers can customize a Verilog HDL simulator to their needs with the PLI.
Top-Down Design:
In a top-down design methodology, we define the top-level block and identify the sub-
blocks necessary to build the top-level block. We further subdivide the sub-blocks until
we come to the leaf cell, which are the cells that cannot be further subdivided.
Bottom-Up Design:
In a bottom-up design methodology, we first identify the building blocks that are
available to us. We build bigger cells, using these building blocks. These cells are then
used for higher-level blocks until we build the top-level block in the design.
Gate Level:
The module is implemented in terms of logic gates and interconnections between these
gates. Design at this level is similar to describing a design in terms of a gate-level logic
diagram.
Switch Level:
This is the lowest level of abstraction provided by Verilog. A module can be implemented
in terms of switches, storage nodes, and the interconnections between them. Design at
this level requires knowledge of switch-level implementation details.
10.4 Modules:
A module is the basic building block in Verilog. A module can be an element or a collection
of lower-level design blocks. Typically, elements are grouped into modules to provide
common functionality that is used at many places in the design. A module provides the
necessary functionality to the higher-level block through its port interface (inputs and
outputs), but hides the internal implementation. This allows the designer to modify
module internals without affecting the rest of the design.
In Verilog, a module is declared by the keyword module. A corresponding keyword
endmodule must appear at the end of the module definition. Each module must have a
module_name, which is the identifier for the module, and a module_terminal_list, which
describes the input and output terminals of the module.
output [3:0] q;
//Four instances of the module T_FF are created. Each has a unique name. Each
instance is passed a set of signals. Notice, that each instance is a copy of the
T_FF tff2(q[2],q[1],reset);
Endmodule
Examples:
• reg r; // 1-bit reg variable
• wire w1, w2; // 2 1-bit wire variable
• reg [7:0] reg; // 8-bit register
• reg [7:0] memory [0:1023]; // a 1 KB memory
10.7 Ports:
Ports provide the interface by which a module can communicate with its environment.
For example, the input/output pins of an IC chip are its ports.
All ports in the list of ports must be declared in the module. Ports can be declared as
follows:
Each port in the port list is defined as input, output, or inout, based on the direction of
the port signal.
Logic Synthesis:
It is the process of deriving a list of components and their interconnections (called a
netlist) from the model of digital system described in HDL.
The gate level netlist can be used to fabricate an integrated circuit or to layout a printed
circuit board.
AND/OR Gates:
And/or gates have one scalar output and multiple scalar inputs. The first terminal in the
list of gate terminals is an output and the other terminals are inputs. The output of a gate
is evaluated as soon as one of the inputs changes. The and/or gates available in Verilog
are shown below:
• AND
• OR
• NAND
• NOR
• XOR
• XNOR
• NOT
Buf/Not Gates:
Buf/not gates have one scalar input and one or more scalar outputs. The last terminal in
the port list is connected to the input. Other terminals are connected to the outputs. We
will discuss gates that have one input and one output.
Two basic buf/not gate primitives are provided in Verilog.
• Buf
• Not
Bufif/Notif Gates:
Gates with an additional control signal on buf and not (tristate buffer and tristate inverter)
gates are also available.
Two basic buf/not gate primitives are provided in Verilog.
• Bufif 0
• Notif 0
• Full Adder:
module FullAdder(A ,B, C, Sum,Cout);
input A; input B; input C;
output Sum; output Cout;
wire w1,w2,w3;
xor g1(w1,A,B);
and g2(w2,A,B);
xor u1(Sum,w1,C);
and u2(w3,w1,C);
or u3(Cout,w2,w3);
endmodule
❖ Task-2:
✓ Implement the following circuits using gate level modeling.
1)
2)
Lab Rubrics
3 2 1 0
Can independently Can setup, and Can setup, and Cannot setup or
Apparatus setup, operate and handle the apparatus handle the handle the
Handling handle the apparatus with minimal help apparatus with apparatus
some help
Assembly/ Can assemble Can assemble Can assemble but Cannot assemble
Apparatus according to the design according to design inaccurately
design within least time
Date: ______________________
Lab-11
Introduction to Verilog HDL
DataFlow Modeling
11.1 Why Use Verilog HDL:
A continuous assignment is the most basic statement in dataflow modeling, used to drive
a value onto a net. This assignment replaces gates in the description of the circuit and
describes the circuit at a higher level of abstraction. The assignment statement starts with
the keyword assign.
//Same effect is achieved by an implicit continuous assignment wire out = in1 &
in2;
assign out = i1 & i2; //Note that out was not declared as a wire
11.2 Delays:
Delay values control the time between the change in a right-hand-side operand and when
the new value is assigned to the left-hand side. Three ways of specifying delays in
continuous assignment statements are regular assignment delay, implicit continuous
assignment delay, and net declaration delay.
The first method is to assign a delay value in a continuous assignment statement. The
delay value is specified after the keyword assign. Any change in values of in1 or in2 will
result in a delay of 10 time units before recomputation of the expression in1 & in2, and
the result will be assigned to out. If in1 or in2 changes value again before 10 time units
when the result propagates to out, the values of in1 and in2 at the time of recomputation
are considered.
This property is called inertial delay. An input pulse that is shorter than the delay of the
assignment statement does not propagate to the output. assign #10 out = in1 & in2; //
Delay in a continuous assign
The waveform in Figure is generated by simulating the above assign statement. It shows
the delay on signal out. Note the following change:
1. When signals in1 and in2 go high at time 20, out goes to a high 10 time units later (time
= 30).
2. When in1 goes low at 60, out changes to low at 70.
3. However, in1 changes to high at 80, but it goes down to low before 10 time units have
elapsed.
4. Hence, at the time of recomputation, 10 units after time 80, in1 is 0. Thus, out gets the
value 0. A pulse of width less than the specified assignment delay is not propagated to
the output.
Expressions:
Expressions are constructs that combine operators and operands to produce a result.
// Examples of expressions.
Combines operands and operators a ^ b
addr1[20:17] + addr2[20:17] in1 | in2
Operands:
Operands can be any one of the data types. Some constructs will take only certain types
of operands. Operands can be constants, integers, real numbers, nets, registers, times,
bit- select (one bit of vector net or a vector register), part-select (selected bits of the
vector net or register vector), and memories or function calls (functions are discussed
later).
integer count, final_count;
final_count = count + 1;//count is an integer operand real a, b, c;
Operators:
Operators act on the operands to produce desired results. Verilog provides various types
of operators.
d1 && d2 // && is an operator on operands d1 and d2 !a[0] //
! is an operator on operand a[0]
B >> 1 // >> is an operator on operands B and 1
Operator Types:
Verilog provides many different operator types. Operators can be arithmetic, logical,
relational, equality, bitwise, reduction, shift, concatenation, or conditional. Some of these
operators are similar to the operators used in the C programming language. Each operator
type is denoted by a symbol. Table shows the complete listing of operator symbols
classified by category.
❖ Task-1:
✓ 8 to 3 line encoder, truth table is given below.
❖ Task-2:
✓ Implement 8 to 1 multiplexer.
(Hint: use three control signals s0,s1,s2 for choosing the multiplexer output)
Lab Rubrics
3 2 1 0
Can independently Can setup, and Can setup, and Cannot setup or
Apparatus setup, operate and handle the apparatus handle the handle the
Handling handle the apparatus with minimal help apparatus with apparatus
some help
Assembly/ Can assemble Can assemble Can assemble but Cannot assemble
Apparatus according to the design according to design inaccurately
design within least time
Date: ______________________
Lab-12
Introduction to Verilog HDL
Behavioral Modeling
12.1 Structured Procedures:
Initial Statement:
All statements inside an initial statement constitute an initial block. An initial block starts
at time 0, executes exactly once during a simulation, and then does not execute again. If
there are multiple initial blocks, each block starts to execute concurrently at time 0. Each
block finishes execution independently of other blocks. Multiple behavioral statements
must be grouped, typically using the keywords begin and end. If there is only one
behavioral statement, grouping is not necessary. Example illustrates the use of the initial
statement.
Example of initial Statement:
module stimulus;
reg x,y, a,b, m;
initial
m = 1'b0; //single statement; does not need to be grouped
initial begin
#5 a = 1'b1; //multiple statements; need to be grouped
#25 b = 1'b0;
end
initial begin
#10 x = 1'b0;
#25 y = 1'b1;
end
initial
#50 $finish;
Endmodule
In the above example, the three initial statements start to execute in parallel at time 0. If
a delay #<delay> is seen before a statement, the statement is executed <delay> time units
after the current simulation time. Thus, the execution sequence of the statements inside
the initial blocks will be as follows.
time statement executed
0 m = 1'b0;
5 a = 1'b1;
10 x = 1'b0;
30 b = 1'b0;
#50 $finish;
35 y = 1'b1;
Always Statement:
All behavioral statements inside an always statement constitute an always block. The
always statement starts at time 0 and executes the statements in the always block
continuously in a looping fashion. This statement is used to model a block of activity that
is repeated continuously in a digital circuit. An example is a clock generator module that
toggles the clock signal every half cycle. In real circuits, the clock generator is active from
time 0 to as long as the circuit is powered on. Example illustrates one method to model a
clock generator in Verilog
Example of Always Statement:
module clock_gen (output reg clock);
//Initialize clock at time zero
initial clock = 1'b0;
//Toggle clock every half-cycle (time period = 20)
always #10
clock = ~clock;
initial #1000
$finish;
endmodule
In Example, the always statement starts at time 0 and executes the statement clock =
~clock every 10 time units. Notice that the initialization of clock has to be done inside a
separate initial statement. If we put the initialization of clock inside the always block, clock
will be initialized every time the always is entered. Also, the simulation must be halted
inside an initial statement. If there is no $stop or $finish statement to halt the simulation,
the clock generator will run forever. The activity is stopped only by power off ($finish) or
by an interrupt ($stop).
Blocking Assignments:
Blocking assignment statements are executed in the order they are specified in a
sequential block. A blocking assignment will not block execution of statements that follow
in a parallel block., The = operator is used to specify blocking assignments.
Example of Blocking Statement:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
//All behavioral statements must be inside an initial or always block
initial begin
x = 0; y = 1; z = 1; //Scalar assignments
count = 0;
//Assignment to integer variables
reg_a = 16'b0; reg_b = reg_a; //initialize vectors
#15 reg_a[2] = 1'b1; //Bit select assignment with delay
#10 reg_b[15:13] = {x, y, z}
//Assign result of concatenation to part select of a vector
count = count + 1; //Assignment to an integer (increment)
end
Non-Blocking Assignments:
Nonblocking assignments allow scheduling of assignments without blocking execution of
the statements that follow in a sequential block. A <= operator is used to specify
nonblocking assignments. Note that this operator has the same symbol as a relational
operator, less_than_equal_to. The operator <= is interpreted as a relational operator in
an expression and as an assignment operator in the context of a nonblocking assignment.
To illustrate the behavior of nonblocking statements and its difference from blocking
statements, let us consider below example where we convert some blocking assignments
to nonblocking assignments, and observe the behavior.
In this example, the statements x = 0 through reg_b = reg_a are executed sequentially at
time 0.
Then the three nonblocking assignments are processed at the same simulation time:
1. reg_a[2] = 0 is scheduled to execute after 15 units (i.e., time = 15)
2. reg_b[15:13] = {x, y, z} is scheduled to execute after 10 time units (i.e., time =
10)
3. count = count + 1 is scheduled to be executed without any delay (i.e., time = 0)
• 4 to 1 Multiplexer:
// 4-to-1 multiplexer. Port list is taken exactly fromthe I/O diagram.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
//output declared as register reg out;
//recompute the signal out if any input signal changes.
//All input signals that cause a recomputation of out to occur must go into the
always @(...) sensitivity list.
always @(s1 or s0 or i0 or i1 or i2 or i3)
begin case ({s1, s0}) 2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;
2'b11: out = i3;
default: out = 1'bx;
endcase
end
endmodule
• 4-bit Counter:
//4-bit Binary counter module counter(Q , clock, clear);
// I/O ports
output [3:0] Q; //output defined as register reg [3:0] Q
input clock, clear;
always @( posedge clear or negedge clock)
begin
if (clear)
Q <= 4'd0;
//Nonblocking assignments are recommended for creating sequential logic such
as flipflops else
Q <= Q + 1;// Modulo 16 is not necessary because Q is a 4-bit value and wraps
around.
end
endmodule
• D Flip Flop:
module d_FF(Clock,Data,Q,Reset);
input Clock,Data,Reset;
output Q; reg Q;
always@(posedge clock)
begin
if (reset==1) Q<=0;
else Q<=Data;
end
endmodule
❖ Task-1:
✓ Implement JK Flip flop using behavioral modeling, Truth table is given below.
J K Q(t+1)
0 0 Q(t)(No change)
0 1 0 (Set)
1 0 1 (Reset)
1 1 Q’(t) (Toggle)
❖ Task-2:
✓ Implement T Flip flop using behavioral modeling, Truth table is given below.
T Q(t+1)
0 Q(t)(No change)
1 Q’(t) (Toggle)
❖ Task-3:
✓ Implement 4 bit ripple counter, Figure is given below
Lab Rubrics
3 2 1 0
Can independently Can setup, and Can setup, and Cannot setup or
Apparatus setup, operate and handle the apparatus handle the handle the
Handling handle the apparatus with minimal help apparatus with apparatus
some help
Assembly/ Can assemble Can assemble Can assemble but Cannot assemble
Apparatus according to the design according to design inaccurately
design within least time
Date: ______________________
Lab-13
Open Ended lab (OEL)
13.1 Objective:
To make a joint project within lab addressing a real life task/problem using all the
available apparatus in the lab.
13.3 Exercise:
To be announced on spot or in previous lab.