2014 International Symposium on Computer, Consumer and Control
Design of a Counter-Based DPWM Using RC Charge
Hsin-Chuan Chen
Department of Electronic Engineering
St. John’s University
Tamsui District, New Taipei City, Taiwan
robin@mail.sju.edu.tw
Abstract—Conventional counter-based digital PWM
(DPWM) has simple hardware architecture to generate the
PWM pulse; however, the resolution of the counter-based
DPWM is directly proportional to its input reference clock,
and thus the higher clock frequency is required, which
means higher dynamic power consumption and noise
interference may be incurred. In this paper, by the design
approach of RC charge, the proposed DPWM device can
extend its resolution without increasing the reference clock
frequency. Moreover, this DPWM scheme with resolution
extension also can reduce the hardware complexity and the
impact caused by capacitance error compared with the
conventional DPWM.
Keywords- Counter-Based DPWM, Resolution, RC Charge,
Duty Cycle, Capacitance Error.
I. INTRODUCTION
Pulse width modulation (PWM), an effective
technology, is used to regulate the average power by
changing its duty cycle of the output pulse in discrete time
domain [1]. Due to that the PWM using digital control can
improve the cost and performance of the system, therefore,
the digital PWM (DPWM) is often applied to many
control systems, such as DC motors, DC-DC converters
[4], LED controllers [9], D/A converters [5], and even
vehicle brakes [1]. Nowadays, the digital PWM (DPWM)
has become an important device in the modern systems,
even some microcontrollers also directly integrate the
DPWM into their chips [6]. High resolution is necessary
for the DPWM to achieve precise output control and avoid
undesirable quantization effects [2]; however, the
resolution of the counter-based DPWM is directly
proportional to its input reference clock. When seeking
high resolution for the counter-based DPWM, the higher
dynamic power consumption and noise interference may
be incurred [4] because a higher clock frequency is
required. For example, an 8-bit counter-based DPWM
with 1 MHz output frequency needs a reference clock up
to 256 MHz.
In the past, for solving the high-frequency problem
existing in the counter-based DPWM, one of the most
used approaches is using a tapped delay line controlled by
digital code to select the desired pulse width [3]. This
delay-line DPWM does not need high clock frequency
while satisfying high resolution, but a high hardware
complexity is required for obtaining better linearity and
performance compared with the counter-based DPWM.
In this paper, a new DPWM device using RC charge is
proposed to extend its resolution. This proposed DPWM
978-1-4799-5277-9/14 $31.00 © 2014 IEEE
DOI 10.1109/IS3C.2014.327
does not need high clock frequency while satisfying high
resolution; and it only adds a reasonable hardware
complexity when extending the resolution of the original
counter-based DPWM. Besides, this proposed DPWM
device also effectively reduces the impact of capacitance
error on duty cycle error.
II. COUNTER-BASED DPWM
In the conventional analog type of PWM, it uses a
comparator to compare a reference voltage with the ramp
or triangle wave, by adjusting the level of reference
voltage, and then the pulse width can be obtained from the
output of the comparator. Similarly, the counter-based
DPWM (CNT DPWM), the simplest digital PWM
architecture, can be easily implemented only by an n-bit
counter and an n-bit digital comparator shown in Fig. 1
[2][7], where the digital setting code K is used to set the
comparing value of the digital comparator. The counter
counts at each positive transit of the reference clock, when
the value of counter is less than K, the output (A<B) of
the comparator remains high-level state until the content
of the counter is equal to or large than K. Therefore, this
output will generate a pulse width corresponding to the
digital setting code. For an n-bit counter-based DPWM
structure with output frequency fPWM, it requires a
reference clock fCLK = 2n ×ʳ fPWM, and thus the modulation
rate (i.e. duty cycle) D of the counter-based DPWM is
given by:
TK K  TCLK K
D   n (1)
TPWM 2 n  TCLK 2
where TK is ON time of the PWM pulse controlled by K
value from 0 to 2n-1. However, the resolution of the
counter-based DPWM is directly proportional to its input
reference clock [4]. Therefore, this DPWM scheme does
not suit for high-resolution implementation due to
requiring a higher reference clock frequency.
(n bits)
Digital Setting Code: K B
PWM
A<B
Output
n-bit
fCLK A
Counter
n-bit
Comparator
Figure 1. Basic structure of counter-based DPWM.
To avoid using high-frequency clock, the often used
DPWM scheme, delay-line DPWM shown in Fig. 2 [7],
employs a cascade of delay cells, a multiplexer, and a SR
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flip-flop to construct the PWM pulse generator [2]. When TK 2 K
the clock enters into the tapped delay line, the SR flip-flop  m 2n , (5)
TPWM 2
is set to “Hi”. By the selection of n-bit setting code, the
Substituting Eq. (3) and Eq. (5) into Eq. (2), the duty
desired delay signal appears at the output of 2n to 1
cycle D will become:
multiplexer, and then resets the SR flip-flop until the next
K K 2 n  K1  K 2
clock enters again. Such an operation, a modulated pulse D  m1  m 2n  (6)
width can be generated from the output of SR flip-flop. 2 2 2 mn
Due to mismatch delay cells caused by which means the resolution of DPWM is extended as m+n
process/temperature variation, the linearity of the delay- bits from original m bits [8], and K1 and K2 can be treated
line DPWM will be affected [5], and thus more hardware as high bits and low bits of the digital setting code,
components are required for better performance and respectively. Here, we try to use a RC charge approach to
linearity [3]. For achieving high resolution, this DPWM generate the extended pulse time TK2 less than one clock
has a large hardware complexity including quantities of time. Consequently, Eq. (4) can also be modified as:
delay cells and a large-scale multiplexer [3]. 1 T 1
 K 2  n  VC (7)
2n Delay Cells K 2 TCLK 2
Consider that VC is the charging voltage performed by
VS
current I charging through R and C after TK2 time, and VC
fCLK is given by:
dly0 dly1 dly2n-1 TK 2

VC  I  R  (1  e RC ) (8)
Setting where I from the current source selector with a unit
2n to 1 Multiplexer
(n bits) Code
current i for each current source is controlled by 1/K2. Let
RC > TK2, then we expand the exponential of Eq. (8) in a
R series and ignore the items with high power, so we obtain:
PWM
Q  TK 2
Output
S
e RC
 1  TK 2 / RC  . (9)
Figure 2. Delay-line DPWM scheme. Substituting Eq. (9) into Eq. (8), finally, VC will become
as:
III. PROPOSED DPWM DEVICE USING RC CHARGE
I 1 i 1
Unlike the delay-line DPWM (DLY DPWM) using a VC   TK 2    TK 2  n (10)
tapped delay line, we try to provide a new approach for C K2 C 2
DPWM design, which uses RC charge to perform digital to which behaves like capacitor integration. By selecting i/C
time conversion and further extend the resolution of the = 1/TCLK, when VC charges to the reference voltage VREF
conventional counter-based DPWM. The detail of this corresponding to 1/2n at t = TK2, the extended pulse output
proposed DPWM device (called RC-CNT DPWM) TK2 with n-bit resolution will be generated.
including principle, architecture, and operation will be
described in the following sub-sections. m-bit Counter-Based DPWM
SET PWM
CLK Q OUT
A. Principle (m bits) TK1 DFF1
A A<B
According to the duty cycle of the counter-based m-bit m-bit “1” D CLR Q
fCLK
Counter Comparat
DPWM shown as Eq. (1), consequently, it can also be K1 B A=B
extended as: TP
CLK Q TK2
T T  TK 2 T T DFF2
D  K  K1  K1  K 2 (2) “1” D CLR Q
TPWM TPWM TPWM TPWM (n bits)
Current
K2 Source I VREF
VCMP
where TK contains two parts: TK1 and TK2 [8]. When using Selector CMP
VC
an m-bit counter-based DPWM with the reference clock
fCLK for TK1, therefore, TK1/TPWM is given by: R C
TK 1 K T K S
 m1 CLK  m1 (3)
TPWM 2  TCLK 2 Figure 3. Architecture of proposed DPWM device.
m B. Architecture
where K1 is the digital setting code from 0~2 -1.
In our proposed DPWM scheme shown in Fig.3, an m-
Considering TK2 with n-bit resolution is extended from the bit counter and an m-bit digital comparator construct as an
m-bit counter-based DPWM under the same fCLK, the TK2 m-bit counter-based DPWM to generate TK1, and the RC
is expressed by: charging circuit including current source selector and
K comparator is used to associate with a D flip-flop to
TK 2  n2  TCLK (4)
2 generate TK2. The current source selector controlled by
n
where K2 is the digital setting code from 0~2 -1. Similarly, digital value K2 is shown in Fig. 4, and it uses an n to 2n
TK2/TPWM is also given by: decoder to select 2n current sources corresponding to 1/ K2

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[7]. Each output of the decoder enable one current source,
where the current source I0 selected by K2 = 0 has a large
charging current to make VC be immediately larger than
the reference voltage VREF, such that the Q output of DFF1
(PWM OUT) is almost equal to TK1 once K2 = 0. Although
this proposed RC-CNT DPWM results in hardware
overhead due to RC charge, it still has less hardware
complexity than that of the DLY DPWM.
n to 2n Decoder
K2
E2n-1 …. E2 E1 E0
i/2n-1 i/2 i I0
….
I from capacitance error can be significantly reduced by
Figure 4. Structure of current source selector.
C. Operation
To explicate how the proposed RC-CNT DPWM
device works, the operating steps are described as follows:
(1) Initially, all Q outputs of two D flip-flops (DFF1 and
DFF2) are “Lo”, and the /Q output of DFF2 remains
“Hi” to make switch S on, and thus the voltage of the
capacitor is zero (VC = 0).
(2) When the m-bit counter counts to K1, the A<B output
of comparator can generate TK1 and trigger the DFF1
to set “Hi”. The other A=B output (TP) of comparator
will activate the RC charge for achieving a resolution
extension of n bits.
(3) At the rising transit of TP, the /Q output of DFF2
immediately turns S off and the output (TK2) of DFF2
is “Hi”, thus the current I corresponding to 1/ K2 from
the current source selector will start the RC charge.
(4) TP always will be generated regardless of K1 value.
Therefore, in case of K1 = 0, even though there is no
TK1 to trigger the DFF1, the output (TK2) of DFF2 still
can set DFF1 “Hi” by TP only if K2ʳ≠ 0.
(5) When VC charges to the reference voltage VREF
corresponding to 1/2n, the falling transit output (VCMP)
of comparator will clear the DFF1 and DFF2 so that
TK2 returns back to “Lo” and the Q output of DFF1
(PWM OUT) also becomes “Lo”. Simultaneously, the
switch S turns on and VC discharges to zero until the
next rising edge of TP comes again.
(6) In case of K2 = 0, due to that a larger current source I0
is selected, DFF1 and DFF2 are immediately cleared
when starting the RC charge, which means almost no
TK2 is generated.
Finally, the output PWM OUT almost equals TK1+TK2;
therefore, the proposed RC-CNT DPWM will generate the
PWM output with a resolution of m+n bits under the same
reference clock fCLK.
IV. ANALYSIS OF CAPACITANCE ERROR IMPACT
Because the capacitance error is usually larger than the
other components, therefore, using a capacitor component
in our proposed RC-CNT DPWM may affect its precision
of duty cycle. If the capacitor has a capacitance error (err),
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according to Eq. (10), TK2 can be given by:
K2  C K
TK 2    n2  TCLK  (1  err ) (11)
2n i 2
Referring to Eq. (5) and Eq. (6), similarly, the duty cycle
D should be modified as:
2 n  K1  K 2  (1  err )
D (12)
2 m n
Therefore, the duty cycle error ED caused by capacitance
error is given by:
K  ( err ) .
ED  n 2 (13)
2  K1  K 2
Fortunately, small duty cycle is not realistic for most
applications, in other words, K1 is usually larger than 0.
Therefore, the impact of PWM duty cycle error resulted
combining counter-based DPWM with RC charging circuit,
especially for large n or K1. When K1 equals 0, the duty
cycle error directly depends on the capacitance error, and
thus a capacitor with precise capacitance is necessary for
this situation to obtain an acceptable duty cycle error.
V. SIMULATION RESULTS
In our simulation, a circuit simulation tool, Pspice, is
used to verify the operation and measure the performance
of the proposed 8-bit DPWM device, which is
implemented by a 4-bit counter-based DPWM combining
4-bit RC charging circuit. Therefore the required main
components include one 4-bit counter, one 4-bit digital
comparator, two D flip-flops, one 4 to 16 decoder, 16
current sources, and one comparator. Besides, the
reference clock frequency and output frequency of the
proposed DPWM are fCLK = 16 MHz and fPWM =1 MHz,
respectively. For our proposed RC-CNT DPWM, we
choose the capacitance C = 62.5 pF, the resistance R =
100 KΩ, and the reference voltage VREF corresponding to
1/24 is 0.0625 V. In the current source selector, the unit
current i is 1 mA for each current source, where I0 is
chosen as 10 times of unit current i in order to make VC be
immediately larger than the reference voltage VREF.
Figure 5. Simulation waveforms at K1 = 8 and K2 = 8.
Fig. 5 shows the P-Spice simulation waveforms for the
proposed RC-CNT DPWM, where the final PWM output
is synthesized by TK1 at K1 = 8 and TK2 at K2 = 8 [8]. We
find that the duty cycle becomes 53.22% from 50% for the
original 4-bit counter-based DPWM; therefore, the
resolution of the proposed DPWM indeed can be extended
as 8 bits from the original 4-bit counter-based DPWM
without increasing the reference clock frequency.
Considering K2 = 0, TK2 is only an impulse when TP goes
“Hi” from “Lo”, and this impulse with very short duration
time does not cause DFF1 being set to “Hi”. Hence, the
PWM output TK1 still keeps the original output, and the
duty cycle remains at 50% shown in Fig. 6.
Figure 6. Simulation waveforms at K1 = 8 and K2 = 0.
Due to that the capacitance error may affect the
precision in duty cycle for the DPWM using capacitor
components, hereby considering the capacitor has a
capacitance error from 1% to 20%, we find that the duty
cycle error for different K2ʳ atʳ K1 = 0 increases as the
capacitance error increases for our proposed RC-CNT
DPWM shown in Fig. 7, and these duty cycle errors almost
equal the capacitance error. However, when K1 is larger
than 0 at K2 = 8, the duty cycle error shown in Fig. 8 can be
significantly reduced especially for large K1. Even the
capacitance error increases up to 20%, only not over 7%
for K1 = 1 and 2% for K1ʳ Њ 5 duty cycle errors are
achieved.
0.25 K2=2
K2=4
Duty Cycle Error
VI. CONCLUSIONS
In this paper, a new DPWM device using RC charge is
proposed to successfully extend the resolution of the
original counter-based DPWM while maintaining the
same clock frequency. By this approach of resolution
extension, our proposed RC-CNT DPWM also effectively
reduces the duty cycle error caused by capacitance error,
which is more significant especially for large duty cycle.
According to our simulation, the duty cycle of our
proposed RC-CNT DPWM can be modulated from 0 to
99.6%, and its duty cycle error also indeed can be reduced
to about 0.63% when the duty cycle is 96.8% at 20%
capacitance error. Considering a trade-off between high
frequency of the conventional counter-based DPWM and
high hardware complexity of the delay-line DPWM, the
proposed DPWM device using RC charge therefore can
suit for the digital PWM design with high resolution and
low cost.
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0.07 K1=1
K1=3
0.06
Duty Cycle Error

K1=5
0.05 K1=7
K1=9
0.04 K1=11
K1=13
0.03 K1=15
0.02
0.01
0
0% 1% 5% 10% 15% 20%
Capacitance Error
Figure 8. Duty cycle error of proposed DPWM device for K1 > 0.

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