February 28, 2022 IIITD ECE 111 Section A 1

Functionally Complete Sets:

1. {NAND}
2. {AND, NOT}
3. {NOR}
4. {OR, NOT}
5. {AOI} --- AND OR INVERT (𝐴 " 𝐵 + 𝐶 " 𝐷)
6. {OAI} --- OR AND INVERT 𝐴 + 𝐵 " 𝐶 + 𝐷

February 28, 2022 IIITD ECE 111 Section A 2

Combinational Circuits:

February 28, 2022 IIITD ECE 111 Section A 3

 Multiplexer also called MUX:

A multiplexer helps in transmitting, selectively, any of the several available

signal inputs to the only available output.

𝑓 = 𝑠̅ " 𝑤! +𝑠 " 𝑤"

2:1 Multiplexer

February 28, 2022 IIITD ECE 111 Section A 4

4:1 Multiplexers

𝑓 = 𝑠-"𝑠-!𝑤! + 𝑠-"𝑠!𝑤" + 𝑠"𝑠-!𝑤# + 𝑠"𝑠!𝑤$

Shannon’s Theorem

𝑓 = 𝑠-" " 𝑠-!𝑤! + 𝑠!𝑤" + 𝑠" " 𝑠-!𝑤# + 𝑠!𝑤$

4:1 MUX
February 28, 2022 IIITD ECE 111 Section A 5
 8:1 Multiplexers:

s2 s1 s0 f
0 0 0 w0
0 0 1 w1
0 1 0 w2
0 1 1 w3
1 0 0 w4
1 0 1 w5
1 1 0 w6
1 1 1 w7

𝑓 = 𝑠#! 𝑠#" 𝑠## 𝑤# + 𝑠#! 𝑠#" 𝑠# 𝑤" + 𝑠#! 𝑠" 𝑠## 𝑤! + 𝑠#! 𝑠" 𝑠# 𝑤$ + 𝑠! 𝑠#" 𝑠## 𝑤% + 𝑠! 𝑠#" 𝑠# 𝑤& + 𝑠! 𝑠" 𝑠## 𝑤' + 𝑠! 𝑠" 𝑠# 𝑤(
𝑓 = 𝑠#! % 𝑠#" 𝑠## 𝑤# + 𝑠#" 𝑠# 𝑤" + 𝑠" 𝑠## 𝑤! + 𝑠" 𝑠# 𝑤$ + 𝑠! % 𝑠#" 𝑠## 𝑤% + 𝑠#" 𝑠# 𝑤& + 𝑠" 𝑠## 𝑤' + 𝑠" 𝑠# 𝑤(
𝑓 = 𝑠#! % 𝑠#" % 𝑠## 𝑤# + 𝑠# 𝑤" + 𝑠" % 𝑠## 𝑤! + 𝑠# 𝑤$ + 𝑠! % 𝑠#" % 𝑠## 𝑤% + 𝑠# 𝑤% + 𝑠" % 𝑠## 𝑤' + 𝑠# 𝑤(
February 28, 2022 IIITD ECE 111 Section A 6
 Boolean Functions Using Multiplexers

• Shannon’s Expansion Theorem. ----- Nested

𝑓 𝑤%&", … . . 𝑤! = 𝑤! " 𝑓 𝑤%&", … . . 𝑤", 0 + 𝑤! " 𝑓 𝑤%&", … . . 𝑤", 1

𝑓 𝑤%&", … . . 𝑤! = 𝑤" " 𝑤! " 𝑓 𝑤%&", … 𝑤#, 0,0 + 𝑤" " 𝑤! " 𝑓 𝑤%&", … . . 𝑤", 0,1
= 𝑤" " 𝑤! " 𝑓 𝑤%&", … 𝑤#, 1,0 + 𝑤" " 𝑤! " 𝑓 𝑤%&", … . . 𝑤", 1,1

𝑓 𝑤%&", … . . 𝑤! = 𝑤# " 𝑤" " 𝑤! " 𝑓 𝑤%&", … 𝑤$, 0,0,0 + 𝑤# " 𝑤" " 𝑤! " 𝑓 𝑤%&", … 𝑤$, 0,0,1
= 𝑤# " 𝑤" " 𝑤! " 𝑓 𝑤%&", … 𝑤$, 0,1,0 + 𝑤# " 𝑤" " 𝑤! " 𝑓 𝑤%&", … 𝑤$, 0,1,1
= 𝑤# " 𝑤" " 𝑤! " 𝑓 𝑤%&", … 𝑤$, 1,0,0 + 𝑤# " 𝑤" " 𝑤! " 𝑓 𝑤%&", … 𝑤$, 1,0,1
= 𝑤# " 𝑤" " 𝑤! " 𝑓 𝑤%&", … 𝑤$, 1,1,0 + 𝑤# " 𝑤" " 𝑤! " 𝑓 𝑤%&", … 𝑤$, 1,1,1
February 28, 2022 IIITD ECE 111 Section A 7
4:1 Multiplexer Using 2:1 Multiplexer

𝑓 = 𝑠-" " 𝑠-!𝑤! + 𝑠!𝑤" + 𝑠" " 𝑠-!𝑤# + 𝑠!𝑤$ A

A B
B

February 28, 2022 IIITD ECE 111 Section A 8

Multiplexer (HW)
• Draw gate level circuit diagram (only AND, OR, NOT gates) for 4:1 and
8:1 multiplexers
• Design 8:1 multiplexer using only 4:1 multiplexers
• Design 8:1 multiplexer using 4:1 and 2:1 multiplexers
• Design 8:1 multiplexer using only two 4:1 multiplexers and basic gates
• Similarly, design various combinations of 16:1 multiplexers

February 28, 2022 IIITD ECE 111 Section A 9

 Logic Functions Using Multiplexers:

Realize a 3-input majority function using 4:1 and 2:1 Multiplexers

𝑠! 𝑠" 𝑠# 𝑓
0 0 0 0 𝑠! 𝑠" 𝑓
0 0 1 0 0 0 0
0 1 𝑠#
0 1 0 0
1 0 𝑠#
0 1 1 1
1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
𝑠! 𝑓
1 1 1 1 0 𝑠" ) 𝑠#
1 𝑠" + 𝑠#

February 28, 2022 IIITD ECE 111 Section A

10
 Basic Functions Using Multiplexers: Alternative:
𝑓 𝑤#, 𝑤", 𝑤! = 𝑤# " 𝑤! + 𝑤" " 𝑤!

February 28, 2022 IIITD ECE 111 Section A 11

 Boolean Functions Using Multiplexers:

• 𝑓 𝑤, 𝑥, 𝑦 = ∑ 𝑚 3,5,6,7 using minimum number of 2:1 MUXs (Don’t use

any logic gates)

𝑓 𝑤, 𝑥, 𝑦 = 𝑤𝑦 + 𝑤𝑥 + 𝑥𝑦

=𝑤
- " 𝑥"𝑦 +𝑤" 𝑥+𝑦

= 𝑥̅ " 𝑤 " 𝑦 + 𝑥 " 𝑤 + 𝑦

= 𝑦; " 𝑥 " 𝑤 + 𝑦 " 𝑥 + 𝑤
February 28, 2022 IIITD ECE 111 Section A 12
Logic Functions Using Multiplexers:
• 𝑓 𝑤, 𝑥, 𝑦, 𝑧 = ∑ 𝑚 1,4,5,7,9,10,12,13 using 4:1 MUX and 2:1 MUX only
w x y z f w x y f
0 0 0 0 0 0 0 0 z
0 0 0 1 1 0 0 1 0
w f
0 0 1 0 0 0 1 0 1
0 x 𝑦# + 𝑧 + 𝑦z
#
0 0 1 1 0 0 1 1 z
1 𝑥 𝑦# + 𝑥𝑦
̅ 𝑧̅ + 𝑦𝑧
#
0 1 0 0 1 1 0 0 z
0 1 0 1 1 1 0 1 𝑧̅
0 1 1 0 0 1 1 0 1
0 1 1 1 1 1 1 1 0
x f
1 0 0 0 0
0 𝑦𝑧
# + 𝑤𝑦𝑧̅
1 0 0 1 1 W x f
1 𝑦# + 𝑤𝑧
)
1 0 1 0 1 0 0 𝑦z
#
1 0 1 1 0 0 1 𝑦+z
#
1 1 0 0 1 1 0 𝑦𝑧
# + 𝑦 𝑧̅
1 1 0 1 1 1 1 𝑦#
1 1 1 0 0
1 1 1 1 0
February 28, 2022 IIITD ECE 111 Section A 13
 Boolean Functions Using Multiplexers:

• 𝑓 𝑤, 𝑥, 𝑦, 𝑧 = ∑ 𝑚 1,4,5,7,9,10,12,13 using 4:1 MUX and 2:1 MUX only

February 28, 2022 IIITD ECE 111 Section A 14

Boolean Circuits Using Multiplexers (HW)

• 𝑓 𝑤, 𝑥, 𝑦, 𝑧 = ∑ 𝑚 1,4,5,7,9,12,13 using 8:1 MUX and logic gates

only
• Design 1-bit full adder using 4:1 multiplexers
• Design a 2-input XNOR gate using 4:1 multiplexer
• Design a 2-input XNOR gate using 2:1 multiplexers

February 28, 2022 IIITD ECE 111 Section A 15

 Decoder:
• A n-to-m-line decoder is a combinational circuit that converts binary information
from n input lines to a maximum of m ≤ 2n unique output lines.
• Their purpose is to generate the 2n (or fewer) minterms of n input variables.

2:4 Decoder:
Functional Block Schematic Diagram:
Truth Table: Diagram:

February 28, 2022 IIITD ECE 111 Section A 16

2:4 Decoder with Enable input:

• An n-to-m-line decoder with Enable input is a combinational circuit that

converts binary information from n input lines to a maximum of m ≤ 2n
unique output lines only when it is enabled. When not enabled all outputs are
set to logic 0.
• The decoders discussed so far are called ‘Active High Enable’ and ‘Active
High Output’.

February 28, 2022 IIITD ECE 111 Section A 17

2:4 Decoder with Active High Enable :

Decoder with Active High Decoder with Active High

Enable and Active High Output Enable and Active High
using AND Gates Output using NOR Gates

February 28, 2022 IIITD ECE 111 Section A 18

2:4 Decoder with Enable Using NAND Gates:

Active Low Enable Active Low Output

February 28, 2022 IIITD ECE 111 Section A 19