Imran Chowdhury | Lecture Note | VLSI II

VLSI II Design Abstraction Levels:

Very Large Scale Integration VLSI design abstraction levels refer to the fact that what
level or kind of knowledge is required to be a VLSI design
Introduction engineer. The ‘system’ level is the highest level of
abstraction where someone has the knowledge of a system
and its outcome on a macro level without having the
Electronic circuits can broadly be categorized into 2 (two)
knowledge of underlying components that make the
types: (i) Discrete circuits, (ii) Integrated circuits. Very
system. Whereas the ‘device’ level is the lowest level of
large-scale integration (VLSI) is the process of creating
design abstraction where someone has the knowledge of
an integrated circuit (IC) by combining millions of
physical design of the most fundamental device of the
transistors onto a single chip.
system on a micro level. It refers to the fact that a VLSI
design engineer is supposed to have the knowledge of
The integrated circuits or IC`s are devices used in almost
physical design of transistors which are the fundamental
any electronic device today. The development of
building block of a chip.
semiconductor technology, and fabrication methods lead
to the invention of Integrated Circuits. Prior to the
invention of the IC, all the equipment for computational
tasks used vacuum tubes for implementation of logic gates
and switches. Vacuum tubes, in nature, are relatively
large, high power consuming devices. For any circuit, the
discrete circuit elements had to be connected manually.
The influence of these factors resulted in rather large and
expensive electronic devices even for the smallest
computational task. Therefore, a computer, five decades
ago was enormous in size and very expensive, and
personal computers were a very distant dream.

Semiconductor based transistors and diodes, which have

higher energy efficiency and microscopic in size, replaced
vacuum tubes and their uses. Hence a large circuit could
be integrated on a small piece of semiconductor material
allowing more sophisticated electronic devices to be
created. Even though the first integrated circuits had only
a small number of transistors in them, at present in an area
of your thumb nail billions of transistors are integrated.
The course will be mainly focused on VLSI Design, with
a brief touch on VLSI Technology. Based on the tasks an
IC needs to do, VLSI design can be categorized into 3
(three) branches: (a) Analog VLSI Design (b) Digital
VLSI Design, and (c) Mixed Signal VLSI Design. This
course will be more focused on Digital VLSI Design.
Level of Integration / Integration Complexity:
Depending on the number of gates or transistors per chip,
or level of complexity, the field of chip or IC design can
be categorized into 6 (six) schemes as tabulated below.
Although, according to the definitions of the schemes we
are now in the GSI era, but the term VLSI becomes a
‘name’ and still used to refer the field of IC design.
Scheme #gates/chip Year
Small Scale Integration (SSI) Up to 100 1965
Medium Scale Integration (MSI) Up to 1,000 1970
Large Scale Integration (LSI) Up to 10,000 1980
Very large Scale Integration (VLSI) Over 10k 1985
Ultra large Scale Integration (ULSI) Over 100k 1990
Giga Scale Integration (GSI) Over 1Billion 2005
Fig: Design abstraction levels of VLSI.
Role of a VLSI Engineer:
The field of VLSI can be broadly categorised into 2 (two)
branches:
1) VLSI Design
2) VLSI Technology
Both branches have their set of engineers responsible for
different set of tasks. Broadly, VLSI Design engineers are
responsible for designing the chip, and VLSI Technology
engineers are responsible for fabricating or manufacturing
the chip. VLSI Design engineers can be categorised into 2
(two) types:
a) Front-end VLSI Design Engineers
b) Back-end VLSI Design Engineers
Front-end VLSI Design engineers are responsible for
designing the system (e.g. circuits), defining the functions
and behaviour of the system, defining the architecture of
the system, and synthesizing the design to verify it, etc.
before starting the physical design.
Back-end VLSI Design engineers are responsible for
designing the physical layout of the chip (sometimes
including pad frames), performing post-layout simulation,
placement and routing, etc.
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 Imran Chowdhury | Lecture Note | VLSI II
IC Packaging:

Integrated Circuit Packaging refers to the encasing of a

semiconductor component. The package is a case that
surrounds the circuit material to protect it from corrosion
or physical damage and allow mounting of the electrical
contacts connecting it to the printed circuit board (PCB).

Importance of IC Packaging:
Fig: Small Outline Package (SOP/SOIC/SO).
The packaging of an integrated circuit is as important as
the integrated circuit, the semiconductor device within.
The packaging mainly serves 3 (three) purposes:
– First, it protects the semiconductor circuit from
physical impairment or damage.
– Secondly, it protects the circuit from corrosion.
– Finally and most important, it decides how electrical
contacts are laid out from the semiconductor device
over a PCB. This is an important consideration for
both IC designing as well as PCB designing. Like how Fig: Quad Flat Package (QFP).
the connections are organized in an IC, how they are
laid out using a standard IC package must be coherent
with the application and various use cases of the
respective IC.

Types of IC Packaging:

There are many different types of integrated circuits, and

therefore there are different types of IC packaging systems
to consider, as different types of circuit designs will have Fig: Quad Flat Non-leaded Package (QFN/LCC).
different needs when it comes to their outer shell.
Although, most of the ICs come in more than one package.
The classifications of IC packaging is mainly done based
on their mounting style. Some of the most common
broader categories of IC packaging are:
1) Through-Hole Mount Packages
2) Surface Mount Packaging
3) Flat Packages
4) Ball Grid Array
5) Chip-Scale Packages
Fig: Ball Grid Array Package (BGA).
Each of the broader categories have numerous types of
sub-categories of packages based on the application and
types of PCBs. But in academics, most commonly we will
encounter only 2 (two) types of IC packages which are
Dual in-line Packages (DIP) and Quadruple in-line
Packages (QIP) as shown below, those falls into the
‘Through-Hole Mount’ category. Some of the other sub-
categories of IC packages are depicted below as well.

Fig: Chip-Scale Packages (CSP).

Inside an IC Package:

Although we call the whole package an integrated circuit

or a chip, but technically that is not the case. If an IC
Fig: Dual in-line Packages Fig: Quadruple in-line package is opened, there are several components can be
(DIP). Packages (QIP). seen, one of which is the IC or chip.

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 Imran Chowdhury | Lecture Note | VLSI II
IC Layout:

The network in an IC is consisted of different layers like

tubs (n-type or p-type), diffusions (drain and source),
polysilicons (a sandwich of polycrystalline silicon and
SiO2), metals (interconnections), contacts (vias), etc. in
three dimension. The geometry of the area-patterns of this
network of layers is known as the IC layout or chip layout.
Connections from the chip to the outside world are made
around the edge of the chip.

In other words, chip layout or IC layout is the

representation of an integrated circuit in terms of planar
geometric shapes which correspond to the patterns of
metal, oxide, or semiconductor layers that make up the
components of the integrated circuit.

Fig: Block diagram of inside the packaging of an IC or Chip.

Chip: The chip is the rectangular semiconductor die sit at

the middle of the package that contains the entire
integrated circuits.

Cavity: It is the rectangular well at the middle of the

package that holds the chip sturdy.

Leads: These are also called pins which are used to mount
and make contacts with a PCB to connect the outside
electronic components of a circuit to the chip.

Bonding Wires: These are very tiny connecting wires that

connect the leads to the chip’s input/output and power
terminals. Generally bonding wires are made up of gold
for better conductivity.
Fig: IC layout a of a RF receiver for ISM-900M.
Pad Frames: These are the small rectangular contacts
sitting at the edge of the chip. Pad frames are used as vias
in between the bonding wires and chip to protect the chip
VLSI Design Fundamentals
from unwanted high current through the leads and bonding
Moore’s Law:
wires. A single part of the pad frame is called a pad. A pad
is made much larger in area than the average width of the Moore’s law is not really a law of physics or even a proven
interconnecting metals of the IC, with multiple layers of
theory in the scientific sense (such as E=MC2). Rather, it
metals stack on top of each other for higher thermal was an ‘empirical relationship’ based on observation and
tolerance. projection of a historical trend of semiconductor
technology by Gordon E. Moore in 1965 while he was
working at Fairchild Semiconductor. Moore later went on
to co-founder Intel Corporation and his observation
became the driving force behind the semiconductor
technology revolution at Intel and elsewhere.

Moore’s Law:

The number of transistors per chip would grow double

every 18 months, and the growth would be exponential.

Moore’s 2nd Prediction:

The capital cost of a semiconductor fabrication would

Fig: Real-life image of inside the packaging of an IC. increases exponentially over time.

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Fig: Number of transistors per chip for Intel microprocessors
over the years.
Fig: Global smartphone RAM capacity (in MB) over the years
(from GSMArena.com).
Fig: Global smartphone NAND Flash capacity (in GB) over
the years (from IEEE).
Importance of Moore’s Law:
Moore's Law has been used in the semiconductor industry
to guide long-term planning and to set targets for research
and development, thus functioning to some extent as a
self-fulfilling prophecy. It created a roadmap for the
ubiquity of computer technology, including that in
consumer electronics, artificial intelligence, and
supercomputers. In effect, Moore’s Law also predicted the
increasing affordability and accessibility of computer
technology, as the cost per transistor decreases when there
are more transistors available on a single chip.
Imran Chowdhury | Lecture Note | VLSI II
The End of Moore’s Law:
In recent years, Moore’s Law has slowly fallen out of
relevance. Recently, semiconductor foundry (fabrication
house) TSMC has announced that it plans to release chips
in 3nm (nanometer) process sometime in 2022. By
comparison, the diameter of a single atom measures
somewhere between 0.1 and 0.5 nanometers, so there is a
finite limit to how small a single transistor can become.
According to renowned theoretical physicist Michio Kaku
"in about ten years or so, we will see the collapse of
Moore's Law. In fact, already we see a slowing down of
Moore's Law. Kaku also says that when Moore's law
finally collapse by the end of the next decade, we will
simply tweak it a bit with chip-like computers in three
dimensions. He then says "we may have to go to molecular
computers and perhaps late in the 21st century quantum
computers".
Feature Size / Process Technology / Node:
Feature Size is an element of semiconductor chip used to
measure and designate the chip generation at the
fabrication level. It refers to a specific semiconductor
manufacturing process and its design rules. Different
feature size often imply different circuit generations and
architectures. Generally, the smaller the feature size the
smaller the transistor size in the chip, producing higher
number of transistors in a single chip, which are both faster
and more power-efficient.
Technically, Feature Size is the minimum distance
between the source and drain or channel length of a
MOSFET, which today is measured in nanometers.
Feature Size is also called Process Technology, Process
Node, Technology node, or simply Node.
Fig: Channel Length = Gate Length – (2 × Diffusion Length).
Discrepancy in Feature Size Naming Convention:
Most recently, due to various marketing and discrepancies
among foundries, the number has lost the exact meaning it
once held. Recent technology nodes such as 22nm, 16nm,
14nm, and 10nm refer purely to a specific generation of
chips made in a particular technology. It does not
correspond to any channel length. For example, Intel's
10nm is comparable to TSMC's 7nm and Global
Foundries' 12nm processes, while Intel's 7nm is
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 Imran Chowdhury | Lecture Note | VLSI II
comparable to other foundries’ 5nm process.
Nevertheless, the naming convention has stuck and it is
what the leading foundries call their nodes.

VLSI Design Rules:

Design rules are geometric constraints provided by

semiconductor manufacturers and imposed on integrated
circuit (IC) designers to ensure their designs function
properly and can be produced with acceptable yield in as
small area as possible without compromising reliability of
the circuit. Design rules are developed by process
engineers based on the capability of their processes.
Design rules are specific to a particular semiconductor Fig: Semiconductor wafer.
manufacturing process. There are 2 (two) types of design
rules available broadly:

1. Absolute Design Rules (μ-based design rules): In this

approach, the design rules are expressed in absolute
dimensions (e.g. 0.75μm) and therefore can exploit the
features of a given process to a maximum degree. These
rules tend to be more complex especially for deep
submicron. Even for the same minimum dimension,
design rules tend to differ from company to company, and
from process to process. Now, CAD tools allow designs to
migrate between compatible processes.

2. Scalable Design Rules (λ-based design rules): In this

approach, all rules are defined in terms of a single
parameter λ. The rules are so chosen that a design can be Fig: The wafer shown in the VLSI class during my MS at
easily ported over a cross section of industrial process, Texas A&M University – Kingsville, USA.
making the layout portable. Scaling can be easily done by
simply changing the value of λ. The key disadvantage of
this approach is that it is too conservative and hence
cannot exploit the features of a given process to a
maximum degree.

Wafer and Die:

Wafer: A wafer (also called a slice or substrate) is a thin

slice of semiconductor material, such as a crystalline
silicon, used in electronics for the fabrication of integrated
circuits. It undergoes many microfabrication processes,
such as doping, ion implantation, etching, thin-film
deposition of various materials, and photolithographic
patterning. Finally, the individual microcircuits are
separated by ‘wafer dicing’ and packaged as an integrated
circuit. Wafer diameter can be of various sizes from 25mm
to 675mm, with various thickness under 1mm.
Die: A die is a small block of semiconductor material, on
which a given functional circuit is fabricated. Typically,
integrated circuits are produced in large batches on a
single wafer of electronic-grade silicon (EGS) or other
semiconductor (such as GaAs). The wafer is cut (“diced”)
into many pieces, each containing one copy of the circuit.
Each of these pieces is called a die. Die size varies from
about 5mm2 to 15mm2.
Fig: Semiconductor die.
Photomask:
A photomask is basically a “master template” of an IC
design. A photomask is an opaque plate with holes or
transparencies that allow light to shine through in a
defined pattern. They are commonly used in
photolithography and the production of integrated circuits
(IC). Masks are used to produce the pattern of an IC layout
on a semiconductor wafer. Several masks are used in turn,
each one reproducing a layer of the completed design, and
together they are known as a mask set. A single IC may
contain 5-40 layers, resulting in a need for 5-40 unique
photomasks for every IC.

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Fig: Photomask.
Fig: Photomask in IC manufacturing process.
Photomasks are also known as Optical Masks or Glass
Masks. Photomasks help with the miniaturization of
computer chips. This is because smaller chips require
highly precise images of their general arrangement, which
is near impossible without a lithographic process.
VLSI Design Styles:
Several design styles can be considered for chip
implementation of specified algorithms or logic functions.
Each design style has its own merits and shortcomings,
and thus a proper choice has to be made by designers in
order to provide the functionality at low cost.
1) Programmable Logic Devices (PLD)
a. Field Programmable Gate Array (FPGA)
b. Gate Array (GA) Design
2) Application-Specific Integrated Circuit (ASIC)
a. Standard Cell-based Design (Semi-custom)
b. Full Custom Design
Field Programmable Gate Array (FPGA): A field-
programmable gate array (FPGA) is an integrated circuit
that can be programmed or reprogrammed to the required
functionality or application after manufacturing. This
design style provides a means for fast prototyping and also
for cost-effective chip design, especially for low-volume
Imran Chowdhury | Lecture Note | VLSI II
applications. A typical FPGA chip consists of I/O buffers,
an array of configurable logic blocks (CLBs), and
programmable interconnect structures. Hardware
Description Language (HDL) like Verilog or VHDL is
used as the language of the programming.
Gate Array (GA) Design: In PLD, GA design comes
after FPGA, although it is not programmable by the users,
but fundamental architectures are almost same. Unlike
FPGA, a GA design needs to be sent to a fabrication house
to manufacture the designed circuits onto the chip. But
unlike ASIC, the manufacturing process of GA is much
shorter and requires only 2 (two) steps. The first phase,
which is based on generic (standard) masks, results in an
array of uncommitted transistors (without any
interconnections) on each GA chip. Then, these
uncommitted chips can be customized later, which is
completed by defining the metal interconnects between
the transistors of the array. In a way, ‘GA design’ falls
under the ‘semi-custom design’ as well.
Standard Cell-based Design: Standard cells are pre-
characterized cells used in ASIC Design flow as basic
building blocks. The standard cell is also called the
polycell, and the design style is also called semi-custom
design. In this design style, all of the commonly used logic
cells are developed, characterized, and stored in a standard
cell library. A typical library may contain a few hundred
cells including inverters, NAND gates, NOR gates,
complex AOI, OAI gates, D-latches, and flip-flops. Each
gate type can have multiple implementations to provide
adequate driving capability for different fanouts. For
instance, the inverter gate can have standard size
transistors, double size transistors, and quadruple size
transistors so that the chip designer can choose the proper
size to achieve high circuit speed and layout density.
Full Custom Design: In this design style, the entire mask
design is done anew without use of any library. However,
the development cost of such a design style is becoming
prohibitively high. In real full-custom layout in which the
geometry, orientation and placement of every transistor is
done individually by the designer, design productivity is
usually very low - typically 10 to 20 transistors per day,
per designer. Thus, in digital CMOS VLSI, full-custom
design is rarely used. Exceptions to this include the design
of high-volume products such as memory chips, high-
performance microprocessors, etc. For logic chip design,
a good compromise can be achieved by using a
combination of different design styles on the same chip.
VLSI Design Flow:
VLSI design flow can be broadly categorized into two
parts: (i) Front-End design, and (ii) Back-End design.
Front-end and back-end design can also be referred to as
High-level design and Low-level design respectively.
Generally, front-end design includes circuit modeling and
synthesis using schematic capture and Verilog/VHDL. It
also includes design and testing through various custom
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and Semi-custom methodologies. The back-end design
comprises of IC layout, cell and library design, its
characterization using specific process technology, and
post-layout simulation.
Fig: Typical VLSI design flow (top-down design abstraction).
MOS Transistor Technology
The fundamental building block of integrated circuits is
transistor, and for modern VLSI it is MOSFET, to be
specific, enhancement type MOSFET. MOSFET has 4
(four) terminals Gate, Drain, Source and Body. However,
the body terminal is always connected with the source
terminal. Therefore, we are left with only three terminals.
MOSFETs are classified into 2 (two) types:
1) Depletion type MOSFET (D-MOSFET)
2) Enhancement type MOSFET (E-MOSFET)
Both MOS transistors are further classified as n-type
named nMOS (or n-channel) and p-type named pMOS (or
p-channel) MOSFETs.
The Depletion type MOSFETs are doped so that a channel
exists even with zero voltage from gate to source during
manufacturing of the device. To control the channel, a
negative voltage is applied to the gate (for an n-channel
device), depleting the channel, which reduces the current
flow through the device. In essence, the Depletion type
MOSFET is equivalent to a closed (ON) switch, while the
Enhancement type MOSFET does not have the built in
channel and is equivalent to an open (OFF) switch. Due to
the difficulty of turning off the Depletion MOSFET, they
are rarely used.
Imran Chowdhury | Lecture Note | VLSI II
Fig: n-channel Enhancement type MOSFET (left) and n-
channel Depletion type MOSFET (right).
Fig: p-channel Enhancement type MOSFET (left) and p-
channel Depletion type MOSFET (right).
E-MOSFET (n-type) Fabrication Process:
The aim of this course is not to present a detailed
discussion of silicon fabrication technology, which
deserves separate treatment in a dedicated course. Rather,
the emphasis will be on the general outline of the process
flow and on the interaction of various processing steps.
There is a large number and variety of basic fabrication
steps used in the production of modern integrated circuits.
The same process can be used for the fabrication of nMOS
or pMOS or CMOS devices. The step-by-step procedure
of Enhancement type nMOS fabrication steps are
discussed below:
Step 1 (Substrate Doping): The process starts with a
semiconductor wafer of pure silicon (Si), were p-type
impurities (boron, gallium, indium, aluminum, etc.) are
added through diffusion or ion implantation technique to
make it a p-type substrate for the nMOS. The size of such
wafer is about 75-150mm in diameter and 0.4mm in
thickness, and the doping concentration is about 1015/cm3
to 1016/cm3.
Fig: Step 1 – Silicon substrate is being doped p-type.
Step 2 (Oxidization – Thick Oxide): In order to select
the specific area to form gate, source and drain on the
surface of the substrate, the fabrication process goes
through two steps called oxidization and
photolithography. Growing a think oxide is a part of
oxidization process, where a layer of SiO2 (silicon
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dioxide) typically 1μm thick is grown all over the surface
of the wafer to protect it. It is done by heating the silicon
substrate at around 900℃ and sending water vapor onto it.
Fig: Step 2 – Thick oxide layer grown onto silicon substrate.
Step 3 (Photolithography – Photoresist): The surface is
now covered to photoresist which is deposited onto the
wafer and spun to an even distribution of the required
thickness. Which is done by pouring liquid photoresist
onto the surface of the substrate and spinning it.
Fig: Step 3 – Photoresist deposited onto the surface on top of
the thick oxide layer.
Step 4 (Photolithography – Masking): The photoresist
layer is then exposed to ultraviolet (UV) light through
photomask, which defines those regions into which
diffusion is to take place. Here negative photoresist is used
which gets harden when exposed to UV light, and remain
soften where it is not exposed to UV light. The black
potion of the photomask or optical mask means closed
section and yellow portions mean open section where UV
light can go through. So, the photoresist under the black
portion will remain soften while the photoresist under the
yellow portions will get harden.
Fig: Step 4 – Photoresist being exposed to UV light through
patterned photomask.
Step 5 (Etching): These areas are subsequently readily
etched away together with photoresist and underlying
thick oxide so that the surface of the silicon substrate is
exposed to the window defined by the mask. The soften
photoresist is removed by using some kind of solvent to
wash it away. So, the harden photoresist area remains. The
exposed thick oxide layer is removed by pouring
hydrofluoric acid all over the surface. The harden
photoresist areas act as a protective layer so the underlying
thick oxide layer remains. After mixing with the thick
oxide layer, the hydrofluoric acid gets converted into
hydrofluorosilicic acid which can be easily washed away.
Imran Chowdhury | Lecture Note | VLSI II
Using some other kind of solvent, the remaining harden
photoresist areas are removed as well. The thick oxide
layer outside the window remains.
Fig: Step 5a – The soften photoresist area is being etched away
by using some solvent.
Fig: Step 5b – The thick oxide layer in the window is being
etched away by hydrofluoric acid, and the remaining
harden photoresist areas are being etched away by using
some solvent.
Step 6 (Thin Oxide): A thin layer of SiO2 typically 0.1μm
thick or less is grown all over the surface of the wafer to
make the insulation layer between the polysilicon and
silicon substrate. It is done by heating the silicon substrate
at around 1200℃ and sending oxygen gas or water vapor
onto it. The thickness of the thin oxide layer can be
controlled by the temperature and the reaction time.
Fig: Step 6 – Thin oxide layer gown onto the surface of the
entire wafer.
Step 7 (Poly Formation): Polysilicon is deposited using
chemical vapor deposition (CVD) method on top of the
thin oxide layer in the window to form the gate structure.
The polysilicon is basically heavily doped silicon which is
as good as a conductor. The thickness of this polysilicon
layer is typically 1-2μm.
Fig: Step 7 – Polysilicon is being deposited on top of the thin
oxide layer in the window.
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Step 8 (Exposing Drain and Source Region): After
forming the gate structure, the silicon substrate needs to be
exposed again exactly where the drain and source are to be
formed, using photolithography (applying photoresist and
exposed to UV lights) and etching (removing photoresist
and oxide layer).
Fig: Step 8 – Drain and source regions are being exposed using
photolithography and etching.
Step 9 (Drain and Source Formation): After exposing
the regions where drain and source are to be formed, the
regions are then doped with n-type impurities using either
diffusion or ion implantation method. Diffusion involves
placing the semiconductor wafer in a high temperature
gaseous atmosphere called ‘diffusion furnace’ containing
the desired impurity, where the doping occurs based on
concentration gradient. Ion implantation generally takes
place at a lower temperature than diffusion, where a beam
of impurity ions is accelerated and then directed to the
surface of the semiconductor wafer to make the desired n-
type regions. Depth of the drain and source doping is
generally 1μm. In this process the polysilicon with
underlying thin oxide and the thick oxide acts as the mask
during formation of drain and source, hence the process is
called self-aligning.
Fig: Step 9 – Drain and source regions are being formed either
by diffusion or ion implantation.
Step 10 (Contact Patterning): After forming the gate,
drain and source region, the area on top of them needs to
be exposed where the metal contacts are to be formed,
using oxidization (adding thick oxide), photolithography
(applying photoresist and exposed to UV lights) and
etching (removing photoresist and oxide layer).
Fig: Step 10 – Contact regions are being patterned using
oxidization, photolithography and etching.
Imran Chowdhury | Lecture Note | VLSI II
Step 11 (Metallization): After forming the contact cuts,
the whole wafer then has metal (e.g. Aluminum) deposited
over its surface to a thickness typically of 1μm. This metal
layer then goes through photolithography (applying
photoresist and exposed to UV lights) and etching
(removing photoresist and metal layer).to form the
required contact pattern.
Fig: Step 11 – Metal contacts are being formed using
metallization, photolithography and etching.
Body Effect of MOSFET:
A transistor is a 4-terminal device. Gate, drain and source
are the 3 terminals that are used to control the transistor,
but the bulk or body, if not properly biased, may put the
transistor inoperable.
According to the above figure, the p-n junctions defined
by source-bulk and drain-bulk, which are basically two
diodes, must be reverse-biased to stop them from leaking
current from the source/drain to the substrate. That means
that the source potential must always be equal or greater
than the bulk potential. Since drain voltage is always
greater or equal than source voltage, we don't even
consider the drain-bulk junction.
When VS > VB, the depletion width of the p-n junction
increases. That makes it more difficult to create a channel
with the same VGS, effectively reducing the channel depth.
In order to return to the same channel depth, VGS needs to
increase accordingly.
The body effect can be seen as a change in threshold
voltage and it is modeled as just that:
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 Imran Chowdhury | Lecture Note | VLSI II
vii. Transistor-Transistor Logic (TTL)

 VT0n = threshold voltage when VSB = 0. Non-saturated Bipolar Logic Family is further categorized
 2ϕf = surface potential (2ϕf ≈ 0.6V for NMOS and into 2 (two) types:
0.75V for PMOS). i. Schottky TTL
 γ = body-effect parameter (γ ≈ 0.4V1/2 for NMOS and ii. Emitter Coupled Logic (ECL)
−0.5V1/2 for PMOS).
Unipolar or MOS Logic Family is further categorized
For PMOS, the bulk voltage should always be higher than into 3 (three) types:
the source because the p-n junction is in the opposite
direction (source p+ and bulk n−). Then, the threshold a) pMOS Logic Family
voltage should be rewritten as: b) nMOS Logic Family
c) CMOS Logic Family

Characteristics of Digital IC:

Digital Logic Families Different logic families possess different characteristic.

(IC Design Technologies) One family may be best suited to one situation whereas
another family in some other situation. For example in
Almost all electronic gadgets make use of different digital certain cases, low power consumption may be the prime
systems for their operation. All the digital systems use requirement whereas in some other cases it is speed.
some kind of digital ICs. For the sake of simplicity in
design and compatibility in constructing any complex Along with power consumption and speed, digital ICs
digital system, all digital circuits (ICs) used in the design have other characteristics as well, which are:
process should be from same logic family. Besides, for the 1) Propagation Delay / Operating Speed
expansion of the system, it is necessary to connect 2) Power Dissipation
different logic circuits together. In order to connect the 3) Figure of Merit
output of one logic circuit to the input of another logic 4) Fan-In and Fan-Out
circuit, one must have circuits with similar characteristics. 5) Operating Temperature Range
6) Power Supply Requirements
Logic Family/Technology 7) Voltage and Current Parameters
8) Noise Immunity / Noise Margin
A group of compatible logic circuits having same logic
levels, supply voltages, and electrical characteristics 1) Propagation Delay / Operating Speed: Propagation
fabricated on a single IC for performing various logical Delay is the time interval between the application of the
functions are referred to as logic family. input pulse and the occurrence of the output. If the
propagation delay is less, then the operating speed at
According to the components used to make a logic circuit which the IC operates will be faster.
and as per the construction of the basic logic circuits, there
are different types of logic families. Broadly, logic
families are categorized into 3 (three) types:
1) Bipolar Logic Family
2) Unipolar or MOS Logic Family
3) BiCMOS

Bipolar Logic Family is further categorized into 2 types:

a) Saturated Bipolar Logic Family
b) Non-saturated Bipolar Logic Family
Let TPLH is the time delay when the output changes from
logic 0 to 1, and TPHL is the delay when the output changes
Saturated Bipolar Logic Family is further categorized into
from logic 1 to 0. The average value of THL and TLH is
7 (seven) types:
considered as the propagation delay (TP). The delay times
i. Diode Logic (DL) or Diode-Resistor Logic (DRL) are measured in between the 50% voltage levels of input
ii. Resistor-Transistor Logic (RTL) and output wave forms.
iii. Direct Coupled Transistor Logic (DCTL)
𝑇𝑃𝐿𝐻 + 𝑇𝑃𝐻𝐿
iv. Integrated Injection Logic (IIL or I2L) 𝑃𝑟𝑜𝑝𝑎𝑔𝑎𝑡𝑖𝑜𝑛 𝐷𝑒𝑙𝑎𝑦, 𝑇𝑃 =
v. Diode-Transistor Logic (DTL) 2
vi. High Threshold Logic (HTL)

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2) Power Dissipation: It is the amount of power that a
digital circuit or IC dissipates. The power dissipated is
determined by the average current that is drawn from the
supply voltage (𝑉𝐶𝐶 ). The average current (𝐼𝐶𝐶(𝑎𝑣𝑔)) is the
average value of the current at LOW gate output (𝐼𝐶𝐶𝐿 ) and
the current at HIGH gate output (𝐼𝐶𝐶𝐻 ).
𝐼𝐶𝐶𝐻 + 𝐼𝐶𝐶𝐿
𝐴𝑣𝑒𝑟𝑎𝑔𝑒 𝑐𝑢𝑟𝑒𝑛𝑡, 𝐼𝐶𝐶(𝑎𝑣𝑔) =
2 performance of the IC is effective is called as operating
𝑃𝑜𝑤𝑒𝑟 𝐷𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑖𝑜𝑛, 𝑃𝑑 = 𝑉𝐶𝐶 × 𝐼𝐶𝐶(𝑎𝑣𝑔)
If there are ‘n’ number of logic gates, then the power
dissipation per logic gate would be:
𝑉𝐶𝐶 × 𝐼𝐶𝐶(𝑎𝑣𝑔)
𝑃𝑜𝑤𝑒𝑟 𝐷𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑖𝑜𝑛 𝑝𝑒𝑟 𝑔𝑎𝑡𝑒, 𝑃𝑑𝑛 =
𝑛
3) Figure of Merit: In digital logic circuits, a trade-off
exists between power dissipation and the speed. That is,
for higher speed, the power dissipation will be more. For
an efficient operation of any device, achieving a higher
speed with less power dissipation is desirable but a highly
challenging task.
The figure of merit or Speed Power Product is a common
means of measuring the performance of circuits in the
digital logic family.
𝐹𝑖𝑔𝑢𝑟𝑒 𝑜𝑓 𝑀𝑒𝑟𝑖𝑡 = 𝑃𝑟𝑜𝑝𝑎𝑔𝑎𝑡𝑖𝑜𝑛 𝐷𝑒𝑙𝑎𝑦 × 𝑃𝑜𝑤𝑒𝑟 𝐷𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑖𝑜𝑛
To achieve higher performance, the value of figure of
merit should be as low as possible.
4) Fan-In and Fan-Out: Fan-in is the number of inputs
connected to the gate without any degradation in the
voltage level. For the example given in the figure below,
the EX-OR gate has three inputs. So fan-in for the given
EX-OR gate is 3.
Fan-out refers to the number of inputs that is driven by the
output of another logic gates without any degradation in
the voltage level and keeping the proper function. For
example, the following circuit has an EX-OR gate, which
drives 4 NOT gates. So fan-out of EX-OR gate is 4.
Imran Chowdhury | Lecture Note | VLSI II
Fan-out is calculated from the amount of current available
in the output of a gate and the amount of current needed in
each input of the connecting gate. It is specified by
manufacturer and is provided in the data sheet.
5) Operating Temperature Range: All the gates which
are made up of semiconductor devices are temperature
sensitive in nature. The temperature in which the
temperature range. The accepted temperature range for
consumer ICs is from 0℃ to 70℃, from 0℃ to 85℃ for
industrial applications, and from -55℃ to 125℃ for
military applications.
6) Power Supply Requirements: Every IC requires a
certain amount of electrical power to operate, and different
logic family requires a different level of supply voltage.
Usually there is only one power-supply terminal on the
chip and it is marked VCC for bipolar logic family or VDD
for MOS logic family. Obviously low power consumption
is a desirable feature in any digital IC.
7) Voltage and Current Parameters: Voltage and
current parameters are defined by the span of input and
output voltage and current. In order to achieve proper
operation in multistage gates or logic circuits, these
parameters should be matched.
𝑉𝑂𝐻(𝑚𝑖𝑛) = 𝑚𝑖𝑛𝑖𝑚𝑢𝑚 𝑂/𝑃 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑓𝑜𝑟 𝑙𝑜𝑔𝑖𝑐 1
𝑉𝑂𝐿(𝑚𝑎𝑥) = 𝑚𝑎𝑥𝑖𝑚𝑢𝑚 𝑂/𝑃 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑓𝑜𝑟 𝑙𝑜𝑔𝑖𝑐 0
𝑉𝐼𝐻(𝑚𝑖𝑛) = 𝑚𝑖𝑛𝑖𝑚𝑢𝑚 𝐼/𝑃 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑓𝑜𝑟 𝑙𝑜𝑔𝑖𝑐 1
𝑉𝐼𝐿(𝑚𝑎𝑥) = 𝑚𝑎𝑥𝑖𝑚𝑢𝑚 𝐼/𝑃 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑓𝑜𝑟 𝑙𝑜𝑔𝑖𝑐 0
𝐼𝑂𝐻 = ℎ𝑖𝑔ℎ 𝑙𝑒𝑣𝑒𝑙 𝑂/𝑃 𝑐𝑢𝑟𝑟𝑒𝑛𝑡
𝐼𝑂𝐿 = 𝑙𝑜𝑤 𝑙𝑒𝑣𝑒𝑙 𝑂/𝑃 𝑐𝑢𝑟𝑟𝑒𝑛𝑡
𝐼𝐼𝐻 = ℎ𝑖𝑔ℎ 𝑙𝑒𝑣𝑒𝑙 𝐼/𝑃 𝑐𝑢𝑟𝑟𝑒𝑛𝑡
𝐼𝐼𝐿 = 𝑙𝑜𝑤 𝑙𝑒𝑣𝑒𝑙 𝐼/𝑃 𝑐𝑢𝑟𝑟𝑒𝑛𝑡
Version 1.3 | Page 11 of 18

8) Noise Immunity / Noise Margin: In digital logic
circuits, the binary values 0 and 1 represent the LOW and
HIGH voltage levels. Due to the interference of the noises,
the voltage levels may increase or decrease. This may lead
to the wrong operation of the device. The noise immunity
is the ability of the logic device to tolerate the noise
without causing spurious change to the output voltage.
Noise margin allows the logic device to function properly
within the specified limits. It is expressed in volts.
Noise Margin at input or output of a gate:
𝐼𝑛𝑝𝑢𝑡 𝑁𝑜𝑖𝑠𝑒 𝑀𝑎𝑟𝑔𝑖𝑛, 𝑉𝑁(𝑖𝑛) = 𝑉𝐼𝐻(𝑚𝑖𝑛) − 𝑉𝐼𝐿(𝑚𝑎𝑥)
𝑂𝑢𝑡𝑝𝑢𝑡 𝑁𝑜𝑖𝑠𝑒 𝑀𝑎𝑟𝑔𝑖𝑛, 𝑉𝑁(𝑜𝑢𝑡) = 𝑉𝑂𝐻(𝑚𝑖𝑛) − 𝑉𝑂𝐿(𝑚𝑎𝑥)
Noise Margin in between two stages of gates:
𝐻𝑖𝑔ℎ 𝑆𝑡𝑎𝑡𝑒 𝑁𝑜𝑖𝑠𝑒 𝑀𝑎𝑟𝑔𝑖𝑛, 𝑉𝑁𝐻 = 𝑉𝑂𝐻(𝑚𝑖𝑛) − 𝑉𝐼𝐻(𝑚𝑖𝑛)
𝐿𝑜𝑤 𝑆𝑡𝑎𝑡𝑒 𝑁𝑜𝑖𝑠𝑒 𝑀𝑎𝑟𝑔𝑖𝑛, 𝑉𝑁𝐿 = 𝑉𝐼𝐿(𝑚𝑎𝑥) − 𝑉𝑂𝐿(𝑚𝑎𝑥)
CMOS Logic Family
(CMOS Technology)
The term CMOS stands for “Complementary Metal Oxide
Semiconductor”. It is a class of digital circuits built using
both enhancement type nMOS and pMOS. The advantages
of CMOS logic family includes high speed, low power
dissipation, high noise margins in both states, and a wide
range of source and input voltages (fixed source voltage).
CMOS logic family was developed for the Very Large
Scale Integration (>10000 gates) and beyond. This logic
family can be classified into the following categories:
1) Static CMOS Logic
a) Conventional Static CMOS Logic
b) Pseudo-nMOS Logic (Ratioed Logic)
c) Pass Transistor & Transmission Gate Logic
2) Dynamic CMOS Logic
a) Domino Logic
b) np-CMOS Logic
Imran Chowdhury | Lecture Note | VLSI II
Conventional Static CMOS Logic
The basic idea for Conventional Static CMOS technology
is to combine n-channel and p-channel MOSFETs such
that there is never a conducting path from the supply
voltage to ground. As a consequence, these logic circuits
consume very little energy. Power is only dissipated in
case the circuit actually switches. This logic family
incorporates enhancement type nMOS in the pull-down
network and pMOS in the pull-up network in equal
numbers. Both n-channel and p-channel MOSFETs are
designed to have matching characteristics. Conventional
Static CMOS technology is simply called CMOS.
Fig: Static CMOS Inverter.
According to the above schematic, if HIGH voltage (logic
1) is applied at 𝑉𝑖𝑛 , the pMOS turns OFF and the nMOS
turns ON. Since the nMOS is ON, the resistance between
𝑉𝑜𝑢𝑡 and ground will be ideally zero, and hence the voltage
drop at 𝑉𝑜𝑢𝑡 becomes LOW (logic 0). And, if LOW
voltage is applied at 𝑉𝑖𝑛 , the pMOS turns ON and the
nMOS tuens OFF. Since the nMOS is OFF, the resistance
between 𝑉𝑜𝑢𝑡 and ground will be ideally infinite, and
hence the voltage drop at 𝑉𝑜𝑢𝑡 will be HIGH.
Static CMOS Combinational Logic Design:
In this logic family, nMOSs are arranged in a pull-down
network (PDN) between the output and the ground rail
(VSS) while pMOSs are in a pull-up network (PUN)
between the output and the supply voltage rail (VDD). All
the inputs are distributed to both the PUN and PDN. Thus,
an nMOS will be ON when the corresponding pMOS is
OFF, and vice-versa. For any input pattern, one of the
networks is ON and the other is OFF.
Fig: General block diagram of static CMOS logic.
Version 1.3 | Page 12 of 18

Designing combinational circuits with Static CMOS logic
technically means designing the pull-down and pull-up
network. The number of nMOS in the PDN and pMOS in
the PUN depends on the number of inputs, and their
connection depends on the Boolean function. The
following table shows the type of connection in the PND
and PUN based on the logic operation in the Boolean
function. Like nMOS logic, Static CMOS logic works for
inverted logic by default.
Pull-down Pull-up
Logic Operation
Network (PDN) Network (PUN)
Addition Parallel Series
Multiplication Series Parallel
Pseudo-nMOS Logic
Although CMOS is superior in terms of static power loss
and operating speed to its predecessor, but it needs more
transistors than others in the same logic family like nMOS
logic. Hence area consumption is more for CMOS. This is
where Pseudo-nMOS logic comes in which is based on
nMOS logic structure keeping the CMOS definition
satisfied by incorporating pMOS load in the nMOS logic
circuit. The advantages of Pseudo-nMOS logic includes
less area consumption, hence low gate capacitance, thus
higher operating speed. But the main disadvantage of this
logic is it carries on the static power loss from nMOS logic
since the load is always ON. Like nMOS logic, Pseudo-
nMOS logic was developed for the Large Scale Integration
(≤10000 gates).
Fig: Pseudo-nMOS Inverter.
The operation of the above Pseudo-nMOS inverter is same
as an nMOS inverter since the load pMOS is always ON,
because according to the load configuration 𝑉𝐺(𝐿𝑜𝑎𝑑) = 0,
which makes 𝑉𝐺𝑆(𝐿𝑜𝑎𝑑) = −𝑉𝐷𝐷 .
Pseudo-nMOS Combinational Logic Design:
The design of Pseuso-nMOS combinational logic circuits
is similar to the basic principles developed for nMOS logic
circuits, except for the fact that the load is always a pMOS.
So, the structure of driver (or pull-down) network with
nMOS, number of nMOS and their interconnection, input
connections, etc. remain same.
Imran Chowdhury | Lecture Note | VLSI II
Fig: General block diagram of Pseudo-nMOS logic.
As with nMOS logic, designing combinational circuits
with Pseudo-nMOS logic technically means designing the
driver (or pull-down) network, since there is only one
pMOS load in the pull-up network. Again, as with nMOS
logic, the number of nMOS and their connection in the
driver network depends on the number of inputs and their
Boolean function respectively. Like nMOS and CMOS
logic, Pseudo-nMOS works for inverted logic by default.
Driver Network or Pull-
Logic Operation
down Network (PDN)
Addition Parallel
Multiplication Series
Pass Transistor Logic
Pass Transistor:
Like Pseudo n-MOS logic, Pass Transistor logic comes in
to reduce the number of transistor from a logic circuit that
the CMOS logic circuits encounter. The basic principle of
Pass Transistor is to pass a voltage from one point to
another, and single nMOS or pMOS transistor is the basic
building block of this logic. So, based on the type of
transistor, Pass Transistor can be 2 (two) types:
1) nMOS Pass Transistor
2) pMOS Pass Transistor
nMOS Pass Transistor:
When nMOS is used as the building block of the Pass
Transistor logic, it is called nMOS Pass Transistor. In
nMOS Pass Transistor, a positive supply voltage (𝑉𝐷𝐷 ) is
applied to the gate (𝑉𝐷𝐷 = 𝑉𝐺 ), the input voltage is applied
to the drain (𝑉𝑖𝑛 = 𝑉𝐷 ), and the output voltage is taken
from the source ( 𝑉𝑜𝑢𝑡 = 𝑉𝑆 ). The range of the output
voltage can be 0 to 𝑉𝐷𝐷 − 𝑉𝑇𝑛 , since 𝑉𝐺𝑆 needs to be at
least equal to 𝑉𝑇𝑛 (generally 1V) to turn ON the nMOS.
Fig: nMOS Pass Transistor.
Version 1.3 | Page 13 of 18
 Imran Chowdhury | Lecture Note | VLSI II
Considering the supply voltage 𝑉𝐷𝐷 = 5𝑉 and threshold
voltage 𝑉𝑇𝑛 = 1𝑉 for the nMOS, for different values of If 𝑉𝑖𝑛 ≤ |𝑉𝑇𝑝 | Then 𝑉𝑜𝑢𝑡 = |𝑉𝑇𝑝 |
𝑉𝑖𝑛 the values of 𝑉𝑜𝑢𝑡 will be as follows: If 𝑉𝑖𝑛 > |𝑉𝑇𝑝 | Then 𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛

𝑉𝐷𝐷 = 5𝑉  Observation #1: Since this logic passes exact 5V for

𝑉𝑇𝑛 = 1𝑉 input 5V but 1V for input 0V, it is said that pMOS
𝑽𝒊𝒏 (V) 𝑽𝒐𝒖𝒕 (V) Pass Transistor passes strong HIGH but weak LOW.
0 0  Observation #2: To pass Strong LOW, 𝑉𝑆𝑆 needs to
0.5 0.5 be connected to at least −1V.
1 1
2 2
Cascading Pass Transistor:
3 3
4 4
When multiple Pass Transistors are connected such a way
4.5 4
that one Pass Transistor is driving another, it is called
5 4
cascading Pass Transistors. Based on the connection
cascading can be be done in 2 (two) ways:
If 𝑉𝑖𝑛 ≤ 𝑉𝐷𝐷 − 𝑉𝑇𝑛 Then 𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛
If 𝑉𝑖𝑛 > 𝑉𝐷𝐷 − 𝑉𝑇𝑛 Then 𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 − 𝑉𝑇𝑛 1) Driving next Pass Transistor’s gate (not recommended)
2) Driving next Pass Transistor’s drain (recommended)
 Observation #1: Since this logic passes exact 0V for
input 0V but 4V for input 5V, it is said that nMOS The following type of cascading is based on the first
Pass Transistor passes strong LOW but weak HIGH. category where one Pass Transistor is driving the gate of
 Observation #2: To pass Strong HIGH, 𝑉𝐷𝐷 needs to the next one. The problem with this cascading is that, since
be higher than 𝑉𝑖𝑛 by 𝑉𝑇𝑛 , meaning 𝑉𝐷𝐷 − 𝑉𝑖𝑛 = 𝑉𝑇𝑛 . the output voltage at drain is dependent on the supply
voltage at gate, at every stage the 𝑉𝑜𝑢𝑡 degrades by 𝑉𝑇𝑛
pMOS Pass Transistor: until it becomes 0. This is why this type of cascading is
not recommended. This type of cascading is not even
When pMOS is used as the building block of the Pass possible for pMOS Pass Transistors.
Transistor logic, it is called pMOS Pass Transistor. In
nMOS Pass Transistor, ground (𝑉𝑆𝑆 ) is applied to the gate
( 𝑉𝑆𝑆 = 𝑉𝐺 ). As with nMOS Pass Transistor, the input
voltage is applied to the drain (𝑉𝑖𝑛 = 𝑉𝐷 ), and the output
voltage is taken from the source (𝑉𝑜𝑢𝑡 = 𝑉𝑆 ). The range of
the output voltage can be |𝑉𝑇𝑝 | to 𝑉𝑖𝑛 since 𝑉𝐺𝑆 needs to
be at least −𝑉𝑇𝑝 (generally −1V) to turn ON the nMOS.
Fig: Cascading by driving next pass transistor’s gate.

The following type of cascading is based on the second

category where one Pass Transistor is driving the drain of
the next one. Unlike the first category of cascading, the
output voltage in this cascading does not degrades at every
stage as long as the supply voltage at the gate of every Pass
Transistor is same.
Fig: pMOS Pass Transistor.

Considering the gate is grounded 𝑉𝑆𝑆 = 0𝑉 and threshold

voltage |𝑉𝑇𝑝 | = 1𝑉 for the pMOS, for different values of
𝑉𝑖𝑛 the values of 𝑉𝑜𝑢𝑡 will be as follows:
Fig: Cascading by driving next pass transistor’s drain.
𝑉𝑆𝑆 = 0𝑉
Pass Transistor Combinational Logic Design:
|𝑉𝑇𝑝 | = 1𝑉
𝑽𝒊𝒏 (V) 𝑽𝒐𝒖𝒕 (V) A popular and widely-used alternative to complementary
0 1 static CMOS is pass-transistor logic, which attempts to
0.5 1 reduce the number of transistors required to implement a
1 1
logic circuit by allowing the primary inputs to drive gate
1.5 1.5
terminals as well as source/drain terminals. This is in
2 2
3 3
contrast to logic families that we have studied so far,
4 4 which only allow primary inputs to drive the gate
5 5 terminals of MOSFETS.

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Transmission Gate or Pass Gate Logic
The Transmission Gate Logic is developed to solve the
voltage drop problem of the Pass Transistor Logic. This
technique uses the complementary properties of nMOS
and pMOS transistors. i.e.:
 nMOS passes strong LOW (logic 0)
 pMOS passes strong HIGH (logic 1)
The transmission gate combines the best of the two
devices by placing an nMOS transistor in parallel with a
pMOS transistor as shown in Figure below. The control
signals to the transmission gate 𝐶 and 𝐶̅ are
complementary to each other. The transmission gate is a
bidirectional switch enabled by the gate signal 'C'.
Fig: Transmission Gate symbols.
According to the transmission gate in the following figure,
 When C = 1, both MOSFETs are ON and the signal
pass through the gate i.e. A = B if C = 1.
 Whereas C = 0 makes the MOSFETs cut off creating
an open circuit between nodes A and B, which
produces a High Impedance (Z) output at B.
C A B and the transconductance can be optimized separately.
0 0 Z
0 1 Z fabricated based on p-well process.
1 0 0
1 1 1
Fig: Transmission Gate circuit.
Transmission Gate Combinational Logic Design:
In the previous section, nMOS Pass Transistors were used
to implement logic circuits to reduce the number of
transistors in comparison to CMOS logic circuits. But the
voltage reduction at the output still remains, since nMOS
passes weak HIGH. Transmission Gate logic solves this
issue by connecting a pMOS with the nMOS in parallel,
so that nMOS can be used to pass strong LOW and pMOS
can be used to pass strong HIGH. The fundamental logic
circuit structure of Transmission Gate is same as with the
Pass Transistor logic.
CMOS Fabrication Technology
(CMOS Fabrication Process Types)
The CMOS fabrication technology is recognized as the
leader of VLSI systems technology. CMOS provides an
inherently low power static circuit technology that has the
capability of providing lower power-delay product than
Imran Chowdhury | Lecture Note | VLSI II
bipolar, nMOS, or GaAs technologies. CMOS can be
obtained by integrating both nMOS and pMOS transistors
over the same silicon wafer. Depending on which type of
silicon wafer is primarily chosen, the fabrication process
can be classified into 3 (three) types:
1) P-well Process
2) N-well Process
3) Dual-well or Twin-tub Process
P-well Process: In this process of CMOS, the substrate or
silicon wafer is chosen to be n-type in which pMOS
devices are formed by suitable masking and diffusion. In
order to accommodate nMOS devices, a deep p-well is
diffused into the n-type substrate.
N-well Process: In this process of CMOS, the substrate or
silicon wafer is chosen to be p-type in which nMOS
devices are formed by suitable masking and diffusion. In
order to accommodate pMOS devices, a deep n-well is
diffused into the p-type substrate. N-well CMOS circuits
are superior to p-well because of the lower substrate bias
effect on threshold voltage and inherently lower parasitic
capacitances associated with the source and drain regions.
Twin-tub Process: In this process of CMOS, the substrate
or silicon wafer is chosen to be intrinsic. This allows two
separate tubs to be implanted into the silicon, which in turn
allows the doping profiles in each tub region to be tailored
independently so that neither type of device will suffer
from excessive doping effects. The main advantage of this
process is that the threshold voltage, body effect parameter
For an example, the following CMOS based device is
Fig: Cross-section of a CMOS device based on p-well process.
CMOS Layout Design
After designing the circuit schematic and synthesizing the
operation, the physical circuit/mask layout is designed
which is to be fabricated onto a chip. The layout design
process is done in 2 (two) steps:
1) Stick Diagram
2) Mask/Circuit Layout
Stick Diagram
A stick diagram is a kind of diagram which is used to plan
the layout of a transistor cell or a complex circuit. Stick
diagram is a means of capturing topography and layer
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 Imran Chowdhury | Lecture Note | VLSI II
information using simple diagrams. It uses "sticks" or lines Exercise 1:
to represent the devices and conductors. It acts as an
interface between symbolic circuit and the actual layout. Draw the stick diagram of a CMOS inverter.
Stick diagram conveys layer information of the CMOS Solution:
circuit through:
Stick Diagram Notations:
a) Color codes, or
b) Monochrome encoding

Stick Diagram shows:

 all components and vias (interconnections).
 relative placement of components.

Stick Diagram does not show: Sick Diagram of a CMOS Inverter:

 exact placement of components.
 transistor sizes.
 wire lengths, wire widths, tub boundaries.

Some Rules of Sick Diagram:

Rule 1: When two or more ‘sticks’ of the same type cross

or touch each other that represents electrical contact.

Rule 2: When two or more ‘sticks’ of different type cross
or touch each other there is no electrical contact (If
electrical contact is needed we have to show the
connection explicitly).
Circuit Layout
VLSI design ultimately aims to translate circuit concepts
onto silicon, which is done by designing circuit layout.
Circuit layout is also called Mask Layout or Physical
Layout. Layout Design is a schematic of the Integrated
Circuits (IC) which describes the exact area and placement
of the components for fabrication. The layout is a physical
representation of circuit design, or the drawing the masks
which will be used in the manufacturing process.

Layout Design shows:

 all components and vias (interconnections).
 exact placement of components.
Rule 3: When a poly crosses diffusion it represents a  transistor sizes.
transistor (if a contact is shown then it is not a transistor).  wire lengths, wire widths, tub boundaries.

Fig: Physical layout of nMOS (left) and pMOS (right).

Rule 4: In CMOS, a separation line is drawn to avoid

touching of p-diff with n-diff. All pMOS must lie on one
side of the line and all nMOS on the other side.

Fig: Layout Design Flow (schematic to physical layout).

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Exercise 1:
Draw the physical layout of a CMOS inverter considering
n-well fabrication process.
Solution:
Layout Notations:

Physical Layout of a CMOS Inverter:

Exercise 4:

Draw the physical layout of the following CMOS logic

circuit considering twin-tub fabrication process.
𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴 + 𝐵 + 𝐶𝐷

Solution:
Exercise 2:

Draw the physical layout of a CMOS 2-input NAND gate

considering n-well fabrication process.

Solution:

Problem 1:

Draw the physical layout of the following CMOS logic

circuit considering twin-tub fabrication process.
𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴+𝐵+𝐶

Why nMOS used in pull-down:

Let’s consider pMOS in the pull-down and nMOS in the

pull-up. When pMOS is OFF, nMOS should be ON and its
gate to source voltage would be,
Exercise 3:

Draw the physical layout of a CMOS 2-input NOR gate ⇒ 𝑉𝐺𝑠 = 𝑉𝑡ℎ = 𝑉𝐺 − 𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡
considering twin-tub fabrication process. ⇒ 𝑉𝐺𝑠 = 𝑉𝐷𝐷 − 𝑉𝑜𝑢𝑡
Solution: ∴ 𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 − 𝑉𝐺𝑠
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Thus, the output voltage is always reduced by 𝑉𝐺𝑠 . Now,

if we increase 𝑉𝐺𝑆 in order to get higher current, the output
reduces even more. This is why nMOS is not used in the
pull-up network in CMOS design.

Latch-up:

Latch-up is a condition in which the parasitic components

give rise to the establishment of low resistance conducting
paths between VDS and VSS with disastrous results. Careful
control during fabrication is necessary to avoid this
problem.

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