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    assala benmalek
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    The document discusses programming for high performance and parallel architectures. It covers Moore's Law about transistors doubling every 1.5 years, leading processors to increase cores instead of frequency. It classifies parallel architectures as SISD, SIMD, MISD, and MIMD based on whether instructions and data are single or multiple. The objective is to program for parallel architectures like GPUs using approaches like OpenCL and take advantage of instruction sets like SSE and AVX.

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    The document discusses programming for high performance and parallel architectures. It covers Moore's Law about transistors doubling every 1.5 years, leading processors to increase cores instead of frequency. It classifies parallel architectures as SISD, SIMD, MISD, and MIMD based on whether instructions and data are single or multiple. The objective is to program for parallel architectures like GPUs using approaches like OpenCL and take advantage of instruction sets like SSE and AVX.

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    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    4 views1 page

    Session 5

    Uploaded by

    assala benmalek
    The document discusses programming for high performance and parallel architectures. It covers Moore's Law about transistors doubling every 1.5 years, leading processors to increase cores instead of frequency. It classifies parallel architectures as SISD, SIMD, MISD, and MIMD based on whether instructions and data are single or multiple. The objective is to program for parallel architectures like GPUs using approaches like OpenCL and take advantage of instruction sets like SSE and AVX.

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    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
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    programming for high performance :

    Moor's law
    paallel architecte taxonmy classification

    SIMD pogamming
    SSE > AVX
    GPU ->open CL
    (intel)

    MIMD

    shared memory
    prrivate memory

    Moor's Law:

    number of transistors in a cp doubles in each 1 ear and a half


    processor frequency is limited ! 5Ghz for the power consmption !! and heat

    incease the number of cores > paralel architecture > parallel progamming !

    objective : progamme in paallel achitectre !

    parallell achitectre classification :

    SISD : isngle instuction single data (old cpu processor!


    SIMD single multiple
    MISD multiple single -> not eal class onl exist in theory !
    MIMD multiple multiple

    processing Unit execute a strim of instructions to process data

    cp capabity check :

    cp info command !!!!cat /proc /cp info ?

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