K S INSTITUTE OF TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

DIGITAL COMMUNICATION
SYNCHRONISATION
INTRODUCTION: the current I, has a waveform with equal width, equal amplitude

The transmitter and Receiver is said to be synchronous when an positive and negative portions. The net change in the charge across

event occur simultaneously in both transmitter and receiver at a the capacitor is zero, the VCO control voltage remains constant, and

particular instant of time. The process of making a situation no

synchronous and maintaining it in this condition is called

synchronization.

WHAT IS SYNCHRONISATION?

In baseband PAM systems the output of the receiving filter Y(t) must

be sampled at precise sampling instants fm = mT, + t To do this

sampling we need a clock signal at the receiver that is synchronized

adjustment is made on the rate and phase of the clock signal. As the
with the clock signal at the transmitter. Three general methods in
clock signal drifts out of phase, the phase comparison operation at
which this synchronization can be obtained are:
time t₂ results in a current pulse I, with a more positive component.
1. derivation of clock information from a primary or secondary
Now, there is a change q in the capacitor charge and hence a change
standard; for example, the transmitter and receiver can be slaved to
in the VCO control voltage. This change in the VCO control voltage
a master clock;
results in a correction of the clock phase. In the example shown in
2. transmitting a
Figure (b), the clock phase is shown corrected before the next phase
synchronizing clock
comparison operation is initiated at 13. Several versions of the clock
signal;
recovery network shown in Figure (a&b) are used in practice. Almost
3. derivation of the
all self-synchronizing networks depend on level changes or zero
clock signal from the
crossings in the received waveform Y(t). The performance of these
received waveform itself.
networks will degrade considerably if the signal stays at a constant
An example of a system used to derive a clock signal from the
level for long periods of time and if the zero crossings in Y(t) are
received waveform is shown in Figure(b) The clock recovery network
obliterated by noise. The lack of level changes in the data can be
consists of a voltage controlled oscillator (VCO) and a phase
corrected by using one of the coding methods suggested in the
comparator consisting of the phase comparison logic and transistor
preceding section. The effect of noise on the zero crossing can be
controlled current switches. The phase comparison logic circuit is
minimized by setting an error threshold in the phase comparator
triggered by the one shot multivibrator that outputs a pulse of
output below which no clock phase correction is attempted.
duration T2 when the input Y(t) is <0. The correction or error signal
APPLICATIONS:
comes out of the phase comparator in the form of I. The charging
Some examples of its applications include time synchronization and
and discharging of the capacitor is controlled by I, and the voltage
scheduling in large-scale distributed networks; distributed fusion in
across the capacitor controls the VCO, which generates the clock
sensor networks; rapid consensus in various network topologies;
signal.To illustrate the operation of the phase comparator network,
distributed formation control of multiple vehicles; and solutions of
let us look at the timing diagram shown in Figure (b). At time t₁, the
nonlinear optimization problems.
clock signal is in phase and between time t, and to the clock signal
AADHYA B N (1KS21EC001)
drifts by a small amount. As Y(t) goes negative at t₁, the one shot is
ARCHANA M (1KS21EC011)
triggered and it puts out a pulse of duration 0.5T. The phase
DEEPIKA D (1KS21EC027)
comparison logic generates two equal width pulses QC and QC, and