Professional Documents
Culture Documents
D D
Mars ST3 Base Board
Revision 1.1
A A
http://www.enclustra.com Copyright © 2019 by Enclustra GmbH Sheet Name MA-ST3_P01_Cover.SchDoc Customer No 0000 Revision R1.1 DNE = Do Not Equip Free
http://www.enclustra.com Company Enclustra FPGA Solutions Project ST3 Project No 455 Designed HMEY Date 05.09.2019 Sheet/sheets 1 / 13
6 5 4 3 2 1
D J200A
VCC_OUT
J200B
D
1 2 101 102
VIN_MOD GND VOUT IO_P MIPI_D0_P 7
3 4 103 104
VIN_MOD MGT_CLK_P CLK_P 6 10 IO0_D12_P SCLK_P IO_N MIPI_D0_N 7
5 6 105 106
VIN_MOD MGT_CLK_N CLK_N 6 10 IO0_D13_N SCLK_N VOUT VMON_P106 2
VCC_5V 7 8 107 108
VIN_MOD GND GND IO_P MIPI_D1_P 7
9 10 109 110
VIN_MOD MGT_CLK_P IO1_CLK_P 10 9 HDMI_CLK_P IO_P IO_N MIPI_D1_N 7
11 12 111 112
VIN_MOD MGT_CLK_N IO1_CLK_N 10 9 HDMI_CLK_N IO_N PCLK_P MIPI_CLK_P 7
13 14 VCC_IOB 113 114
12, 13 PWR_EN PWR_EN GND 9 HDMI_D0_P IO_P PCLK_N MIPI_CLK_N 7
15 16 115 116
GND MGT_RX_P IO1_D20_P 10 9 HDMI_D0_N IO_N GND
17 18 117 118
8 DP_LANE1_P MGT_TX_P MGT_RX_N IO1_D21_N 10 VIN_IO IO_P IO0_D6_P 10
19 20 119 120
8 DP_LANE1_N MGT_TX_N GND 9 HDMI_D1_P IO_P IO_N IO0_D7_N 10
21 22 121 122 VCC_IOB
GND MGT_RX_P IO1_D18_P 10 9 HDMI_D1_N IO_N IO_P IO0_D4_P 10
23 24 123 124
8 DP_LANE0_P MGT_TX_P MGT_RX_N IO1_D19_N 10 9 HDMI_D2_P IO_P IO_N IO0_D5_N 10
25 26 125 126
8 DP_LANE0_N MGT_TX_N GND 9 HDMI_D2_N IO_N VIN_IO
27 28 127 128
GND MGT_RX_P USBH_SSRX_P 5 GND SCLK_P IO0_D0_P 10
29 30 129 130
5 USBH_SSTX_P MGT_TX_P MGT_RX_N USBH_SSRX_N 5 10 IO0_D18_P IO_P SCLK_N IO0_D1_N 10
31 32 131 132
5 USBH_SSTX_N MGT_TX_N GND 10 IO0_D19_N IO_N IO_P IO0_D2_P 10
33 34 VCC_CFG 133 134
GND MGT_RX_P IO1_D22_P 10 10 IO0_D20_P IO_P IO_N IO0_D3_N 10
35 36 135 136
10 IO1_D16_P MGT_TX_P MGT_RX_N IO1_D23_N 10 10 IO0_D21_N IO_N GND
37 38 137 138
10 IO1_D17_N MGT_TX_N GND VIN_CFG IO_P DP_AUX_OE 8
39 40 139 140
GND PWR_GOOD PWR_GOOD 11, 12, 13, 6, 9 6 SDIO_CLK IO_P IO_N HDMI_CEC 9
141 142 VCC_CFG
6 SDIO_CMD IO_N IO_P DP_AUX_OUT 8
143 144
6 SDIO_D0 IO_P IO_N DP_AUX_IN 8
41 42 145 146
2 VMON_P41 VOUT VOUT VMON_P42 2 6 SDIO_D1 IO_N VIN_CFG
43 44 147 148
10 IO1_D0_P PCLK_P IO_P IO1_D2_P 10 GND IO_P GPIO0_LED0# 10, 11, 7
C 10 IO1_D1_N
45
47
PCLK_N
GND
IO_N
IO_P
46
48
IO1_D3_N
IO1_D4_P
10
10
6
6
SDIO_D2
SDIO_D3
149
151
SCLK_P
SCLK_N
IO_N
IO_P
150
152
GPIO1_LED1#
SDCARD_CD#
10, 11, 7
6
C
VCC_IOA 49 50 153 154
10 IO1_D10_P SCLK_P IO_N IO1_D5_N 10 4 UART_RX IO_P IO_N BTN# 11
51 52 155 156
10 IO1_D11_N SCLK_N GND 4 UART_TX IO_N GND
53 54 157 158
VIN_IO IO_P IO1_D6_P 10 GND JTAG_TCK JTAG_TCK 10, 4
55 56 VCC_USBMOD 159 160
10 IO1_D12_P IO_P IO_N IO1_D7_N 10 5 USBH_D_P USB_DP JTAG_TDI JTAG_TDI 10, 4
57 58 VCC_IOA 161 162
10 IO1_D13_N IO_N IO_P IO1_D8_P 10 5 USBH_D_N USB_DM JTAG_TMS JTAG_TMS 10, 4
59 60 163 164
10 IO1_D14_P IO_P IO_N IO1_D9_N 10 VBUS_HDP JTAG_TDO JTAG_TDO 10, 4
61 62 165 166
10 IO1_D15_N IO_N VIN_IO 5 USBMOD_ID ID_HDM USB_CPEN USBMOD_CPEN 5
63 64 167 168
GND IO_P IO2_D4_P 10 GND RSVD RVSD_CLKEXT 6
65 66 169 170
10 IO2_D0_P IO_P IO_N IO2_D5_N 10 7 ETH_A_N ETH_A_N RSVD BOOT_MODE1 11
67 68 171 172
10 IO2_D1_N IO_N IO_P IO2_D6_P 10 7 ETH_A_P ETH_A_P GND
VCC_IOA 69 70 173 174
10 IO2_D2_P IO_P IO_N IO2_D7_N 10 7 ETH_LED1# ETH_LED1# I2C_INT# I2C_INT# 10
71 72 175 176
10 IO2_D3_N IO_N GND 7 ETH_LED2# ETH_LED2# I2C_SDA I2C_SDA 10, 4
73 74 177 178
VIN_IO IO_P IO3_D0_P 10 7 ETH_B_N ETH_B_N I2C_SCL I2C_SCL 10, 4
75 76 179 180
6 I2C_SCL_FPGA IO_P IO_N IO3_D1_N 10 7 ETH_B_P ETH_B_P GND
77 78 VCC_IOB 181 182
6 I2C_SDA_FPGA IO_N IO_P IO3_D2_P 10 ETH_CTREF FLASH_CLK FLASH_CLK 4
79 80 183 184
8 DP_HPD IO_P IO_N IO3_D3_N 10 7 ETH_C_N ETH_C_N FLASH_DO FLASH_DO 4
81 82 185 186
9 HDMI_HPD IO_N VIN_IO 7 ETH_C_P ETH_C_P FLASH_DI FLASH_DI 4
83 84 10 187 188
VCC_OUT GND IO_P IO0_D22_P ETH_LED1# FLASH_CS# FLASH_CS# 4
85 86 10 189 190
10 IO0_CLK_P PCLK_P IO_N IO0_D23_N ETH_LED2# BOOT_MODE BOOT_MODE0 11, 4
87 88 191 192
10 IO0_CLK_N PCLK_N GND 7 ETH_D_N ETH_D_N SRST#_RDY# SRST#_RDY# 10, 13, 3, 4
89 90 193 194
VOUT IO_P IO0_D10_P 10 7 ETH_D_P ETH_D_P FPGA_DONE FPGA_DONE 11, 4
91 92 VCC_3V3_MOD 195 196 VCC_BAT
10 IO0_D14_P IO_P IO_N IO0_D11_N 10 GND POR#_LOAD# POR#_LOAD# 11, 13, 3, 4, 6
93 94 197 198
10 IO0_D15_N IO_N VOUT VMON_P94 2 VIN_3V3 VMON VMON_P198 2
95 96 199 200
GND IO_P IO0_D8_P 10 VIN_3V3 VIN_BAT
97 98
10 IO0_D16_P IO_P IO_N IO0_D9_N 10
99 100 1565917-4
10 IO0_D17_N IO_N GND
B 1565917-4
B
GND GND GND GND
A C200
100n
C201
100n
C202
100n
C203
100n
C204
100n
C205
10u
C206
1u
C207
10u
C208
1u
C209
100n
C210
100n
C211
10u
C212
1u
C213
100n
C214
100n
C215
10u
C216
1u
C217
100n
C218
22u
6V3
C219
22u
6V3
C220
10u
C221
1u
C222
10u
C223
1u A
25V 25V 25V 25V 25V 10V 10V 10V 10V 25V 25V 10V 10V 25V 25V 10V 10V 25V 10V 10V 10V 10V
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
http://www.enclustra.com Copyright © 2019 by Enclustra GmbH Sheet Name MA-ST3_P02_Module_Connector.SchDoc Customer No 0000 Revision R1.1 DNE = Do Not Equip Free
http://www.enclustra.com Company Enclustra FPGA Solutions Project ST3 Project No 455 Designed HMEY Date 05.09.2019 Sheet/sheets 2 / 13
6 5 4 3 2 1
FTDI USB 2.0 Device Controller JTAG Detect & Enable FTDI EEPROM
VCC_3V3_FTDI VCC_3V3_FTDI
U300
FTDI_OSCI 2 16 FTDI_TCK R300
OSCI ADBUS0 FTDI_TCK 4
FTDI_OSCO 3 17 FTDI_SRST#_JTAGOE
OSCO ADBUS1 FTDI_TDI 4 DNE
18 R301
ADBUS2 FTDI_TDO 4 0R
19 R302 10k
D FTDI_RESET# 14
RESET#
ADBUS3
ADBUS4
ADBUS5
21
22
FTDI_D4
FTDI_TMS 4
10 JTAG_PRSNT#
FTDI_JTAG_OE
FTDI_JTAG_OE 4
R303
10k
R304
10k R305
D
23 FTDI_POR# 0R
ADBUS6 R306
24 FTDI_SRST#_JTAGOE FTDI_D4 FTDI_TCK
ADBUS7 DNE 1k
0R U301
7 26 FTDI_EE_CS 1 4 FTDI_EE_DO
5 USBD_D_N USB_DM ACBUS0 CS DO
8 27 FTDI_EE_CLK 2
5 USBD_D_P USB_DP ACBUS1 CLK
28 7
ACBUS2 NC
29 FTDI_EE_DATA 3 VCC_3V3_FTDI
ACBUS3 DI
30 FTDI_SRST#_OE# 6
ACBUS4 ORG
32 FTDI_SRST#
ACBUS5
60 33 5 8
PWREN# ACBUS6 VSS VCC
34
ACBUS7
93AA66C-I/MS
GND
38 FTDI_BDBUS0
BDBUS0
39 FTDI_BDBUS1
BDBUS1
36
SUSPEND# BDBUS2
BDBUS3
BDBUS4
40
41
43
FTDI_BDBUS2
FTDI_BDBUS3 FPGA Reset Generation FTDI Miscellaneous
44 VCC_3V3_FTDI
BDBUS5
FTDI_REF 45
BDBUS6
R308 46 R307 10k
BDBUS7 U302 3, 4 FTDI_MODE0
6 R309 10k
REF 3, 4 FTDI_MODE1
1
12k B1
C GND
BCBUS0
BCBUS1
48 FTDI_LED
52
FPGA_DONE_LS 4
FTDI_SRST# 3
B0 A
4
SRST#_RDY# 10, 13, 2, 3, 4
FTDI_D4 R310
FTDI_SRST#_OE# R311
4k7
10k C
53 FTDI_SRST# R312 10k
BCBUS2 SRST#_RDY#_LS 4
54 FTDI_SRST#_OE# 6 VCC_3V3_FTDI
BCBUS3 POR#_LOAD#_LS 4 SELECT
55 C300 R313 1k
BCBUS4 BOOT_MODE0_LS 4 DNE
57 2 5 100p
BCBUS5 FTDI_MODE0 3, 4 GND VCC
FTDI_EE_CLK 62 58 25V FTDI_D4 R314 4k7
EECLK BCBUS6 FTDI_MODE1 3, 4 DNE
FTDI_EE_CS 63 59 FTDI_RESET# NLASB3157DFT2G
EECS BCBUS7
FTDI_EE_DATA 61 GND DNE GND FTDI_JTAG_OE R315 4k7
EEDATA DNE
31
VCCIO
13 20 GND
TEST VCCIO U303
42
VCCIO
56
VCCIO
1 FTDI_POR# 1 6 11, 13, 2, 4, 6
GND 1A 1Y POR#_LOAD#
5 12 FTDI_BDBUS0 R316 22R
GND VCORE FTDI_SCK_SCL_TXD 4
11 37 FTDI_BDBUS1 R317 0R
GND VCORE FTDI_MOSI_SDA_RXD 4
15 64 VCC_3V3_VPHY FTDI_BDBUS2 R318 0R
GND VCORE FTDI_MISO_SDA 4
25 FTDI_SRST#_JTAGOE 3 4 10, 13, 2, 3, 4 FTDI_BDBUS3 R319 0R
GND 2A 2Y SRST#_RDY# FTDI_CS# 4
35 4 VCC_3V3_VPLL VCC_3V3_FTDI
GND VPHY
47
GND
51 9 2 5
GND VPLL GND VCC
VCC_1V8_FTDI
10
AGND
49
VCC_3V3_FTDI
GND
74LVC2G07FZ4-7
FTDI_LED
R320 D300
FTDI_LED_D
FTDI
VREGOUT
65 50
PAD VREGIN 1k
Yellow GND
FT2232HQ
B GND
B
A A
C308 C309 C310 C311 C312 C313 C314 C315
100n 100n 100n 100n 100n 100n 100n 100n
25V 25V 25V 25V 25V 25V 25V 25V
GND GND GND GND GND GND GND GND
http://www.enclustra.com Copyright © 2019 by Enclustra GmbH Sheet Name MA-ST3_P03_USB_Controller.SchDoc Customer No 0000 Revision R1.1 DNE = Do Not Equip Free
http://www.enclustra.com Company Enclustra FPGA Solutions Project ST3 Project No 455 Designed HMEY Date 05.09.2019 Sheet/sheets 3 / 13
6 5 4 3 2 1
1B2
3 FLASH_CLK_LS
10, 13, 2, 3, 4 SRST#_RDY#
FTDI_UARTMODE# 6
A2
OE
B2 SRST#_RDY#_LS 3
FLASH_DO_LS 4
A2
A3
B2
B3
8
FLASH_DI
FLASH_DO
2
2
D
6 FLASH_DI_LS FLASH_CLK_LS 5 7
2B2 A4 B4 FLASH_CLK 2
10 FLASH_DO_LS
3B2
13 FLASH_CS#_LS 2 FLASH_LS_OE 12
4B2 GND OE
FTDI_MODE1 1
3 FTDI_MODE1 S
FTDI_MODE0 15 GND NTS0102GT115 6
3 FTDI_MODE0 OE# GND
VCC_3V3_FTDI VCC_3V3_FTDI
8 GND NTB0104GU12;115
GND
17 16 VCC_CFG VCC_3V3_FTDI
GND VCC U403
74CBTLV3257BQ R402 3 7 VCC_3V3_FTDI
VCCA VCCB
GND 4k7 R403
5 8 FLASH_LS_OE
11, 2 FPGA_DONE A1 B1 FPGA_DONE_LS 3
4 1 Q400A
U404 11, 2 BOOT_MODE0 A2 B2 BOOT_MODE0_LS 3 10k
EM6K6T2R
4 2 6
3, 4 FTDI_SCK_SCL_TXD 1A 1B1 I2C_SCL 10, 2 OE
7 5
3, 4 FTDI_MOSI_SDA_RXD 2A 2B1 I2C_SDA 10, 2, 4
9 11
3, 4 FTDI_MISO_SDA 3A 3B1 I2C_SDA 10, 2, 4 10, 13, 2, 3, 4 SRST#_RDY#
12 14 2
4A 4B1 GND
3 UART_RX_LS GND NTS0102GT115
1B2
GND 6 UART_TX_LS
2B2
10 GND
3B2
13 FTDI_UARTMODE#
4B2
FTDI_MODE1 1
S
C FTDI_MODE0# 15
OE#
VCC_3V3_FTDI C
8
17
GND
GND VCC
16
C400
100p FTDI LDO 3.3V 0.3A FTDI JTAG Level Shifters
25V
74CBTLV3257BQ VCC_CFG VCC_3V3_FTDI
GND GND U405
3 7
VCCA VCCB
VCC_3V3_MOD VCC_3V3_FTDI
Q401
5 8
VCC_3V3_FTDI 10, 2 JTAG_TDI A1 B1 FTDI_TDI 3
4 1
10, 2 JTAG_TCK A2 B2 FTDI_TCK 3
R404
FTDI_MODE0# 6
3, 4 FTDI_JTAG_OE OE
VCC_3V3
10k Q400B
VCC_USBD
EM6K6T2R R405
AO3401A 2
GND
FTDI_MODE0 0R
DNE NTS0102GT115
GND
U406
R406 1 5 VCC_CFG VCC_3V3_FTDI
IN OUT U407
1k C401 C402
22u 100n 4 3 7
NC VCCA VCCB
GND 25V 25V C403 C404
3 2 1u 22u 5 8
EN GND 10, 2 JTAG_TDO A1 B1 FTDI_TDO 3
10V 6V3 4 1
10, 2 JTAG_TMS A2 B2 FTDI_TMS 3
LD39015M33R
GND GND GND GND GND GND 6
3, 4 FTDI_JTAG_OE OE
B FTDI UART Level Shifter B
2
GND
VCC_CFG VCC_3V3_FTDI NTS0102GT115
GND
1k U408 1k
3 7
VCCA VCCB
5 8 UART_RX_LS
2 UART_RX A1 B1 UART_RX_LS 10
4 1 UART_TX_LS
2 UART_TX A2 B2 UART_TX_LS 10
POR#_LOAD# 6
11, 13, 2, 3, 4, 6 POR#_LOAD# OE
2
GND
NTS0102GT115
GND
FTDI_MODE1 FTDI_MODE0
A FPGA serial
I2C
0
0
0
1 A
SPI flash 1 0
UART 1 1
http://www.enclustra.com Copyright © 2019 by Enclustra GmbH Sheet Name MA-ST3_P04_USB_Mux_LS.SchDoc Customer No 0000 Revision R1.1 DNE = Do Not Equip Free
http://www.enclustra.com Company Enclustra FPGA Solutions Project ST3 Project No 455 Designed HMEY Date 05.09.2019 Sheet/sheets 4 / 13
6 5 4 3 2 1
R501
2 USBMOD_ID
C 0R C
GND
VCC_USBH VCC_USBMOD
R502
1k
USBH_SSTX_J_P 5 GND
K_D
A 6
A
D3V3F4U10LP-7
http://www.enclustra.com Copyright © 2019 by Enclustra GmbH Sheet Name MA-ST3_P05_USB_Connectors.SchDoc Customer No 0000 Revision R1.1 DNE = Do Not Equip Free
http://www.enclustra.com Company Enclustra FPGA Solutions Project ST3 Project No 455 Designed HMEY Date 05.09.2019 Sheet/sheets 5 / 13
6 5 4 3 2 1
A1
VCCB
B1
8 SDCARD_CLK_R R602 22R SDCARD_CLK
SDCARD_D2
SDCARD_D3
1
2
DAT1
DAT2
DAT3/CD
CMD
3 SDCARD_CMD VCC_OSC
Y600
DNE
C600 D
22R 4 1 SDCARD_CMD 11 1 4 CLK_C_P
2 SDIO_CMD A2 B2 CD1 SDCARD_CD# 2 E/D# OUT_P CLK_P 2
6 9 VCC_CFG 100n
11, 13, 2, 3, 4, 6 POR#_LOAD# OE GNDC
10 12 R603 25V
GNDC CD2 R604 10k
13 100R
2
GND
SD 14
GNDC
GNDC
15 GND VCC_3V3 C601
GNDC
NTS0102GT115 5 CLK_C_N
OUT_N CLK_N 2
GND 6 4
VSS VDD
2 VCC_OSC 100n
C602 NC
503182-1832 25V
VCC_CFG VCC_3V3 GND 1u 3 6
U601 10V GND VCC
3 7 GND OSC6P_7.5X5.2+5X3.2+3.2X2.5_GENERIC
VCCA VCCB
GND DNE
5 8 SDCARD_D1
2 SDIO_D1 A1 B1
4 1 SDCARD_D0
2 SDIO_D0 A2 B2
6
11, 13, 2, 3, 4, 6 POR#_LOAD# OE
2
GND
C GND
NTS0102GT115
Power Sequencing User Oscillator C
VCC_CFG VCC_3V3
U602 VCC_3V3 VCC_OSC
3 7 VCC_3V3_MOD VCC_3V3
L600
VCCA VCCB U603 BLM18SG121TN1D
5 8 SDCARD_D3 C603 100n 1 4
2 SDIO_D3 A1 B1 IN OUT
4 1 SDCARD_D2 25V VCC_IO
2 SDIO_D2 A2 B2 C604
GND
L601 BLM18SG121TN1D
6 3 1u
11, 13, 2, 3, 4, 6 POR#_LOAD# OE 11, 12, 13, 2, 6, 9 PWR_GOOD EN 10V
DNE
2 GND VCC_IOA
GND
2 5 L602
GND GNDPAD BLM18SG121TN1D
NTS0102GT115 SIP32408DNP-T1-GE4 DNE
GND C605 C606
GND 10u 100n
10V 25V
GND GND
B B
I2C Level Shifter Reset Circuit Miscellaneous
23ms delay
VCC_3V3
U604
RESET_CT 3 1 R605 0R
CT VOUT POR#_LOAD# 11, 13, 2, 3, 4, 6 2 RVSD_CLKEXT DNE
VCC_IOB VCC_3V3 R606 R607 2
U605 SUB
2k2 2k2 C607 5 4 VCC_3V3 R608
GND VDD
3 7 47k GND
VCCA VCCB 1n BU4230FVE-TR
5 8 R609 0R 50V GND
2 I2C_SDA_FPGA A1 B1 I2C_SDA_HDMI 9
4 1 R610 0R
2 I2C_SCL_FPGA A2 B2 I2C_SCL_HDMI 9
GND GND
6
11, 12, 13, 2, 6, 9 PWR_GOOD OE
R611 0R
I2C_SDA_MIPI 7
R612 0R
I2C_SCL_MIPI 7
2
GND
NTS0102GT115 I2C_SDA_FPGA_LS 10
A GND
I2C_SCL_FPGA_LS 10 A
http://www.enclustra.com Copyright © 2019 by Enclustra GmbH Sheet Name MA-ST3_P06_Osc_SDCard.SchDoc Customer No 0000 Revision R1.1 DNE = Do Not Equip Free
http://www.enclustra.com Company Enclustra FPGA Solutions Project ST3 Project No 455 Designed HMEY Date 05.09.2019 Sheet/sheets 6 / 13
6 5 4 3 2 1
yellow
MIPI 9 MIPI_CLK_J_P
14 ETH_YELLOW_A R703 150R 10 R704
11 MIPI_GPIO0 MIPI_D1_J_P
MIPI_D1_P 2
13 ETH_LED1# 12 MIPI_GPIO1
13 I2C_SCL_MIPI 0R R705
14 I2C_SDA_MIPI 150R
11 ETH_A_P 15 R706
TRD1+ ETH_A_P 2
10 ETH_A_N VCC_3V3 MIPI_D1_J_N
TRD1- ETH_A_N 2 MIPI_D1_N 2
12 ETH_CT1 1u SFW15S-2STE1LF
TRCT1 0R
C700 10V GND
4 ETH_B_P
TRD2+ ETH_B_P 2
5 ETH_B_N Raspberry Pi Cam I2C Addresses
TRD2- ETH_B_N 2
6 ETH_CT2 1u R707
TRCT2
C701 10V MIPI_CLK_J_P
MIPI_CLK_P 2
TRD3+
3 ETH_C_P
ETH_C_P 2 Sony Camera: 0010 000Rw
2 ETH_C_N 0R R708
TRD3-
1 ETH_CT3 1u
ETH_C_N 2 ATSHA204A: 1100 100Rw
TRCT3 150R
C702 10V R709
C TRD4+
TRD4-
8
9
ETH_D_P
ETH_D_N
ETH_D_P
ETH_D_N
2
2
MIPI_CLK_J_N
0R
MIPI_CLK_N 2 C
7 ETH_CT4 1u
TRCT4
C703 10V
ETH_LED1#
ETH_LED1# 2
18 GND ETH_LED2#
CHASSIS ETH_LED2# 2
19
CHASSIS
VCC_3V3
orange green
16 GNDE
17
ETH_GREEN_A
ETH_LED2#
R710 150R
MIPI ESD Protection MIPI GPIO & I2C
15
D700
MIPI_D1_J_P 1 R711
K_A
6-2301994-1 10 MIPI_GPIO0
GPIO0_LED0# 10, 11, 2
MIPI_D1_J_N 2 0R
K_B
9 3
GND
R712
MIPI_D0_J_P 4 8 MIPI_GPIO1
K_C GND GPIO1_LED1# 10, 11, 2
7
0R
MIPI_D0_J_N 5 I2C_SCL_MIPI
K_D I2C_SCL_MIPI 6
6 I2C_SDA_MIPI
I2C_SDA_MIPI 6
D3V3F4U10LP-7
B MIPI_CLK_J_N 1
D701
K_A
B
10
MIPI_CLK_J_P 2
K_B
9 3
GND
MIPI_GPIO0 4 8
K_C GND
7
MIPI_GPIO1 5
K_D
6
D3V3F4U10LP-7
D702
I2C_SCL_MIPI 2
3
I2C_SDA_MIPI 1
D5V0F2U3LP-7B GND
A A
http://www.enclustra.com Copyright © 2019 by Enclustra GmbH Sheet Name MA-ST3_P07_Ethernet_MIPI.SchDoc Customer No 0000 Revision R1.1 DNE = Do Not Equip Free
http://www.enclustra.com Company Enclustra FPGA Solutions Project ST3 Project No 455 Designed HMEY Date 05.09.2019 Sheet/sheets 7 / 13
6 5 4 3 2 1
100n 2129320-3
25V
GND R806 R807 R808 GNDE
47k 47k 47k
SN74AVC4T245RSVR
GND GND D801
GND 1 DP_AUX_J_P
3
2 DP_AUX_J_N
GND D5V0F2U3LP-7B
A A
http://www.enclustra.com Copyright © 2019 by Enclustra GmbH Sheet Name MA-ST3_P08_DisplayPort.SchDoc Customer No 0000 Revision R1.1 DNE = Do Not Equip Free
http://www.enclustra.com Company Enclustra FPGA Solutions Project ST3 Project No 455 Designed HMEY Date 05.09.2019 Sheet/sheets 8 / 13
6 5 4 3 2 1
TMDS_DATA1_SHIELD
5 BLM18SG121TN1D D
25V HDMI_D1_J_N 6 GND_HDMI_D2
TMDS_DATA1-
HDMI_D1_AC_P 28 13 HDMI_D1_J_P HDMI_D0_J_P 7 8 L901
IN_D2+ OUT_D2+ TMDS_DATA0+ TMDS_DATA0_SHIELD
HDMI_D1_AC_N 27 14 HDMI_D1_J_N HDMI_D0_J_N 9
IN_D2- OUT_D2- TMDS_DATA0-
C902 100n HDMI_D1_AC_P HDMI_CLK_J_P 10 11
2 HDMI_D1_P TMDS_CLOCK+ TMDS_CLOCK_SHIELD BLM18SG121TN1D
25V HDMI_D0_AC_P 30 11 HDMI_D0_J_P HDMI_CLK_J_N 12
IN_D3+ OUT_D3+ TMDS_CLOCK-
HDMI_D0_AC_N 29 12 HDMI_D0_J_N GND_HDMI_D1
IN_D3- OUT_D3-
C903 100n HDMI_D1_AC_N HDMI_SCL 15 13 HDMI_CEC_J L902
2 HDMI_D1_N SCL CEC
25V HDMI_CLK_AC_P 32 9 HDMI_CLK_J_P HDMI_SDA 16
IN_D4+ OUT_D4+ SDA
HDMI_CLK_AC_N 31 10 HDMI_CLK_J_N
IN_D4- OUT_D4- BLM18SG121TN1D
VCC_5V_HDMI M1 14
SHIELD RSVD/HEC-
C904 100n HDMI_D0_AC_P M2 19 HDMI_HPD_J GND_HDMI_D0
2 HDMI_D0_P SHIELD HPD/HEC+
25V 17 M3 17 L903
OE# SHIELD DDC/CEC/HEC_GND
M4 18
SHIELD 5V_50MA_POWER
C905 100n HDMI_D0_AC_N
2 HDMI_D0_N BLM18SG121TN1D
25V HDMI_EQ_0 GND 8 R900 R901 685119134923
EQ_0
HDMI_EQ_1 2 2k2 2k2 GND_HDMI_CLK
EQ_1
GNDE
L904
C906 100n HDMI_CLK_AC_P VCC_5V
F900 VCC_5V_HDMI
2 HDMI_CLK_P
25V HDMI_HPD_SRC 5 19 HDMI_SCL
HPD_SRC SCL_SINK BLM18SG121TN1D
20 HDMI_SDA
SDA_SINK
C907 100n HDMI_CLK_AC_N GND_HDMI GND
2 HDMI_CLK_N
25V 7 0ZCJ0012FF2E
6 I2C_SCL_HDMI SCL_SRC
6 C908
6 I2C_SDA_HDMI SDA_SRC
21 HDMI_HPD_J 10n
HPD_SINK
C VCC_3V3
R903 REXT
4
HDMI_REXT 50V
C
HDMI_DDC_EN 22 GND_HDMI
DDC_EN
R902
10k HDMI_DDET 3 23 12k
DDET NC
VCC_3V3
HDMI_HIZ_EN 24
HIZ_EN
1
VDD
R904 33 18 GND R905
GND VDD
10k 10k
PTN3363BSMP
GND
DNE
DNE
0R 0R 0R
D3V3F4U10LP-7 GND D5V0F2U3LP-7B
2
HDMI_SDA
HDMI_HPD_J
7 HDMI_D0_J_P
8 4 GND D5V0F2U3LP-7B
GND K_C
VCC_IOB VCC_3V3 3 9 HDMI_CLK_J_N
U901 GND
2
K_B
3 7 GND
VCCA VCCB
10 HDMI_CLK_J_P
R912 100R HDMI_CEC_R 5 8 HDMI_CEC_J 1
2 HDMI_CEC A1 B1 K_A
4 1 HDMI_HPD_SRC
2 HDMI_HPD A2 B2
D3V3F4U10LP-7
6
11, 12, 13, 2, 6 PWR_GOOD OE
2
GND
A NTS0102GT115 A
GND
http://www.enclustra.com Copyright © 2019 by Enclustra GmbH Sheet Name MA-ST3_P09_HDMI.SchDoc Customer No 0000 Revision R1.1 DNE = Do Not Equip Free
http://www.enclustra.com Company Enclustra FPGA Solutions Project ST3 Project No 455 Designed HMEY Date 05.09.2019 Sheet/sheets 9 / 13
6 5 4 3 2 1
C C
R1005A
2
2
IO1_D4_P
IO1_D2_P
27
29
28
30
IO1_D5_N
IO1_D3_N
2
2
2 IO3_D3_N
100R 100R
UART_TX_LS 4 B
31 32
SRST#_RDY# 13, 2, 3, 4 2 IO1_D0_P IO1_D1_N 2
33 34
100R 35 36
2 IO1_CLK_P IO1_CLK_N 2
I2C_EN1 37 38
D1000 I2C_SDA 2, 4
I2C_INT# 39 40
2 I2C_INT# I2C_SCL 2, 4
JTAG_TCK_R 1
K_A
10 WE 613 040 211 21
GND GND
JTAG_TDO_R 2
K_B
9 3
GND
JTAG_TMS_R 4
7
K_C GND
8
Anios I2C Enable
JTAG_TDI_R 5
K_D
6
VCC_3V3
D3V3F4U10LP-7 R1007
I2C_EN0
D1001 1k
A SRST#_RDY#_R 2
3 R1008
A
1 I2C_EN1
D5V0F2U3LP-7B GND 1k
http://www.enclustra.com Copyright © 2019 by Enclustra GmbH Sheet Name MA-ST3_P10_IOS_JTAG.SchDoc Customer No 0000 Revision R1.1 DNE = Do Not Equip Free
http://www.enclustra.com Company Enclustra FPGA Solutions Project ST3 Project No 455 Designed HMEY Date 05.09.2019 Sheet/sheets 10 / 13
6 5 4 3 2 1
D R1100
VCC_3V3_MOD
Q1201B
EM6K6T2R
D
VCC_IOB
1k VCC_BAT_IN VCC_BAT
R1101 R1102 D1100 R1103
VCC_BAT_R
LED_YELLOW_A 1k 1k
BAS40SL 10k
D1101 LED_GREEN_Q2
Yellow LED_GREEN_A J1100 C1100
DONE Q1101A
EM6K6T2R
CR1220 CR1220 100n
VCC_CFG BC501SM 25V
D1102
LED_YELLOW_C Green
Q1100A
PWGD GND GND
EM6K6T2R LED_GREEN_C
Q1100B LED_GREEN_Q3
2, 4 FPGA_DONE EM6K6T2R Q1101B
VCC_IOA
EM6K6T2R
R1104
47k
12, 13, 2, 6, 9 PWR_GOOD
LED_GREEN_Q1
C GND GND
C
GND
A Yellow
GPIO1_LED1#_D
1k
GPIO1_LED1# 10, 2, 7
11 12
TE_440054-2 A
WE 613 012 211 21 GND
VSEL
http://www.enclustra.com Copyright © 2019 by Enclustra GmbH Sheet Name MA-ST3_P11_User_Interface.SchDoc Customer No 0000 Revision R1.1 DNE = Do Not Equip Free
http://www.enclustra.com Company Enclustra FPGA Solutions Project ST3 Project No 455 Designed HMEY Date 05.09.2019 Sheet/sheets 11 / 13
6 5 4 3 2 1
D1201 4u7
LDO 1.2V 0.2A Power Switch PMEG4050EP115
C1210
R1203
10k
1n
VCC_3V3_MOD VCC_CFG VCC_IOB PWR_5V_FB 50V
VCC_3V3 VCC_IOB GND C1211 C1212 C1213 C1214
U1201 C1215 U1202 22u 22u 22u 22u
C1216 100n 4 1 R1204 1 4 6V3 6V3 6V3 6V3
BIAS OUT IN OUT
25V 10k R1205
C GND
VCC_3V3
VSEL_IOB# 3
EN C1218
1u 11, 13 VSEL_IOB
GND 100n
25V 3
EN
C1217
1u
10V
2k2
C
6
IN 10V 2 GND
GND
GND VSEL_IOB VCC_IOB 5 GND GND GND GND GND
GNDPAD
C1219 7 2 low 1.2V
GNDPAD NC
100n 5 default high VCC_CFG
GND SIP32408DNP-T1-GE4
25V GND
GND GND
NCP133AMX120TCG
VCC_3V3_MOD
R1206
Dual Buck Converter
VSEL_IOB#
Output 1: 1.8/2.5V 2A 3%
10k
Q1201A Output 2: 3.3V 2A 3%
Board Decoupling EM6K6T2R
VCC_5V
L1203
VCC_5V_3V3_IO
A VCC_CFG
3
B0 A
4
PWR_IO_FB2_R2 A
6 VCC_3V3_MOD
11, 13 VSEL_IO SELECT
VSEL_IO VCC_IO C1251 2 5
GND VCC
C1252 C1253 C1254 C1255 C1256 C1257 low 2.5V 100p
100n 100n 100n 100n 100n 100n default high 1.8V 25V NLASB3157DFT2G
25V 25V 25V 25V 25V 25V GND GND
GND GND GND GND GND GND
http://www.enclustra.com Copyright © 2019 by Enclustra GmbH Sheet Name MA-ST3_P12_Power_Supply.SchDoc Customer No 0000 Revision R1.1 DNE = Do Not Equip Free
http://www.enclustra.com Company Enclustra FPGA Solutions Project ST3 Project No 455 Designed HMEY Date 05.09.2019 Sheet/sheets 12 / 13
6 5 4 3 2 1
250V Copper triangle 0.75mm Copper triangle 0.75mm Copper triangle 0.75mm Copper triangle 0.75mm 1mm
4n7
M1334 M1333 M1335 M1336 M1337 M1338 M1339 GND GND_IN
C1301
Layer Display Copper triangle 0.75mm 1mm
PWR_EN 12, 2 1mm 1mm 1mm 1mm 1mm 1mm 1mm
B 250V
4n7 M1340 M1341 M1342 M1343 PWR_5V_FB PWR_5V_ADJ PWR_5V_RT PWR_EN_3V3 B
M1344
C1302 VSEL_IO 11, 12
DISPLAY
Impedance Test Strip 1mm
A MARS_MOUNTING_HOLES (4 pad)
L3_100_N
L3_100_P
13
14
L6_100_N
L6_100_P
13
14 S1751-46
A
TOP_100_N 15 BOT_100_N 15 GND
TOP_100_P 16 BOT_100_P 16 M1358 M1359 M1360 M1361 M1362 M1363
GND 1mm 1mm 1mm 1mm 1mm 1mm
IMP_TEST_STRIP IMP_TEST_STRIP
http://www.enclustra.com Copyright © 2019 by Enclustra GmbH Sheet Name MA-ST3_P13_Mechanics.SchDoc Customer No 0000 Revision R1.1 DNE = Do Not Equip Free
http://www.enclustra.com Company Enclustra FPGA Solutions Project ST3 Project No 455 Designed HMEY Date 05.09.2019 Sheet/sheets 13 / 13