CHAPTER 6

CENTRAL PROCESSING UNIT

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Dhiraj Shrestha
INRODUCTION

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GENERAL REGISTER ORGANIZATION

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GENERAL REGISTER ORGANIZATION

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STACK ORGANIZATION

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STACK ORGANIZATION

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STACK ORGANIZATION
Reverse Polish Notation(RPN)
⚫ Infix Notation- operator is written between two operand A + B
⚫ Prefix Notation- operator is written before two operand +AB
⚫ Postfix/reverse polish Notation- operator is written after two
operand AB+
⚫ RPN is suitable for stack manipulation
⚫ Expression: A×B + C×D
⚫ RPN: AB×CD×+

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 STACK ORGANIZATION
Conversion to RPN
1. Print operands as they arrive.

2. If the stack is empty or contains a left parenthesis on top, push the incoming operator onto the stack.

3. If the incoming symbol is a left parenthesis, push it on the stack.

4. If the incoming symbol is a right parenthesis, pop the stack and print the operators until you see a left
parenthesis. Discard the pair of parentheses.

5. If the incoming symbol has higher precedence than the top of the stack, push it on the stack.

6. If the incoming symbol has equal precedence with the top of the stack, use association. If the association
is left to right, pop and print the top of the stack and then push the incoming operator. If the association
is right to left, push the incoming operator.

7. If the incoming symbol has lower precedence than the symbol on the top of the stack, pop the stack and
print the top operator. Then test the incoming operator against the new top of stack.

8. At the end of the expression, pop and print all operators on the stack. (No parentheses should remain.)

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STACK ORGANIZATION

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STACK ORGANIZATION

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INSTRUCTION FORMAT
Fields in Instruction Formats
⚫ 1) Operation Code Field : specify the operation to be
performed
⚫ 2) Address Field : designate a memory address or a
processor register
⚫ 3) Mode Field : specify the operand or the effective
address (Addressing Mode)

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INSTRUCTION FORMAT

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INSTRUCTION FORMAT

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INSTRUCTION FORMAT

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ADDRESSING MODE

To give programming versatility to the user

⚫ pointers to memory, counters for loop control, indexing of data,
….
To reduce the number of bits in the addressing field of the
instruction
Instruction Cycle
1) Fetch the instruction from memory and PC + 1
2) Decode the instruction
3) Execute the instruction
Program Counter (PC)
⚫ PC keeps track of the instructions in the program stored in memory
⚫ PC holds the address of the instruction to be executed next
⚫ PC is incremented each time an instruction is fetched from
memory
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ADDRESSING MODE
Addressing Mode of the Instruction
1) Distinct Binary Code
Instruction format contains Opcode, addressing mode
field and may or may not contains address field. If there is, it
designates memory address or a processor register

2) Single Binary Code

Specifies both operation and the mode field

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 ADDRESSING MODE
1. Implied / Immediate Addressing mode (AM)

Operand = A

2. Direct AM

Effective Address (EA) = A

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ADDRESSING MODE
EA = (A)
Indirect AM

Register direct AM

EA = R

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ADDRESSING MODE
3. Register Indirect AM

EA = ( R )

4. Displacement AM

EA = A + (R)

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ADDRESSING MODE
4 a) Relative Address mode
EA = A + (PC)
b) Indexed Addressing mode
EA = A + (IR) IR= Index register
c) Base register Addressing mode
EA = A + (BR) BR= Base register

5 Stack AM EA = Top of Stack (TOS)

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Mode Algorithm Principal Advantage Principal
Disadvantage
Immediate Operand = A No memory Limited operand
reference magnitude
Direct EA = A Simple Limited address
space
Indirect EA = (A) Large address space Multiple memory
references
Register EA = R No memory Limited address
reference space
Register Indirect EA = (R) Large address space Extra memory
references
Displacement EA = A + (R) Flexibility Complexity
Stack EA = top of stack No memory Limited applicability
reference

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DATA TRANSFER AND MANIPULATION

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PROGRAM CONTROL

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PROGRAM CONTROL

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RISC AND CISC
Read yourself characteristics of RISC and CISC
Architecture

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END of Chapter 6

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