CHAPTER ONE

BOOLEAN ALGEBRA, BOOLEAN FUNCTIONS,VHDL, AND GATES

REFERENCE: RICHARD S. SANDIGE AND MICHAEL L. SANDIGE, FUNDAMENTALS OF DIGITAL AND

COMPUTER DESIGN WITH VHDL, MCGRAW-HILL, 2012
INTRODUCTION

 Boolean functions are used in industry to specify logic or digital circuits. Logic gates or digital circuits
represent a class of circuits that produce operations of the yes–no (true–false or 1–0) variety.
 These types of circuits are the ones used in the computer industry and many other areas that use
digital circuits. For example, digital circuits are used in cell phones, calculators, computers, washing
machines, microwave ovens, and kid’s toys—the list is practically endless.
 Three different ways are used to express Boolean functions :
➢ Boolean algebra is a mathematical form used to represent a Boolean function.
➢ Gates are a graphical form to represent a Boolean function.
➢ VHDL (Very High Speed Integrated Circuit Hardware Description Language) is a textual form to
represent a Boolean function.
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 BASICS OF BOOLEAN ALGEBRA

 Boolean algebra consists of a set of independent

statements called postulates.
 The term Boolean is derived from the writings of
George Boole and a book he published in 1854 called
An Investigation of the Laws of Thought.
 In addition, H. E. Huntington published several sets of
independent statements or postulates for Boolean
algebra in a paper published in 1904 called “Sets of
Independent Postulates for the Algebra of Logic.”
 The simplest way to describe Boolean algebra is to
illustrate the major binary operators (“ ¯ ”, “ . ”, and
“+”) with variables (or signals) in a list like the one
shown in Table 1.1.

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VENN DIAGRAMS

 A Venn diagram is a graphical interpretation of an algebraic operation.

 Note : universe is the area of the large rectangle

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 BLACK BOXES FOR BOOLEAN FUNCTIONS

 The term black box is used in circuit theory to

specify the inputs and outputs for a digital circuit.
 What’s inside the black box are not visible. The black
box shows only the input signal and the output signal
for a digital circuit, but it does not show the actual
logic circuitry for the Boolean function.
 A digital circuit may be described by a Boolean
function, which provides the relationship between
output and input signals.
 The definition of a Boolean function is a dependent  A function may be assigned a value of 0 or 1
variable such as F set (normally an output signal) for each of the possible 2n combinations of the
equal to a Boolean expression such as X + Y, where X binary values for n independent variables.
and Y are independent variables (input signal).
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BASIC LOGIC SYMBOLS

 The gate symbols are needed to draw a logic circuit diagram, a digital circuit, or a schematic for the
Boolean function.

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BASIC LOGIC SYMBOLS

 A truth table is a tabular form for presenting the yes–no, true–false, or 1–0, values of its variables or signals, these
values also called identity elements in Boolean algebra. .
 Note: Number of rows in a truth table = 2Number of input signals or variables.
 The complement (NOT operator) only applies to one variable at a time , while intersection or union applies to
two or more variables.

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BOOLEAN ALGEBRA POSTULATES

 Boolean algebra postulates and theorems

are used to minimize Boolean expressions
so that logic circuits can be constructed
using the fewest number of gates.
 In general, it is better to use fewer logic
gates to minimize complexity, cost, and the
power requirement when designing logic
circuits.

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BOOLEAN ALGEBRA THEOREMS

 Figure 1.6 shows the comparison of the two

different, but equivalent circuits

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PROVING BOOLEAN ALGEBRA THEOREMS

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 DERIVING BOOLEAN FUNCTIONS FROM TRUTH TABLES

 A standard way of expressing a logic function or Boolean function is by a truth table.

 After a truth table is written and filled in,
➢ the Boolean function can be derived in terms of the input signals for the 1s of the function written
ത 𝑌+
as a Boolean expression. For example, the Boolean function XOR (Exclusive OR), 𝐹𝑋𝑂𝑅 = 𝑋.
𝑋. 𝑌ത = 𝑋 ⊕ 𝑌
➢ or a Boolean function can be derived in terms of the input signals for the 0s of the function written
ത 𝑌ത + 𝑋. 𝑌, 𝐹𝑋𝑂𝑅 = 𝑋.
as a Boolean expression. For example, 𝐹𝑋𝑂𝑅 = 𝑋. ത 𝑌ത + 𝑋. 𝑌 = 𝑋 + 𝑌 . 𝑋ത + 𝑌ത
(by Apply DeMorgan’s theorem). When a function has fewer 0s, it may be advantageous to use the
0s to obtain the function rather than using the 1s. A smaller number of variables results in less
complexity.

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DERIVING BOOLEAN FUNCTIONS USING MINTERMS AND MAXTERMS

 Boolean function can be derive from a truth table by obtaining intermediate product terms called minterms.
 The minterms are then ORed together to form the Boolean function.
 Minterms are used to write Boolean functions in a simple and concise form.
 A minterm designator mi is assigned to every row of a truth table where i = 0, 1, 2, . . . , which represents the
decimal values of the inputs.
 In the XOR Boolean function, the minterms are uniquely defined as follows: 𝑚0 = 𝑥.ҧ 𝑦,
ത 𝑚1 = 𝑥.ҧ 𝑦, 𝑚2 = 𝑥. 𝑦ത and
𝑚3 = 𝑥. 𝑦.
 Each minterm expression is defined such that its value evaluates to 1 when the minterm number i in binary is
applied to the expression, because 0s are replaced by a complemented variable. Note: 𝑚1 = 𝑥.ҧ 𝑦 , where 𝑥𝑦 = 01.
 The XOR Boolean function is written as 𝐹𝑋𝑂𝑅 𝑋, 𝑌 = σ 𝑚 1,2 = 𝑚1 + 𝑚2 = 𝑋. ത 𝑌 + 𝑋. 𝑌.
ത which is referred to
as the canonical sum of products (CSOP) form of the function
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DERIVING BOOLEAN FUNCTIONS USING MINTERMS AND MAXTERMS

 Intermediate sum terms called maxterms may also be used to derive a Boolean function.
 A maxterm designator Mi is assigned to every row of a truth table where i = 0, 1, 2, . . . , which represent the
decimal values of the inputs.
 In the XOR function, the maxterms are uniquely defined as follows: 𝑀0 = 𝑥 + 𝑦, 𝑀1 = 𝑥 + 𝑦,
ത 𝑀2 = 𝑥ҧ + 𝑦,
and 𝑀3 = 𝑥ҧ + 𝑦.
ത
 Each maxterm expression is defined such that its value evaluates to 0 when the maxterm number i is
applied to the expression, because 0s are replaced by an uncomplemented variable and 1s are replaced by a
complemented variable. Note: 𝑀1 = 𝑥 + 𝑦ത , where 𝑥𝑦 = 01.
 The XOR Boolean function is written as 𝐹𝑋𝑂𝑅 𝑋, 𝑌 = ς 𝑀 0,3 = 𝑀0 . 𝑀3 = 𝑋 + 𝑌 . (𝑋ത + 𝑌) ത which is
referred to as the canonical product of sums (CPOS) form of the function.
 It is interesting to observe that minterms and maxterms for the same variables are complements of each
other—that is, one can be obtained from the other by complementation.

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VHDL DESIGN INITIAL REMARKS

 A VHDL design consists of the three parts:

➢ library part : It is the lines in the VHDL design that begin with library and use. It is required to
include the library part in all VHDL designs.
➢ entity declaration : It is the lines in the VHDL design that begin with entity and end with end
entity_name.The VHDL entity declaration represents the black box for the digital circuit.
➢ architecture declaration : It is the lines in the VHDL design that begin with architecture and end
with end architecture_name.The VHDL architecture declaration represents the actual logic circuit.
 The syntax (the rules for writing a VHDL design) must be followed explicitly for the design to compile
correctly.
 The words for example; library, use, entity, is, port, in, out, and end are called keywords. Keywords are
reserved words that cannot be used for signal names or labels.
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VHDL DESIGN FOR A NOT FUNCTION

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VHDL DESIGN REMARKS

 In the entity declaration, the external signal X is declared as an input via the keyword in, and the external signal F1 is
declared as an output via the keyword out. Both signals X and F1 are declared as data type std_logic.
 In the architecture declaration, the Boolean expression not X is assigned to the signal F1 via the signal assignment
symbol (<=); that is, F1 <= not X. The Boolean function F1 <= not X is placed in the architecture declaration between
begin and end Boolean_function.
 Signal names (such as X and F1) and labels (such as not_1 and Boolean_function) have the following rules:
(a) the first character must be a letter,
(b) numbers may be included as well as the underscore character ( _ ),
(c) no adjacent underscore characters may be used,
(d) an underscore character may not be used as the last character,
(e) spaces are not allowed. Signal names and labels are formally called identifiers.

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VHDL DESIGN REMARKS

 The label not_1 provides a meaningful description of the VHDL design. It is used as the label for the
entity declaration.
 The keyword “not” cannot be used for a label, because not is a keyword that represents the NOT
operator in VHDL.
 Label not_1 must be used in the architecture declaration because it is the label that is used in entity
declaration.
 VHDL is not case sensitive, which means that upper- or lowercase letters can be used for keywords,
names and labels.
VHDL also has a free format, which means that there is no formatting convention for spacing
andindentations

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WAVEFORM DIAGRAMS FOR THE VHDL DESIGN FOR THE NOT FUNCTION

 Running a simulation for a VHDL design results in waveform diagrams that allows the designer to verify the
correct functionality of a design.
 Observe that F1 is 1 when X is 0, and F1 is 0 when X is 1. This shows that the output waveform for F1 is
the complement of the input waveform for X.
 The Waveform shows that the VHDL design in fact, provide a correct design for the Boolean function 𝐹1 =
ത The values 0 and 1 that are listed in the second column of Waveform are the values of X and F1,
𝑋.
respectively, at the beginning of the simulation

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VHDL DESIGN FOR AN AND FUNCTION

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WAVEFORM DIAGRAMS FOR THE VHDL DESIGN FOR THE AND FUNCTION

 The waveform diagram shows the actual simulation of the VHDL design.
 Observe that F2 is only 1 when both X and Y are 1, and F2 is 0 for all other conditions of X and Y. This
shows that the output waveform for F2 is the ANDing of the input waveforms for X and Y.
 The waveform shows that the VHDL design does, in fact, provide a correct design for the Boolean function
F2 = X.Y.
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VHDL DESIGN FOR AN OR FUNCTION

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WAVEFORM DIAGRAMS FOR THE VHDL DESIGN FOR THE OR FUNCTION

 The waveform diagram shows the actual simulation of the VHDL design.
 Observe that F3 is 1 any time X is 1 or Y is 1, and F3 is 0 when both X and Y are 0.
 This shows that the output waveform for F3 is the ORing of the input waveforms for X and Y.
 The waveform shows that the VHDL design provides a correct design for the Boolean function F3 = X + Y.

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VHDL DESIGN FOR AN XOR FUNCTION

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VHDL DESIGN REMARKS

 A comment may be placed in VHDL code by using two hyphens in series, that is, “--”. The Boolean
function Fxor <= (not X and Y) or (X and not Y) following the comment symbol can be used in place
of the Boolean function Fxor <= X xor Y.
 The AND and OR binary operators have the same precedence in VHDL. This means that parentheses
must be used to select the order of precedence of the binary operators in VHDL. No parentheses are
required around the NOT operator, because it has a higher priority than any of the binary operators
in VHDL.
 The XOR function is an odd function, which has a value of 1 when the combination of all the inputs
has an odd number of 1s (1, 3, 5, . . .).

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WAVEFORM DIAGRAMS FOR THE VHDL DESIGN FOR THE XOR FUNCTION

 The waveform diagram shows the actual simulation of the VHDL design.
 Observe that FXOR is 1 any time X has the opposite value of Y, and FXOR is 0 when X has the same value of Y.
 This shows that the output waveform for FXOR is the XORing of the input waveforms for X and Y.
 The waveform shows that the VHDL design provides a correct design for the Boolean function FXOR=X⊕Y

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VHDL DESIGN FOR A NAND FUNCTION

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VHDL DESIGN REMARKS

 Note that a NAND gate can have two or more inputs.

 For three input signals, 𝑋. 𝑌. 𝑍 = 𝑋ത + 𝑌
ത + 𝑍ҧ by DeMorgan’s Theorem and is equivalent to NOT X
OR NOT Y OR NOT Z in VHDL.
 For three input signals, 𝑋. 𝑌. 𝑍 is not equivalent to X NAND Y NAND Z.
 The expression X NAND Y NAND Z is an illegal expression in VHDL.
 In VHDL, NOT (X AND Y AND Z) is equivalent to the expression 𝑋. 𝑌. 𝑍.

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WAVEFORM DIAGRAMS FOR THE VHDL DESIGN FOR THE NAND FUNCTION

 The waveform diagram shows the actual simulation of the VHDL design.
 Observe that FNAND is 0 when both X and Y are 1, and FNAND is 1 for all other conditions of X and Y.
 This shows that the output waveform for FNAND is the NANDing of the input waveforms for X and Y.
 The waveform shows that the VHDL design provides a correct design for the Boolean function FNAND =
𝑋. 𝑌.

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VHDL DESIGN FOR A NOR FUNCTION

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VHDL DESIGN REMARKS

 Note that a NOR gate can have two or more inputs.

ത 𝑌.
 For three input signals, 𝑋 + 𝑌 + 𝑍 = 𝑋. ത 𝑍ҧ by DeMorgan’s Theorem and is equivalent to NOT X
AND NOT Y AND NOT Z in VHDL.
 For three input signals, 𝑋 + 𝑌 + 𝑍 is not equivalent to X NOR Y NOR Z.
 The expression X NOR Y NOR Z is an illegal expression in VHDL.
 In VHDL, NOT (X OR Y OR Z) is equivalent to the expression 𝑋 + 𝑌 + 𝑍.

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WAVEFORM DIAGRAMS FOR THE VHDL DESIGN FOR THE NOR FUNCTION

 The waveform diagram shows the actual simulation of the VHDL design.
 Observe that FNOR is 1 when both X and Y are 0, and FNOR is 0 for all other conditions of X and Y.
 This shows that the output waveform for FNOR is the NORing of the input waveforms for X and Y.
 The waveform shows that the VHDL design provides a correct design for the Boolean function FNOR =
𝑋 + 𝑌.

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VHDL DESIGN FOR AN XNOR FUNCTION

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VHDL DESIGN REMARKS

 The XNOR function with two inputs is often referred to as a comparator because the XNOR
function is a 1 when both input signals are the same value and is a 0 when they are different values.
 Note that a XNOR gate can have two or more inputs.
 For three input signals, 𝐴 ⊕ 𝐵 ⊕ 𝐶 is not equivalent to A XNOR B XNOR C.
 The expression A XNOR B XNOR C is an illegal expression in VHDL.
 In VHDL, NOT (A XOR B XOR C) is equivalent to the expression 𝐴 ⊕ 𝐵 ⊕ 𝐶 .
 The XNOR function is an even function, which has a value of 1 when the combination of all the inputs
has an even number of 1s (0, 2, 4, . . .). Observe that 0 represents an even number of 1—that is, no 1s.

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WAVEFORM DIAGRAMS FOR THE VHDL DESIGN FOR THE XNOR FUNCTION

 The waveform diagram shows the actual simulation of the VHDL design.
 Observe that FXNOR is 1 when both X and Y are 0 or when both X and Y are 1—that is, both inputs are the same
value—and FXNOR is 0 for all other conditions of X and Y—that is, when the inputs are different values.
 This shows that the output waveform for FXNOR is the XNORing of the input waveforms for X and Y.
 The waveform shows that the VHDL design provides a correct design for the Boolean function FXNOR = 𝑋 ⊕ 𝑌.

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VHDL DESIGN FOR A BUFFER FUNCTION

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VHDL DESIGN REMARKS

 A BUFFER can be used in a design for the purpose of amplification so that the output can drive a
larger number of gates.
 A BUFFER can also be used in a design for the purpose of documentation so that different signal
names can be used on the input and output of the BUFFER.

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WAVEFORM DIAGRAMS FOR THE VHDL DESIGN FOR BUFFER FUNCTION

 The waveform diagram shows the actual simulation of the VHDL design.
 Observe that FBUF is 0 when X is 0, and FBUF is 1 when X is 1.
 This shows that the output waveform for FBUF is the BUFFERing of the input waveform for X.
 The waveform shows that the VHDL design provides a correct design for the Boolean function FBUF = X.

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VHDL DESIGN FOR ANY BOOLEAN FUNCTION WRITTEN IN CANONICAL
FORM

A VHDL design can be obtained for any Boolean function written in canonical form.
 First, obtain a truth table for the function or a compact minterm or maxterm form of the function.
 Next, write the function in a canonical form—that is, either in a canonical SOP (CSOP) form or a
canonical POS (CPOS) form.
 Then, write the assignment statement for the Boolean function in VHDL.
 When writing an assignment statement for a function in VHDL, use the fewest number of 1s or 0s in
the truth table for the function. The function written with the fewest number of 1s or 0s has fewer
minterms and is easier to type. If the function has the same number of 1s and 0s, then choose the 1s,
for less typing.

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VHDL DESIGN FOR ANY BOOLEAN FUNCTION WRITTEN IN CANONICAL
FORM

Truth Table for a Two-1s

function F

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VHDL DESIGN REMARKS

 An assignment statement in VHDL for the function F can be written in many different ways.
 First, a compact minterm forms for the function using its 1s is written as: F(A,B,C) = ∑m(3, 5, 6)
 Then the canonical SOP (CSOP) form is written as: F(A,B,C) = 𝐴.ҧ 𝐵. 𝐶 + 𝐴. 𝐵.
ത 𝐶 + 𝐴. 𝐵. 𝐶ҧ
 The assignment statement for the 1s of the function F can now be written in CSOP form as:
F <= (not A and B and C) or (A and not B and C) or (A and B and not C)
 Another way to write an assignment statement for the function F is to write a compact minterm form for the function
ത
using its 0s as: 𝐹(A,B,C) = ∑ m(0,1,2,4,7)
 The canonical SOP (CSOP) form is written as: 𝐹ത 𝐴, 𝐵, 𝐶 = 𝐴.ҧ 𝐵.
ത 𝐶ҧ + 𝐴.ҧ 𝐵.
ത 𝐶 + 𝐴.ҧ 𝐵. 𝐶ҧ + A. 𝐵.
ത 𝐶ҧ + 𝐴. 𝐵.C
 The assignment statement for the 0s of the function F can now be written in CSOP form as: F <= not ((not A and not B
and not C) or (not A and not B and C) or (not A and B and not C) or (A and not B and not C) or (A and B and C))
 The purpose of including both function F_1s and function F_0s is to verify that both functions generate the same output
when we run a simulation. So, F = F_1s =F_0s should be true.
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WAVEFORM DIAGRAMS FOR THE VHDL DESIGN FOR TWO-1S FUNCTION

 The waveform diagram shows the actual simulation of the VHDL design.
 Observe that both function F_1s and function F_0s in Waveform provide the same output as function F in
the Table.
 This shows that the VHDL design does, in fact, provide a correct design for Boolean function F—that is, F =
F_1s or F = F_0s can be used to generate the function F.
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EQUIVALENT GATE SYMBOLS

 Logic gate symbols can be

represented by different equivalent
gate symbols called DeMorgan
equivalent gate symbols.

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FUNCTIONALLY COMPLETE GATES

 Using the three gates NOT, AND, and

OR, we can design any logic circuit.
The NAND gate is referred to as a
functionally complete gate, because a
set of just NAND gates can be used
to design any logic circuit.
 The Figure shows NAND gate
equivalent circuits for the NOT, AND,
and OR gates.
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FUNCTIONALLY COMPLETE GATES

 The NOR gate is also a functionally

complete gate, because a set of just
NOR gates can be used to design any
logic circuit.
 The Figure shows NOR gate
equivalent circuits for the NOT, AND,
and OR gates.
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EQUIVALENT GATE CIRCUITS

 Logic gates that use bubbles at

their inputs or outputs can be
drawn in different but equivalent
ways.
 The Figure shows a summary of
several logic gates and their
equivalent gate circuits.

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COMPACT DESCRIPTION
NAMES FOR GATES

 Figure 1.18 shows a summary of several logic

symbols and their associated compact description
names.
 The notation AND2B1 for example stands for a 2
input AND gate with one bubble input.
 Bubbled inputs are used to make a circuit diagram
simpler to draw.
 The bubble represents a complemented input or
output, depending on where the bubble is placed.
 A gate with a bubble input (or output) may be
referred to as an active low input (or active low
output). A gate that does not contain a bubble input
(or output) may be referred to as an active high
input (or active high output).

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