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Setting standards in VLSI Design

Final Test
Time: 3 Hrs. Total Marks: 100
Part – A
Marks: 15
Digital (15 Marks)
1. Use minimum no. of 4-bit ring counters, 5-bit Johnson counters & mod 8 counters to
generate clocks with frequencies of 1Mhz, 2Mhz & 10Mhz from a source clock with a
frequency of 320Mhz. 8M

2. Draw a Moore model FSM for a sequential circuit whose output will be toggled with the
occurrence of ‘11’ sequence in an overlapping manner. 7M

PART – B

Verilog (15 Marks) Marks: 15

1. Find the hardware inferred by the following code. 4M

module test(input [3:0]a,

input [3:0]b,
input clk, rst_n,
output reg [4:0] sum);

always @(posedge clk)

begin
if(!rst_n)
sum <= 5'b0;
else
sum <= a+b;
end

endmodule

2. Write an RTL code to design a sequence detector in MOORE non-overlapping

manner to detect 1010 with MSB first. 7M

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Setting standards in VLSI Design

3. Predict the output of the following Verilog program 4M

module test();
integer a = 0;
initial
begin
#2 a = #2 2;
a <= #3 3;
#2 a = 4;
#2 a <= 5;
#2 a = #2 6;
a = #2 7;
a <= #2 8;
#2 a <= #2 9;
#3 a = 10;
end
initial
$monitor ("at time t = %0t, a = %0d", $time, a);
endmodule

PART – C

Physical Design Marks : 60

1. Calculate Va , Vb, Vc and Vo for given the circuit using the Pass transistor logic. 4M
(Vt =0.8)

2. Consider the AND gate shown below: 6M

The delay and the output slew of different arcs are shown below:

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Setting standards in VLSI Design

The arrival time at different input pins are as follows:

a. What will be the arrival time and the output slew at the pin Z when Graph Based
Analysis (GBA) is performed for the setup check or late-mode check?
b. What will be the arrival time and the output slew at the pin Z when Path Based
Analysis (PBA) is performed for the setup check or late-mode check through the arc
B→Z?

3. Consider the following synchronous circuit. 6M

The following attributes are valid for the flip-flops FF1 and FF2: setup time=45
ps, hold time=10 ps, and CLK-to-Q delay=20 ps. The delay of each inverter is
50 ps. Ignore the wire delay.
Assume that the period of the clock is 1000 ps.
a. What is the setup slack at the timing end-point FF2/D?
b. What is the hold slack at the timing end-point FF2/D?

4. What is floor planning? Explain the different parameters w.r.t floor planning 4M

5. What is partitioning? What are the goals of floor planning? 4M

6. What are Macros? Explain the different types of Macros. 4M

7. What are the Sanity checks need to be done before and After CTS? 4M
8. What do you mean by logical mapping during logical synthesis? What kind of
violations (Setup/Hold) are solved during Synthesis? And Why 3M

9. What is SDC? Explain the following SDC command with an example. 5M

(i) Set_input_delay
(ii) Set_output_delay
(iii) Set_max_delay
(iv) Set_max_transition

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Setting standards in VLSI Design

10. What is slew, skew,latency,jitter and uncertainity? Mention how you are going to set
these values in the SDC file. 5M
11. What is signoff? Explain the signoff steps 5M
12. What is DMM? Explain the significance of DMM in Fusion Compiler tool 5M
13. Explain the Synthesis flow and What will be the synthesis result of the following
piece of Verilog code: 5M

Part – D (Basic Electronics, Networks and Aptitude) Marks: 10

1. For the following specifications, check the circuit for any violations & fix them if any. 4M

2. Calculate the output voltage for this circuit when V1 = 2.5 V and V2 = 2.25 V.
4M

3. A can lay railway track between two given stations in 16 days and B can do the same job in
12 days. With help of C, they did the job in 4 days only. Then, C alone can do the job in:2M

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