Professional Documents
Culture Documents
Prof. Ming C. Wu
wu@eecs.berkeley.edu
511 Sutardja Dai Hall (SDH)
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Example of Non-Ideal Bias
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VG = VGS + RS I D
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Practical Implementations
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Bias Design Example
Goal: design bias for ID = 0.5 mA. General rule of thumb:
MOS has Vt = 1V and kn = 1 mA/V2 Equal (1/3 each) voltage drop across
RD , RS , and VDS
15V −10V
Choose RD = = 10 kΩ
0.5 mA
5V − 0V
Choose RS = = 10 kΩ
0.5 mA
Determine VGS :
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0.5 mA = kn (VGS −1)2 ⇒ VGS = 2V
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VG = VGS + 5V = 7V
We can choose any combination of voltage
divider, RG1 and RG1, that gives VG = 7V.
Remember RG1 || RG1 becomes Rin
So use large RG1 and RG1, in the MΩ range.
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vBE
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Good (Stable) Bias Circuits for BJT
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