Analog Circuits (18EC42) - Module 1

Ravi Shankara.M.N. Asso. Professor ECE Dept SCE Bangalore ravi_shankar_mn@yahoo.co.
in
Module 1(a) : BJT Biasing: Biasing in BJT amplifier circuits:

Transistor Biasing:
Transistor biasing means applying suitable external dc voltages to transistor terminals to establish a constant dc
current in the collector of the transistor so that this current is calculable, predictable and insensitive to variation
in temperature and other transistor parameters.
Transistor biasing is required to maintain the operating point in the middle of the active region so that
maximum output signal swing can take place and Q point will not shift into saturation or cut-off region.
2.2.1 - Require ments of Biasing Circuits
(1) E - B junction should be forward biased and C – B junction should be reverse biased i,e the transistor should
be operated in the active region. (2) The circuit should provide temperature stability. (3) The operating point
should be made independent of transistor parameters , β and .
There are mainly three types of biasing circuits – Fixed bias or Base bias circuit, Collector to Base bias circuit
and Voltage Divider Bias (VDB) circuit.
The Classical Discrete Circuit Bias or Voltage Divide r Bias (VDB) Circuit
Introduction: Voltage divider bias is also known as Emitter current bias which gives the most stable operating
point when compared to base bias and collector to base bias schemes. In this scheme, the levels of I C and VCE
are almost independent of β of the transistor.
In this scheme, a single power supply and a voltage divider network consisting of two resistors R1 and R2 are
used for supplying a fraction of the supply voltage VCC. The additional resistor RE provides the stability
Figure shows a VDB circuit. In this method, the base current IB is considered. The power supply VCC, the
voltage divider network (R1 – R2 ) are replaced with a Thevenin’s equivalent circuit consisting of a voltage
source VT H in series with a resistance RB between VCC and ground.
This is a supporting material for the SCE students. Any use for commercial purpose has to be permitted by the author ©Ravi Shankara.M.N. Page 1
Ravi Shankara.M.N. Asso. Professor ECE Dept SCE Bangalore ravi_shankar_mn@yahoo.co.in
V CC R 2 R1R2
VBB = and RB = R 1 ||R 2 =
R 1 +R 2 R 1 +R 2
The modified circuit is shown with voltage source VBB and base resistor RB.
Applying KVL to the base circuit

IE
VBB − R B IB − VBE − IE R E = 0 or VBB − R B − VBE − IE R E = 0
β+1
VBB − VBE IE VBB − VBE

Emitter Current IE = and Base current IB = =
R β+ 1 R B + (1 + β)R E
R E + β +B1
Applying KVL to collector –emitter loop,
VCC – IC RC – VCE – IERE = 0 since IE  IC , the equation modifies into
VCC – IC RC – VCE – IC RE = 0
V CC −V CE
Solving for VCE , VCE = VCC – IC(RC + RE) = 0 or IC = R C +R E
Observations
RB
To make IE insensitive to temperature and  variation, choose (i) VBB >> VBE and (ii) R E ≫ β+1
If VBB is higher, then the sum (ICRC + VCB ) becomes lowered. On the other- hand if VBB is kept small value,
then, IC RC and V CB will be large results in high voltage gain. General thumb rule is that the voltages are
selected as V BB = VCE = IC RC = (1/3) VCC for most of the requirements.
 To make IE insensitive to temperature and  variation can be achieved by choosing RB small and can be
achieved by using low values of R1 and R2 . This causes higher current drain from the supply and results in low
input resistance of the amplifier. The second condition implies that the base current I B is very small compared
to the voltage divider current (I). The voltage divider current is the range I E > I > 0.1IE.
 The resistor RE provides the stability the current IE by negative feedback action shown below.
Proble m: Design a voltage divider bias circuit to establish a current I E = 1mA using a powe r supply
VCC = 12V. The transistor is specified to have a normal  value of 100.
V CC 12
Solution: Choose VBB = IC R C = VCB = = =4V
3 3
VE 3.3V
VE = VBB – V BE = 4 – 0.7 = 3.3 V and R E = = = 3.3 k
IE 1mA
Let the voltage divider current I = 0.1 IE = 0.1 mA and since IB << I,
VCC 12V
(R 1 + R 2 ) = = = 120 k
I 0.1mA
VCC R 2 12R 2
and VBB = 4V = =
R1 + R2 R1 + R2
Solving R1 = 80 k and R2 = 40 k
VCC − VC VCC − (VCE + VE ) 12 − 7.3

RC = = = = 3.7 k
IC IE 1mA
Proble m : A Voltage divider bias circuit using Silicon transistor has R C =1.5 k , R E =1 k , R1 = 47 k ,
R 2 = 15 k & VCC = 15V. Determine the values of VE, VCE and VC .
Solution: Note: Given: β not given; use approximate analysis (IB is very small and IC  IE)
Given VCC = 15V, R1 = 47 k, R2 = 15 k, RC = 1.5 k, RE = 1 k

V CC R 2 15 ×15k 
VBB = I2 R2 = = = 3.629 V
R 1 +R 2 (47+15)k
KVL to base – emitter loop; (VB – VBE – VE) = 0
VE = VBB –V BE = 3.629 – 0.7 = 2.929 Volts

V 2.929
IE = RE = 1000
= 2.929 mA and I C  IE = 2.929 mA
E
We have VCC − IC R C − VCE − VE = 0
VCE = VCC − IC R C − VE = 15 − 2.929 × 1.5 − 2.929 = 7.68 V
VC = VCE + VE = 7.68 + 2.929 = 10.6 Volts.
Proble m 8:Draw the dc load line for the VDB circuit shown, also determine the collector current and Q
point.
Solution: Given: V CC = 30V, R1 = 6.8 k, R2 = 1 k, RC = 3 k, RE = 750 & β =100
R 1R 2 6.8 k ×1k
R B = R 1 ||R 2 = = = 871.79
R 1 +R 2 6.8k +1k 
V CC R 2 30 ×1k
VBB = VB = I2 R2 = = = 3.846 V
R 1 +R 2 (6.8+1)k
VB − VBE 3.846 − 0.7

IB = = = 41μA
(1 + β)R E + R B 1 + 100 750 + 871.79
IC = β IB = 100(41 µ) = 4.1 mA
IE = IC + IB = 4.14 mA
KVL equation to collector loop as VCC –I C RC –VCE – IERE = 0
VCE = VCC – IC RC – IERE
VCE = 30 – 4.110-3 (3k) + 4.14 10-3 (750) = 14.595V
DC Load line: KVL equation to collector loop yeilds
VCC –IC (RC + RE) –VCE = 0
(i) When IC = 0  V CE = VCC = 30 Volts (end point on X axis)

V CC 30
(ii) When VCE = 0  IC = = = 8 mA (end point on Y axis)
R C +R E 3k +750
Proble m 9: Design a VDB circuit using Silicon transistor with the following specifications: V CC = 12 V,
V E = 5 V VCE = 3 V and IC = 1 mA.
I 1 mA
Solution:  is not given , use approximate analysis and assume I2 = 10C = = 100µA
10
VE VE 5V
VE = IE RE  R E = = = = 5 k ( since IE  IC )
IE IC 1mA
VB = VBE + VE = 0.7 + 5 = 5.7 V

VB 5.7V
and VB = I2 R2  R 2 = = = 57 k
I2 100µA
Applying KVL to VCC – R1 – R2 – ground path,
 VCC – I1 R1 – I2 R2 = 0
V CC −V B 12−5.7
but I1  I2 and I2 R2 = VB  R1 = = = 63 k
I2 100µ
Applying KVL to collector - emitter loop,
 VCC – IC RC – VCE – IERE = 0 since IE  IC ,

Or VCC – ICRC – VCE – VE = 0
V CC −V CE −V E 12−3−5
 RC = = = 4 k
IC 1 mA
Biasing Using a Collector –to – Base Feedback Resistor
In Collector to Base bias, the biasing resistor RB is connected between Collector and Base terminals of the
transistor. The transistor is operated in common emitter configuration. The resistor RC carries a current of (IC +
IB) while RB carries a current of IB only.
DC analysis : Applying KVL to the Collector – base loop,
VCC – (I C +IB) RC –IBRB –VBE = 0
VCC – (β IB +IB ) RC – IB RB –V BE = 0
VCC − VBE
Base Current IB =
1 + β RC + RB
VCC − VBE
Emitter Current IE = 1 + β IB =
RB
RC +
1+ β
Also applying KVL to collector to emitter via RB
V CE −V BE
–IBRB – VBE + VCE = 0 or IB = RB
Applying KVL to Collector – Emitter loop
VCC – (I C + IB) RC –VCE = 0  VCE = VCC – (IC + IB) RC --------------- (A)

V CC −V CE V CC −V CE V CE −V BE V CC −V CE
(IC + IB ) = IE =  IC = (IE − IB ) = − or RC =
RC RC RB IE
IE R B
Also VCB = IB R B =
1 +β
Stability:
RB
To make IE insensitive to  variation, choose R C ≫ β+1
The resistor RB provides the stability the current IE by negative feedback action shown below
Consider the equation (2); When IC increases, IC RC drop increases, resulting in decrease of VCE. To keep the
current constant, now IB also decreases, which in-turn decreases the collector current IC as I C = βIB
Similarly when IC decreases, I B increases, which again maintains the level of IC constant. Hence any change in
the value of IC is countered by change in IB in opposite direction which results in the stability of the bias point.
Design the CB bias circuit to obtain a dc e mitter current of 1 mA and to ensure a + 2V signal swing at the
collector; that is design for VCE = 2.3 V. Let VCC = 10V and  =100.
V CC −V CE 10−2.3
Solution: V CC – IERC – VCE = 0 or RC = = = 7.7 k
IE 1 mA
V CE −V BE V CE −V BE 2.3−0.7
–IBRB – VBE + VCE = 0 or RB = = 1+  = 101 = 161.6 k
IB IE 1mA
Proble m: Determine the Q point for the biasing circuit shown below
Solution:
VCC − VBE 12 − 0.7
Base Current IB = = = 10.18μA
1 + β RC + RB 1 + 100 10 + 100
IC = IB = 100(10.18A) = 1.018 mA
VCE = VCC – (IC + IB ) RC = 12 – (1.01810–3 + 10.1810–6 ) (10103 ) =1.7182 V
Q point = (V CE, IC) = (1.7182V, 1.018mA)
Module 1(b) : Small Signal Operation and BJT Models

The Collector Current iC and Transconductance gm :
Figure shows the transistor amplifier with the applied signal vbe.
The instantaneous base to emitter voltage is given by
vBE = VBE + vbe
The corresponding collector current is given by
V BE + v be V BE v be V be
iC = IS ev BE /VT = IS e VT = IS e VT e VT = IC e VT
If Vbe << VT then iC can be approximated as
V be V be
iC  IC 1 + = IC + IC − − − − − − − (𝑎)
VT VT
Equation (a) is an approximation for v be < 10 mV and is known as small signal

approximation. The collector current has dc bias current I C as well signal
component ic .
IC
The signal component collector current ic = V = g m Vbe
VT be
IC
Where gm is called transconductance and defined as g m = VT
The transconductance of the BJT is directly proportional to the collector bias current IC. The transconductance
gm of an amplifier is equal to the slope of the iC –vBE characteristic curve at iC = IC (i.e., at the bias point Q).
𝜕𝑖 𝐶
𝑔𝑚 =
𝜕𝑣𝐵𝐸 𝑖 𝐶 =𝐼𝐶
The analysis above suggests that for small signals (vbe << VT ), the transistor behaves as a voltage-controlled
current source. The input port of this controlled source is between base and emitter, and the output port is
between collector and emitter. The transconductance of the controlled source is gm, and the output resistance is
infinite.
The Base Current iB and Input Resistance r
iC I + ic I 1 IC vbe
Total base current iB = = C = C+ = IB + ib
β β β β VT
I C v be
ib = represents the signal component of base current.
βV T
IC g m v be
Using g m = gives ib =
VT β
The small signal input resistance between base and emitter looking into the base is represented by r 
vbe v β β VT
rπ = = g be = = =
ib m vbe gm IC IB
β VT
The input base resistance r is dependent on  and inversely proportional to IC.
The Emitter Curre nt and the Input Resistance re

iC IC i
Under signal operation, iE = = + αc = IE + ie
α α
ic 1 I C v be IC v be v be
The small signal current ie = =α = = IE
α VT α VT VT
Looking into the emitter, the small signal resistance between base and emitter is r e can be defined as
vbe vbe V VT  0.998 1

re = = = T = = = =
ie IE vbe IE IC gm gm gm
VT
Relationship between re and r
ie (β+1)i b
vbe = ibr = ie re or rπ = re = re = [β + 1]re
ib ib
Voltage Gain
The transistor senses the base-emitter signal vbe and causes proportional current gmvbe to flow in the high
impedance collector circuit acting as a voltage controlled current source. The output voltage is taken across R C
The total collector voltage vC = VCC − iC R C = VCC − (IC + ic )R C = [VCC − IC R C ]− ic R C = VC − ic RC
The quantity VC is the dc bias voltage and can be ignored under signal operation
vC = − ic RC = −g m vbe R C = (−g m R C )vbe

vc
Voltage gain of the amplifier Av = = −g m R C
vbe
I
Since gm is directly proportional to the stable collector bias current and hence is constant. And using g m = VC
T
IC R C
Av = −g m R C = −
VT
Proble m: Calculate the value of gm for a BJT biased at IC = 0.5mA.
Solution: Assuming VT = 0.025 V ---------------------------------------- ( since vbe < VT )
IC 0.5 × 10−3
gm = = = 20 mA/V
VT 0.025
Proble m: A BJT amplifie r is biased to ope rate at a constant collector current 0.5mA irrespective of the
value  . If the transistor manufacturer specifies to  range from 50 to 200, give the expected range of g m ,
IB and r .
IC 0.5 × 10−3
gm = = = 20 mA/V
VT 0.025
IC 0.5×10 −3 IC 0.5×10 −3
For  = 200; IB = = = 2.5 μA and For  = 50; IB = = = 10 μA
 200  50
VT 25 ×10 −3 VT 25×10 −3
For  = 200; rπ = = = 10 k and For  = 50 rπ = = = 2.5 k
IB 2.5×10 −6 IB 10×10 −6
Proble m: A BJT having β = 100 is biased at a dc collector current of 1 mA. Find the value of gm , re , and
rπ at the bias point.
IC 1 × 10−3
gm = = = 40 mA/V
VT 0.025
IC 1×10 −3
For  = 100; IB = = = 10 μA
 100
VT 25×10 −3 r 2500
rπ = IB
= 10×10 −6
= 2.5 k and π
re = +1 = 100 +1 = 25 
Proble m: For the circuit shown below, VBE is adjusted to yield a dc collector current of 1 mA.
Let VCC = 15 V, RC = 10 kΩ, and β = 100. Find the voltage gain (vce /vbe ). If vbe = 0.005 sinωt volt, find
vC (t) and iB (t).
Solution:
IC 1 × 10−3
gm = = = 40 mA/V
VT 0.025
AV = −g m R C = − 40 mA 10k = −400
vce = AV vbe = −400 0.005sinωt = −2sinωt
vC (t) = VC − vce = [VCC − IC R C ] − vce
vC t = 15 − 1 × 10−3 10 × 103 − −2sinωt = 5 + 2sinωt
iC t = IC + ic = IC + g m vbe = 1 × 10−3 + 40 × 10−3 0.005sinωt
iC t = 1 + 0.2sinωt mA
iC t (1 + 0.2sinωt) × 10−3
iB t = = = 10 + 2sinωt μA
β 100
Separating the Signal and the DC Quantities

The analysis above indicates that every current and voltage in the amplifier circuit is composed of two
components: a dc component and a signal component. For instance, vBE = VBE + vbe, iC = IC + ic, and so on. The
dc components are determined from the dc circuit shown below. On the other hand, a representation of the
signal operation of the BJT can be obtained by eliminating the dc sources, as shown in below.
The Hybrid  Model: :
It has been found that in the small signal analysis model of transistor amplifier, every current and voltage is
composed of two components: a dc component and a signal component. (vbe = vBE + VBE). The biasing circuit
gives the dc components and by eliminating the DC sources and dc components,, signal operation of BJT can
be obtained as shown in the circuit below. BJT can be modeled as a voltage controlled current source with the
input resistance r looking into the base.
𝑣𝑏𝑒
The collector current is given by 𝑖 𝑐 = 𝑔𝑚 𝑣𝑏𝑒 and 𝑖𝑏 = 𝑟𝜋
At the emitter node,

𝑣𝑏𝑒 𝑣𝑏𝑒 𝑣 𝑣𝑏𝑒 𝑣
𝑖 𝑒 = 𝑖 𝑏 + 𝑖𝑐 = 𝑔𝑚 𝑣𝑏𝑒 + = 1 + 𝑔𝑚 𝑟𝜋 = 𝑏𝑒 1 + 𝛽 = = 𝑏𝑒
𝑟𝜋 𝑟𝜋 𝑟𝜋 𝑟𝜋 𝑟𝑒
1 +𝛽
The another way of modeling the BJT as a current controlled current source (gmvbe) interms of base current ib
𝑔𝑚 𝑣𝑏𝑒 = 𝑔𝑚 [𝑖𝑏 𝑟𝜋 ] = 𝑔𝑚 𝑟𝜋 [𝑖𝑏 = 𝛽𝑖 𝑏
The above models are known Hybrid  models of BJT amplifier.
Review Questions:
1. Derive the expression for the transconductance gm of BJT amplifier.
2. Define the input resistance r and emitter resistance re and derive the relation between them.
3. Derive the expression for voltage gain of the BJT amplifier
4. Draw and explain the various hybrid  models of BJT with necessary equations.
Module 1(c) – MOSFETs : Biasing in MOS Amplifier Circuits

Biasing is needed to establish an appropriate dc operating point for the transistor. Biasing provides a stable and
predictable dc drain current ID by dc drain-to-source voltage VDS which ensures the operation of the MOSFET
in the saturation region for all expected input-signal levels.
Biasing by Fixing VGS
The simplest approach for biasing a MOSFET is to fix its gate-to-source voltage VGS to the value required to
provide the desired ID. This voltage value can be derived from the power-supply voltage VDD through the use of
an appropriate voltage divider. But this is not a good approach to biasing a MOSFET and the reason for the
same is explained below.
The drain current ID can be expressed as
1 W
ID = μ C (V − Vt )2
2 n ox L GS
W
The threshold voltage Vt , the oxide-capacitance Cox , and the transistor aspect ratio vary widely among
L
devices of supposedly the same size and type. This results change in ID if device gets replaced. Furthermore,
both Vt and μ n depend on temperature. Hence if the value of V GS is fixed, the drain current ID becomes very
much temperature dependent.
Biasing by Fixing VG and Connecting a Resistance in the Source
An excellent biasing technique for discrete MOSFET circuits consists of fixing the dc voltage at the gate, VG,
and connecting a resistance in the source lead, as shown in Figure.
For the circuit shown; V G = V GS + ID RS
If VG >> VGS, then ID will be mostly determined by the values of VG and RS. However, even if VG is not much
larger than V GS, resistor RS provides negative feedback, which acts to stabilize the value of the bias current ID.
Consider due to some reason, ID increases , since VG is constant, VGS will have to decrease. This in turn results
in a decrease in ID, and hence ID level is held constant. Thus the action of RS works to keep ID as constant as
possible. This negative feedback action of RS gives it the name degeneration resistance.
(a) Voltage divider bias : Figure shows one of the methods of biasing by fixing VG using a single power-
supply VDD and which derives VG through a voltage divider (RG1 , RG2 ). Since I G = 0, RG1 and RG2 can be
selected to be very large (in the Meg-ohm range, so that the circuit can give high input impedance).
Here capacitor CC1 acts a s a coupling capacitor by blocking the dc and coupling the signal vsig to the amplifier
input without disturbing the MOSFET dc bias
point. The value of CC1 should be selected large
enough to approximate a short circuit at all
signal frequencies of interest.
The resistor RD is selected to be as large as
possible to obtain high gain but small enough to
allow for the desired signal swing at the drain
while keeping the MOSFET in saturation at all
times.
V R
Since IG = 0; VG = R DD+RG 2
G1 G2
VS V G −V GS
Applying KVL to Gate – source loop, V G – VGS – ID RS = 0 or R S = =
ID ID
V DD −V D
KVL to Drain to source loop; VDD – IDRD – VD = 0 or RD = ID
Usually V G = V S = IDRD = [VDD/3]
(b) II Method :
Constant V G biasing is achieved using two power supplies with as shown in the figure.
Resistor RG establishes a dc ground at the gate and presents a high input resistance to a
signal source that may be connected to the gate through a
coupling capacitor.
VSS + ID RS –VGS = 0 and VDD – ID RD – VD = 0
V DD −V D V SS −V GS
ID = also ID =
RD RS
Proble m: It is required to design constant VG bias circuit using a voltage divider network to establis h a
dc drain curre nt ID = 0.5 mA. The MOSFET is specified to have Vt = 1 V, Kn 1 (W/L) =1mA/V2 . Neglect
the channel-length modulation effect (i.e., assume λ = 0). Use a power-supply VDD = 15 V. Calculate the
percentage change in the value of ID obtained when the MOSFET is replaced with another unit having
the same Kn 1 (W/L), but Vt = 1.5 V.
Solution: As a thumb rule, the VDD is equally distributed across R D, RS

and VDS. VD = VDS + VRs
V − VD 15 − 10
R D = DD = = 10k
ID 0.5 × 10−3
V 5
R S = Rs = = 10k
ID 0.5 × 10−3
1 W
Using the relation, ID = 2 K n ′ [VOV ]2
L
2ID 2 × 0.5 × 10−3

VOV = = =1V
W 1 × 10−3
Kn ′ L
Also V GS = Vt + VOV = 1 + 1 = 2V and V G = VRs + VGS = 5 + 2 = 7V

VDD R G 2 15R G 2
VG = or 7= or 7 RG 1 = 8R G 2
RG1 + RG2 RG1 + RG2
Let RG2 = 7 M; then RG1 = 8 M
Now consider the case where the device is replaced with Vt = 1.5 V
1 ′ W 1 W 1
ID = Kn [VOV ]2 = K n ′ [VGS − Vt ]2 = 1 [VGS − 1.5]2
2 L 2 L 2
2ID – 1.414VGS = –2.121 ----------(A)
VG = 7 = VRs + VGS = IDRs + 2 or 10ID + VGS = 7 --------- (2)
Solving equations (1) and (2) results ID = 0.4818 mA
∆ID 0.4818 − 0.5
% Change in ID = = × 100 = −3.64 %
ID 0.5
Proble m : Design the MOSFET bias circuit shown below for a drain curre nt of 0.5 mA and V D = + 2V.
The supply voltages are VDD = VSS = 5V and the device parameters are Vt = 1 V, Kn 1 (W/L) =1mA/V2 .
Neglect the channel-length modulation effect (i.e., assume λ = 0).
Solution:
VDD − VD 5− 2
RD = = = 6 k
ID 0.5 × 10−3
1 W 1
ID = 0.5 = 2 K n ′ [VGS − Vt ]2 = 1 [VGS − 1]2 or V GS = 2V
L 2
VSS − VGS 5− 2
RS = = = 6 k
ID 0.5 × 10−3
To make IG  0; Choose RG in the range of 1 M to 10 M
Biasing Using Drain to Gate Feedback Resistor
Since I G = 0; a large feedback Resistor R G is connected between drain and gate will
provide the required bias Applying KVL to Drain – to source via gate loop results
VDD − ID R D − IG R G − VGS = 0
VGS = VDD − ID R D or VDD = VGS + ID R D
Thus, if ID for some reason changes, say increases, then VGS must decrease. The decrease
in V GS in turn causes a decrease in ID, a change that is opposite in direction to the one
originally assumed. Thus the negative feedback or degeneration provided by RG works to
keep the value of ID as constant as possible.
Proble m : (i) Design the MOSFET bias circuit shown below for a drain current of 0.5 mA and V D = + 2V.
The supply voltages are VDD = 5V and the device parameters are Vt = 1 V, Kn 1 (W/L) =1mA/V2 . Neglect
the channel-length modulation effect (i.e., assume λ = 0).(ii) Using standard resistor values, determine the
current ID and VD
1 W 1
𝐒𝐨𝐥𝐮𝐭𝐢𝐨𝐧: ID = 0.5 = 2 K n ′ [VGS − Vt ]2 = 1 [VGS − 1]2
L 2
Solving V GS = 2V = VD
VDD − VD 5− 2
RD = = = 6 k choose R D = 6.2 k
ID 0.5 × 10−3
To make IG  0; Choose RG in the range of 1 M to 10 M
V DD −V D 1 W V DD −V D 1 W
ID = = Kn ′ [VGS − Vt ]2 or = Kn ′ [VGS − Vt ]2
RD 2 L RD 2 L
5−V D 1
= (1)[VD − 1]2 solving for VD = 1.986 V = V GS
6.2 2
VDD − VD 5 − 1.986
ID = = = 0.486 mA
RD 6.2
Module 1(d) : Small-Signal Operation and MOSFET Models

The DC Bias Point:
By biasing the MOSFET to operate in the saturation region and by keeping the input signal small, linear
amplification can be obtained. Figure shows a conceptual MOSFET amplifier circuit in which MOS transistor
is biased by applying a dc voltage VGS, and the input signal to be amplified vgs, is superimposed on the dc bias
voltage VGS. The output voltage is taken at the drain. Neglecting channel length modulation ( = 0) and setting
vgs = 0, the drain current ID is given as
1 1
ID = k n [VGS − Vt ]2 = k n [VOV ]2
2 2
Where VOV = VGS – Vt is the overdrive voltage.
The dc voltage at the drain VDS = VDD – ID RD
The desired condition is that [VDS > VOV] for MOSFET to be in saturation region for required signal swing.
The Signal Current in the Drain Terminal

With the input signal v gs applied. The total instantaneous gate-to source voltage will be
vGS = VGS + vgs
The total instantaneous drain current iD is given by

1 1 1
iD = k n [VGS + vgs −Vt ]2 = k n [VGS −Vt ]2 + k n VGS −Vt vgs + k n [vgs ]2 − − − −(A)
2 2 2
The first term on the right- hand side of Eq. (A) can be recognized as the dc bias current ID. The second term
represents a current component that is directly proportional to the input signal vgs. The third term is a current
component that is proportional to the square of the input signal. This last component is undesirable because it
represents nonlinear distortion. To reduce the nonlinear distortion introduced by the MOSFET, the input signal
should be kept small so that
1
k [v ]2 ≪ k n VGS −Vt vgs or vgs ≪ 2 VGS −Vt or vgs ≪ 2VOV
2 n gs
1
Under this condition; iD  2 k n [VGS −Vt ]2 + k n VG S −Vt vgs = ID + id
Where id = k n VGS −Vt vgs

id
The transconductance gm is defined as gm = = k n VGS −Vt = k n VOV
v gs
The transconductance gm is equal to the slope of the iD − vGS characteristic at the bias point and is given as
𝜕𝑖 𝐷
g𝑚 =
𝜕𝑣𝐺𝑆 𝑣𝐺𝑆 =𝑉𝐺𝑆
The Voltage Gain:

The instantaneous drain voltage vDS = VDD – RD iD
In presence of the signal; vDS = VDD – RD (ID + id) = VDD – IDRD – id RD = VDS – idRD
The signal component of the drain voltage v ds = – id RD = – (gm vgs)RD
v ds
The voltage gain AV = = −g m R D
v gs
The negative sign indicates that the input and output are phase shifted by 180 o
Small-Signal Equivalent-Circuit MOSFET Models

From a signal point of view, the MOSFET behaves as a voltage-controlled current source. It accepts a signal vgs
between gate and source and provides a current gmvgs at the drain terminal. The input resistance of this
controlled source is very high—ideally, infinite. The output resistance—that is, the resistance looking into the
drain—also is high (ideally infinite). The small-signal model or a small- signal equivalent circuit of MOSFET is
shown in figure.
In figure (a), the drain current is assumed in saturation to be independent of the drain voltage. However from
the MOSFET characteristics in saturation, the drain current does in fact depend on vDS in a linear manner. Such
dependence was modeled by a finite resistance ro between drain and source as shown in figure (b).
|V A | 𝑙
The value of r o is defined as ro = where VA =
ID 
Typically, ro is in the range of 10 kΩ to 1000 kΩ.

v ds
The voltage gain AV = = −g m (R D | ro
v gs
Thus, the finite output resistance ro results in a reduction in the magnitude of the voltage gain.
The Transconductance gm
i W
Consider the equation g m = v d = k n VGS −Vt Using k n = k n 1
gs L
W W
g m = kn 1 VGS −Vt = k n 1 V −− −− −− −− A
L L OV
From equation (A), the transconductance gm is proportional to the (i) process transconductance parameter
k n 1 = μn Cox (ii) (W/L) ratio of the MOS transistor and (iii) over drive voltage VOV = VGS – Vt
2I D
Using VOV = W in the transconductance equation,
kn 1
L
W 2ID W W
g m = kn 1 = 2ID k n 1 = 2k n 1 ID − − − − − (B)
L W L L
kn 1 L
This expression (B) shows two things : ( i) For a given MOSFET, gm is proportional to the square root of the dc
W
bias current. (ii) At a given bias current, gm is proportional to L
W 2I D
Using k n 1 = results
L V GS −V t 2
W 2I D 2I D 2I D
g m = kn 1 VGS −Vt = 2 VGS −Vt = = − − − − − − − −(𝐶)
L V GS −V t V GS −V t V OV
In summary, there are three different relationships for determining transconductance gm—Eqns. (A),(B), and
(C) and there are three design parameters (W/ L), VOV, and ID, any two of which can be chosen independently.
That is, the designer may choose to operate the MOSFET with a certain overdrive voltage VOV and at a
particular current ID; the required (W/ L) ratio can then be found and the resulting gm determined.
Proble m: For the MOSFET amplifier circuit s hown below, if VDD = 5V, Vt = 0.7, =0 and Kn = 1
mA/V2 . Find VO V, ID, R D and R G to obtain a voltage gain of 25 and an input resistance of 0.5 M . What
is the maximum allowable input signal vi ?
vo
Solution: The voltage gain AV = = −25 𝑎𝑛𝑑 R in = 500 k
vi
Also A V = –gm RD = –25 or gm RD = 25 = kn VOV RD
Figure shows the small signal equivalent of the given amplifier circuit
vi vi vi
R in = = vi − vo = R
ii vi − vo G
RG
v i −v o v
RG = R in = 1 − vo R in
vi i
R G = 1 − (−25) 500k = 13 M
1 1
Using ID R D = K n vov 2 R D = K n vov R D Vov
2 2
1
ID R D = 25 Vov = 12.5 Vov
2
Vov = VGS − Vt = VDD − ID R D − Vt = 5 − 12.5 Vov − 0.7 or Vov = 0.319 Volts
1 1
ID = K n vov 2 = 1 × 10−3 × 0.3192 = 50.8 μA
2 2
12.5 Vov 12.5 0.319
ID R D = 12.5 Vov or RD = = = 78.5 k
ID 50 × 10−6
25 25
gm = = = 0.3185 mA/V
R D 78.5 × 103
The largest allowable input signal vi is to satisfy the condition (vDS  vGS – vt ) so that the MOSFET is in
saturation region. Hence vDS (min ) = vGS (max ) − Vt  VDS − AV vi = VGS + vi − Vt
Vt 0.7
Since VDS = VGS, the expression modifies to vi = = 25+1 = 27 mV
A V +1
The maximum allowable input signal is 27 mV
Review Questions
1. Draw the conceptual MOSFET amplifier circuit and derive the expression for (i) small signal drain current iD
(ii) Transconductance gm and (iii) voltage gain Av
2. Draw and explain the small signal equivalent circuit models for the MOSFET amplifier.
3, Mention the design parameters for a MOSFET amplifier and how transconductance can be computed using
these parameters.

Analog Circuits (18EC42) - Module 1

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Analog Circuits (18EC42) - Module 1

Uploaded by

Copyright:

Available Formats

Ravi Shankara.M.N. Asso. Professor ECE Dept SCE Bangalore ravi_shankar_mn@yahoo.co.

Module 1(a) : BJT Biasing: Biasing in BJT amplifier circuits:

in temperature and other transistor parameters.

2.2.1 - Require ments of Biasing Circuits

Applying KVL to the base circuit

VBB − VBE IE VBB − VBE

Applying KVL to collector –emitter loop,

VCC – IC RC – VCE – IERE = 0 since IE  IC , the equation modifies into

VCC − VC VCC − (VCE + VE ) 12 − 7.3

Given VCC = 15V, R1 = 47 k, R2 = 15 k, RC = 1.5 k, RE = 1 k

KVL to base – emitter loop; (VB – VBE – VE) = 0

VE = VBB –V BE = 3.629 – 0.7 = 2.929 Volts

We have VCC − IC R C − VCE − VE = 0

VCE = VCC − IC R C − VE = 15 − 2.929 × 1.5 − 2.929 = 7.68 V

VC = VCE + VE = 7.68 + 2.929 = 10.6 Volts.

VB − VBE 3.846 − 0.7

KVL equation to collector loop as VCC –I C RC –VCE – IERE = 0

VCE = VCC – IC RC – IERE

VCE = 30 – 4.110-3 (3k) + 4.14 10-3 (750) = 14.595V

DC Load line: KVL equation to collector loop yeilds

VCC –IC (RC + RE) –VCE = 0

(i) When IC = 0  V CE = VCC = 30 Volts (end point on X axis)

VB = VBE + VE = 0.7 + 5 = 5.7 V

Applying KVL to VCC – R1 – R2 – ground path,

Applying KVL to collector - emitter loop,

 VCC – IC RC – VCE – IERE = 0 since IE  IC ,

Biasing Using a Collector –to – Base Feedback Resistor

DC analysis : Applying KVL to the Collector – base loop,

VCC – (I C +IB) RC –IBRB –VBE = 0

Also applying KVL to collector to emitter via RB

Applying KVL to Collector – Emitter loop

VCC – (I C + IB) RC –VCE = 0  VCE = VCC – (IC + IB) RC --------------- (A)

IC = IB = 100(10.18A) = 1.018 mA

VCE = VCC – (IC + IB ) RC = 12 – (1.01810–3 + 10.1810–6 ) (10103 ) =1.7182 V

Q point = (V CE, IC) = (1.7182V, 1.018mA)

Module 1(b) : Small Signal Operation and BJT Models

vBE = VBE + vbe

The corresponding collector current is given by

If Vbe << VT then iC can be approximated as

Equation (a) is an approximation for v be < 10 mV and is known as small signal

The Base Current iB and Input Resistance r

The input base resistance r is dependent on  and inversely proportional to IC.

The Emitter Curre nt and the Input Resistance re

vbe vbe V VT  0.998 1

Relationship between re and r

The total collector voltage vC = VCC − iC R C = VCC − (IC + ic )R C = [VCC − IC R C ]− ic R C = VC − ic RC

vC = − ic RC = −g m vbe R C = (−g m R C )vbe

Solution: Assuming VT = 0.025 V ---------------------------------------- ( since vbe < VT )

vce = AV vbe = −400 0.005sinωt = −2sinωt

vC (t) = VC − vce = [VCC − IC R C ] − vce

vC t = 15 − 1 × 10−3 10 × 103 − −2sinωt = 5 + 2sinωt

iC t = IC + ic = IC + g m vbe = 1 × 10−3 + 40 × 10−3 0.005sinωt

Separating the Signal and the DC Quantities

The Hybrid  Model: :

At the emitter node,

𝑔𝑚 𝑣𝑏𝑒 = 𝑔𝑚 [𝑖𝑏 𝑟𝜋 ] = 𝑔𝑚 𝑟𝜋 [𝑖𝑏 = 𝛽𝑖 𝑏

The above models are known Hybrid  models of BJT amplifier.

1. Derive the expression for the transconductance gm of BJT amplifier.

3. Derive the expression for voltage gain of the BJT amplifier

Module 1(c) – MOSFETs : Biasing in MOS Amplifier Circuits

Usually V G = V S = IDRD = [VDD/3]

Solution: As a thumb rule, the VDD is equally distributed across R D, RS

2ID 2 × 0.5 × 10−3