Combinational+Sequential Design

4 BOOLEAN ALGEBRA
At the end of the lesson, students should be able to:

1. Explain the INVERTER, AND, OR, NAND and NOR gate using Boolean
Algebra.
2. Describe DeMorgan’s theorems to Boolean expression and evaluate Boolean
expression.
3. Simplification using Boolean algebra into Sum-Of-Product (SOP) form.
4. Explain of ‘don’t care’ condition.
UNIT 4: BOOLEAN ALGEBRA
INTRODUCTION
Boolean algebra is the mathematic of digital system. This topic covers laws, rules and
theorem of Boolean algebra and their application to digital circuits. You will also learning
the Boolean operations and expressions in terms of their relationship to NOT, AND, OR,
NAND and NOR gates introduce.
NOT, AND, OR, NAND AND NOR GATES USING

4.1
BOOLEAN ALGEBRA
Boolean algebra is the mathematics of digital systems. A basic knowledge of Boolean

algebra is indispensable to the study and analysis of logic circuits.
► Variable, complement and literal
Variable, complement and literal are the terms used in Boolean algebra.
i. Variable - Symbol (usually an italic uppercase letter to

represent a logical quantity)
- Single variable can have a 1 or 0 value.
ii. Complement - Is the inverse of a variable and is indicated by a

bar over the variable (over bar)
- Example: A  A , if A = 1 then A  0
iii. Literal - A literal is a variable or the complement of a

variable.
- For example: B’ indicates the complement of B.
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► Boolean Addition
Boolean addition is equivalent to the OR operation and the basic rules are
illustrated with their relation to the OR gate as follows:
In Boolean algebra, a sum term is a sum of literals. Some examples of sum terms
are:
_ _ _ _
A + B, A + B, A + B + C and A + B + C + D.
A sum term is equal to 1 when one or more of the literals in the term are1. A sum
term is equal to 0 only if each of the literals is 0.
Example 1:
Determine the values of A, B, C and D that make the sum term

A  B  C  D equal to 0.
Solution;
A  B  C  D  0 1 0 1  0  0  0  0  0
► Boolean Multiplication
Boolean Multiplication is the equivalent to the AND operation and the basic rules
are illustrated with their relation to the AND gate as follows:
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In Boolean algebra, a product term is the product of literals. Some examples of

product terms are
AB, AB, ABCandABCD
A product term is equal to 1 only if each of the literals in the term is 1.

A product term is equal to 0 when one or more of the literals are 0.
Example2:
Determine the values of A, B, C and D that make the product term ABC D
equal to 1.
Solution;
ABC D  1.0.1.0  1.1.1.1  1
► Laws And Rules Of Boolean Algebra
 Laws of Boolean Algebra
The basic of Boolean algebra: -
1. A + B = B + A
2. AB = BA
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3. A + (B + C) = (A + B) + C
4. A (BC) = (AB) C
5. A (B + C) = AB + AC
 Twelve Basic Rules of Boolean Algebra
There are 12 basic rules that are useful in manipulating and simplifying
Boolean expressions.
Rule 1. A + 0 = A
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Rule 2. A + 1 = 1
Rule 3. A . 0 = 0
Rule 4. A . 1 = A
Rule 5. A + A = A
Rule 6.
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Rule 7. A . A = A
Rule 8. A A  0
Rule 9. A A
Rule 10. A + AB = A
A  AB  A1  B  - factoring
 A 1 - rule 2: (1 + B) = 1
 A - rule4: A . 1 = A
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Rule 11. A  AB  A  B
A  AB   A  AB   AB - rule 10: A = A + AB
  AA  AB   AB - rule 7: A = AA
 AA  AB  A A  AB - rule 8: adding AA = 0
 
 A  A  A  B - factoring
1   A  B - rule 6: A  A  1
  A  B - rule 4: drop the 1
Rule 12. (A + B)(A + C) = A + BC
 A  B A  C   AA  AC  AB  BC
 A  AC  AB  BC - rule 7: AA = A
 A1  C   AB  BC - factoring
 ( A  1)  AB  BC - rule 2: 1 + C=1
 A1  B  BC - factoring
  A  1  BC - rule 2: 1 + B=1
 A  BC - rule 4: A .1 =A
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4.2 DEMORGAN’S THEOREMS
DeMorgan’s theorem is important because it show us how to find the equivalent of NAND
and NOR gates.
► State DeMorgan’s Theorem
Two DeMorgan’s theorem are: -
Sign ‘.’ Change to ‘+’, breaks the bar
a.
Sign ‘+’ Change to ‘.’, breaks the bar
b.
► Relate DeMorgan’s Theorem to the equivalency of the: -
i. NAND and negative-OR gates
Inputs Output
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0
ii. NOR and negative-AND gates
Inputs Output
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0
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Notice the equality of the two output columns in each truth table. This
shows that the equivalent gates perform the same logic function.
Example 1:
Apply DeMorgan’s theorems to the expression XYZ and X  Y  Z
Solution;
XYZ  X Y  Z
X Y  Z  XY Z
► Applying DeMorgan’s Theorem
Example 1:
Applying DeMorgan’s theorem to the expression below:
Solution;
Assume and
From DeMorgan rule (b):
… … (1)
… … (2)
Insert (2) into (1)
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Example 2:
Simplify the expression
Solution:
Step 1: DeMorgan Rule (a) :
Assume and
Step 2: DeMorgan Rule (b) :
Example 3:
Simplify the expression
Solution:
Step 1 : … … Rule 1: A+(B+C)=(A+B)+C
Step 2 : DeMorgan Rule (b) :
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SIMPLIFICATION USING BOOLEAN ALGEBRA INTO SUM – OF –

4.3 PRODUCTS (SOP) AND PRODUCT – OF –SUM (POS) FORM
When two or more product terms are summed by Boolean addition, the resulting
expression is a sum-of-products (SOP). Some examples are: -
AB  ABC
ABC  CDE  BC D
AB  ABC  AC
Also an SOP expression can contain a single-variable term as in A + A B C + B C D. In an

SOP expression, a single over bar cannot extend over more than one variable; however,
more than one variable in a term can have an over bar. For example, an SOP expression can
have the term ABC but not ABC
► Domain of a Boolean expression
The domain of a general Boolean expression is the set of variables contained in the
expression in either complemented or un-complemented form.
For example: -
i. AB  ABC is the set of variables A, B and C

ii. ABC  C DE  BC D is the set of variables A, B, C, D and E
► Implementation of an SOP expression.
Implementation an SOP expression simply requires from the outputs of two or more
AND gates. A product term is produced by an AND operation, and the sum
(addition) of two or more product terms is produced by an OR operation.
Therefore, an SOP expression can be implemented by AND-OR logic in which the
output of a number of AND gates connect to the inputs of an OR gate. Example AB
+ BCD + AC in figure 4.1.
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Figure 4.1: Implementation of the SOP expression AB + BCD + AC
 Convert a General Expression to SOP Form
Example 1:
Convert each of the following Boolean expression to SOP form:
a. A B + B (CD + EF)
b. (A + B) (B + C + D)
c. A  B  C
Solution;
a. A B + B (CD + EF)
=
b. (A + B) (B + C + D)
=AB+AC+AD+BB+BC+BD
= AB+AC+AD+B+BC+BD
c.
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► The Standard SOP Form
A standard SOP expression is one in which all the variables in the domain appear in
each product term in the expression. For example: -
ABCD  ABC D  ABC D is a standard SOP expression.
 Convert Product Terms to Standard SOP
Step 1: multiply each nonstandard product term by made up of the sum of a

missing variable and its complement.
Step 2: repeat step 1 until all resulting product terms contain all variables in the
domain in either complemented or un-complemented form.
Example 1:
Convert the following Boolean expression into standard SOP form:

ABC  AB  ABCD
Solution;
 ABC  AB  ABCD - A B C is missing variable D or D

ABC ( D  D)  ABCD  ABC D
 AB - AB is missing variable C or C and D or D

AB(C  C )  ABC  ABC
ABC ( D  D)  ABCD  ABC D
ABC( D  D)  ABCD  ABC D
ABC  AB  ABCD
 ABCD  ABC D  A BCD  A BC D
 A BC D  ABC D  ABC D
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 Binary Representation of a Standard Product Term
A standard product term is equal to 1 for only one combination of variable

values.
Example 1:
The product term ABC D  1; when A = 1, B = 0, C = 1 and D = 0

ABC D  1  0  1  0  1  1  1  1  1
Example 2:
Determine the binary values for the following standard SOP expression equal to
1.
ABCD  ABCD  ABC D

Solution;
The term ABCD  1 ; when A = 1, B = 1, C = 1 and D = 1

ABCD  1  1  1  1  1
The term ABCD  1 ; when A = 1, B = 0, C = 0 and D =1

ABCD  1  0  0  1  1  1  1  1  1
The term ABC D  1 ; when A = 0, B = 0, C = 0 and D = 0

ABC D  0  0  0  0  1  1  1  1  1
The SOP expression equals 1 when any or all of the three product terms is 1
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► Simplification Using Boolean Algebra Into Product – Of – Sums (Pos) Form
 Product-of-Sums (POS).
When two or more sum terms are multiplied, the resulting expression is a
product-of-sums (POS). Some examples are: -
( A  B)( A  B  C )
( A  B  C )(C  D  E)( B  C  D)
( A  B)( A  B  C )( A  C )
A POS expression can contain a single-variable term as in

A( A  B  C )( B  C  D) . In a POS expression, a single over bar cannot extend
over more than one variable; however, more than one variable in a term can have
an over bar. Example, a POS expression can have term A  B  C but not
A B C.
 Implementation of a POS Expression.
POS expression simply requires AND in the outputs of two or more OR gates. A
sum term is produced by an OR operation, and the product of two or more sum
terms is produced by AND operation. Therefore, a POS expression can be
implemented by logic in which the outputs of a number of OR gates connect to
the inputs of an AND gate.
Example (A + B)(B + C + D)(A +C) in Figure 4.2.
Figure 4.2: Implementation of the POS expression (A + B)(B + C + D)(A +C)
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 The Standard POS Form.
A standard POS expression is one in which all the variables in the domain appear
in each sum term in the expression. For example: -
Is a standard POS expression, any nonstandard POS expression can be

converted to the standard form using Boolean algebra.
 Convert a Sum Term to Standard POS
Procedure: -
1. Add to each nonstandard product term a term made up of the product of

the missing variable and its complement. This results in two sum terms.
2. Apply rule 12: A + B C = (A + B)(A + C)
3. Repeat step 1 until resulting sum terms contain all variables in the domain
in either complemented or un-complemented form.
Example 1:
Convert the following Boolean expression into standard POS form.

( A  B  C )( B  C  D)( A  B  C  D)
Solution;
 ( A  B  C) - Missing D D
- Add D D
 ( A  B  C  D)( A  B  C  D)
 ( B  C  D) - Missing A A
- Add A A
 ( A  B  C  D)( A  B  C  D)
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 ( A  B  C  D)( A  B  C  D)( A  B  C  D)( A  B  C  D)( A  B  C  D)
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 Binary representation of a standard sum Term.
A standard sum term is equal to 0, for only one combination of variables

values.
Example 2:
The sum term A  B  C  D = 0 when A = 0, B = 1, C = 0 and D = 1
A  B  C  D  0 1 0 1
Example 3:
Determine the binary values of the variables for which the following standard
POS expression is equal to 0.
( A  B  C  D)( A  B  C  D)( A  B  C  D)
Solution;
The term ( A  B  C  D)  0 when A=0, B=0, C=0 and D=0

( A  B  C  D)  0  0  0  0  0

( A  B  C  D)  0  1  1  0  0

( A  B  C  D)  1  1  1  1  0
 The POS expression equals 0 when any of the three SUM terms equals 0.
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 Convert Standard SOP to Standard POS
The binary values of the product terms in a given standard SOP expression are
not present in the equivalent standard POS expression. Also, the binary values
that are not represented in the SOP expression are present in the equivalent
POS expression. Therefore, to convert from standard SOP to standard POS,
the following steps are taken:
Step 1: Evaluate each product term in the SOP expression. That is, determine
the binary numbers that represent the product terms.
Step 2: Determine all of the binary numbers not included in the evaluation in
step 1.
Step 3: Write the equivalent sum term for each binary number from step 2
and express in POS form.
Example 4:
Convert the following SOP expression to an equivalent POS expression

ABC  ABC  ABC  ABC  ABC
Solution;
ABC  ABC  ABC  ABC  ABC = 000 + 010 + 101 + 110 + 111
Variables = 3
 N=2n = 23 = 8 possible combinations
Truth table
A B C SOP/POS
0 0 0 SOP
0 0 1 POS
0 1 0 SOP
0 1 1 POS
1 0 0 POS
1 0 1 SOP
1 1 0 SOP
1 1 1 SOP
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So, the POS must contain the other three, which are 001, 011 and 100.
► The Different Between SOP and POS Form
SOP POS
Equation  Equation 
From Truth Table Output = 1 From Truth Table Output = 0
Where A = 1 Where A = 0
A = 0 A = 1
USE OF DON’T CARE CONDITION TO SIMPLIFY LOGIC

4.3 FUNCTION
Sometimes a situation arises in which some input variable combinations are not allowed. For
example, recall that in the BCD code, there are six invalid combinations: 1010, 1011, 1100,
1101, 1110 and 1111, Since these un-allowed states will never occur in a application involving
BCD code, they can be treated as “don’t care” terms with respect to their effect on the
output. That is, for these “don’t care” terms either a 1 or 0 may be assigned to the output;
it really does not matter since they will never occur.
The “don’t care” terms can be used to advantage on the Karnaugh map. Figure 4.3 shows
that for each “don’t care” term, an X is placed in the cell. When grouping the 1s, the Xs
can be treated as 1s to make larger grouping or as 0s if they cannot be used to advantage.
The larger a group, the simpler the resulting term will be. The truth table in figure 4.3(a)
describes a logic function that has a 1 output only when the BCD code for 7, 8 or 9 is
present on the inputs. If “don’t cares” are used as 1s, the resulting expression for the
function is A + BCD, as indicated in part (b). If the “don’t care” are not used as 1s, the
resulting expression is:
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So you can see the advantage of using “don’t care” terms to get the simplest expression.
Figure 4.3: Example of the use of “don’t care” condition to simplify an expression
SUMMARY
In this topic, we have learn about the operation of the basic logic gate like the INVERTER
or NOT, AND, OR, NAND and NOR gate. Student also should be understand about the
operation of the exclusive-OR gate and exclusive-NOR gate.
Student should be able to identify the shape of logic gate symbols according to the
ANSI/IEEE (American National Standard Institute/ International Electrical Electronic
Engineering). To understand more about digital signal input and output, student must be
construct timing diagrams that showing the proper time relationships of inputs and outputs
for the various logic gates.
Student also learned about the characteristic of IC CMOS(Complimentary Metal Oxide

Semiconductor) and TTL(Transistor-Transistor Logic) families to know the differ from
each other in propagation delay time, power dissipation, speed-power product and fan-out,
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They also learned how to troubleshoot the logic gates for opens and shorts by using the
oscilloscope.
EXERCISE
1. If A = 0, what does A equal?
______________________________
2. Determine the values of A, B and C that make the sum term A  B  C equal to 0.
_____________________________
3. Determine the values of A, B and C that make the product term ABC equal to 1.
______________________________
4. Apply the associative law of addition to the expression A + (B + C + D)
5. Apply the distributive law to the expression A (B + C + D).
6. Which of the following rules states that if one input of an AND gate is always 1, the
output is equal to the other input?
a. A + 1 = 1
b. A + A = A
c. A . A = A
d. A . 1 = A
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7. Apply DeMorgan’s theorems to each of the following expressions:
a. (A + B + C) D
b. ABC + DEF
c. AB + CD + EF
8. Convert A B C + (A + B)(B + C + A B) to SOP form.
9. Convert the expression WX Y  XYZ  W X Y to standard form.
10. Convert the expression (A + B)(B + C) to standard POS form.
11. Determine the binary values for the POS expression below equal to 0
( X  Y  Z )( X  Y  Z )( X  Y  Z )( X  Y  Z )( X  Y  Z )
REFERENCE
1. Digital System – Principle And Applications, Tocci, R.J, Prentice Hall international
2. Digital Fundamentals, Floyd T.L, Merrill Publishing.
3. BPL(K) Module : TFV 2033 Digital Electronics 1.
4. Digital Electronics (Teaching Module), KUITHO.
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5 COMBINATIONAL GATES
At the end of the lesson, students should be able to:

1. Analyze a basic combinational logic circuits (AND-OR, AND-OR INVERT),
exclusive-OR and exclusive-NOR.
2. Use AND-OR and AND-OR INVERT circuits to implement sum-of-product
(SOP) and product-of-sum (SOP) expression.
3. Develop a truth table from Boolean output expression for combinational logic
circuit.
4. Use the Karnaugh map as a tool to simplify and design combinational logic
circuit.
5. Select SSI (small scale integration) digital IC.
6. Troubleshoot logic circuits by using signal tracing and waveform analysis.
UNIT 5: COMBINATIONAL GATES
5.1 BASIC COMBINATIONAL LOGIC CIRCUITS
► AND – OR Logic
(a) Logic diagram (ANSI standard (b) ANSI standard distinctive shape
symbol) rectangular outline symbol
Figure 5.1: An AND-OR circuit
 The Boolean expressions for the AND gate outputs and the resulting SOP
expression for the output X are shown on the diagram.
 An AND-OR circuit directly implements an SOP expression, assuming the
complements (if any) of the variables are available.
 For a 4-input AND-OR logic circuit, the output X is HIGH (1) if both input A
and input B are HIGH (1) or both input C and input D are HIGH (1)
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INPUT OUTPUT
A B C D AB CD X = AB + CD
0 0 0 0 0 0 0
0 0 0 1 0 0 0
0 0 1 0 0 0 0
0 0 1 1 0 1 1
0 1 0 0 0 0 0
0 1 0 1 0 0 0
0 1 1 0 0 0 0
0 1 1 1 0 1 1
1 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 0 0 0
1 0 1 1 0 1 1
1 1 0 0 1 1 1
1 1 0 1 1 1 1
1 1 1 0 1 1 1
1 1 1 1 1 1 1
Table 5-1: Truth table for the AND-OR logic.
► AND – OR INVERT Logic
(a) AND-OR Invert circuit (b) Rectangular outline symbol
Figure 5.2: An AND-OR-Invert circuit produces a POS output.
 In general, an AND-OR Invert circuit can have any number of AND gates
each with number of inputs.
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► EXCLUSIVE – OR Logic
(a) Exclusive – OR Logic Diagram
(b)ANSI distinctive shape symbol (c) Rectangular outline symbol
Figure 5.3: Exclusive-OR logic diagram and symbols
 This circuit is considered a type of logic gate with its own unique symbol, it
is actually a combination of two AND gates, one OR gate and two
inverters as shown in figure 5.3(a).
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► EXCLUSIVE – NOR Logic
 The exclusive NOR function is as follows:

X  AB  AB  AB  AB  ( A  B)( A  B)  AB  AB
 Output X is HIGH when A and B are both HIGH or both LOW(same level)
 The exclusive-NOR can be implemented by simply inverting the output of an
exclusive-OR as shown in figure 5.4(a) or by directly implementing the
expression AB + AB as shown in part (b).
(c) ANSI distinctive shape symbol (d) ANSI rectangular outline
Figure 5.4 : Exclusive-NOR logic diagram and symbols
 An XNOR has only two inputs. The bubble on the output of the XNOR symbol
indicates that its output is opposite that of the XOR gate. When the two
input logic levels are opposite, the output of the exclusive-NOR gate is
LOW. The operation can be stated as follows (A and B are inputs, X is the
output).
 For an exclusive-NOR gate, output X is LOW when input A is LOW and input
B is HIGH, or when A is HIGH and B is LOW; X is HIGH when A and B are
both HIGH or both LOW.
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USE AND-OR AND AND-OR INVERT CIRCUITS TO IMPLEMENT

5.2 SUM-OF-PRODUCT (SOP) AND PRODUCT-OF-SUM (POS)
 When the output of an AND-OR circuit is completed (inverted), it results in an AND-

OR Invert circuit.
 Recall that AND-OR logic directly implements SOP expressions. POS expressions can
be implemented with AND-OR Invert logic.
 This is illustrated as follows, starting with a POS expression and developing the
corresponding AND-OR Invert expression.
 Example :
X  ( A  B)(C  D)  ( AB )(CD)  ( AB )(CD)  AB  CD  AB  CD
POS SOP
DEVELOP A TRUTH TABLE FROM BOOLEAN OUTPUT EXPRESSION

5.3 FOR COMBINATIONAL LOGIC CIRCUIT
► Example 1:
For the output expression for the circuit in Figure 5.3 is
X  AB  AB
Evaluation of this expression results in the truth table in table 5.2.
INPUTS OUTPUT
A B X
0 0 0
0 1 1
1 0 1
1 1 0
Table 5.2: Truth table for an exclusive-OR
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► Example 2:
Develop a truth table for the standard SOP expression:
X  ABC  ABC  ABC
Solution;
There are 3 variables.

So, binary values = 23 = 8
ABC  001 = 1
ABC  100 = 1
ABC  111 = 1
INPUT OUTPUT
A B C X
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Table 5.3 : Truth table
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► Example 3 :
Determine the truth table for the following standard POS expression:
( A  B  C )( A  B  C )( A  B  C )( A  B  C )( A  B  C )
Solution;
There are 3 variables.
So, binary values = 23 = 8
( A  B  C)  0 0 0 = 0
( A  B  C)  0 1 0 = 0
( A  B  C)  0 1 1 = 0
( A  B  C)  0 1 0 = 0
( A  B  C)  1 1 0 = 0
INPUT OUTPUT
A B C X
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Table 5.4: Truth table
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THE KARNAUGH MAP AS A TOOL TO SIMPLIFY AND DESIGN

5.4 COMBINATIONAL LOGIC CIRCUIT
The Karnaugh map provides a systematic method for simplifying Boolean expressions
and if properly used, will produce the simplest SOP or POS expression possible, known
as the minimum expression. The Karnaugh map, on the other hand, basically provides a
“cookbook” method for simplification.
► The Karnaugh Map (K-Map)
Figure 5.5: Karnaugh map
 The number of cells in a Karnaugh map is equal to the total number of

possible input variable combinations as is the number of rows in a truth
table.
 For three variables, the number of cells is 23 = 8. For four variables, the
number of cells is 24 = 16.
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► Mapping a Standard SOP Expression
 For an SOP expression in standard form, a 1 is placed on the Karnaugh map

for each product term in the expression.
 For example, , a 1 in the 101 cell on a 3-variable map.
Figure 5.6: Karnaugh Map
 Step of mapping process:
i. Determine the binary value of each product term in the standard SOP
expression.
ii. As each product term is evaluated, place a 1 on the map in the cell having
the same value as the product term and the 0s left off the map.
 Example :
Map the following standard SOP expression on a Karnaugh map:
ABC  ABC  ABC  ABC
Solution:
Step 1: Determine the binary value
000 001 110 100
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Step 2: Place 1 on the k-map cell
Figure 5.7 : Karnaugh map
► Mapping a Standard POS Expression
 For a POS expression in standard form, a 0 is placed on the Karnaugh map

for each sum term in the expression.
 Example:
( A  B  C  D)( A  B  C  D)( A  B  C  D)( A  B  C  D)

( A  B  C  D)( A  B  C  D)
 Step of mapping process:
i. Determine the binary value of each sum term in the standard POS
expression.
ii. As each sum term is evaluated, place a 0 on the map in the cell having the
same value as the sum term and the 1s left off the map.
 Example:
Map the following standard POS expression on a Karnaugh map:
( A  B  C  D)( A  B  C  D)( A  B  C  D)( A  B  C  D)( A  B  C  D)
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Solution:

1100 0100 0001 0011 1001
Step 2: Place 0 to K-map cell
Figure 5.8: Karnaugh Map
► Direct Mapping From a Non-standard Boolean Expression
You can also directly map a non-standard Boolean expression to k-map.
Example:
Map the Boolean expression directly into k-map.
Solution:
Figure 5.9
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► Looping
 The expression for output Y can be simplified by properly combining those

squares in the Karnaugh map which contain is. The process for combining
these is called looping.
 Adjacent cell in k-map:
C.D
A.B
00 01 11 10
00
01
Each cell is adjacent to the
11 cell at its right, left, above
and below
10
C.
A.D Each cell at the outer left
0 00 10
B
01 11 column is adjacent to the
0
corresponding cell at the
0 outer right corner
1
1
1
1 C.D
0 00 01 11 10
A.B
00
Each cell at the top row is
01 adjacent to the
corresponding cell at the
11 bottom row
10
Figure 5.10 : Adjacent cell of 4-variable k-map
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 A group can only contain either 1, 2(pairs), 4(Quads), or 8(octets) which are all
power of two.
i. Pairs
The examples of pairs looping are shown in Figure 5.11.
Figure 5.11 : Looping a pair of adjacent
ii. Quads
 Contain a group of four that are adjacent to each other.

 When a quad is looped, the resultant term will contain only the
variables that do not change form for all the squares in the quad.
 For example in Figure 5.12(a), from the terms -
, only the variable C remains unchanged.
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(c) (d)
(e)
Figure 5.12 : Looping a quads of adjacent
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iii Octests
A group of eight 1s that are adjacent to one other is called octet.

Several examples for octet are shown in Figure 5.13.
Figure 5.13 : Looping a octets of adjacent
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► Karnaugh Map POS and SOP Minimization
 Rules of minimizing the Boolean Expression (POS and SOP)
o To obtain the minimal Boolean Expression, loop the largest group as possible.
o The „1‟ must be enclosed in a group (at least one) and „1‟s that already in a
group can overlap (included) in other group as long as it contains the non-
common 1‟s.
CD Overlapped cell
AB 00 01 11 10
00 0 1 1 0
Non-common cell
01 0 1 1 1
11 0 1 1 1
10 0 1 1 0
Figure 5.14: Explanation of rule 1 and 2
 Example
Using a Karnaugh map, convert the following standard POS expression into a
minimum POS expression, a standard SOP expression, and a minimum SOP
expression:
( A  B  C  D)( A  B  C  D)( A  B  C  D)( A  B  C  D)

( A  B  C  D)( A  B  C  D)
Solution;

1100 0100 0001 0011 1001 0010
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Step 2: Place 0 to K-map cell.
Figure 5.15(a): Karnaugh map
Step 3: Group 0 to obtain the minimum POS expression.
Minimum POS expression:
__________________________________________
Step 4: Place 1 to k-map cell that do not contains 0s.
Figure 5.15(b): Karnaugh map
Step 5: Group 1 to obtain the minimum SOP expression.
Minimum SOP expression:
_________________________________________________
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 Example 2:
Obtain the minimum SOP form for truth table below:
Input Output
A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
Table 5.5: Truth table
Solution:
Step 1: Map the output in k-map.
CD
AB 00 01 11 10
00 1 0 1 1
01 0 0 0 0
11 0 1 1 0
10 1 0 1 1
Figure 5.16
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Step 2; Group „1‟ (Loop the largest group as possible)
Step 3: Determine the minimum product term for each group.
Step 4; Sum all the term to obtain the minimize SOP.
X = ___________________________________
► Draw The Combinational Logic Circuit After Simplify Using Karnaugh Map
Example 1:
Using the minimum POS expression from Figure 5.12(a), draw the
combinational Circuit.
Minimum POS expression: ___________________________________
Combinational Circuit:
Figure 5.17:Logic circuit
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Example 2 :
Using the minimum SOP expression from Figure 5.15(b), draw the
combinational Circuit.
Minimum SOP expression: ___________________________________
Combinational Circuit:
Figure 5.18: Logic circuit
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TROUBLESHOOT LOGIC CIRCUIT BY USING SIGNAL TRACING AND

5.5 WAVEFORM ANALYSIS
 Example 1:
We are given Figure 5.18(a) and the truth tables in Table 5.6. The timing diagrams
are shown in Figure 5.18(b).
Troubleshooting Example 1
Figure 5.18 (a): Given circuit
Table 5.6: Truth Table
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Figure 5.18(b): Timing diagrams
NOTE:
THE DIFFERENT BETWEEN SOP AND POS EXPRESSION
SOP POS
Equation  Equation 
From true table output = 1 From True Table Output = 0

Where Where
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SUMMARY
In this topic, students should be able to analyze basic combination of logic circuit were
discussed in topic 3.0 and 4.0 such as AND-OR, AND-OR INVERT, exclusive-OR and
exclusive-NOR. Implementation of sum-of-product (SOP) and product-of-sum(POS)
expression in AND-OR and AND-OR INVERT circuit.
Student should know how to develop truth table from the output expression. Simplify and
design combination logic by using Karnaugh map. Student also should be able to select SSI
(small scale integration) digital IC.
Beside that, student should be able to troubleshoot logic circuit by using signal tracing and
waveform analysis.
EXERCISE
1. Write out the output X expression for the circuit.
Figure 5.19: Combinational logic circuit
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2. Use AND gates, OR gates or combinations of both to implement the following logic
expressions as stated:
(a) X = AB + CD + (A + B)(ACD + BE)
(b) X = ABC D + DEF + AF
(c) X = A [B + C(D + E )]
3. Draw the ANSI rectangular outline symbol for exclusive -OR and
exclusive-NOR gate.
4. Create a truth table for the standard SOP expression ABC  ABC .
5. Develop a truth table for the following standard POS expression:

( A  B  C )( A  B  C )( A  B  C )
6. Use a Karnaugh map to convert the following expression to minimum SOP and POS
form and design that logic circuit:
(W  X  Y  Z )(W  X  Y  Z )(W  X  Y  Z )(W  X  Y  Z )(W  X  Y  Z )
REFERENCE
1. Digital System – Principle And Applications, Tocci, R.J, Prentice Hall international
2. Digital Fundamentals, Floyd T.L, Merrill Publishing.
3. BPL(K) Module : TFV 2033 Digital Electronics 1.
4. Digital Electronics Teaching Module, KUITHO
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UNIT-2: BOOLEAN EXPRESSIONS AND COMBINATIONAL LOGIC
CIRCUITS
STRUCTURE
2.0 Objectives
2.1 Introduction
2.2 Simplification of Boolean Expressions
2.2.1 Sum of Products
2.2.2 Product of Sums
2.2.3 Canonical SOP and POS Forms
2.2.4 Karnaugh Maps
2.2.5 Implementing Boolean Expressions Using NAND Gates
2.2.6 Implementing Boolean Expressions Using NOR Gates
Check Your Progress 1
2.3 Combinational Logic Circuits
2.3.1 Half Adder
2.3.2 Full Adder
2.3.3 Half Subtractor
2.3.4 Full Subtractor
2.3.5 Parallel Binary Adder
2.3.6 BCD Adder
2.3.7 Encoders
2.3.8 Decoders
2.3.9 Multiplexers
2.3.10 Demultiplexers
2.4 Summary
2.5 Glossary
2.6 References
2.7 Answers to Check Your Progress Questions
2.0 Objectives
At the end of the unit you will be able to
• Simplify Boolean expressions using algebraic method

• Describe sum of products and product of sums and convert them into canonical
form
• Design karnaugh maps and use them to simplify Boolean expressions
• Implementing Boolean expressions using NAND and NOR gates
• Describe half adder, full adder, half subtractor, full subtractor, parallel binary
adder and BCD adder
• Find, based on input conditions, the output of an encoder and decoder
• Determine the output of multiplexer and demultiplexer based on input conditions
2.1 Introduction
We have studied so far logic gates and Boolean algebra. Boolean algebra and
theorems are used for the manipulations of logical expressions. It has also been seen that
a logical expression can be realized by using the logic gates. The number of gates
required and the number of input terminals for the implementation of a logical expression,
in general, get reduced considerably if the expression can be simplified. Therefore, the
simplification of logical expression is very important as it saves the hardware required to
design a specific system
We know that logical expressions are implemented by connecting specific logic
gates. These logic gates produce a specific output for certain specified combinations of
input variables, with no storage involved. These circuits are commonly known as
combinational circuits. In combinational circuits, the output level is always dependent on
the combinations of the input levels.
The combinational circuits can be specified in one of the following ways:
• A set of statements
• Boolean expression, and
• Truth table.
In this section we will continue our study of combinational circuits and we will
further study various methods of simplifications of logical circuits.
2.2 Simplification of Boolean Expressions:
Simplification of Boolean functions is mainly used to reduce the gate count of a
design. Less number of gates means less power consumption, sometimes the circuit works
faster and also when number of gates is reduced, cost also comes down. There are many
ways to simplify a logic design; some of them are given below. We will be looking at
each of these in detail in the next few pages.
• Algebraic Simplification.
 Simplify symbolically using theorems/postulates.

 Requires good skills
• Karnaugh Maps.
 Diagrammatic technique using 'Venn - diagram'.

 Limited to not more than 6 variables
Some of the examples are given here:
1. Simplify the Boolean expression

XY′Z′+XY′Z′W+XZ′
The above expression can be written as

XY′Z′ (1+W) +XZ′
=XY′Z′+XZ′ as 1+W=1
=XZ′ (Y′+1)
=XZ′ as Y′+1=1

X+X′Y+Y′+(X+Y′) X′Y

X+X′Y+Y′+XX′Y+Y′X′Y
=X+X′Y+Y′ as XX′=0, and YY′=0
=X+Y+Y′ as X+X′Y=X+Y
=X+1 as Y+Y′=1
=1 as X + 1=1

Z(Y+Z) (X+Y+Z)

(ZY+ZZ)(X+Y+Z)
= (ZY+Z) (X+Y+Z) as ZZ=Z
=Z(X+Y+Z) as Z+ZY=Z
=ZX+ZY+ZZ
=ZX+ZY+Z as ZZ=Z,
=ZX+Z as Z+ZY=Z
=Z as Z+ZX=Z
(X+Y)(X′+Z)(Y+Z)

(XX′+XZ+YX′+YZ)(Y+Z)
=(XZ+YX′+YZ) (Y+Z) as XX′=0
=XZY+YYX′+YYZ+XZZ+YX′Z+YZZ
=XZY+YX′+YZ+XZ+YX′Z+YZ as YY=Y, ZZ=Z
Rearranging the terms we get
XZY+XZ+YX′+YX′Z+YZ as YZ+YZ=YZ
=XZ(Y+1) +YX′+YZ (X′+1) as Y+1=1, X′+1=1
=XZ+YX′+YZ
Now it seems that it cannot be reduced further. But apply the following trick:
XZ+YX′+YZ(X+X′) as X+X′=1
=XZ+YX′+YZX+YZX′
XZ+YXZ+Y X′+YX′Z
=XZ (1+Y) +YX′ (1+Z)
=XZ+YX′ as 1+Y=1, 1+Z=1
2.2.1 Sum of Products:

A sum of products expression consists of several product terms logically added. A
product term is a logical product of several variables. The variables may or may not be
complemented. The following are the examples of sum of products expressions.
1. XY+X'Y+XY'
2. AB+ABC+BC'
3. A+AB'+B'C
4. ABC+A'B+AB'C+A'BC'
Sometimes a product term may consist of a single variable.
2.2.2 Products of Sums:
A product of sums expression consists of several sum terms logically multiplied.
A sum term is the logical addition of several variables. The variables may or may not be
complemented. The following are examples of product of sums expressions:
A) (A+B) (A'+B')
B) A (B'+C') (B+C)
c) (X+Y') (X+Y+Z) (Y+Z)
Sometimes a sum term may consist of a single variable.
2.2.3 Canonical SOP and POS Forms:

When each term of a logic expression contains all variables, it’s said to be in the
canonical form. When a sum of products form of logic expression is in canonical form,
each product term is called minterm. Each minterm contains all variables. The canonical
form of a sum of products expression is also called minterm canonical form or standard
sum of products. Similarly, when a product of sums form of logic expression is in
canonical form, each sum term is called a maxterm. Each maxterm contains all variables.
The canonical form of a product of sums expression is also called maxterm canonical
form or standard product of sums.
When a logic expression is not in the canonical form, it can be converted into
canonical form. In the canonical form there is uniformity in the expression, which
facilitates minimization procedure
The following are examples of the canonical form of sum of products expressions
(or minterm canonical form):
(i). Z = XY + XY′
(ii). F = XYZ′ + X′YZ + X′YZ′ + XY′Z + XYZ
In case of 2 variables, the maximum possible product terms are 4, for 3 variables, the
possible product terms are 8, for 4 variables 16, and for n variables, 2ⁿ.
In the above examples the expression (ii) contains 5 out of 8 possible product terms.
When the expression is in the canonical form all terms are mutually exclusive. It means
that for a given set of values of the variables, when one of the terms is equal to 1, all
others must be 0. Of course, it is possible that all terms may be 0.
The following are examples of canonical form of product of sums expressions (or
maxterm canonical form).
(i). Z = (X + Y) (X + Y′)
(ii). F = (X′ + Y + Z′) (X′ + Y + Z) (X′ + Y′ + Z′)
The following table gives the minterms and maxterms for a three variable logical function
where the number of minterms as well as maxterms is 2³ = 8. In general, for an n-variable
logical function there are 2ⁿ minterms and an equal number of maxterms.
Variables Minterms Maxterms

A B C mi Mi
0 0 0 A' B' C' = m0 A + B + C = M0
0 0 1 A' B' C = m1 A + B + C' = M1
0 1 0 A' B C' = m2 A + B' + C = M2
0 1 1 A' B C = m3 A + B' + C' = M3
1 0 0 A B' C' = m4 A' + B + C = M4
1 0 1 A B' C = m5 A' + B + C' = M5
1 1 0 A B C' = m6 A' + B' + C = M6
1 1 1 A B C = m7 A' + B' + C' = M7
Minterms and Maxterms for Three variables
As shown in the above table each minterm is represented by mi and each maxterm
is represented by Mi where i is the decimal number equivalent of the natural binary
number. With these shorthand notations logical functions can be represented as follows:
1. Y = A' B' C’ + A’ B’ C + A’ B C + A B C’
= m0 + m1 + m3 + m6
= ∑m( 0, 1, 3, 6 )
2. Y = ( A + B + C’ ) ( A + B’ + C’ ) ( A’ + B’ + C )
= M1 + M3 + M6
= πM( 1, 3, 6 )
Where ∑ denotes sum of product while π denotes product of sum
Conversion of Sum of Products Expressions into Canonical Form:

The following examples will illustrate how logic expressions can be converted into
canonical form.
Example 1: Convert the expression X + XY’ into canonical form.
The expression has two variables. The first term has only one variable. So to make it
of two variables it can be multiplied by (Y + Y’), as Y + Y’ = 1. After multiplication the
given logic expression can be written as
X(Y + Y′) + XY′, as Y + Y′ = 1
or XY + XY′ + XY′
or XY + XY′
Conversion of Product of Sums Expression into Canonical Form:

Before we proceed with such a conversion a few identities should be examined.
We can write A = (A + B) (A + B′)
This can be proved as follows:
A = A +A + 0
= A( B + B′ ) + A.A + B.B′, as B + B′ =1, AA=A, BB′=1
= AB + AB′ + AA + BB′
= A (A +B) + B′ (A + B)
= (A + B) (A + B′)
Similarly, we can write A + B = (A + B +C) (A + B + C′).
(A + B + C) (A + B + C′)
= AA + AB + AC′ + AB + BB + BC′ + AC + BC + CC′
AA + BB + AC′ + BC′ + AC + BC + AB + AB, as CC′ = 0
= (A + B) + C′ (A + B) + C (A + B) + AB + AB [AA = A; BB = B]
= (A + B) + (A + B) (C + C′) + AB + AB
= (A + B) + (A + B) + AB + AB as C + C′ = 1
= A + B + AB + AB as (A + B) + (A + B) = (A + B)
= A + AB + B + AB
= A (1 + B) + B (1 + A)
=A+B as 1 + B = 1, 1 + A =1
This technique can be extended to any number of variables such as

(A + B′ + C) = (A + B′ + C + D) (A + B′ + C + D′)
Example 1: Convert the following expression into canonical form:
(A + B) (B + C)
To convert the above expression into canonical form the following identity can be used:
X + Y = (X + Y + Z) (X + Y + Z′)
Applying the above identity, the given logic expression can be written as
(A + B + C) (A + B + C′) (A + B + C) (A′ + B + C)
= (A + B + C) (A + B + C′) (A′ + B + C)
2.2.4 Karnaugh Maps

Karnaugh maps provide a systematic method to obtain simplified sum-of-products
(SOPs) Boolean expressions. This is a compact way of representing a truth table and is a
technique that is used to simplify logic expressions. It is ideally suited for four or less
variables, becoming cumbersome for five or more variables. Each square represents either
a minterm or maxterm. A K-map of n variables will have 2 squares. For a Boolean
expression, product terms are denoted by 1's, while sum terms are denoted by 0's.
A K-map consists of a grid of squares, each square representing one canonical minterm
combination of the variables or their inverse. The map is arranged so that squares
representing minterms which differ by only one variable are adjacent both vertically and
horizontally. Therefore XY'Z' would be adjacent to X'Y'Z' and would also adjacent to
XY'Z and XYZ'.
Minimization Technique
• Based on the Unifying Theorem: X + X' = 1

• The expression to be minimized should generally be in sum-of-products form (If
necessary, the conversion process is applied to create the sum-of-products form).
• The function is mapped onto the K-map by marking a 1 in those squares
corresponding to the terms in the expression to be simplified (The other squares
may be filled with 0's).
• Pairs of 1's on the map which are adjacent are combined using the theorem
Y(X+X') = Y where Y is any Boolean expression (If two pairs are also adjacent,
then these can also be combined using the same theorem).
The minimization procedure consists of recognizing those pairs and multiple pairs
->These are circled indicating reduced terms.
o Groups which can be circled are those which have two (2 1) 1's, four (22)
1's, and eight (23) 1's.
->Note that because squares on one edge of the map are considered adjacent to those
on the opposite edge, group can be formed with these squares.
->Groups are allowed to overlap.
The objective is to cover all the 1's on the map in the fewest number of groups and to
create the largest groups to do this.
Once all possible groups have been formed, the corresponding terms are identified.
->A group of two 1's eliminates one variable from the original minterm.
->A group of four 1's eliminates two variables from the original minterm.
->A group of eight 1's eliminates three variables from the original minterm, and so on.
->The variables eliminated are those which are different in the original minterms of
the group.
In any K-Map, each square represents a minterm. Adjacent squares always differ by just
one literal (So that the unifying theorem may apply: X + X' = 1). For the 2-variable case
(e.g.: variables X, Y), the map can be drawn as in Figure 2.2.4 (a). Two variable map is
the one which has got only two variables as input.
Figure 2.2.4 (a)

Equivalent Labeling
K-map need not follow the ordering as shown in the Figure 2.2.4(a). What this means is
that we can change the positions of m0, m1, m2, m3 of the above figure as shown in the
Figure 2.2.4 (b) and Figure 2.2.4(c).
Position assignment is the same as the default k-map positions. This is the one which we
will be using throughout this unit.
Figure 2.2.4 (b)

This figure is with changed positions of m0, m1, m2, m3.
Figure 2.2.4(c)
The K-map for a function is specified by putting a '1' in the square corresponding to a
minterm, a '0' otherwise.
Grouping/Circling K-maps
The power of K-maps is in minimizing the terms, K-maps can be minimized with the help
of grouping the terms to form single terms as shown in Figure 2.2.4 (d). When forming
groups of squares, observe/consider the following:
• Every square containing 1 must be considered at least once.
• A square containing 1 can be included in as many groups as desired
A group must be as large as possible.
Figure 2.2.4 (d)
• If a square that is containing 1 which cannot be placed in a group, then leave it out
to include in final expression.
• The number of squares in a group must be equal to 2(pair), 4(quad), 8(octet).
The map is considered to be folded or spherical; therefore squares at the end of a row or
column are treated as adjacent squares.
The simplified logic expression obtained from a K-map is not always unique.
Groupings can be made in different ways as shown in Figure 2.2.4(e).
Before drawing a K-map the logic expression must be in canonical form.

Figure 2.2.4 (e)
In the next few pages we will see some examples of grouping.
2-Variable K-Map:
Example - F= X'Y+XY
In this example we have the equation as input, and we have one output function. Draw the
k-map for function F with marking 1 for X'Y and XY positions. Now combine two 1's as
shown in Figure 2.2.4 (f) to form the single term. As you can see X and X' get canceled
and only Y remains F = Y
Figure 2.2.4 (f)
Example - X'Y+XY+XY'
In this example we have the equation as input, and we have one output function. Draw the
k-map for function F with marking 1 for X'Y, XY and XY positions. Now combine two
1's as shown in Figure 2.2.4(g) to form two single terms.
F=X+Y
Figure 2.2.4(g)
3-Variable K-Map
There are 8 minterms for 3 variables (X, Y, Z). Therefore, there are 8 cells in a 3-variable
K-map. One important thing to note is that K-maps follow the gray code sequence, not
the binary one.
Using gray code arrangement ensures that minterms of adjacent cells differ by only one
literal.
Each cell in a 3-variable K-map has 3 adjacent neighbours. In general, each cell in an n-
variable K-map has n adjacent neighbours as shown in Figure 2.2.4(h)
Figure 2.2.4(h)
There is wrap-around in the K-map
• X'Y'Z' (m0) is adjacent to X'YZ' (m2)
XY'Z' (m4) is adjacent to XYZ' (m6) as shown in Figure 2.2.4(i)
Figure 2.2.4(i)
Example
F = XYZ'+XYZ+X'YZ
F = XY + YZ
Example
F(X, Y, Z) = (1, 3, 4, 5, 6, 7)
F=X+Z
4-Variable K-Map
There are 16 cells in a 4-variable (W, X, Y, Z) K-map as shown in the Figure 2.2.4 (j).
Figure 2.2.4(j)
There are 2 wrap-arounds: a horizontal wrap-around and a vertical wrap-around. Every

cell thus has 4 neighbours. For example, the cell corresponding to minterm m0 has
neighbours m1, m2, m4 and m8 as shown in Figure 2.2.4(k).
Figure 2.2.4(k)
Example
F (W, X, Y, Z) = (1, 5, 12, 13)
F=WXY'+W'Y'Z
Example
F (W, X, Y, Z) = (4, 5, 10, 11, 14, 15)
F = W'XY' + WY
Don’t Care:
In some digital systems, certain input conditions never occur during normal operations;
therefore the corresponding output never appears. Since the output does not appear it is
indicated by an X in the truth table.
X is called don’t care condition. So don’t cares can be treated as 0’s and 1’s which ever is
more convenient in the process of k-map simplification.
Consider the following truth table in which the output is low for all input entries from
1001 and ‘X’ from 1010 through 1111. The don’t care conditions are denoted by ’X’.
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
Here three don’t cares are treated as 1’s to get a quad which eliminates two
variables. The remaining don’t cares are treated as 0’s.
Steps to be followed to apply don’t care conditions:
1. For the given truth table, draw a K-map with 0’s, 1’s and don’t cares.
2. Encircle the actual 1’s on the K-map in the largest groups, by treating the don’t cares as
1’s.
3. After the actual 1’s have been included in groups discard the remaining don’t cares
visualizing them as 0’s.
2.2.5 Implementing Boolean Expressions Using NAND Gates:
The implementation of a Boolean function with NAND-NAND logic requires that the
function be simplified in the sum of product form. The relationship between AND-OR
logic and NAND-NAND logic is explained using the following example.
Consider the Boolean function: Y = A B C + D E + F
This Boolean function can be implemented using AND-OR logic as shown in

Figure 2.2.5 (a).
Figure 2.2.5 (a) AND-OR

Figure 2.2.5 (b) NAND-Bubbled OR
Figure 2.2.5 (b) shows the AND gates are replaced by NAND gates and the OR gate is
replaced by a bubbled OR gate. The implementation shown in Figure 2.2.5(b) is
equivalent to implementation in Figure 2.2.5 (a), because two bubbles on the same line
represent double inversion (complementation) which is equivalent to having no bubble on
the line. In case of single variable, F, the complemented variable is again complemented
by bubble to produce the normal value of F.
Figure 2.2.5(c) NAND-NAND
In Figure 2.2.5 (c), the output NAND gate is redrawn with the conventional symbol. The
NAND gate with same inputs gives complemented result; therefore F′ is replaced by
NAND gate with F input to its both inputs. Thus all the three implementations of the
Boolean function are equivalent.
From the above example we can summarize the rules for obtaining the NAND-NAND
logic diagram from a Boolean function as follows:
1. Simplify the given Boolean function and express it in sum of products
form (SOP form).
2. Draw a NAND gate for each product term of the function that has two
or more literals. The inputs to each NAND gate are the literals of the term. This
constitutes a group of first-level gates.
3. If Boolean function includes any single literal or literals draw NAND gates for
each single literal and connect corresponding literal as an input to the NAND
gate.
4. Draw a single NAND gate in the second level, with inputs coming from
outputs of first level gates.
2.2.6 Implementing Boolean Expressions Using NOR Gates:
The NOR function is a dual of the NAND function. For this reason, the implementation
procedures and rules for NOR-NOR logic are the duals of the corresponding procedures
and rules developed for NAND-NAND logic.
The implementation of a Boolean function with NOR-NOR logic requires that the
function be simplified in the product of sums form. In product of sums form, we
implement all sum terms using OR gates. This constitutes the first level. In the second
level all sum terms are logically ANDed using AND gates. The relationship between OR-
AND logic and NOR-NOR is explained using following example
Consider the Boolean function: Y = (A + B +C) (D + E) F

The Boolean function can be implemented using OR-AND logic, as shown in the
Figure 2.2.6 (a)
Figure 2.2.6 (a) OR-AND
Figure 2.2.6 (b) NOR-Bubbled AND
In Figure 2.2.6 (b) the OR gates are replaced by NOR gates and the AND gate is replaced
by a bubbled AND gate. The implementation shown in Figure 2.2.6 (b) is equivalent to
implementation shown in Figure 2.2.6 (a) because two bubbles on the same line represent
double inversion (complementation) which is equivalent to having no bubble on the line.
In case of single variable, F, the complemented variable is again complemented by bubble
to produce the normal value of F.
Figure 2.2.6(c) NOR-NOR
In Figure 2.2.6 (c), the output NOR gate is redrawn with the conventional symbol. The
NOR gate with same inputs gives complemented result, therefore, F is replaced by NOR
gate with F input to its both inputs. Thus all the three implementations of the Boolean
function are equivalent.
From the above example, we can summarize the rules for obtaining the NOR-NOR logic
diagram from a Boolean function as follows:
1. Simplify the given Boolean function and express it in product of sums

form(POS form)
2. Draw a NOR gate for each sum term of the function that has two or more
literals. The inputs to each NOR gate are the literals of term. This constitute a
group of first level gates.
3. If Boolean function includes any single literal or literals, draw NOR gate for
each single literal and connect corresponding literal as an input to the NOR
gate.
4. Draw a single NOR gate in the second level, with inputs coming from outputs
of first level gates
1. The simplified form of Boolean expression(X+Y+XY) (X+Z) is
(a) X+Y+Z (b) XY+YZ
(c)X+YZ (d) XZ+Y
2. The simplified form of Boolean expression(X +Y'+Z) (Z+ Y'+Z') is
(a) X' Y+Z' (b) X+Y' +Z
(c) X (d) XY+Z'
3. The canonical form of logical expression A+A' B is
(a)AB+AB'+A'B (b) A'B' +AB+AB'
(c) AB'+A'B+AB' (c) A'B+A B' +A'B'
4. The canonical form of logical expression (A+B') (B'+C) is
(a) (A+B'+C') (A+B'+C) (A'+B'+C)
(b) (A+B'+C') (A+B'+C) (A'+B+C')
(c) (A+B+C') (A+B'+C') (A'+B'+C)
(d) (A+B'+C) (A+B'+C) (A'+B'+C)
2.3 Combinational Circuits

A combinational circuit consists of input variables, logic gates and output variables. The
logic gates accept signals from the input variables and generate output signals. This
process transforms binary information from the given input data to the required output
data. Figure 2.3 shows the block diagram of a combinational circuit. As shown in the
figure the combinational circuit accepts n input binary variables and generates m output
variables depending on the logical combination of gates.
Figure 2.3
In this section we shall discuss about the functions of Half Adder, Full Adder, Half
Subtractor, Full Subtractor, Parallel Binary Adder, BCD Adder, Encoders, Decoders,
Multiplexers and Demultiplexers.
2.3.1 Half Adder
Half adder is a logic circuit that finds the arithmetic sum of two binary digits at a
time. Its logic circuit is shown in Figure 2.3.1(a).
Figure 2.3.1(a) Half Adder
The outputs of the XOR and AND gates produces the sum and carry respectively.
THE TRUTH TABLE:
A B SUM CARRY
A B
A.B
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Map for SUM

Map for CARRY
CARRY = A . B
The input variables of half adder are augend and addend. The output variables are sum
and carry. It is necessary to specify two output variables, because the sum of 1+1=10. Let
A & B be input variables SUM and CARRY be output variables.
The output ‘CARRY’ represents an AND function. The output SUM represents exclusive
OR function. The Boolean functions of the two outputs are
SUM =A B and
CARRY = A . B
2.3.2 Full Adder
When two binary numbers are added a carry may be generated onto the subsequent bit
positions. Hence, it is required to add three bits for the subsequent additions. A
combinational circuit that finds the arithmetic sum of three bits is called a Full adder. A
Full adder can be constructed using two half adders and an OR gate as shown in the
Figure 2.3.2(a).
Figure 2.3.2(a) Full Adder
Truth table:
A B C CARRY SUM
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Thus a full-adder is a combinational circuit that performs the arithmetic sum of three
input bits. It consists of three inputs and two outputs. Two of the input variables denoted
by A, B represents the two significant bits to be added. The third input C represents the
carry from the lower significant position. The two outputs are denoted by SUM and
CARRY. The Boolean expressions for SUM and CARRY outputs are given below.
2.3.3 Half Subtractor:
A Half subtractor is a combinational logic circuit which is used to find the difference
between two binary digits. Its logic circuit is shown in Figure 2.3.3(a).
Figure 2.3.3(a) Half Subtractor
TRUTH TABLE:
A B BORROW DIFFERENCE
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
Map for DIFFERENCE:
DIFFERENCE = A'B + AB'

=A B
Map for BORROW:
BORROW = A'B
A half subtractor consists of two input variables A and B (minuend and subtrahend) and
two output variables DIFFERENCE and BORROW. The DIFFERENCE output is
obtained by a 2-input XOR gate. The BORROW output is obtained by the expression
A'B
Hence DIFFERENCE = A B
BORROW = A'B
2.3.4 Full Subtractor:
A full subtractor (Figure 2.3.4 (a)) is a combinational circuit that performs a subtraction
between two bits taking into account that a 1 may have been borrowed by a lower
significant stage.
Figure 2.3.4 (a) Full Subtractor

This circuit has three inputs and two outputs. The three inputs A, B and C denote the
minuend, subtrahend and previous borrow respectively. The two outputs DIFFERENCE
and BORROW represent the difference and borrow, respectively. The truth table for the
circuit is as follows.
A B C BORROW DIFFERENCE
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
The Boolean functions for the two outputs of the full subtractor are derived in the K-map
as shown below.
Map for BORROW
BORROW = A'C + A'B + B
Map for DIFFERENCE
2.3.5 Parallel Binary Adder:
A parallel binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers in parallel. It consists of full adders connected in cascade, with the output carry
from one full adder connected to the input carry of the next full adder. Figure 2.3.5 shows
the circuit diagram of a 4-bit parallel binary adder.
Figure 2.3.5 Parallel Binary Adder
The augend bits of A and the addend bits of B are designated by subscript number from
right to left, with subscript 0 denoting the low-order bit. The carries are connected in a
chain through the full adders. The input carry to the adder is C 0 and the output carry is C4.
The S outputs generate the required sum bits. An n-bit parallel binary adder requires n full
adders.
The following example illustrates the parallel binary addition
2.3.6. BCD adder
A BCD adder is a circuit that adds two BCD digits and produces a sum digit also in BCD.
BCD numbers use 10 digits, 0 to 9 which are represented in the binary form 0000 to
1001, i.e. each BCD digit is represented as a 4-bit binary number. When we write BCD
number say 526, it can be represented as
5 2 6
0101 0010 0110

Here, we should note that BCD cannot be greater than 9.
The addition of two BCD numbers can be best understood by considering the two cases
that occur when two BCD digits are added.
Sum Equals 9 or less with carry 0 :
Let us consider additions of 3 and 6 in BCD.
6 0110 BCD for 6
+3 0011 BCD for 3
_____ _____
9 1001 BCD for 9
The addition is carried out as in normal binary addition and the sum is 1001,
which is BCD code for 9.
Sum greater than 9 with carry 0 :
Let us consider addition of 6 and 8 in BCD
6 0110 BCD for 6
+8 1000 BCD for 8
_____ ______
14 1110 Invalid BCD number
The sum 1110 is an invalid BCD number. This has occurred because the sum of
the two digits exceeds 9. Whenever this occurs the sum has to be corrected by the
addition of six (0110) in the invalid BCD number, as shown below
6 0110 BCD for 6
+8 1000 BCD for 8
_______ ______
14 1110 Invalid BCD number
+ 0110 add 6 for correction
_____
0001 0100 BCD for 14
After addition of 6, carry is produced into the second decimal position.

Going through these two cases of BCD addition we can summarize the BCD addition
procedure as follows:
1. Add two BCD numbers using ordinary binary addition.
2. If the 4-bit sum is equal to or less than 9, no correction is needed. The sum
is in proper BCD form.
3. If the 4-bit sum is greater than 9 or if a carry is generated from the 4-bit
sum, the sum is invalid.
4. To correct the invalid sum, add 01102 to the 4-bit sum. If a carry results
from this addition, add it to the next higher-order BCD digit.
Thus to implement BCD adder we require:
 A 4-bit binary adder for initial addition
 Logic circuit to detect sum greater than 9 and
 One more 4-bit adder to add 01102 if the sum is greater than 0 or carry is 1.
Figure 2.3.6 shows the block diagram of a BCD adder.
Figure 5.3.6 BCD adder
As shown in Figure 5.3.6 the two BCD numbers, together with input carry, are first
added in the top 4-bit binary adder to produce a binary sum. When the output carry is
equal to zero (i.e. when sum <=9 and Cout=0) nothing (zero) is added to the binary
sum. When it is equal to one (i.e. when sum>9 or Cout=1), binary 0110 is added to the
binary sum through the bottom 4-bit binary adder. The output carry generated from
the bottom binary adder can be ignored.
2.3.7 Encoders
An encoder (Figure 2.3.7(a)) converts an active input signal into a coded output
signal. There is n input lines of which only one is active. Internal logic within the
encoder converts this active input to a coded binary output with m bits.
Figure 2.3.7(a) Encoders
Decimal to BCD Encoder
The Figure 2.3.7 (b) shows a common type of encoder such as a Decimal to BCD
Encoder. The switches are push-button switches like those of a pocket calculator.
When button 3 is pressed, the C and D OR gates receive high inputs.
Therefore the output is
ABCD=0011
If button 5 is pressed, the output becomes
ABCD=0101
When switch 9 is pressed the output is
ABCD=1001
Figure 2.3.7 (b) Decimal to BCD Encoder
2.3.8 Decoders
A decoder is a combinational circuit that converts binary information from ‘n’ input lines
to a maximum of 2n unique output lines. The circuit in Figure 2.3.8(a) represents a 2-to-4
line decoder.
Figure 2.3.8 (a) 2-to-4 decoder.
The two inputs are decoded into 4 outputs each output representing one of the minterms
of the 2-input variables. The two inverters provide the complement of inputs and each of
the four AND gates generate one of the minterms.
The following is the truth table of the 2-to-4 line decoder with two inputs and 4 outputs.
A B D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
2.3.9 Multiplexer
A multiplexer is circuit with many inputs but only one output. By applying
control signals, we can steer any one of the inputs to the output. Figure 2.3.9 (a)
illustrates the general idea.
The circuit has n input signals, m control signals and one output signal.
Figure 2.3.9(a) Multiplexer
Figure 2.3.9 (b) 4-to-1 Multiplexer
A B Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Figure 2.3.9 (b) shows a 4-to-1 Multiplexer. A multiplexer is also called Data
selector because the output bit depends on the input data bit that is selected. The input
bits are labeled D0 through D4. Only one of these inputs is transmitted to the output,
depending on the control inputs AB.
For instance, when AB=00 the upper AND gate is enabled while all other AND
gates are disabled. Therefore, data bit D0 is transmitted to the output, giving
Y=D0. If D0 is low, Y is low; If D0 is high, Y is high. The point is that Y depends
only on the value of D0. If control bits are changed to AB=11, all gates are disabled
except the bottom AND gate. In this case D3 is the only bit transmitted to the output
and Y= D3. As you can see, the control bits determine which of the input data bits is
transmitted to the output.
2.3.10 Demultiplexer
A demultiplexer is a logic circuit with one input and may outputs. By applying control
signals, we can steer the input signal to one of the output lines. Figure 2.3.10(a) illustrates
the general idea. The circuit has 1 input signal, m control signals and n output signals.
Figure 2.3.10 (a) Demultiplexer

Figure 2.3.10 (b) 1x4 Demultiplexer
Figure 2.3.10 (b) shows a 1x4 Demultiplexer. The input bit is labeled as D. This data bit
(D) is transmitted to the data bit of the output lines. This depends on the value of AB, the
control inputs. When AB=00 the upper AND gate is enabled while all other AND gates
are disabled. Therefore the data bit (D) is transmitted only to the Y0 output, giving Y0 = D.
If D is low, Y0 is low. If D is high, Y0 is high. As you can see, the value of Y0 depends on
the value of D. All other outputs are in the low state. If the control bits are changed to
AB=11 all gates are disabled except the bottom AND gate. Then D is transmitted only to
the Y3 output and Y3=D.
1. A half adder adds………………………..bits.

(a) 16 (b) 10 (c) 8 (d) 2
2. Parallel binary adders are
(a)Combinational logic circuits (b) Sequential logic circuits
(c) Both of the above (d) None of the above
3. A combinational circuit which is used to change a decimal number into an equivalent
BCD number is
(a) Decoder (b) Encoder (c) Multiplexer (d) Demultiplexer
4. A combinational circuit which is used to change a BCD number into an equivalent

decimal number is
5. Multiplexer is also known as

(a) Data selector (b) Data distributor (c) Multiplexer (d) Encoder
6. A combinational circuit which is used to send data coming from a single source to two
or more separate destinations is called as:
2.4 Summary
With Boolean algebra you may be able to simplify a Boolean equation.

Given the truth table, you can identify the fundamental products that produce output 1s.
By ORing these products, you get the sum of products for the truth table. Therefore sum-
of-product equation always results in an AND-OR circuit or its equivalent NAND-NAND
circuit.
The Karnaugh method of simplification starts by converting a truth table into a karnaugh
map. Next, you encircle all the octets, quads and pairs. This allows you to write a
simplified Boolean equation and to draw a simplified logic circuit. When a truth table
contains don’t cares, you can treat them as 0s or 1s, whichever produces the greatest
simplification.
Half adder is a logic circuit with two inputs and two outputs. It adds two bits at a time,
producing a sum and a carry output.
Full adder is a logic circuit with three inputs and two outputs. The circuit adds three bits
at a time, giving a sum and a carry output.
Half subtractor is a logic circuit that subtracts two bits and produces their difference.
Full subtractor is a logic circuit that performs a subtraction between two bits, taking into
account borrowing by lower significant stage. It has three inputs and two outputs.
BCD adder adds two BCD digits and produces a sum digit also in BCD form.
Encoder is circuit that converts an active input signal into coded output form.
A decoder is a combinational circuit that converts binary information from ‘n’ input lines
to a maximum of 2n unique output lines.
A multiplexer is circuit with many inputs but only one output. By applying control
signals, we can steer any one of the inputs to the output.
Demultiplexer is a circuit with one input and many outputs. By applying control signals,
we can steer the input signal to one of the outputs.
2.5 Glossary
BCD adder A logic circuit that adds two BCD digits and produces a sum digit also in
BCD.
Decoder is a combinational circuit that converts binary information from ‘n’ input lines
to a maximum of 2n unique output lines.
Demultiplexer A circuit with one input and many outputs.
Don’t care conditions An input output condition that never occurs during normal
operations. Since the condition never occurs, you can use X in the truth table.
Encoder An circuit that converts an active input signal into coded output form.
Full adder A logic circuit with three inputs and two outputs. The circuit adds three bits at
a time, giving a sum and a carry output.
Half adder A logic circuit with two inputs and two outputs. It adds two bits at a time,
producing a sum and a carry output.
Half subtractor A logic circuit that subtracts two bits and produce their difference.
Full subtractor A logic circuit that performs a subtraction between two bits, taking into
account borrowing by lower significant stage. It has three inputs and two outputs.
Karnaugh map A map that shows all the fundamental products and the corresponding
output values of a truth table.
Multiplexer A circuit with many inputs but with only one output.
Octet Eight adjacent 1s in a karnaugh map.
Overlapping groups Using the same 1 more than once when looping the 1s of a
karnaugh map.
Pair Two horizontally or vertically adjacent 1s in a Karnaugh map..
Parallel binary adder A logic circuit with number of full adders connected in cascade.
The carry output of each adder is connected to the carry input of the next higher adder.
Product of sum equation The logical product of those fundamental sums that produce
output 1s in the truth table.
Quad Four horizontal, vertical, or rectangular 1s in a Karnaugh map.
Redundant group A group of 1s in a karnaugh map that is a part of other groups.
Sum of products equation The logical sum of those fundamental products that produce
output 1s in the truth table.
Truth table A table that shows all the input-output possibilities of a logic circuit.
2.6 References
1.”Digital logic and computer design” M.Moris Mano, prentice-hall of India private
limited.
2.”Digital principles and applications” Albert Paul Malvino, Tata McGraw-Hill book
company
3.”Digital computer fundamentals” Thomous c. Bartee, Tata McGraw-Hill book
company.
4.”Computer fundamentals- architecture and organization”, B.Ram, New age
international (P) Ltd.
2.7 Answers to Check Your Progress Questions

Check your progress1
1. c
2. b
3. a
4. a
Check your progress 2
1. d
2. a
3. b
4. a
5. a
6. d
Chapter 4
Combinational
Logic Design
The foundations for the design of digital logic circuits were established in the
preceding chapters. The elements of Boolean algebra (two-element “switching
algebra”) and how the operations in Boolean algebra can be represented
schematically by means of gates (primitive devices) were presented in Chapter
2. How switching expressions can be manipulated and represented in different
ways was the subject of Chapter 3, which also presented various ways of imple-
menting such representations in a variety of circuits using primitive gates.
With all of the tools for the purpose now in hand, we will be concerned in
this chapter with the design of more complex logic circuits. Circuits in which all
outputs at any given time depend only on the inputs at that time are called com-
binational logic circuits. The design procedures will be illustrated with impor-
tant classes of circuits that are now universal in digital systems.
The approach taken is to examine the tasks that a combinational logic cir-
cuit is intented to perform and then identify one or more circuits that can per-
form the task. One circuit may have some specific advantages over others, but
it may also have certain deficiencies. Often one factor can be improved, but
only at the expense of others. Some important factors are speed of operation,
complexity or cost of hardware, power dissipation, and availability in prefabri-
cated units. We will take up a number of different operations that are useful in
different contexts and show how appropriate circuits can be designed to carry
out these operations.
1 BINARY ADDERS
One of the most important tasks performed by a digital computer is the opera-
tion of adding two binary numbers.1 A useful measure of performance is speed.
Of course, speed can be improved by using gate designs that favor speed at the
1As discussed in Chapter 1, subtraction of two numbers is included in the meaning of addition, since sub-
traction is performed first by carrying out some operation on the subtrahend and then adding the result.
(What operation is first performed depends on the type of computer—either inverting the subtrahend or
taking its two’s complement, as discussed in Chapter 1.)
132
Binary Adders 133
X xi Si
S
Y yi Ci+1
Ci
(a) (b)
Figure 1 Binary addition. (a) General adder. (b) Full adder
of two 1-bit words.
expense of other measures, such as power consumption (using advanced

Schottky, for example, versus low-power Schottky designs). But for the logic de-
signer, the important question is how to design an adder to increase the speed,
regardless of the type of gate used. It may be that increased speed can be
achieved at the expense of increased circuit complexity. That is, there might be
several designs, each characterized by a certain speed and a certain circuit com-
plexity. A judgment must be made as to the acceptable trade-offs between them.
A symbolic diagram representing a binary adder is shown in Figure 1a. Each
open arrowhead represents multiple variables; in this case the inputs are two bi-
nary numbers. If each number has n digits, then each line shown really repre-
sents n lines. The sum of two n-bit numbers is an (n + 1)-bit number. Thus, S
(sum) represents n + 1 output lines. If this circuit were designed by the methods
of Chapter 3, we would require a circuit with n + 1 output functions, each one
dependent on 2n variables. The truth table for each of the output functions
would have 22n rows. Since n could easily be in the range 20–40, a different ap-
proach is obviously needed.
Full Adder
An alternative approach for the addition of two n-bit numbers is to use a sep-
arate circuit for each corresponding pair of bits. Such a circuit would accept the
2 bits to be added, together with the carry resulting from adding the less signif-
icant bits. It would yield as outputs the 1-bit sum and the 1-bit carry out to the
more significant bit. Such a circuit is called a full adder. A schematic diagram is
shown in Figure 1b. The 2 bits to be added are xi and yi , and the carry in is Ci.
The outputs are the sum Si and the carry out Ci+1. The truth table for the full
adder and the logic maps for the two outputs are shown in Figure 2.
The minimal sum-of-products expressions for the two outputs obtained
from the maps are
Si = xi'yiCi' + xi yi'Ci' + xi'yi'Ci + xi yiCi (1a)
Ci+1 = xi yi + xiCi + yiCi
= xi yi + Ci(xi + yi) (1b)
(Make sure you verify these.) Each minterm in the map of Si constitutes a prime
implicant. Hence, a sum-of-products expression will require four 3-input AND
Short gates and a 4-input OR gate. The carry out will require three AND gates and an
Even
134 Chapter 4 Combinational Logic Design
Ci Xi Yi Si Ci + 1 x x
0 1 0 1
0 0 0 0 0
0 0 1 1 0 00 1 00
0 1 0 0 1
0 1 1 1 0 01 1 01 1
1 0 0 1 0 yz yz
1 0 1 0 1 11 1 11 1 1
1 1 0 1 1
10 1 10 1
1 1 1 0 1
(a) (b) (c)
Figure 2 Truth table and logical maps of the full adder. (a) Truth table.
(b) Si map. (c) Ci+1 map.
OR gate. If we assume that each gate has the same propagation delay tp, then a
two-level implementation will have a propagation delay of 2tp.
In the map of the carry out, minterm m7 is covered by each of the three
prime implicants. This is overkill; since m7 is covered by prime implicant xiyi,
there is no need to cover it again by using it to form prime implicants with m5
and m6. If there is some benefit to it, we might use the latter two minterms as
implicants without forming prime implicants with m7. The resulting expression
for Ci+1 becomes
Ci+1 = xi yi + Ci(xi'yi + xi yi') = xi yi + Ci(xi ⊕ yi) (2)
(Confirm this result.) We already have an expression for Si in (1a), but it is in
canonic sum-of-products form. It would be useful to seek an alternative form
for a more useful implementation.
Exercise 1 With the use of switching algebra, confirm that the expression for
the sum in (1a) can be converted to
Si = xi ⊕ yi ⊕ Ci (3) ◆
Using the expressions for Si and Ci+1 containing XORs, confirm that we can
obtain the implementation of the full adder shown in Figure 3a. Notice that the
circuit consists of two identical XOR-AND combinations and an additional OR
gate. The circuit inside each dashed box is shown in Figure 3b; it is named a half
adder. Its only inputs are the 2 bits to be added, without a carry in. The two out-
puts are (1) the sum of the 2 bits and (2) the carry out.
Assuming that an XOR gate (implemented in a two-level circuit) has a
propagation delay of 2tp, the full adder in Figure 3a has a propagation delay of
4tp, both for the sum and for the carry. (Verify these claims.)
We will observe in the following section that the overall speed in the addition of
two n-bit binary numbers depends mainly on the speed with which the carry propa-
gates from the least significant bit to the most significant bit. Hence, reducing the
delay experienced by the carry of a full adder is a significant improvement. This is an
incentive in seeking other implementations of the full adder. In some of the cases in Short
Problem 1 at the end of the chapter, additional implementations of the full adder are Even
Binary Adders 135
Ci
xi Si
yi xi ⊕yi
Ci+1
xi ⋅yi
(a)
xi
xi ⊕yi
yi xi Si
xi ⋅yi yi Ci+1
(b) (c)
Figure 3 Full adder implemented with half adders. (a) Full adder.
(b) Half adder. (c) Half adder schematic diagram.
S1 S2 S3 S4
A1
A2 A3 A4
B1 B2 B3 B4
C1 = 0 C5
C2 C3 C4 Figure 4 Four-bit ripple-carry adder.
proposed in which the propagation delay for the carry is 2t p instead of 4t p. Henceforth,
for a full adder, we will assume that the propagation delay of the carry is 2tp.
Ripple-Carry Adder
The problem of adding two multidigit binary numbers has the following form.
Two n-bit binary numbers are available, with all digits being presented in par-
allel. The addition is performed by using a full adder to add each correspond-
ing pair of digits, one from each number. The full adders are connected in
tandem so that the carry out from one stage becomes the carry into the next
stage, as illustrated for the case of four-digit numbers in Figure 4. Thus, the
carry ripples through each stage. For binary addition, the carry into the first
(least significant) stage is 0. The last carry out (the overflow carry) becomes the
most significant bit of the (n + 1)-bit sum.
Since the carry of each full adder has a propagation delay of 2tp, the total
delay in carrying out the sum of two n-bit numbers is 2ntp. Not every pair of two
n-bit numbers will experience this much delay. Take the following two numbers
as an example:
Short 101010
Even 010101
Ai
Bi Ci+2
Ai+1
Bi+1
Ci+1
Ci
Si Si+1
Figure 5 Carry-lookahead circuit schematic.
Assuming that the carry into the first stage is zero, no carries are generated at
any stage in taking the sum. Hence, there will be no carry ripple, and so no
propagation delay along the carry chain.
However, to handle the general case, provision must be made for the worst
case; no new numbers should be presented for addition before the total delay
represented by the worst case. The maximum addition speed, thus, is limited by
the worst case of carry propagation delay.
Carry-Lookahead Adder
In contemplating the addition of two n-digit binary numbers, we were appalled
by the thought of a single combinational circuit with all those inputs. So we con-
sidered the repeated use of a simpler circuit, a full adder, with the least possi-
ble number of inputs. But what is gained in circuit simplicity with this approach
is lost in speed. Since the speed is limited by the delay in the carry function,
some of the lost speed might be regained if we could design a circuit—just for
the carry—with more inputs than 2 but not as many as 2n. Suppose that several
full-adder stages are treated as a unit. The inputs to the unit are the carry into
the unit as well as the input digits to all the full adders in that unit. Then per-
haps the carry out could be obtained faster than the ripple carry through the
same number of full adders.
These concepts are illustrated in Figure 5 with a unit consisting of just two
full adders and a carry-lookahead circuit. The four digits to be added, as well as
the input carry Ci, are present simultaneously. It is possible to get an expression
for the carry out, Ci+2, from the unit by using the expression for the carry of the
full adder in (2).
For reasons which will become clear shortly, let’s attach names to the two
terms in the carry expression in (2), changing the names of the variables to A
and B from x and y in accordance with Figure 5. Define the generated carry Gi
and the propagated carry Pi for the ith full adder as follows:
Gi = AiBi (4a)
Pi = Ai ⊕ Bi (4b)
Inserting these into the expression for the carry out in (2) gives
Short
Ci+1 = Ai Bi + Ci(Ai ⊕ Bi) = Gi + PiCi (5) Even
Binary Adders 137
A carry will be generated in the ith full adder (that is, Gi = 1) if Ai and Bi both
equal 1. But if only one of them is 1, a carry out will not be generated. In that
case, however, Pi will be 1. (Confirm this.) Hence, the carry out will be Ci+1 =
Ci. We say that the carry will be propagated forward.
The expression for the carry out in (5) can be updated by changing the
index i to i + 1:
Ci+2 = Gi+1 + Pi+1Ci+1 = Gi+1 + Pi+1(Gi + PiCi)

= Gi+1 + Pi+1Gi + Pi+1PiCi (6)
The last expression can be interpreted in the following way. A carry will appear
at the output of the unit under three circumstances:
• It is generated in the last stage: Gi+1 = 1.

• It is generated in the first stage, Gi = 1, and propagated forward: Pi+1 = 1.
• The input carry Ci is propagated through both stages: Pi = Pi+1 = 1.
Obviously, this result can be extended through any number of stages, but the
circuit will become progressively more complicated.
Exercise 2 Extend the previous result by one more stage and write the ex-
pression for Ci +3. Then describe the ways in which this carry out can be 1.
Confirm your result using the general result given next. ◆
Extending the design to j stages, the expression in (6) becomes
Ci+j+1 = Gi+j + Pi+jGi+j–1 + Pi+jPi+j–1Gi+j–2 + ... + (Pi+jPi+j–1 ... Pi)Ci (7)
This expression looks complicated, but it is easy to interpret. Since the carry out
Ci+j+1 = 1 if any one of the additive terms on the right is 1, the carry out from
the unit will be 1 for several possibilities. Either it is generated in the last (jth)
stage of the unit, or it is generated in an earlier stage and is propagated through
all succeeding stages, or the carry into the unit is propagated through all the
stages to the output.
The greater the number of full-adder stages included in a unit, the greater
the improvement in speed—but also the greater the complexity of the carry-
lookahead circuit. There is an obvious trade-off between the two. Consider a
unit of four stages. This unit is to add two 4-bit words A and B. Each stage can
be considered as having a sum circuit (S) and a separate carry circuit (C). The
sum circuit of each stage has as inputs the carry from the preceding stage and
the corresponding bits of the A and B words. The inputs to the carry network of
each stage consist of all the bits of the A and B words up to that stage and the
carry—not just from the preceding stage, but from the input to the whole unit.
Thus, if the first stage is stage i, the inputs to the carry circuit of stage i + 2 are:
Ai, Ai+1, Ai+2, Bi, Bi+1, Bi+2, and Ci.
Exercise 3 Draw a schematic diagram for a three-stage unit using rectangles

Short to represent the sum and carry circuits of each stage. (Let the first stage be 1 in-
Even stead of the general i.) ◆
Gi+3
Pi+3
Gi+2
Pi+3
Pi+2
Gi+1
Pi+3 Ci+4
Pi+2
Pi+1
Gi
Pi+3
Pi+2
Pi+1
Pi Figure 6 Four-stage carry-lookahead
Ci circuit.
Ak
Pk = Ak⊕Bk
Bk
G k = A k⋅ B k Figure 7 Half adder for generated and propagated

carries.
A circuit implementation of the carry network of the last stage in a four-

stage unit is shown in Figure 6. Except for Ci, the carry into the unit, all other
inputs to the AND gates are generated carries and propagated carries from the
various stages of the unit. These generated and propagated carries are pro-
duced by the half-adder circuits in Figure 7.
A semi-block diagram of the four-stage carry-lookahead adder is shown in
Figure 8. (Note that pins that carry the same label in different subcircuits are
assumed to be connected.) Since each propagated carry P i+j is the output of an
XOR gate, the overall propagation delay of the carry circuit having the design
of Figure 7 is 4tp. However, all generated and propagated carries, Gi+j and Pi+j,
of all units become available within 2tp after the two words are first presented
for addition, as evident from Figure 6. Hence, in all carry-lookahead units be-
sides the first, the propagation delay of the carry network is only 2tp.
Exercise 4 Suppose that a carry-lookahead adder is to have k 4-bit units to

carry out the addition of two 4k-bit words. From the preceding discussion, from
the diagram of Figure 8 implementing each unit, and from a consideration of
the first and last units, determine the propagation delay of this adder in terms
of tp, the propagation delay through one gate. (Don’t peek at the answer until
you do the work.)
Answer 2
2The sum of the delays through (a) the carry circuit of each unit (2tp each), (b) the sum circuit of the last
unit (2tp) since it depends on having the carry from the last unit, and (c) the extra delay in getting the Short
carry from the first unit. Total delay = (k + 1 + 1)2tp = (2k + 4)tp ◆ Even
Binary Adders 139
S1
C1
A1 P1 P1
B1 C1 G1 P2 S2
C2
C2
A2 P2 P2
P3 S3
C3
G2 G2 C3
P4 S4
A3 P3 P3 C4
C4
B3 G3 G3
C5
A4 P4 P4
B4 G4 G4
Figure 8 Schematic diagram of 4-bit carry-lookahead adder.
CO
B3
B2
B1
S3
B0
S2
S1
A3 S0
A2
A1
A0
CI
Figure 9 High-speed adder: 4-bit words.
If an adder has eight 4-bit units, the propagation delay through a carry-lookahead
adder will be 20tp.The corresponding ripple-carry adder will have a propagation delay
of 4 × 8 × 2tp = 64tp. Thus, the carry-lookahead adder will have an advantage of 320
percent in speed over the ripple-carry adder. All is not gravy, however: the speed ad-
vantage has been paid for in the cost of the added hardware.
Exercise 5 From a count on the number of gates in each implementation, esti-

mate the hardware disadvantage (in percent) of the carry-lookahead adder
compared with the ripple-carry adder. Compare the disadvantage with the 320
percent speed advantage. ◆
The circuits described here are available in IC packages. A single full adder,
for example, is available as a unit. A ripple-carry adder, as illustrated in Figure
4, and a carry-lookahead adder for 4-bit words, as shown in Figure 8, are avail-
able as MSI packages.
Externally, a package consisting of a ripple-carry adder of 4-bit words
Short would look the same as a package consisting of a carry-lookahead adder of 4-
Even bit words. The block diagram in Figure 9 illustrates such a package. There are
nine inputs: the carry in and four inputs per word. There are five outputs: the
carry out and the 4 bits of the sum. (The carry out becomes the most significant
bit of the sum if the circuit is used just to add 4-bit words, and not as part of an
adder of longer words.)
Binary Subtractor
In Chapter 1 two representations of signed binary numbers were studied: one’s
complement and two’s complement. Recall that when numbers are represented
in one of the complement forms, the only special treatment needed in the ad-
dition of a negative number with another positive or negative number is in the
final carry out. Thus, the adders studied in the previous section are suitable for
the addition of complement numbers if some additional circuitry is used to
process the final carry out. Also, binary subtraction can be performed using the
same adder circuits by negating the subtrahend.
Two’s-Complement Adder and Subtractor

Recall from Chapter 1 that when the addition of 2 two’s complement binary
numbers produces a final carry, it can be ignored. However, it is necessary to
detect the overflow that can occur when the result of the addition is out of
range.3 In Chapter 1 it was concluded that an arithmetic overflow could be de-
tected if the carry in and carry out of the most significant bit position are dif-
ferent. Thus, the overflow can be detected with one additional Exclusive-OR
gate. The two’s complement adder is not much different from the binary adder
for unsigned numbers.
What about subtraction? We already suggested that subtraction should be
carried out by complementing the subtrahend and adding. So the task is to de-
sign a circuit whose output is the two’s complement of the input, and use its
output as one input to an adder. Such a circuit can be designed easily, but why
should a system contain some hardware dedicated to addition and other hard-
ware dedicated to subtraction? If the only difference between these two circuits
is a circuit that computes the two’s complement, then why not design a circuit
where either addition or subtraction can be selected with one additional input?
When this additional input is, say, 0 the circuit performs addition, and when the
input is 1 the circuit performs subtraction. It sounds easy; a representation of
the circuit can be derived using the techniques of Chapter 3, but an elegant so-
lution exists that we describe next.
Examine the truth table of the Exclusive-OR operation and notice that it
can be viewed as a conditional inverter. If one input is 0, then the output is
identical to the second input. If one input is 1, then the output is the comple-
ment of the second input. This is convenient for producing the complement of
an input to our adder/subtractor circuit when we want to perform subtraction.
However, to compute the two’s complement of a binary number we have to add
3The range of binary numbers having n binary digits represented in two’s complement form is Short
–2n–1 ≤ m ≤ 2n–1 – 1. Even
Binary Adders 141
B3 B2 B1 B0
M
A3 A2 A1 A0
C4 C3 C2 C1 C0
S3 S2 S1 S0
overflow
Figure 10 Two’s complement adder/subtractor with overflow detection.
B3 B2 B1 B0
M
A3 A2 A1 A0
C4 C3 C2 C1 C0
FA FA FA FA 0
HA HA HA HA
S3 S2 S1 S0
Figure 11 One’s complement adder/subtractor.
1. Any ideas on how to do this without additional gates? (Think about it before
you continue.)
The full adder for the least significant bit has a carry input signal that can
be utilized to add the required 1. The design of our two’s complement
adder/subtractor circuit is complete; a version for adding 4-bit numbers is
shown in Figure 10. If the control signal M is 0, then the circuit performs A+B;
however, if M is 1, the circuit performs A − B.
One’s-Complement Adder and Subtractor

To perform subtraction in one’s complement we can use the Exclusive-OR cir-
cuit used in the two’s complement adder/subtractor. The only difference is that
we do not want to inject a carry into the least significant bit. One’s complement
addition requires the addition of 1 to the sum when a carry out from the most
significant bit position occurs. This can be accomplished using multiple half
Short adders as shown in Figure 11. Overflow detection for one’s complement addi-
Even tion is left as a problem for you.
data • communications dat

•
in channel out
• •
•
•
demultiplexer
multiplexer
Figure 12 A data communication problem.
Two’s complement addition is the most common method implemented in

modern computers due to its reduced circuit complexity compared with one’s
complement.
This is as far as we will go with the addition of multibit words; other adder
circuits are left for the problem set.
2 MULTIPLEXERS
Many tasks in communications, control, and computer systems can be per-
formed by combinational logic circuits. When a circuit has been designed to
perform some task in one application, it often finds use in a different applica-
tion as well. In this way, it acquires different names from its various uses. In this
and the following sections, we will describe a number of such circuits and their
uses. We will discuss their principles of operation, specifying their MSI or LSI
implementations.
One common task is illustrated in Figure 12. Data generated in one location
is to be used in another location; A method is needed to transmit it from one
location to another through some communications channel.
The data is available, in parallel, on many different lines but must be trans-
mitted over a single communications link. A mechanism is needed to select which
of the many data lines to activate sequentially at any one time so that the data this
line carries can be transmitted at that time. This process is called multiplexing. An
example is the multiplexing of conversations on the telephone system. A number
of telephone conversations are alternately switched onto the telephone line many
times per second. Because of the nature of the human auditory system, listeners
cannot detect that what they are hearing is chopped up and that other people’s
conversations are interspersed with their own in the transmission process.
Needed at the other end of the communications link is a device that will
undo the multiplexing: a demultiplexer. Such a device must accept the incoming
serial data and direct it in parallel to one of many output lines. The interspersed
snatches of telephone conversations, for example, must be sent to the correct
listeners.
A digital multiplexer is a circuit with 2n data input lines and one output
line. It must also have a way of determining the specific data input line to be se-
lected at any one time. This is done with n other input lines, called the select or Short
selector inputs, whose function is to select one of the 2n data inputs for connec- Even
Multiplexers 143
D0
0
D1
D2
D3
r
D4
D5
D6
D7
7
s0
s1
s2
Figure 13 Multiplexer with eight data inputs.
tion to the output. A circuit for n = 3 is shown in Figure 13. The n selector lines
have 2n = 8 combinations of values that constitute binary select numbers.
Exercise 6 Write expressions for each of the AND gate outputs in terms of the si
and Di inputs, confirming that the multiplier of Dk is the binary equivalent of k. ◆
When the selector inputs have the combination s2s1s0 = 011, for example, the
outputs of all AND gates except the one to which data line D3 is connected will be
0. All other inputs to that AND gate besides D3 will be 1. Hence, D3 appears at the
output of the circuit. In this way, the select inputs whose binary combination cor-
responds to decimal 3 have selected data input D3 for transmittal to the output.
Standard MSI packages are available as multiplexers. Figure 14a shows the
circuit for a package containing two separate multiplexers for n = 2. Practical
considerations not included in Figure 13 account for some of the features of
this circuit. The enable input E, for example, is used to control the period of
time that the multiplexer is operative. Thus, when the value of E is 1, the out-
Short put will be 0 no matter what the values of the select inputs. The circuit will be
Even operative only when the corresponding enable input is 0. (In other circuits, the
E1
1D0
1D1 output 1
1D2
1D3
s1
s0
1D0
2D0 1D1
1Q
1D2
1D3
2D1 2D0
2D1
output 2 2Q
2D2
2D3 2D3
S0
2D4 S1
EN
E2
(a) (b)
Figure 14 (a) Dual four-input multiplexer with enable. (b) Dual four-input multiplexer with
single enable.
enable signal is not inverted; in such cases, the circuit is operative when E = 1,
just the opposite of the case shown in Figure 14a.)
In addition, note from the figure that both the selector signals and their
complements are inputs to AND gates. The signal inputs themselves are ob-
tained after two inversions. This is especially useful if n is large. In this way, the
circuit that produces the select inputs has as load only a single gate (the in-
verter) rather than several AND gates. In Figure 14a the select inputs are com-
mon to both multiplexers, but each has its own enable. In other designs, the
enable can also be common. A schematic diagram of a dual four-input multi-
plexer (MUX) with a single enable is shown in Figure 14b.
The preferred gate form for many IC logic packages (for example, the
74LS00 and the 74LS10) is the NAND gate. Since the multiplexer design in ei-
ther Figure 13 or 14 is a two-level AND-OR circuit, a direct replacement of all
AND and OR gates by NAND gates will maintain the logic function, as dis-
cussed in the preceding chapter. In this way, the actual implementation of the Short
multiplexer is carried out with NAND gates. Even
Multiplexers 145
Multiplexers as General-Purpose Logic Circuits

It is clear from Figures 13 and 14 that the structure of a multiplexer is that of a
two-level AND-OR logic circuit, with each AND gate having n + 1 inputs, where
n is the number of select inputs. It appears that the multiplexer would constitute
a canonic sum-of-products implementation of a switching function if all the data
lines together represent just one switching variable (or its complement) and each
of the select inputs represents a switching variable.
Let’s work backward from a specified function of m switching variables for
which we have written a canonic sum-of-products expression. The size of multi-
plexer needed (number of select inputs) is not evident. Suppose we choose a mul-
tiplexer that has m − 1 select inputs, leaving only one other variable to
accommodate all the data inputs. We write an output function of these select in-
puts and the 2m–1 data inputs Di. Now we plan to assign m − 1 of these variables
to the select inputs; but how to make the assignment?4 There are really no re-
strictions, so it can be done arbitrarily.
The next step is to write the multiplexer output after replacing the select inputs
with m − 1 of the variables of the given function. By comparing the two expressions
term by term, the Di inputs can be determined in terms of the remaining variable.
EXAMPLE 1
A switching function to be implemented with a multiplexer is

f(x, y, z) = Σ(1, 2, 4, 7) = x'y'z + x'yz' + xy'z' + xyz
Since the function has three variables, the desired multiplexer will have 3 – 1 = 2 se-
lect inputs; half of the dual four-input MUX of Figure 14 will do. The expression for
the multiplexer output is
f = s1's0'D0 + s1's0D1 + s1s0'D2 + s1s0D3
There are no restrictions on how to assign the selector inputs to the variables of the
given function; let s1 = x and s0 = y arbitrarily. Then
f = x'y'D0 + x'yD1 + xy'D2 + xyD3
Comparing this with the original expression for the given function leads to
D0 = D3 = z
D1 = D2 = z'
The original function is thus implemented with a four-input multiplexer. ■
There are five other ways that the two select inputs could have been as-
signed to two of the three switching variables. No conditions need to be satis-
fied by the choice, so it is arbitrary. However, the specific outcome obtained for
the Di inputs depends on that initial choice.
Short
Even 4For a set of m − 1 variables, there are m! ways of assigning m − 1 quantities to specific variables.
s1 = w s0 = x
wx
00 01 11 10
y
00 1
f
z
01 1 O
yz
11 1 1 …………
10 1
(a) (b)
Figure 15 Multiplexer implementation of f = Σ(0, 1, 6, 7, 11).
Exercise 7 In the problem of Example 1, choose s1 = z and s0 = x. Determine

the Di.
Answer 5
Exercise 8 For practice, choose each of the remaining possible ways of assign-
ing select inputs to the switching variables, and then determine the required Di;
specify the external gates needed. ◆
To implement a switching function of m variables, we have seen that a mul-

tiplexer of m – 1 select inputs will work. It might be possible in some cases that
even a smaller multiplexer can be used. It should be expected that, when possi-
ble, this savings in MUX complexity must come at some other cost.
EXAMPLE 2
The function of four variables whose map is shown in Figure 15 is to be imple-

mented by a multiplexer. One with 4 – 1 = 3 select variables is always possible.
However, let’s explore the possibility of using a multiplexer with only two select
variables to implement this function.
Arbitrarily assign the two select inputs s1 and s0 to w and x. The expression
for the output of the multiplexer is the same one given in Example 1, since this
one has the same dimensions. For wx = s1s0 = 00, that expression reduces to D0.
But for the values wx = 00, the expression that covers the 1’s in the map is y'z'
+ y'z = y'. Hence, D0 = y'. Similarly, in the 01 column of the map, the expression
reduces to D1 and the map gives yz + yz' = y; hence, D1 = y. In the same way,
from the 11 column we find D3 = 0 and from the 10 column D2 = yz. (Confirm
these.) The rather simple circuit is shown in Figure 15b. We find that to imple-
Short
5D = D3 = y, D1 = D2 = y' ◆ Even
0
Decoders and Encoders 147
ment a certain specific function of four variables, a multiplexer of order lower

than 3 can be used, at the cost of an additional AND gate. (The inverter would
be necessary even with a higher-order multiplexer, so it does not count as ad-
ditional cost.) ■
Exercise 9 In the preceding example, suppose that s 1 and s 0 are identified

as y and z instead of w and x. Determine expressions for the data inputs in
terms of w and x, and specify the external hardware that will be needed be-
sides the multiplexer. Note the difference in complexity for the two choices
of select inputs.
Answer 6
In the implementation of an arbitrary switching function, different choices

for the select inputs lead to different amounts of external hardware for a
smaller-than-normal multiplexer. Unfortunately, short of trying them, there is
no way to determine which choice will be most economical.
3 DECODERS AND ENCODERS

The previous section began by discussing an application: Given 2n data signals,
the problem is to select, under the control of n select inputs, sequences of these
2n data signals to send out serially on a communications link. The reverse op-
eration on the receiving end of the communications link is to receive data seri-
ally on a single line and to convey it to one of 2n output lines. This again is
controlled by a set of control inputs. It is this application that needs only one
input line; other applications may require more than one. We will now investi-
gate such a generalized circuit.
Conceivably, there might be a combinational circuit that accepts n in-
puts (not necessarily 1, but a small number) and causes data to be routed to
one of many, say up to 2 n , outputs. Such circuits have the generic name de-
coder. Semantically, at least, if something is to be decoded, it must have pre-
viously been encoded, the reverse operation from decoding. Like a
multiplexer, an encoding circuit must accept data from a large number of
input lines and convert it to data on a smaller number of output lines (not
necessarily just one). This section will discuss a number of implementations
of decoders and encoders.
Demultiplexers
Refer back to the diagram in Figure 12. The demultiplexer shown there is a
single-input, multiple-output circuit. However, in addition to the data input,
there must be other inputs to control the transmission of the data to the ap-
propriate data output line at any given time. Such a demultiplexer circuit
0 = D1 = w'x', D2 = w'x, D3 = w ⊕ x; three AND gates and one XOR gate, in addition to a four-input
Short 6D
Even MUX. ◆
data input
x
0 D0
1 D1
2 D2
3 D3
4 D4
Control Data
5 D5 Inputs Outputs
C2 C1 C0 D0 D1 D2 D3 D4 D5 D6 D7
6 D6 0 0 0 x 0 0 0 0 0 0 0
C0 0 0 1 0 x 0 0 0 0 0 0
0 1 0 0 0 x 0 0 0 0 0
7 D7
0 1 1 0 0 0 x 0 0 0 0
C1 1 0 0 0 0 0 0 x 0 0 0
1 0 1 0 0 0 0 0 x 0 0
1 1 0 0 0 0 0 0 0 x 0
C2
1 1 1 0 0 0 0 0 0 0 x
(a) (b)
Figure 16 A demultiplexer circuit (a) and its truth table (b).
having eight output lines is shown in Figure 16a. It is instructive to compare

this demultiplexer circuit with the multiplexer circuit in Figure 13. For the
same number of control (select) inputs, there are the same number of AND
gates. But now each AND gate output is a circuit output. Rather than each
gate having its own separate data input, the single data line now forms one
of the inputs to each AND gate, the other AND inputs being control inputs.
When the word formed by the control inputs C2C1C0 is the binary equiva-
lent of decimal k, then the data input x is routed to output Dk. Viewed in an-
other way, for a demultiplexer with n control inputs, each AND gate output
corresponds to a minterm of n variables. For a given combination of control in-
puts, only one minterm can take on the value 1; the data input is routed to the
AND gate corresponding to this minterm. For example, the logical expression
for the output D3 is xC2'C1C0. Hence, when C2C1C0 = 011, then D3 = x and all
other Di are 0. The complete truth table for the eight-output demultiplexer is Short
shown in Figure 16b. Even
array of 64 AND gates D0

D1
A0′A1′A2
…
0 A0′A1′A2B0 B1B2′
D14
A0 1
decoder A
A1 2
3 × 23
3
…
A2 4 A0 A1′A2
5
6 A0 A1′A2B0B1B2′
7 D46
…
B 0 B 1 B 2′
D63
0 1 2 3 4 5 6 7
decoder B
3 × 23
B0 B1 B2
Figure 17 Design of a 6-to-26-line

decoder from two 3-to-23-line decoders
with an interconnection matrix of 64 AND gates.
n-to-2n-Line Decoder
In the demultiplexer circuit in Figure 16, suppose the data input line is removed.
(Draw the circuit for yourself.) Each AND gate now has only n (in this case three)
inputs, and there are 2n (in this case eight) outputs. Since there isn’t a data input line
to control, what used to be control inputs no longer serve that function. Instead,
they are the data inputs to be decoded. This circuit is an example of what is called
an n-to-2n-line decoder. Each output represents a minterm. Output k is 1 whenever
the combination of the input variable values is the binary equivalent of decimal k.
Now suppose that the data input line from the demultiplexer in Figure 16 is
not removed but retained and viewed as an enable input. The decoder now op-
erates only when the enable x is 1. Viewed conversely, an n-to-2n-line decoder
with an enable input can also be used as a demultiplexer, where the enable be-
comes the serial data input and the data inputs of the decoder become the con-
trol inputs of the demultiplexer.7
Decoders of the type just described are available as integrated circuits
(MSI); n = 3 and n = 4 are quite common. There is no theoretical reason why n
can’t be increased to higher values. Since, however, there will always be practi-
cal limitations on the fan-in (the number of inputs that a physical gate can sup-
port), decoders of higher order are often designed using lower-order decoders
interconnected with a network of other gates.
An illustration is given in Figure 17 for the design of a 6-to-26-line decoder
constructed from two 3-to-23-line decoders. Each of the component decoders
7In practice, the physical implementation of the decoder with enable is carried out with NAND gates. In
that case, it is the complements of the outputs in the circuit under discussion that are obtained, and the
Short enable input is inverted before it is applied to the NAND gates. These are practical details that do not
Even change the principles described here.
2×4 3×8 4×16 5×32

A 4 8 16 32
two-input two-input two-input two-input
...
AND AND AND AND
...
B
...
gates gates gates gates
C
D
E
Figure 18 Design of tree decoder.
has eight outputs. Each of the outputs from the A decoder must be ANDed with
each of the outputs from the B decoder to yield one of the 64 outputs from the
complete decoder. Thus, in addition to the 8 three-input AND gates in each
component decoder, there are 64 two-input AND gates in the interconnection
network. Only two of these are shown explicitly in Figure 17.
Exercise 10 A 6-to-26-line decoder is to be designed using the structure of

Figure 16. Specify the number of AND gates and the total number of input lines
to all gates. Compare this with the design in Figure 17. ◆
Tree Decoder
When higher-order decoders are designed in a hierarchy of several stages of
lower-order ones, a practical difficulty with fan-out (number of gates driven
by one terminal) results. (By a hierarchy of stages we mean, for example, two
3 × 8 stages to form a 6 × 64 decoder, as in Figure 17; then two 6 × 64 stages to
form a 12 × 2 12 decoder; and so on.) Even in Figure 17, each gate in the com-
ponent decoders drives eight other gates. In the next level of the hierarchy,
each of the outputs from the gates in the next-to-last level will have to drive
64 other gates.
This problem is overcome, but only partially, by the decoder design illus-
trated in Figure 18, called a tree decoder. The first stage is a 2-to-4-line decoder.
A new variable is introduced in each successive stage; it or its inverse becomes
one input to each of the two-input AND gates in this stage. The second input to
each AND gate comes from the preceding stage. For example, one of the outputs
of the second stage will be AB'C. This will result in two outputs from the next
stage, AB'CD and AB'CD'. This design does avoid the fan-out problem in the
early stages but not in the later stages. Nevertheless, the problem exists only for
the variables introduced in those stages. Any remedies required will have to be
used for relatively few variables, as opposed to the large number needed by the
design of Figure 17.
Decoders as General-Purpose Logic Circuits: Code Conversion

Since each output from an n-to-2n-line decoder is a canonic product of literals,
simply ORing all the outputs produces a canonic sum of products. And since Short
every switching function can be expressed as a canonic sum of products, it fol- Even
Inputs: Outputs:
Excess-3 Seven-Segment
Decimal
Digit w x y z S1 S2 S3 S4 S5 S6 S7
0 0 0 1 1 1 1 1 1 1 1 0
1 0 1 0 0 0 0 0 1 1 0 0
2 0 1 0 1 1 0 1 1 0 1 1
3 0 1 1 0 0 0 1 1 1 1 1
4 0 1 1 1 0 1 0 1 1 0 1
5 1 0 0 0 0 1 1 0 1 1 1
6 1 0 0 1 1 1 0 0 1 1 1
7 1 0 1 0 0 0 1 1 1 0 0
8 1 0 1 1 1 1 1 1 1 1 1
9 1 1 0 0 0 1 1 1 1 0 1
Figure 19 Excess-3 to seven-segment code conversion.
lows that every switching function can be implemented by an n-to-2n-line de-

coder followed by an OR gate. (If 2n exceeds the fan-in limitation of the OR
gate, additional levels of OR gates will be needed.) Indeed, if more than one
function of the same variables is to be implemented, the same decoder can be
used, with each function having its own set of OR gates.
One major class of logic circuits is known as a code converter. This is a cir-
cuit that accepts as inputs the digits of a word that expresses some information
in a particular code and that yields as outputs the digits of a word in a different
code. (See Chapter 1 for an introduction to codes.) We will illustrate the use of
a decoder as a code converter by designing a circuit to convert from excess-3
code to seven-segment code. (These codes were given in Figure 4 and Exercise
12 in Chapter 1; they are repeated here in Figure 19.)
Assume that a 4-to-16-line decoder is available. Since there are only 10
valid excess-3 code words, only 10 of the 16 AND gate outputs ever become 1.
So only those 10 outputs from a 4-to-16-line decoder will be used. They are in-
dicated in Figure 19 by their decimal equivalents.
Figure 19 is the truth table for each of seven output functions (the Si) in
terms of the four input variables. The circuit external to the decoder will consist
of seven OR gates, one for each segment. Only one decision needs to be made:
Which outputs from the decoder should become inputs to each OR gate? This is
answered for each segment by listing the minterm numbers corresponding to
each code word for which that segment output has the value 1. The minterm lists
for the outputs corresponding to some of the segments are as follows:
S3 = Σ(3, 5, 6, 8, 10, 11, 12)
S4 = Σ(3, 4, 5, 6, 7, 10, 11, 12) (8)
S5 = Σ(3, 4, 6, 7, 8, 9, 10, 11, 12)
S6 = Σ(3, 5, 6, 8, 9, 11)
Short Only one of the OR gates (the one for S6) is shown in Figure 20; there should
Even be six others. Then, when an excess-3 code word corresponding to a decimal
0
w 1
x 2
3
decoder
y
4 × 10
4
z 5
6
7
8
9 3
2 4
7
1 5
6
Figure 20 Excess-3 to seven-segment code converter.
digit appears at the input, the appropriate segments will light up, displaying
the digit.
Exercise 11 Write the minterm lists for the three segments whose minterm
lists were not given in (8). Confirm the inputs to the OR gate in Figure 20. ◆
4 READ-ONLY MEMORY (ROM)

A circuit for implementing one or more switching functions of several variables
was described in the preceding section and illustrated in Figure 20. The compo-
nents of the circuit are
• An n × 2n decoder, with n input lines and 2n output lines
• One or more OR gates, whose outputs are the circuit outputs
• An interconnection network between decoder outputs and OR gate inputs
The decoder is an MSI circuit, consisting of 2n n-input AND gates, that produces
all the minterms of n variables. It achieves some economy of implementation, be-
cause the same decoder can be used for any application involving the same number
of variables. What is special to any application is the number of OR gates and the
specific outputs of the decoder that become inputs to those OR gates. Whatever else
can be done to result in a general-purpose circuit would be most welcome.
The most general-purpose approach is to include the maximum number of
OR gates, with provision to interconnect all 2n outputs of the decoder with the
inputs to every one of the OR gates. Then, for any given application, two things
would have to be done:
• The number of OR gates used would be fewer than the maximum number,
the others remaining unused.
• Not every decoder output would be connected to all OR gate inputs.
This scheme would be terribly wasteful and doesn’t sound like a good idea.
Instead, suppose a smaller number, m, is selected for the number of OR Short
gates to be included, and an interconnection network is set up to interconnect Even
Read-Only Memory (ROM) 153
1
x1 z1
x2 z2
x3 z3
2n × m
...
...
...
mi
xn zm
2n
n inputs m output
n × 2n 2n × m
decoder interconnection
array
Figure 21 Basic structure of a ROM.
the 2n decoder outputs to the m OR gate inputs. Such a structure is illustrated

in Figure 21. It is an LSI combinational circuit with n inputs and m outputs that,
for reasons that will become clear shortly, is called a read-only memory (ROM).
A ROM consists of two parts:
• An n × 2n decoder
• A 2n × m array of switching devices that form interconnections between the
2n lines from the decoder and the m output lines
The 2n output lines from the decoder are called the word lines. Each of the 2n
combinations that constitute the inputs to the interconnection array corresponds to a
minterm and specifies an address. The memory consists of those connections that are
actually made in the connection matrix between the word lines and the output lines.
Once made, the connections in the memory array are permanent.8 So this mem-
ory is not one whose contents can be changed readily from time to time; we “write”
into this memory but once. However, it is possible to “read” the information already
stored (the connections actually made) as often as desired, by applying input words
and observing the output words. That’s why the circuit is called read-only memory.9
Before you continue reading, think of two possible ways in which to fabri-
cate a ROM so that one set of connections can be made and another set left un-
connected. Continue reading after you have thought about it.
The one-time “writing” into memory can be done as follows:
• A ROM can be almost completely fabricated except that none of the con-
nections are made. Such a ROM is said to be blank. Forming the connections
for a particular application is called programming the ROM. In the process
of programming the ROM, a mask is produced to cover those connections
that are not to be made. For this reason, the blank form of the ROM is called
mask programmable.10
8In certain designs, it is possible for the connections to be erasable; this will be described shortly.
9Although “memory” appears in its name, a ROM does not have memory in the usual sense. As will be
described in Chapters 5 and 6, memory is a characteristic of sequential, but not combinational, circuits.
Short 10The mask, requiring minute attention, is expensive to produce. Hence, mask-programmable ROMs are
Even used only when the cost is justified by very large production runs.
x1 x2 z1 z2 z3 m0
m1
0 0 1 0 1
0 1 0 1 0 m2
1 0 1 1 1 m3
1 1 0 0 1
z1 z2 z3
(a) (b)
Figure 22 A ROM truth table and its program.
• A ROM can be completely fabricated such that all potential connections

have been made. Such a ROM is also said to be blank. Programming the
ROM for a specific application in this case consists of opening those connec-
tions that are unwanted. In this case, the blank ROM is said to be field pro-
grammable (designated PROM). The connections are made by placing a fuse
or link at every connection point. In any specific application, the unwanted
connections are opened or “blown out” by passing pulses of current through
them. A measure of PROM cost is the number of fusible links, 2n × m.11
Once a ROM has been programmed, an input word x1x2 ... xn activates a spe-
cific word line corresponding to the minterm formed by the specific values of
the xi. The connections in the output matrix result in the desired output word.
EXAMPLE 3
Figure 22a gives the truth table for the interconnection matrix of a 22 × 3 ROM. The
truth table leads to the ROM program represented by the solid dots at the inter-
sections of the input and output word lines in Figure 22b. Each input word defines
an output word, as required by the truth table. If the input word is 01 (correspond-
ing to minterm m1), for example, only output line z2 will be activated because that
is the only connection with m1 in the connection matrix. Hence, the output word will
be 010, as confirmed also from the truth table. (Confirm from the truth table that
the rest of the program is correct.) ■
Exercise 12 A ROM is to be programmed to implement the conversion from

excess-3 to seven-segment code whose table was given in Figure 19. ROMs
come in standard sizes, and m = 7 is not one of them. The next larger standard
size is m = 8. Hence, the truth table will have six more rows and one more col-
umn than shown in Figure 19. (Specify what the entries in the truth table will
be for these extra rows and column.) Draw the appropriate number of crossing
lines for the input and output words. Using the truth table, program the ROM
by putting dots at the appropriate intersections of the two words. ◆
11Some PROMs are fabricated so that it is possible to restore them to their blank condition after they
have been programmed for a specific application; these are erasable PROMs, or EPROMs. They have Short
some clear advantages over the nonerasable kind, but their cost is correspondingly higher. Even
Other LSI Programmable Logic Devices 155
In Exercise 12 the number of entries in the truth table (which corresponds to

the number of links between the input and output words) is 2n × m = 16 × 8 = 128.
Of these, fully half represent don’t-cares. There are cases far worse than this;
sometimes as few as 1 percent of the links are used, resulting in considerable
“waste” in such ROM implementations. Another implementation that avoids this
waste would be most welcome. That’s the subject of the next section.
5 OTHER LSI PROGRAMMABLE LOGIC DEVICES

One way of looking at the ROM discussed in the previous section is as a device
with a specific structure (a set of AND gates and a set of OR gates) that a de-
signer can use to achieve desired outputs by making a few modifications. We
might say that the ROM has been “programmed” to produce its specific out-
puts. There are other structures that have this property, namely, programmabil-
ity. A generic name for them is programmable (or programmed) logic device
(PLD).
The ROM implements logic functions as sums of minterms. For n input
variables there are 2n minterms and, hence, 2n AND gates, each one with n in-
puts. As just discussed, in a number of important logic functions, many of the
AND gates and the links connecting them to the output OR gates are unused.
We will now discuss two implementations in which some of this “waste” is
avoided.
Programmed Logic Array (PLA)

The canonic sum-of-products implementation of a logic function is wasteful in
two ways: in the number of AND gates used (as many as there are minterms, 2n)
and in the number of inputs to each AND gate (n). Suppose we contemplate a
reduced (possibly minimal) sum-of-products implementation. Given a logic
function of n variables, the largest number of terms in a minimal sum-of-prod-
ucts expression representing this function is 2n–1—just half the number of
minterms. (See Problem 36 in Chapter 3.) That means a savings of 50 percent in
AND gates for the worst single-output case. Since there will be a reduced set of
inputs to the AND gates, this saving in gates is paid for by the need to program
not only the outputs of the AND gates but their inputs as well. The structure of
the circuit that results is called a programmable (or programmed) logic array
(PLA). It is illustrated in Figure 23 for the case n = 3 input variables, m = 4 out-
put functions, and four AND gates.
The diagram in Figure 23 is not a circuit diagram but a schematic diagram.
A single line is shown to represent all inputs to each AND and OR gate. The
number of input lines to each AND gate should be 2n, twice the number of in-
puts, to accommodate the possibility of connecting each variable or its comple-
ment to each AND gate. The number of input lines to each OR gate should
equal the number of AND gates, say p. (For simplicity and without fear of con-
fusion, even the gate symbols can be omitted.) The programmed connections
between the inputs and the AND gates, and between the AND-gate outputs and
Short the OR gates for a specific set of output functions are shown by the heavy dots
Even at the intersections.
A′C′
AB′
AC
B′C
A B C f1 f2 f3 f4
Figure 23 Structure of a PLA.
Maps of the four output functions and minimal sum-of-products expres-

sions are shown in Figure 24. In this example, a total of only four product terms
covers all functions, so only four AND gates are needed in the implementation.
Two sets of lines must be programmed: the input lines and the output lines. To
do this, we construct a programming table as follows:
• The implicants (product terms) are listed as row headings.
• In one set of columns, the headings are the input variables; this part of the
table must provide the information that tells which variables (or their com-
plements) are factors in each implicant.
• In a second set of columns, the headings are the output functions; this part of
the table must provide the information that indicates the output gate to
which each implicant (AND-gate output) is directed.
In the first set of columns, if a variable (uncomplemented) is present in a
particular row, the corresponding entry is 1; if its complement is present, the
entry is 0. If neither is present, the entry can be left blank, but it is preferable
to show some symbol instead; a dash is often used.
In the second set of columns, corresponding to the output functions, if a
particular function covers a particular implicant, then the corresponding entry
is 1; otherwise it could be left blank, but it is customary to enter a dot. To illus-
trate, consider row 4. Since the implicant is y'z, the entry in column z is 1, that
in column y is 0, and that in x is a dash. In the output columns, only f1 does not
cover implicant y'z; hence, the entry will be 1 in every column in row 4 except
the f1 column, where the entry is •. Confirm the remaining rows.
Once the programming is done, fabricating the links (connection points) in
a PLA is carried out in a similar manner as for the ROM. The PLA is either
mask programmable or field programmable (FPLA). In the case of the FPLA, Short
with p = the number of AND gates, there will be 2np links at the inputs and mp Even
Other LSI Programmable Logic Devices 157
x x x x
0 1 0 1 0 1 0 1
00 1 00 00 1 00 1
01 1 01 1 1 01 1 1 01 1 1
yz yz yz yz
11 1 11 1 11 11
10 1 10 10 1 10
f1 f2 f3 f4
Inputs Outputs
Product
Term x y z f1 f2 f3 f4
1: x'z' 0 – 0 1 • 1 • f1 = x'z' + xz
2: xy' 1 0 – • • • 1 f2 = xz + y'z
3: xz 1 – 1 1 1 • • f3 = x'z' + y'z
4: y'z – 0 1 • 1 1 1 f4 = xy' + y'z
Figure 24 Programming the PLA.
links at the outputs. For the example in Figure 23, the number of links is 4(6 +
4) = 40. Only 16 of these are to be kept, meaning that, during field program-
ming, 24 links are to be blown out. Typical PLAs have many more inputs, out-
puts, and AND gates than are shown in the example in Figure 23. (IC type
82S100, for example, has n = 16, m = 8, and p = 48.)
When a set of switching functions is presented for implementation with a PLA,
a design goal would be reduction in p (the number of AND gates). The economy
achieved is not derived from a reduction in the production cost of gates. (The pro-
duction cost of an IC is practically the same for one with 40 gates as it is for one
with 50 gates.) Rather, the removal of one AND gate eliminates 2n + m links; the
main source of savings is the elimination of a substantial number of links due to the
elimination of each AND gate. On the other hand, reduction of the number of
AND gates to a minimum does not mean that each function should be minimized
or that all implicants should be prime implicants. The implicants should be chosen
so that as many as possible of them are common to many of the output functions.
Programmed Array Logic (PAL)

A ROM has a large number of fusible links (m × 2n) because of the large num-
ber (2n) of AND gates. Programming of links is performed only on the outputs
from the AND gates. In a PLA, the number of links is drastically reduced by re-
ducing the number of AND gates. The latter is done by changing the expression
representing the switching function from a canonic sum-of-products form to a
sum of products with fewer terms. The price paid is the need to program not only
the outputs from the AND gates, but also the inputs to the AND gates. What
Short other possibility for programming is there beyond the two cases of (a) pro-
Even gramming the outputs of the AND gates and (b) programming both the inputs
Product Term Inputs Outputs

Number Function 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6
1 • • • • • 1
2 • • • • • 1
3 • • • • • 1
4 • • • • • 1
5 • • • • 1 •
6 • • • • 1 •
7 x1x2'x5x7x11'x12 1 0 – – 1 – 1 – – – 0 1 • • • 1 • •
8 • • • 1 • •
9 • • 1 • • •
10 • • 1 • • •
11 • 1 • • • •
12 • 1 • • • •
13 1 • • • • •
14 1 • • • • •
15 1 • • • • •
16 1 • • • • •
Figure 25 Programming table for a PAL example.
and the outputs? We’re sure you answered, “programming only the inputs.” This
is a possibility, but is it worthwhile?
In the case of the ROM, there is no need to program the inputs because, for
any function of n variables, there will be the same (large) number of AND
gates. In the same way, if the number of OR gates at the output could be fixed,
then programming the outputs of the AND gates could be avoided.
In many circuits with multiple outputs, even though the outputs are func-
tions of a large number of input variables, the number of product terms in each
output is small. Hence the number of AND gates that drive each OR gate is
small. In such cases, permanently fixing the number of OR gates and leaving
only the programming of the AND gate inputs for individual design might
make economic sense. The resulting circuit is called programmed array logic
(PAL).12 The number of fusible links in a PAL is only 2np. Standard PALs for
a number of low values of p exist. For example, the PAL16L8 has a maximum
of 16 inputs and 8 outputs.
A programming table for a PAL is similar to the one for a PLA. A case with
six outputs is illustrated in Figure 25. A ROM with 12 input variables would re-
quire 212 = 4096 AND gates. However, let’s assume that for some possible cases,
the canonic sum-of-products expression can be reduced to 16 implicants, only
one of which is shown in Figure 25. The entries in the table would have the same
meanings as those for the PLA. However, for the PAL, the output columns
would be fixed by the manufacturer on the basis of the number of AND gates
already connected to each OR gate.
In the present case, two of the output OR gates are each driven by four AND
gates; the remaining four OR gates are each driven by two AND gates. For any
Short
12PAL is a registered trademark of Advanced Micro Devices. Even
Chapter Summary and Review 159
given design problem, the first step is to obtain an appropriate sum-of-products

expression, just as in the case of a PLA implementation. The input connections are
indicated in the table as in the case of the PAL: an entry is a 1 if a variable appears
uncomplemented in an implicant, a 0 if it appears complemented, and a dash if it
does not appear at all. This is illustrated for one row in Figure 25. The number of
fusible links in this example is 2 × 12 × 16 = 384. This is 20 percent fewer than the
number of links of a PLA having the same dimensions. Typically, however, PLAs
have many more AND gates and so, for a PAL, the number of links would typi-
cally be many times more than the number for a comparable PLA.
Exercise 13 Suppose two of the rows of inputs in Figure 25 are as follows:

010–0––1––––
101––0––11––
What are the corresponding product terms? ◆
Further attention will be devoted to PLDs in Chapter 8. Attention will also be

given there to the use of hardware description languages in designs using PLDs.
CHAPTER SUMMARY AND REVIEW

In Chapter 3, designs were carried out with primitive gates in SSI circuits. This
chapter advanced the design process to more complex circuits implemented in
MSI units. The topics included were
• Binary adder
• Full adder
• Ripple-carry adder
• Carry-lookahead adder
• Binary subtractor
• Two’s complement adder and subtractor
• One’s complement adder and subtractor
• Multiplexer
• Data input
• Select input
• Implementation of general-purpose logic circuits with multiplexers
• Demultiplexer
• Data input lines
• Control input lines
• Decoder
• n × 2n-line decoder
• Tree decoder
• Implementation of general-purpose logic circuits with decoders
• Code conversion
• Read-only memory (ROM)
• n × 2n decoder
Short • 2n × m interconnection array
Even • Programming a ROM
• Mask-programmable ROM
• Field-programmable ROM
• Programmable logic device (PLD)
• Programmed logic array (PLA)
• Programmed array logic (PAL)
PROBLEMS
1 a. Analyze each of the full adder circuits shown in Figure P1 and write expressions for
the output of each intermediate gate.
b. Obtain logic expressions for the sum and carry circuit outputs.
c. Verify that these expressions are equivalent to the sum and carry functions in
equations (1) in the text.
2 a. A 4-bit carry-lookahead adder is to be designed. In equation (7) in the text for the
carry function, let i = 0 and let j range from 0 to 4. Write the resulting expressions for
C1, C2, C3, and C4.
b. Construct the logic diagram for the 4-bit carry-lookahead whose schematic diagram
is given in Figure 8.
3 A 4-bit binary number Y = y3y2y1y0 is to be multiplied by a 3-bit binary number X = x2x1x0.

Use two 4-bit adders and other gates that you might need to implement this operation, and
draw the corresponding diagram.
4 Prove formally that if the propagate variable Pi for a carry-lookahead adder is defined
as Ai + Bi instead of Ai ⊕ Bi, the sum and carry outputs of the adder will still be computed
correctly. (Give an informal proof also.) Which definition is better for implementation
purposes?
5 Design a circuit for overflow detection in the one’s complement adder/subtractor shown in
Figure 11.
6 a. Show the connections on a schematic diagram of a dual four-input multiplexer for im-
plementing the sum and carry functions of a full adder.
b. Repeat using a 3-to-23-line decoder.
7 Realize each of the following functions using an 8 × 1 multiplexer.
a. f = Σ(0, 1, 10, 11, 12, 13, 14, 15)

b. f = Σ(0, 3, 4, 7, 10)
c. f = Σ(0, 3, 4, 6, 7, 8, 12)
d. f = Σ(1, 2, 5, 8, 11, 12, 14)
8 Realize each of the functions in Problem 7 using half of a dual 4 × 1 multiplexer and the
minimum number of external gates.
9 Repeat Problem 7 using a 3-to-23-line decoder.
10 Use a dual four-input multiplexer to implement each of the following pairs of functions
with the fewest external gates.
a. f1 = Σ(0, 4, 5, 7, 9, 11), f2 = Σ(2, 3, 5, 6, 10, 13)

b. f1 = Σ(0, 4, 7, 10, 12, 14, 15), f2 = Σ(2, 7, 8, 9, 12, 13, 14, 15)
11 a. Show how to connect a 4-bit MSI adder to serve as a BCD-to-excess-3 code converter.
b. Repeat using a 4-to-10-line (BCD-to-decimal) decoder and four AND gates.
12 Design a BCD-to-decimal decoder using two 2-to-4-line decoders and a minimum of in- Short
terconnecting AND gates. Even
Problems 161
Ci+1
xi
yi
Ci
Si
Ci
(a)
xi
Si
xi yi
yi
Ci+1
Ci
Ci+1
Si
(b)
(c)
Ci
xi Si
yi
Ci+1
(d)
Figure P1
13 A circuit is to accept two 2-bit binary numbers x1x0 and y1y0 and emit the product as a 4-bit
binary number z3z2z1z0. (Review binary multiplication in Chapter 1 if you need to.)
a. The result is to be achieved by a (possibly) multilevel circuit with two-input gates.
Determine appropriate expressions for each output. How many levels of gates does
each output have?
b. Design a circuit using a 4-to-24-line decoder with external OR gates.
14 Examine late editions of manufacturers’ data books.
a. What is n for the largest n-to-2n-line decoders?
b. Note what the standard sizes of ROMs are.
c. What are some representative dimensions of a PLA chip?
Short d. What are some representative dimensions of a PAL?
Even e. Is there a BCD adder in a single MSI package?
15 A switching function of n variables is to be implemented by an n-to-2n-line decoder fol-

lowed by an external OR gate. The physical gate available for this purpose has both an OR
and a NOR output. (It is an ECL gate.) For practical reasons (to avoid fan-in problems), it
would be best to try to reduce the number of inputs to an external gate.
a. Describe how to implement the function using the available physical gate if the num-
ber of minterms contained in the function is more than 2n–1 = 2n/2.
b. Illustrate with the following function:
f = Σ(0, 1, 2, 3, 4, 5, 7, 8, 9, 10, 13, 14, 15)
16 a. Design a BCD-to-decimal decoder using the minimal number of two-input AND gates.
b. Repeat, using two 2-to-4-line decoders and a few interconnecting AND gates.
17 a. Use two identical n-to-2n-line decoders with enable inputs to construct an (n +1)-to-
2n-line decoder without enable. Show how the outputs are obtained.
b. Illustrate with two 2-to-4-line decoders.
18 Design an octal to binary encoder. This is a circuit with 8 inputs, xi, and 3 outputs, zi. Only
one of the outputs is 1 at any one time. Octal digit k is represented by xk = 1.
19 A decimal-digit code converter from 2-out-of-5 to seven-segment code is to be designed.
A number of different possibilities are to be explored, assuming that only valid code words
will occur as inputs.
a. Draw a circuit diagram using a complete 5 × 25 decoder design.
b. Assuming a design using discrete gates:
i. Draw a circuit for a sum-of-minterms design. (This would constitute a partial decoder.)
ii. The AND gates in the preceding design are five-input gates. Is it possible to use
the same structure but with two-input gates? Justify your answer.
iii. Carry out a minimal sum-of-products design that uses 11 AND gates and 7 OR
gates, each with no more than three inputs.
iv. Consider a minimal product-of-sums design. Is this more economical than the
minimal sum-of-products design?
v. Now suppose that, in addition to valid code words, invalid ones can also occur.
Modify the best of the preceding designs so that, whenever there is an invalid
code word, the symbol E (for error) is displayed.
20 The code converter in Problem 19 is to be designed with a ROM. The closest-size ROM
available is a 25 × 8. Construct the required programming table. Specify the number of links.
21 The code converter in Problem 19 is to be implemented with a PLA. A 5 × 8 PLA with 12
AND gates is available. Draw a programming diagram for implementing the desired code
converter. Specify the number of links.
22 a. Suppose the circuit in Problem 13 is to be implemented with a 24 × 4 PROM. Show
the programming table and draw an appropriate diagram.
b. Suppose instead that the circuit is to be implemented by a 4 × 4 PLA with 10 AND
gates. Show the programming diagram (in the form of Figure 23 in the text). Compare
the number of links with those of the PROM implementation. Construct the pro-
gramming table in the form of Figure 25 in the text.
c. Now suppose that the circuit is to be implemented by a PAL. Construct the pro-
gramming table in the form of Figure 25 in the text.
23 A combinational circuit having three inputs and six outputs is to be designed. The output
word is to be the square of the input word.
Short
a. Design the circuit using a ROM that has the smallest possible dimensions. Construct
the truth table and specify the number of links. Even
Problems 163
A B C D E f1 f2 f3 f4
(a)
10
A B C D E F f1 f2 f3 f4
(b)
Figure P24
b. Design the circuit using a PLA with the fewest number of product terms. Construct
the programming diagram and specify the number of links.
24 The programming diagrams for two PLAs are shown in Figure P24.
a. Write the equations of the outputs realized by each PLA. Specify the number of links.
b. The same functions are to be implemented with a ROM. Specify the dimensions of
the ROM and the number of links. Set up its programming table.
c. The same functions are to be implemented with a PAL. Is it possible to do so? If so,
Short
set up the programming table and specify the number of links. If it is not possible, ex-
Even
plain why not.
25 (Review Chapter 1 on Hamming codes if you need to.) Using an n-to-2n-line decoder (for
an appropriate n) and any additional logic:
a. Design the error-correcting logic for a single-error-correcting Hamming code assum-
ing 3 message bits in each code word. The outputs of the circuit shoud be
• E, indicating that an error has been detected
• IV, indicating that the MSG output is invalid (obviously, IV is 0 when no error, or
only a single error, has occurred)
• MSG, a 3-bit output that contains the corrected transmitted message in the cases of
zero and one error
b. Design the single-error-correcting and double-error-detecting (SEC-DED) logic for
an error-correcting Hamming code extended by the addition of a parity bit over all
(that is, message and parity) positions. Assume 3 message bits in each code word. The
output signals and their meanings are to be the same as in part a.
26 Explain in words the behavior of the diagram in Figure P26. (The open-headed arrows
represent multiple-bit inputs and outputs.)
control C
argument 2
B
sum
when: C= 0: pass A
when: C= 1: bit-by-bit argument 1
binary adder
complement
Figure P26
27 A microprocessor (µp) outputs three control signals that have the meanings given in the
following table. (No knowledge of µp is necessary to solve this problem.)
R' W' M/I'O'

0 1 1 µp wants to read memory
1 0 1 µp wants to write to memory
0 1 0 µp wants to read an input/output device
1 0 0 µp wants to write to an input/output device
1 1 × µp wants none of the preceding operations
a. Design a logic circuit using a suitable multiplexer and minimal additional logic to trans-
form these three signals into the following four signals, each representing an operation:
(M R)', (M W)', (IO R)', (IO W)'
When any of the operations is desired (not desired), the value of the corresponding
signal is to be 0 (1).
b. Design a multiplexer implementation to perform the inverse transformation.
28 The 4-bit lookahead unit shown in Figure P28a receives generate and propagate variables Short
from units 0 through 3 comprising a similar group. It also receives C, the carry input to unit Even
Problems 165
0 of the group. It computes C0, C1, and C2, which are the carry outputs from units 0, 1, and 2,
respectively. It also computes the generate and propagate variables, G and P, for the whole
group. The carry outputs are generated in parallel, not in ripple fashion.
G0 G
P0
P C
G1
P1
G2 S
C0 A
P2
G3 C1
P3 G
C2
B P
4-bit
lookahead 4-bit C4
unit adder
(a) (b)
Figure P28
a. Derive equations for all the outputs, and show the implementation.
b. Using 4-bit lookahead units of the above type and 4-bit adders of the type shown in
Figure P28b, draw the logic diagram for a 48-bit adder using a single-level lookahead.
(The open arrows represent multiple-bit inputs and outputs—in this case, 4 bits. A,
for example, stands for a vector of 4 bits: A0, A1, A2, A3.)
c. Repeat part b using two levels of lookahead, in which the G and P outputs of the
first-level lookahead units feed the Gi and Pi inputs of the second-level lookahead
units. Compare with respect to speed with the design of part b.
29 This problem concerns the design of a 4-bit lookahead subtractor (Figure P29).The 4-bit vec-
tor B (B3B2B1B0) is to be subtracted from 4-bit vector A. The borrow input C0 is 1 if and only if
the next lower unit is borrowing a 1 from this unit. The 4-bit vector D is the difference output,
and C4 is the borrow output. G and P are generate and propagate variables from the whole unit.
C0
A D
B G
C4
4-bit
lookahead
subtractor Figure P29
a. Give an expression for each output and show the implementation.

b. As in Problem 28, there will be more than one way to define the propagate variable.
Give these definitions and compare the differences in their implementation.
c. Suppose that multiple-bit subtraction is to be carried out. For this purpose, can 4-bit
lookahead units, of the type described in Problem 28 in the context of addition, be
used with 4-bit lookahead subtractors of the type defined here? Justify your answer.
Short d. Using 4-bit subtractors of the type described in this problem, and also suitable 4-bit
Even lookahead units, design a 24-bit lookahead subtractor.
30 An 8-input priority encoder (Figure P30) has eight request inputs: I(7. . . 0). A logic 1 on any
of these lines denotes the presence of a request from the corresponding source for some ser-
vice. The priority varies from the highest for 7 to the lowest for 0. Output LR (Local Request)
is 1 if and only if there is at least one request among the eight I inputs. If EI (Enable Input) is
1, the encoder identifies the request having the highest priority and outputs its 3-bit address on
A(0…2). If no request is active, it outputs a zero address. If the encoder is not enabled (EI = 0),
it outputs zeros on A. EO (Enable Output) is 1 if and only if the encoder is enabled (EI = 1) and
there is no request among the eight I inputs.
EI
A(7...0)
I(7...0)
LR
EO
priority
encoder Figure P30
a. Derive expressions for each output and simplify.

b. Design a 48-input priority encoder using 8-bit priority encoders of the type described
in this problem and minimal additional logic. Use a ripple configuration.
c. Considering the enable signals, EI and EO, as the equivalent of carry signals, derive ex-
pressions for the generate and propagate variables for the eight-input priority encoder.
As in Problem 29, give two expressions for the propagate variable and pick the “better”
one. Does it require extra logic to compute the generate and propogate variables, or are
they available from the outputs of the eight-input priority encoder described here?
d. Using suitable 4-bit lookahead units, design a lookahead implementation for a 48-
input priority encoder and compare its speed with the design in part b.
e. Suppose that the eight-input priority encoder has disable signals, DI and DO, instead
of enable signals EI and EO. Repeat parts c and d considering the disable signals as
the equivalent of carry signals.
31 A BCD-to-seven-segment decoder has “blank” signals, BI and BO, to help suppress lead-
ing 0’s in integer displays and trailing 0’s in fraction displays. When BI is 1, if the input digit
is 0, all outputs should be 0; that is, the digit will be blanked. When BI is 0, there is no blank-
ing, but then BO is a blank signal to the next digit. A diagram is shown in Figure P31a.
I3–I0
a
BI BO f b
BCD-to-seven-segment g
decoder
e c
d
a b c d e f g (b)
(a)
Short
Figure P31 Even
Problems 167
a. Give expressions for the outputs BO, a, and f.

b. Design an 8-bit display with four digits each for the integer and fractional parts. The
least significant integer digit should never be blanked, even if the integer part of the
number is 0.
c. Considering sluggish human response times, the ripple implementation in part b
should be adequate. However for pedagogical purposes, suppose you wanted to de-
sign a lookahead implementation of the display, so that each digit would settle into
the blanked or unblanked state faster. Treating BI and BO as carry signals, give ex-
pressions for the generate and propagate variables for this decoder.
d. Suppose that, instead of the BI and BO pins, the decoder has DBI (“don’t blank
input”) and DBO (“don’t blank output”) pins. Treat these as the carry signals this
time, and repeat part c.
32 Prove formally that if the propagate variable Pi for a lookahead adder is defined as the
Boolean sum of Ai and Bi instead of their Exclusive-OR, the sum and carry outputs of the
adder will still be computed correctly. Give an informal proof also. Which definition is better
for implementation purposes?
33 A 4-bit data selector has four data inputs, D3…D0, and two select inputs, s1s0. The output
z is one of the data inputs as selected by the select inputs. Thus, z = D2 when s1s0 = 10.
a. Draw an AND-OR diagram of the data selector.
b. Another circuit consists of two XOR gates. The inputs to XOR1 are two signals A
and B. The inputs to XOR2 are the output of XOR1 and a third signal C. Draw this
circuit and write its output in terms of A, B, and C.
c. Choose the select inputs and the data inputs in part a in terms of A, B, and C so that
the circuits in parts a and b will have the same outputs. If there is more than one
choice, show all of them.
34 a. Design a BCD adder using a ROM (and any other logic needed), assuming only legal
BCD words are used as input. Specify the dimensions of the ROM and show a
schematic diagram.
b. Describe the programming table and illustrate it (at least partially).
c. Specify the number of links.
Short
Even
2 Building Blocks
2.1 Comparators
There is often the need to compare two binary values.
This is done using a comparator.
A comparator determines whether binary values A and B are:

1. A = B
2. A < B
3. A > B
2.1.1 Equality
The XOR can be used to compare equality. It will give a 0 when the two
bits are equal and a 1 when they are unequal.
To get a HIGH for equality and a LOW for inequality an XNOR can be
used.
X Y XOR XNOR Comment

0 0 0 1 Equal
0 1 1 0 Not Equal
1 0 1 0 Not Equal
1 1 0 1 Equal
One XNOR compares one bit.
To compare multiple bits, we need a XNOR for each bit.
The circuit to compare two nibbles (4 bits) is shown below:
A0
B0
A1
B1
=
A2
B2
A3
B3
26
2.1.2 Integrated Circuit Comparators
Many integrated circuit comparators contain outputs for:

A=B
A<B
A>B
They are designed for cascading together and contain inputs for
A = B from the preceding stage
A < B from the preceding stage
A > B from the preceding stage
The 74LS85 is a TTL 4 bit magnitude comparator.
Q. How can we compare an 8 bit number?

A. By cascading two 7485 comparators.
One to compare the Least Significant Nibble.
One to compare the Most Significant Nibble.
A0 A0 A4 A0
A1 A1 A5 A1
A2 A2 A6 A2
A3 A3 A7 A3
B0 B0 B4 B0
B1 B1 B5 B1
B2 B2 B6 B2
B3 B3 B7 B3
A<Bi A<Bo A<Bi A<Bo A < B
A=Bi A=Bo A=Bi A=Bo A = B
A>Bi A>Bo A>Bi A>Bo A > B
LSN MSN
Stage 1 Stage 2
27
2.2 Decoders
Decoding is taking a code (binary, BCD, hex etc) and activating a single
output representing its numeric value.
2.2.1 Method to create a decoder
1. Generate a truth table

2. Find an expression for each output. (Karnaugh)
2.2.2 2 to 4 decoder
A 2 bit value can activate 1 of 4 possible output lines.

0 LSB 0
1 MSB 1
2
DECODER
3
A B Z3 Z2 Z1 Z0 Expression
0 0 0 0 0 1 Z0 = /A . /B
0 1 0 0 1 0 Z1 = /A . B
1 0 0 1 0 0 Z2 = A . /B
1 1 1 0 0 0 Z3 = A . B
Boolean Expressions
Z0 = /A . /B
Z1 = /A . B
Z2 = A . /B
Z3 = A . B
28
We can then construct the circuit for each output.
A B
Z0
Z1
Z2
Z3
29
2.3 Encoders
Encoding is taking a single input representing a numeric value and

converting it to its equivalent code (binary, BCD, hex etc). This is the
reverse of decoding.
2.3.1 Method to create a encoder
1. Generate a truth table

2. Find an expression for each output. (Karnaugh)
2.3.2 4 to 2 line binary encoder
One of 4 lines is encoded into binary.
0 D
Encoder
DECODER
1 C
2 B MSB
1
3 A LSB
0
A B C D Z1 Z0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
Boolean Expressions
Z1 = A + B
Z0 = A + C
Note:
D is not used.
30
We can then construct the circuit for each output.
A
Z1
B
Z0
C
D N/C
31
2.4 Code Convertors
2.4.1 Gray Code
Gray code is a very useful code in electronics and is used for indicating
the angular position of the shaft on a motor.
Gray code allows only one bit to change when moving from one code to
the next. You are familiar with this concept when writing the inputs for a
Karnaugh Map.
_ _ _ _
eg A B , AB , AB , AB
eg 2 bit Gray code ( 00 , 01 , 11 , 10 )

Sensors
2 bit Gray code
Decimal Binary Gray 10 00
0 00 00
1 01 01
2 10 11 01
11
3 11 10
Note:
The Gray code can easily roll back to itself
00, 01, 11, 10 → 00, 01 etc.
The angular position of a motor’s shaft can be determined by connecting

a wheel to the motor’s shaft. The wheel has a code stored at different
positions around it. The more codes stored on the wheel, the greater the
accuracy. Each code is stored on a separate segment of the wheel. Each
segment is divided into rings which allows each sector to represent a
binary digit.
When the motor turns, the wheel connected to the shaft also turns.
Sensors in a fixed position above the wheel pick up the codes and use
them to state the position of the wheel and hence the shaft.
If a binary code is used then as the wheel changes from position 3 to

position 0, the binary read goes from 11 to 00. If the sensors are not
perfectly in line and were read on the transition from position 3 to 0, then
values of 01 or 10 could occur depending upon the misalignment.
Therefore there is a potential for a large error using a binary scheme.
32
If a gray code was used then as the wheel changes from position 3 to
position 0, the binary read goes from 10 to 00. If the sensors were
misaligned and read on a transition from position 3 to position 0 then it
could only read 10 or 00. This eliminates the problem.
Converting Binary to Gray Code.
1. The Most Significant Bit (MSB) in the Gray code is the same as the
binary number.
2. Going from the MSB to LSB (left to right), add the current bit to the
next bit (right) ignoring the carry. The result of the addition is the gray
code bit.
For example to find the gray code for 10110
Binary Action Gray Bit

10110 MSB 1
10110 1+0 1
10110 0+1 1
10110 1+1 0
10110 1+0 1
Therefore the Gray code for 10110 is 11101
B0
G0
B1
G1
B2
G2
B3 G3 (MSB)
33
Converting Gray Code to Binary.
1. The Most Significant Bit (MSB) in the Gray code is the same as the
binary number.
2. Going from the MSB to LSB (left to right), add the current gray code
bit to the last binary bit found ignoring the carry. The result of the
addition is the binary code bit.
For example to convert a gray code of 11011 to binary
Gray Code Previous Action Binary

Binary
11011 N/A MSB 1
11011 1 1+1 0
11011 0 0+0 0
11011 0 1+0 1
11011 1 1+1 0
Therefore the Binary for a Gray code of 11011 is 10010
G0
B0
G1
B1
G2
B2
G3 B3 (MSB)
34
2.4.2 BCD to Binary
BCD is a binary code that is used to represent each decimal digit.

Therefore each decimal digit is represented with 0000 (0) to 1001 (9).
Eg
Weight: 101 100

Decimal: 2 9
BCD: 0010 1001
Binary: 0001 1101
Therefore we must assign a weight to each bit. Wherever there is a 1 in

the BCD digit we add the weight.
BCD Bit Weight Binary

0 1 0000 0001
1 2 0000 0010
2 4 0000 0100
3 8 0000 1000
4 10 0000 1010
5 20 0001 0100
6 40 0010 1000
7 80 0101 0000
BCD 29 is
80 40 20 10 8 4 2 1
0 0 1 0 1 0 0 1
Weight Binary
20 0001 0100 +
8 0000 1000 +
1 0000 0001 +
0010 1101 =
Integrated Circuit Converter
The 74184 is a 6 bit BCD to binary converter.
35
2.4.3 Binary to BCD
BCD is a binary code that is used to represent each decimal digit.

Therefore each decimal digit is represented with 0000 (0) to 1001 (9)
A 4 bit binary code has 16 values 0000 (0) to 1111 (15).

The binary numbers from 0000 (0) to 1001 (9) can represent their values.
The binary numbers from 1010 (10) to 1111 (15) can be converted to
BCD by adding 6. Note that this will generate a carry.
Example
10: 1010 + 0110 = (1) 0000 BCD: 1_0
15: 1111 + 0110 = (1) 0101 BCD: 1_5
The circuit to perform the binary to BCD conversion is given below. It

consists of a magnitude comparator and an adder.
A B C D
A1 S1 LSB
A2 S2
A3 S3
A4 S4
MSB
LO B1
B2
B3 7483A
LO B4
LO C0 C4
A0
A1
A2
A3
HI B0
LO B1 7485
9 LO B2
HI B3
LO A<Bi A<Bo
HI A=Bi A=Bo
LO A>Bi A>Bo
The 74185 is a 6 bit binary to BCD converter.
36
2.4.4 BCD to 7 segment
The 7 segment display is widely used as a numeric display in many

everyday devices
All the digits can be constructed out of 7 lines arranged in an 8 pattern:
In a 7 segment display each line is made up out of a LED or LCD bar.
The bar is switched on according to pattern required by the BCD digit.
A code converter is used to convert from BCD to the 7 segments.
The 7447 is the BCD to 7 segment converter.
Exercise
Draw the circuits to the BCD to 7 segment converter. There should be 7
equations.
Hint: Create the truth table for each segment, minimise using
Karnuagh maps, and draw the resulting circuit.
37
2.5 Multiplexers
A multiplexer is a circuit that allows digital information from several

sources to be routed onto a single line.
This is the equivalent of a digital switch.
Data is input into the lines D0 – D1.

Data select inputs determine which input is connected to the output.
A multiplexor is also known as Data Selector.
A 4 to 1 line multiplexor is shown below.
D0
D1
D2 Z
D3
S1 S0
The control lines S0 & S1 can have 4 binary settings. Therefore the
output (Z) can be connected to any one of the inputs (D0 to D3).
Truth Table for 4 to 1 line multiplexor
S1 S0 Z
0 0 D0
0 1 D1
1 0 D2
1 1 D3
38
2.5.1 Design of Multiplexors
Using the property that X . 1 = X
Selectors ANDed
together to give 1.
1. Decide upon the number of input Data lines required
2n = Number of data lines required
2. The number of selector lines required will be n from the above

equation.
3. Generate a truth table including selector states and output.
4. For each input data line, AND it with its equivalent selector state.
5. OR the result of all the ANDs.
S1 S0
D0
D1
Z
D2
D3
39
2.5.2 Using A Multiplexer for Combinational Logic
A multiplexer can be used to replace combinational logic
If the expression is complex, it may require many ICs. If the logic is

replaced with a single multiplexer then only one IC is required.
The concept is that the inputs from the truth table form the selector for the
multiplexer. Each Data line is set to the appropriate output value from the
truth table. When the selector value is set, the output is connected to the
associated Data Line. Hence the output line of the multiplexer passes the
output value from the truth table that is associated with the input values
from the truth table.
Method
1. Generate a truth table.
2. The inputs in the truth table are the selectors of the Multiplexer.
3. Each output term in the truth table corresponds to one Data Input line
of the Multiplexer.
4. Tie each Data Input Line to the corresponding output value from the
truth table.
Example
Refer to the Judges scoring system example used in module 1.
Green = BC + AC + AB
Truth Table
A B C Green MUX HI LO
0 0 0 0 D0
D0
0 0 1 0 D1 D1
Green
D2 Y
0 1 0 0 D2 D3
D4
0 1 1 1 D3 D5
D6
1 0 0 0 D4 D7
A
1 0 1 1 D5 B A
B
C
1 1 0 1 D6 C
1 1 1 1 D7
The original solution requires 2 x 14 pin ICs. ( 1 x 7432 , 1 x 7408 )

The multiplexer solution requires 1 x 16 pin IC.
40
2.6 Demultiplexers
A demultiplexer is a circuit that takes a single input and routes it to only

one of the possible output lines.
This is the equivalent of a digital switch.
This acts in reverse to a multiplexer.
Data is output from lines D0 – D1.

Data select inputs determine which output is connected to the input.
A demultiplexor is also known as Data Spreader.
A 1 to 4 line demultiplexor is shown below.
D0
D1
Z D2
D3
S1 S0
The control lines S0 & S1 can have 4 binary settings. Therefore the input
(Z) can be connected to any one of the outputs (D0 to D3).
Truth Table for 1 to 4 line demultiplexor
S1 S0 D0 D1 D2 D3
0 0 Z 0 0 0
0 1 0 Z 0 0
1 0 0 0 Z 0
1 1 0 0 0 Z
Where Z is the input data.
41
2.6.1 Design of Demultiplexers
Using the property that X . 1 = X
Selectors ANDed
together to give 1.
1. Decide upon the number of output Data lines required
2n = Number of data lines required
2. The number of selector lines required will be n from the above

equation.
3. Generate a truth table including selector states and data lines.
4. Each output data line will be the input data (Z) ANDed with its
equivalent selector state.
Z S1 S0
D0
D1
D2
D3
42
2.7 Parity
Errors can occur in the transmission of data from one computer to

another.
We need a method to determine if an error has occurred. Parity allows us

to detect a single bit error in the data bits sent. Usually these are grouped
in bytes.
To use parity to detect errors we must append a parity bit to the data bits
transmitted.
Any group of bits may contain an even or odd number of 1’s.
The parity bit is used to set the total number of 1’s to an even number or
an odd number.
Even parity uses the parity bit to make the total number of 1’s an even
number.
Odd parity uses the parity bit to make the total number of 1’s an odd
number.
Example
Q What is value of the parity bit required to make 1011
(a) even parity
(b) odd parity
A 1011 contains three 1’s. This is an odd number of 1’s.

(a) parity bit = 1 to make 4 x 1’s, an even number.
(b) parity bit = 0 to make 3 x 1’s, an odd number.
Error Detection
We must know the type of parity used for the received data.
The received data will have a parity bit. This can be checked by summing
together all the bits in the data received.
For even parity, the sum of all the bits including the parity bit will be 0.
For odd parity the sum of all the bits including the parity bit will be 1.
43
The bits can be summed using XOR circuits in the following manner:
A0
Sum
A1
Summing 2 bits.
A0
A1
Sum
A2
A3
Summing 4 bits (nibble).
A0
A1
A2
A3
Sum
A4
A5
A6
A7
Summing 8 bits (byte).
44
Digital Electronics
Part I – Combinational and
Sequential Logic
Dr. I. J. Wassell
Introduction
Aims
• To familiarise students with
– Combinational logic circuits
– Sequential logic circuits
– How digital logic gates are built using
transistors
– Design and build of digital logic systems
Course Structure
• 11 Lectures
• Hardware Labs
– 6 Workshops
– 7 sessions, each one 3h, alternate weeks
– Thu. 10.00 or 2.00 start, beginning week 3
– In Cockroft 4 (New Museum Site)
– In groups of 2
Objectives
• At the end of the course you should
– Be able to design and construct simple
digital electronic systems
– Be able to understand and apply Boolean
logic and algebra – a core competence in
Computer Science
– Be able to understand and build state
machines
Books
• Lots of books on digital electronics, e.g.,
– D. M. Harris and S. L. Harris, ‘Digital Design
and Computer Architecture,’ Morgan Kaufmann,
2007.
– R. H. Katz, ‘Contemporary Logic Design,’
Benjamin/Cummings, 1994.
– J. P. Hayes, ‘Introduction to Digital Logic
Design,’ Addison-Wesley, 1993.
• Electronics in general (inc. digital)
– P. Horowitz and W. Hill, ‘The Art of Electronics,’
CUP, 1989.
Other Points
• This course is a prerequisite for
– ECAD (Part IB)
– VLSI Design (Part II)
• Keep up with lab work and get it ticked.
• Have a go at supervision questions plus
any others your supervisor sets.
• Remember to try questions from past
papers
Semiconductors to Computers
• Increasing levels of complexity
– Transistors built from semiconductors
– Logic gates built from transistors
– Logic functions built from gates
– Flip-flops built from logic
– Counters and sequencers from flip-flops
– Microprocessors from sequencers
– Computers from microprocessors
Semiconductors to Computers
• Increasing levels of abstraction:
– Physics
– Transistors
– Gates
– Logic
– Microprogramming (Computer Design Course)
– Assembler (Computer Design Course)
– Programming Languages (Compilers Course)
– Applications
Combinational Logic
Introduction to Logic Gates
• We will introduce Boolean algebra and
logic gates
• Logic gates are the building blocks of
digital circuits
Logic Variables
• Different names for the same thing
– Logic variables
– Binary variables
– Boolean variables
• Can only take on 2 values, e.g.,
– TRUE or False
– ON or OFF
– 1 or 0
Logic Variables
• In electronic circuits the two values can
be represented by e.g.,
– High voltage for a 1
– Low voltage for a 0
• Note that since only 2 voltage levels are
used, the circuits have greater immunity
to electrical noise
Uses of Simple Logic
• Example – Heating Boiler
– If chimney is not blocked and the house is cold
and the pilot light is lit, then open the main fuel
valve to start boiler.
b = chimney blocked
c = house is cold
p = pilot light lit
v = open fuel valve
– So in terms of a logical (Boolean) expression
v = (NOT b) AND c AND p
Logic Gates
• Basic logic circuits with one or more
inputs and one output are known as
gates
• Gates are used as the building blocks in
the design of more complex digital logic
circuits
Representing Logic Functions
• There are several ways of representing
logic functions:
– Symbols to represent the gates
– Truth tables
– Boolean algebra
• We will now describe commonly used
gates
NOT Gate
Symbol Truth-table Boolean
a y a y ya
0 1
1 0
• A NOT gate is also called an ‘inverter’

• y is only TRUE if a is FALSE
• Circle (or ‘bubble’) on the output of a gate
implies that it as an inverting (or
complemented) output
AND Gate
a b y y  a.b
a y 0 0 0
b
0 1 0
1 0 0
1 1 1
• y is only TRUE only if a is TRUE and b is

TRUE
• In Boolean algebra AND is represented by
a dot .
OR Gate
a b y y  ab
a y 0 0 0
b
0 1 1
1 0 1
1 1 1
• y is TRUE if a is TRUE or b is TRUE (or

both)
• In Boolean algebra OR is represented by
a plus sign 
EXCLUSIVE OR (XOR) Gate
a b y y  ab
a y 0 0 0
b
0 1 1
1 0 1
1 1 0
• y is TRUE if a is TRUE or b is TRUE (but

not both)
• In Boolean algebra XOR is represented by
an  sign
NOT AND (NAND) Gate
a
a b y y  a.b
y 0 0 1
b
0 1 1
1 0 1
1 1 0
• y is TRUE if a is FALSE or b is FALSE (or

both)
• y is FALSE only if a is TRUE and b is
TRUE
NOT OR (NOR) Gate
a
a b y y  ab
y 0 0 1
b
0 1 0
1 0 0
1 1 0
• y is TRUE only if a is FALSE and b is

FALSE
• y is FALSE if a is TRUE or b is TRUE (or
both)
Boiler Example
• If chimney is not blocked and the house is
cold and the pilot light is lit, then open the
main fuel valve to start boiler.
b = chimney blocked c = house is cold
p = pilot light lit v = open fuel valve
b
c v  b .c. p
p
Boolean Algebra
• In this section we will introduce the laws
of Boolean Algebra
• We will then see how it can be used to
design combinational logic circuits
• Combinational logic circuits do not have
an internal stored state, i.e., they have
no memory. Consequently the output is
solely a function of the current inputs.
• Later, we will study circuits having a
stored internal state, i.e., sequential
logic circuits.
Boolean Algebra
OR AND
a0 a a.0  0
aa a a.a  a
a 1  1 a.1  a
a  a 1 a.a  0
• AND takes precedence over OR, e.g.,
a.b  c.d  (a.b)  (c.d )
Boolean Algebra
• Commutation
ab ba
a.b  b.a
• Association
( a  b)  c  a  (b  c)
( a.b).c  a.(b.c)
• Distribution
a.(b  c  )  (a.b)  (a.c)  
a  (b.c. )  (a  b).(a  c).  NEW
• Absorption
a  (a.c)  a NEW
a.( a  c)  a NEW
Boolean Algebra - Examples
Show
a.( a  b)  a.b
a.( a  b)  a.a  a.b  0  a.b  a.b
Show
a  (a .b)  a  b
a  (a .b)  (a  a ).(a  b)  1.(a  b)  a  b
Boolean Algebra
• A useful technique is to expand each
term until it includes one instance of each
variable (or its compliment). It may be
possible to simplify the expression by
cancelling terms in this expanded form
e.g., to prove the absorption rule:
a  a.b  a
a.b  a.b  a.b  a.b  a.b  a.(b  b )  a.1  a

Boolean Algebra - Example
Simplify
x. y  y.z  x.z  x. y.z
x. y.z  x. y.z  x. y.z  x. y.z  x. y.z  x. y.z  x. y.z
x. y.z  x. y.z  x. y.z  x. y.z
x. y.( z  z )  y.z.( x  x )
x. y.1  y.z.1
x. y  y.z
DeMorgan’s Theorem
a  b  c    a .b .c . 
a.b.c.   a  b  c  
• In a simple expression like a  b  c (or a.b.c )
simply change all operators from OR to
AND (or vice versa), complement each
term (put a bar over it) and then
complement the whole expression, i.e.,
a  b  c    a .b .c . 
a.b.c.   a  b  c  
DeMorgan’s Theorem
• For 2 variables we can show a  b  a .b
and a.b  a  b using a truth table.
a b a  b a.b a b a.b a  b
0 0 1 1 1 1 1 1
0 1 0 1 1 0 0 1
1 0 0 1 0 1 0 1
1 1 0 0 0 0 0 0
• Extending to more variables by induction
a  b  c  (a  b).c  (a .b ).c  a .b .c
DeMorgan’s Examples
• Simplify a.b  a.(b  c)  b.(b  c)
 a.b  a.b .c  b.b .c (DeMorgan)
 a.b  a.b .c (b.b  0)
 a.b (absorbtion)
DeMorgan’s Examples
• Simplify (a.b.(c  b.d )  a.b).c.d
 (a.b.(c  b  d )  a  b ).c.d (De Morgan)
 (a.b.c  a.b.b  a.b.d  a  b ).c.d (distribute)
 (a.b.c  a.b.d  a  b ).c.d (a.b.b  0)
 a.b.c.d  a.b.d .c.d  a .c.d  b .c.d (distribute)
 a.b.c.d  a .c.d  b .c.d (a.b.d .c.d  0)
 (a.b  a  b ).c.d (distribute)
 (a.b  a.b).c.d (DeMorgan)
 c.d (a.b  a.b  1)
DeMorgan’s in Gates
• To implement the function f  a.b  c.d we
can use AND and OR gates
a
b
f
c
d
• However, sometimes we only wish to
use NAND or NOR gates, since they
are usually simpler and faster
• To do this we can use ‘bubble’ logic
Two consecutive ‘bubble’ (or
a x
complement) operations cancel,
b i.e., no effect on logic function
f
c
d y What about this gate?
DeMorgan says x  y  x. y
See AND gates are
now NAND gates Which is a NOT
AND (NAND) gate
So is equivalent to
• So the previous function can be built
using 3 NAND gates
a a
b b
f f
c c
d d
• Similarly, applying ‘bubbles’ to the input
of an AND gate yields
x
f
y Which is a NOT OR
(NOR) gate
What about this gate?
DeMorgan says x . y  x y
So is equivalent to
• Useful if trying to build using NOR gates

Logic Minimisation
• Any Boolean function can be implemented
directly using combinational logic (gates)
• However, simplifying the Boolean function will
enable the number of gates required to be
reduced. Techniques available include:
– Algebraic manipulation (as seen in examples)
– Karnaugh (K) mapping (a visual approach)
– Tabular approaches (usually implemented by
computer, e.g., Quine-McCluskey)
• K mapping is the preferred technique for up to
about 5 variables
Truth Tables
• f is defined by the following truth table
• A minterm must contain
x y z f minterms all variables (in either
0 0 0 1 x . y.z complement or
0 0 1 1 x . y.z uncomplemented form)
0 1 0 1 x . y.z
0 1 1 1 x . y.z • Note variables in a
1 0 0 0 minterm are ANDed
1 0 1 0 together (conjunction)
1 1 0 0
1 1 1 1 x. y.z • One minterm for each
term of f that is TRUE
• So x. y.z is a minterm but y.z is not
Disjunctive Normal Form
• A Boolean function expressed as the
disjunction (ORing) of its minterms is said
to be in the Disjunctive Normal Form (DNF)
f  x . y.z  x. y.z  x. y.z  x . y.z  x. y.z
ORing of ANDed variables (not necessarily
minterms) is often said to be in Sum of
Products (SOP) form, e.g.,
f  x  y.z Note functions have the same truth table
Maxterms
• A maxterm of n Boolean variables is the
disjunction (ORing) of all the variables either
in complemented or uncomplemented form.
– Referring back to the truth table for f, we can
write,
f  x. y.z  x. y.z  x. y.z
Applying De Morgan (and complementing) gives
f  ( x  y  z ).( x  y  z ).( x  y  z )
So it can be seen that the maxterms of f are
effectively the minterms of f with each variable
complemented
Conjunctive Normal Form
conjunction (ANDing) of its maxterms is said
to be in the Conjunctive Normal Form (CNF)
f  ( x  y  z ).( x  y  z ).( x  y  z )
• A Boolean function expressed as the ANDing
of ORed variables (not necessarily maxterms)
is often said to be in Product of Sums (POS)
form, e.g.,
f  ( x  y ).( x  z )
Logic Simplification
• As we have seen previously, Boolean
algebra can be used to simplify logical
expressions. This results in easier
implementation
Note: The DNF and CNF forms are not
simplified.
• However, it is often easier to use a
technique known as Karnaugh mapping
Karnaugh Maps
• Karnaugh Maps (or K-maps) are a
powerful visual tool for carrying out
simplification and manipulation of logical
expressions having up to 5 variables
• The K-map is a rectangular array of
cells
– Each possible state of the input variables
corresponds uniquely to one of the cells
– The corresponding output state is written in
each cell
K-maps example
• From truth table to K-map
x y z f z
yz
0 0 0 1 x 00 01 11 10
0 0 1 1 0 1 1 1 1
0 1 0 1 x 1 1
0 1 1 1
1 0 0 0 y
1 0 1 0
Note that the logical state of the
1 1 0 0
variables follows a Gray code, i.e.,
1 1 1 1
only one of them changes at a time
The exact assignment of variables in
terms of their position on the map is
not important
K-maps example
• Having plotted the minterms, how do we
use the map to give a simplified
expression? • Group terms
z • Having size equal to a power of
yz 2, e.g., 2, 4, 8, etc.
x
00 01 11 10
0 1 1 1 1 • Large groups best since they
x 1 1 contain fewer variables
• Groups can wrap around edges
x y.z y
and corners
So, the simplified func. is,
f  x  y.z as before
K-maps – 4 variables
• K maps from Boolean expressions
– Plot f  a .b  b.c .d c
cd
ab 00 01 11 10
00
01 1 1 1 1
b
a 11 1
10
d
• See in a 4 variable map:
– 1 variable term occupies 8 cells
– 2 variable terms occupy 4 cells
– 3 variable terms occupy 2 cells, etc.
• For example, plot
f b f  b .d
c c
cd cd
ab 00 01 11 10 ab 00 01 11 10
00 1 1 1 1 00 1 1
01 01
b b
a 11 a 11
10 1 1 1 1 10 1 1
d d
• Simplify, f  a .b.d  b.c.d  a .b.c .d  c.d
c
cd
ab 00 01 11 10
00 1
01 1 1 1 1
b
1
a 11
10 1
c.d
a.b d
So, the simplified func. is,

f  a .b  c.d
POS Simplification
• Note that the previous examples have
yielded simplified expressions in the
SOP form
– Suitable for implementations using AND
followed by OR gates, or only NAND gates
(using DeMorgans to transform the result –
see previous Bubble logic slides)
• However, sometimes we may wish to
get a simplified expression in POS form
– Suitable for implementations using OR
followed by AND gates, or only NOR gates
POS Simplification
• To do this we group the zeros in the map
– i.e., we simplify the complement of the function
• Then we apply DeMorgans and
complement
• Use ‘bubble’ logic if NOR only
implementation is required
POS Example
• Simplify f  a .b  b.c .d into POS form.
c c
cd cd
ab 00 01 11 10 ab 00 01 11 10
00 00 0 0 0 0
01 1 1 1 1 Group
b 01 1 1 1 1
zeros b
11 1 11 1 0 0 0
a a
10 10 0 0 0 0
d b a.d d a.c
f  b  a.c  a.d
POS Example
• Applying DeMorgans to a
f  b  a.c  a.d c
f
gives, a
f  b.(a  c ).(a  d ) d
f  b.(a  c ).(a  d ) b
a
a
c
c
f f
a
a
d
d
b
b
Expression in POS form
• Apply DeMorgans and take
complement, i.e., f is now in SOP form
• Fill in zeros in table, i.e., plot f
• Fill remaining cells with ones, i.e., plot f
• Simplify in usual way by grouping ones
to simplify f
Don’t Care Conditions
• Sometimes we do not care about the
output value of a combinational logic
circuit, i.e., if certain input combinations
can never occur, then these are known
as don’t care conditions.
• In any simplification they may be treated
as 0 or 1, depending upon which gives
the simplest result.
– For example, in a K-map they are entered
as Xs
Don’t Care Conditions - Example
• Simplify the function f  a .b .d  a .c.d  a.c.d
With don’t care conditions, a .b .c .d , a .b .c.d , a .b.c .d
c
ab
cd
00 01 11 10 See only need to include
00 X 1 1 X Xs if they assist in making
X 1
01
b a bigger group, otherwise
1
a 11 can ignore.
10 1
c.d
a.b d
f  a .b  c.d or, f  a .d  c.d
Some Definitions
• Cover – A term is said to cover a minterm if that
minterm is part of that term
• Prime Implicant – a term that cannot be further
combined
• Essential Term – a prime implicant that covers a
minterm that no other prime implicant covers
• Covering Set – a minimum set of prime
implicants which includes all essential terms plus
any other prime implicants required to cover all
minterms
Number Representation,
Addition and Subtraction
Binary Numbers
• It is important to be able to represent
numbers in digital logic circuits
– for example, the output of a analogue to digital
converter (ADC) is an n-bit number, where n is
typically in the range from 8 to 16
• Various representations are used, e.g.,
– unsigned integers
– 2’s complement to represent negative numbers
Binary Numbers
• Binary is base 2. Each digit (known as a
bit) is either 0 or 1.
• Consider these 6-bit unsigned numbers
1 0 1 0 1 0  4210
32 16 8 4 2 1 Binary
25 24 23 22 21 20 coefficients MSB – most
MSB LSB significant bit
0 0 1 0 1 1  1110 LSB – least
32 16 8 4 2 1 Binary significant bit
25 24 23 22 21 20 coefficients
MSB LSB
Unsigned Binary Numbers
• In general, an n-bit binary number, bn 1bn 2 b1b0
has the decimal value,
n 1
  bi  2i
i 0
• So we can represent positive integers from
0 to 2n  1
• In computers, binary numbers are often 8
bits long – known as a byte
• A byte can represent unsigned values from
0 to 255
Unsigned Binary Numbers
• Decimal to binary conversion. Perform
successive division by 2.
– Convert 4210 into binary
42 / 2  21 remainder  0
21 / 2  10 remainder  1
10 / 2  5 remainder  0
5 / 2  2 remainder  1
2 / 2  1 remainder  0
1 / 2  0 remainder  1
• So the answer is 1010102 (reading upwards)
Octal: Base 8
• We have seen base 2 uses 2 digits (0 & 1),
not surprisingly base 8 uses 8 digits : 0, 1,
2, 3, 4, 5, 6, 7.
0 5 2  4210
64 8 1 Octal
82 81 80 coefficients
MSB LSB
• To convert from decimal to base 8 either
use successive division, i.e.,
42 / 8  5 remainder  2
5 / 8  0 remainder  5
• So the answer is 528 (reading upwards)
Octal: Base 8
• Or alternatively, convert to binary, divide
the binary number into 3-bit groups and
work out the octal digit to represent
each group. We have shown that
4210  1010102
• So,
1 0 1 0 1 0  4210
5 28
MSB LSB
Hexadecimal: Base 16
• For base 16 we need 16 different digits.
Consequently we need new symbols for
the digits to represent 10-15
10102  1010  A16 11012  1310  D16
10112  1110  B16 11102  1410  E16
11002  1210  C16 11112  1510  F16
0 2 A16  4210
256 16 1 Hex
162 161 160 coefficients
MSB LSB
Hex: Base 16
• To convert from decimal to base 16 use
either use successive division by 16, i.e.,
42 / 16  2 remainder  A
2 / 16  0 remainder  2
• So the answer is 2A8 (reading upwards)
Hex: Base 16
• Or alternatively, convert to binary, divide
the binary number into 4-bit groups and
work out the hex digit to represent each
group. We have shown that
4210  1010102
• So,
0 0 1 0 1 0 1 0  4210
2 A16
MSB LSB
Hex: Base 16
• Hex is also used as a convenient way of
representing the contents of a byte (an
8 bit number), so for example 111000102
1 1 1 0 0 0 1 0  E 216
E 216
MSB LSB
Negative numbers
• So far we have only been able to represent
positive numbers. For example, we have
seen an 8-bit byte can represent from 0 to
255, i.e., 28 = 256 different combinations of
bits in a byte
• If we want to represent negative numbers,
we have to give up some of the range of
positive numbers we had before
– A popular approach to do this is called 2’s
complement
2’s Complement
• For 8-bit numbers:
0 positive 127  128 negative 1
0H 7 FH 80H FFH
• Note all negative numbers have the
MSB set
• The rule for changing a positive 2’s
complement number into a negative 2’s
complement number (or vice versa) is:
Complement all the bits and add 1.
2’s Complement
• What happens when we do this to an 8 bit
binary number x ?
– Invert all bits: x  (255  x)
– Add 1: x  (256  x)
• Note: 256 (= 100H) will not fit into an 8 bit
byte. However if we ignore the ‘overflow’ bit,
then 256  x behaves just like 0  x
• That is, we can use normal binary arithmetic
to manipulate the 2’s complement of x and it
will behave just like -x
2’s Complement Addition
0 0 0 0 0 1 1 1 7
0 0 0 0 0 1 0 0 4
(0) 0 0 0 0 1 0 1 1 11
• To subtract, negate the second number, then add:
0 0 0 0 0 1 1 1 7
1 1 1 1 1 0 0 1  7
(1) 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 1 9
1 1 1 1 1 0 0 1  7
(1) 0 0 0 0 0 0 1 0 2
2’s Complement Addition
0 0 0 0 0 1 0 0 4
1 1 1 1 1 0 0 1  7
( 0) 1 1 1 1 1 1 0 1  3
1 1 1 1 1 0 0 1 7
1 1 1 1 1 0 0 1  7
(1) 1 1 1 1 0 0 1 0  14
2’s Complement
• Note that for an n-bit number bn 1bn 2 b1b0 ,
the decimal equivalent of a 2’s complement
number is, n2
 bn 1  2n 1  i
b  2 i
i 0
• For example, 1 1 1 1 0 0 1 0
6
 b7  27   bi  2i
i 0
 1 27  1 26  1 25  1 24  1 21
 128  64  32  16  2  14
2’s Complement Overflow
• For example, when working with 8-bit
unsigned numbers, we can use the
‘carry’ from the 8th bit (MSB) to indicate
that the number has got too big.
• With signed numbers we deliberately
ignore any carry from the MSB,
consequently we need a new rule to
detect when a result is out of range.
• The rule for detecting 2’s complement
overflow is:
– The carry into the MSB does not equal the
carry out from the MSB.
• We will now give some examples.
0 0 0 0 1 1 1 1 15
0 0 0 0 1 1 1 1  15
(0) 0 0 0 1 1 1 1 0 30 OK
0 1 1 1 1 1 1 1 127
0 0 0 0 0 0 0 1 1
(0) 1 0 0 0 0 0 0 0  128 overflow
1 1 1 1 0 0 0 1  15
1 1 1 1 0 0 0 1  15
(1) 1 1 1 0 0 0 1 0  30 OK
1 0 0 0 0 0 0 1  127
1 1 1 1 1 1 1 0  2
(1) 0 1 1 1 1 1 1 1 127 overflow
Binary Coded Decimal (BCD)
• Each decimal digit of a number is coded
as a 4 bit binary quantity
• It is sometimes used since it is easy to
code and decode, however it is not an
efficient way to store numbers.
124810  0001 0010 0100 1000BCD
123410  0001 0010 0011 0100BCD
Alphanumeric Character Codes
• ASCII: American Standard Code for
Information Exchange:
– Standard version is a 7 bit code with the
remaining bit usually set to zero
– The first 32 are ‘control codes’ originally used
for controlling modems
– The rest are upper and lower case letters,
numbers and punctuation.
– An extended version uses all 8 bits to
provide additional graphics characters
Alphanumeric Character Codes
• EBCDIC – a legacy IBM scheme, now little
used
• Unicode – a 16 bit scheme, includes
Chinese characters etc.
Binary Adding Circuits
• We will now look at how binary addition
may be implemented using combinational
logic circuits. We will consider:
– Half adder
– Full adder
– Ripple carry adder
Half Adder
• Adds together two, single bit binary
numbers a and b (note: no carry input)
• Has the following truth table:
a b cout sum
a sum
0 0 0 0
0 1 0 1 b cout
1 0 0 1
1 1 1 0
• By inspection:
sum  a .b  a.b  a  b
cout  a.b
Full Adder
• Adds together two, single bit binary
numbers a and b (note: with a carry input)
a sum
b cout
cin
• Has the following truth table:
Full Adder
cin a b cout sum
sum  cin .a .b  cin .a.b  cin .a .b  cin .a.b
0 0 0 0 0
0 0 1 0 1 sum  cin .(a .b  a.b )  cin .(a .b  a.b)
0 1 0 0 1
0 1 1 1 0 From DeMorgan
1 0 0 0 1 a .b  a.b  (a  b).(a  b )
1 0 1 1 0
1 1 0 1 0  (a.a  a.b  b.a  b.b )
1 1 1 1 1
 (a.b  b.a )
So,
sum  cin .(a .b  a.b )  cin .(a .b  a.b )
sum  cin .x  cin .x  cin  x  cin  a  b
Full Adder
cin a b cout sum
cout  cin .a.b  cin .a .b  cin .a.b  cin .a.b
0 0 0 0 0
0 0 1 0 1 cout  a.b.(cin  cin )  cin .a .b  cin .a.b
0 1 0 0 1
0 1 1 1 0 cout  a.b  cin .a .b  cin .a.b
1 0 0 0 1
1 0 1 1 0 cout  a.(b  cin .b )  cin .a .b
1 1 0 1 0
1 1 1 1 1 cout  a.(b  cin ).(b  b )  cin .a .b
cout  b.(a  cin .a )  a.cin  b.(a  cin ).(a  a )  a.cin
cout  b.a  b.cin  a.cin
cout  b.a  cin .(b  a )
Full Adder
• Alternatively,
cin a b cout sum
0 0 0 0 0 cout  cin .a.b  cin .a .b  cin .a.b  cin .a.b
0 0 1 0 1
0 1 0 0 1 cout  cin .(a .b  a.b )  a.b.(cin  cin )
0 1 1 1 0 cout  cin .(a  b)  a.b
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
• Which is similar to previous expression

except with the OR replaced by XOR
Ripple Carry Adder
• We have seen how we can implement a
logic to add two, one bit binary numbers
(inc. carry-in).
• However, in general we need to add
together two, n bit binary numbers.
• One possible solution is known as the
Ripple Carry Adder
– This is simply n, full adders cascaded
together
Ripple Carry Adder
• Example, 4 bit adder
c0 a0 b0 a1 b1 a2 b2 a3 b3
a b a b a b a b
cin cout cin cout cin cout cin cout
sum sum sum sum
s0 s1 s2 s3 c4
• Note: If we complement a and set co to

one we have implemented s  b  a
Combinational Logic Design
Further Considerations
Multilevel Logic
• We have seen previously how we can
minimise Boolean expressions to yield
so called ‘2-level’ logic implementations,
i.e., SOP (ANDed terms ORed together)
or POS (ORed terms ANDed together)
• Note also we have also seen an
example of ‘multilevel’ logic, i.e., full
adders cascaded to form a ripple carry
adder – see we have more than 2 gates
in cascade in the carry chain
Multilevel Logic
• Why use multilevel logic?
– Commercially available logic gates usually
only available with a restricted number of
inputs, typically, 2 or 3.
– System composition from sub-systems
reduces design complexity, e.g., a ripple
adder made from full adders
– Allows Boolean optimisation across multiple
outputs, e.g., common sub-expression
elimination
Building Larger Gates
• Building a 6-input OR gate
Common Expression Elimination
• Consider the following minimised SOP
expression:
z  a.d . f  a.e. f  b.d . f  b.e. f  c.d . f  c.e. f  g
• Requires:
• Six, 3 input AND gates, one 7-input
OR gate – total 7 gates, 2-levels
• 19 literals (the total number of times
all variables appear)
Common Expression Elimination
• We can recursively factor out common literals
z  a.d . f  a.e. f  b.d . f  b.e. f  c.d . f  c.e. f  g
z  (a.d  a.e  b.d  b.e  c.d  c.e). f  g
z  ((a  b  c).d  (a  b  c).e). f  g
z  (a  b  c).(d  e). f  g
• Now express z as a number of equations in 2-
level form:
x  abc x  d e z  x. y. f  g
• 4 gates, 9 literals, 3-levels
Gate Propagation Delay
• So, multilevel logic can produce reductions
in implementation complexity. What is the
downside?
• We need to remember that the logic gates
are implemented using electronic
components (essentially transistors) which
have a finite switching speed.
• Consequently, there will be a finite delay
before the output of a gate responds to a
change in its inputs – propagation delay
• The cumulative delay owing to a number of
gates in cascade can increase the time
before the output of a combinational logic
circuit becomes valid
• For example, in the Ripple Carry Adder, the
sum at its output will not be valid until any
carry has ‘rippled’ through possibly every full
adder in the chain – clearly the MSB will
experience the greatest potential delay
• As well as slowing down the operation of
combinational logic circuits, gate delay can
also give rise to so called ‘Hazards’ at the
output
• These Hazards manifest themselves as
unwanted brief logic level changes (or
glitches) at the output in response to
changing inputs
• We will now describe how we can address
these problems
Hazards
• Hazards are classified into two types,
namely, static and dynamic
• Static Hazard – The output undergoes a
momentary transition when it is
supposed to remain unchanged
• Dynamic Hazard – The output changes
more than once when it is supposed to
change just once
Timing Diagrams
• To visually represent Hazards we will use the
so called ‘timing diagram’
• This shows the logical value of a signal as a
function of time, for example the following
timing diagram shows a transition from 0 to 1
and then back again
Logic ‘1’
Logic ‘0’
Time
Timing Diagrams
• Note that the timing diagram makes a number
simplifying assumptions (to aid clarity)
compared with a diagram which accurately
shows the actual voltage against time
– The signal only has 2 levels. In reality the signal
may well look more ‘wobbly’ owing to electrical
noise pick-up etc.
– The transitions between logic levels takes place
instantaneously, in reality this will take a finite
time.
Static Hazard
Logic ‘1’
Static 1 hazard
Logic ‘0’
Time
Logic ‘1’ Static 0 hazard
Logic ‘0’
Time
Dynamic Hazard
Logic ‘1’
Dynamic hazard
Logic ‘0’
Time
Logic ‘1’
Dynamic hazard
Logic ‘0’
Time
Static 1 Hazard
x y
u
y w
t
t
v u
z v
This circuit implements,
w  x. y  z. y w
Consider the output when z  x 1
and y changes from 1 to 0
Hazard Removal
• To remove a 1 hazard, draw the K-map
of the output concerned. Add another
term which overlaps the essential terms
• To remove a 0 hazard, draw the K-map
of the complement of the output
concerned. Add another term which
overlaps the essential terms
(representing the complement)
• To remove dynamic hazards – not
covered in this course!
Removing the static 1 hazard
w  x. y  z. y
z
yz x
x 00 01 11 10
0 1 y w
x 1 1 1 1
y
Extra term added to remove
hazard, consequently,
w  x. y  z. y  x.z
z
To Speed up Ripple Carry Adder
• Abandon compositional approach to the adder
design, i.e., do not build the design up from
full-adders, but instead design the adder as a
block of 2-level combinational logic with 2n
inputs (+1 for carry in) and n outputs (+1 for
carry out).
• Features
– Low delay (2 gate delays)
– Need some gates with large numbers of inputs
(which are not available)
– Very complex to design and implement (imagine
the truth table!
To Speed up Ripple Carry Adder
• Clearly the 2-level approach is not
feasible
• One possible approach is to make use
of the full-adder blocks, but to generate
the carry signals independently, using
fast carry generation logic
• Now we do not have to wait for the carry
signals to ripple from full-adder to full-
adder before output becomes valid
Fast Carry Generation
c0 a0 b0 a1 b1 a2 b2 a3 b3
a b a b a b a b
Conventional
cin cout cin cout cin cout cin cout RCA
sum sum sum sum
s0 s1 s2 s3 c4
c0 a0 b0 a1 b1 a2 b2 a3 b3
Fast Carry
Fast Carry Generation Adder
a b a b a b a b
c0 cin cout c1 cin cout c2 cin cout c3 cin cout
sum sum sum sum
s0 s1 s2 s3 c4
• We will now determine the Boolean
equations required to generate the fast
carry signals
• To do this we will consider the carry out
signal, cout, generated by a full-adder
stage (say i), which conventionally gives
rise to the carry in (cin) to the next stage,
i.e., ci+1.
Carry out always zero.
ci a b si ci+1 ki  ai .bi
Call this carry kill
0 0 0 0 0
0 0 1 1 0 Carry out same as carry in.
0 1 0 1 0 pi  ai  bi
Call this carry propagate
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1 Carry out generated
1 1 0 0 1
independently of carry in. gi  ai .bi
1 1 1 1 1 Call this carry generate
Also (from before), si  ai  bi  ci

• Also from before we have,
ci 1  ai .bi  ci .(ai  bi ) or alternatively,
ci 1  ai .bi  ci .(ai  bi )
Using previous expressions gives,
ci 1  gi  ci . pi
So,
ci  2  g i 1  ci 1. pi 1
ci  2  g i 1  pi 1.( g i  ci . pi )
ci  2  g i 1  pi 1.g i  pi 1. pi .ci
Similarly,
ci 3  g i  2  ci  2 . pi  2
ci 3  g i  2  pi  2 .( g i 1  pi 1.( g i  ci . pi ))
ci 3  g i  2  pi  2 .( g i 1  pi 1.g i )  pi  2 . pi 1. pi .ci
and
ci  4  g i 3  ci 3 . pi 3
ci  4  g i 3  pi 3 .( gi  2  pi  2 .( gi 1  pi 1.g i )  pi  2 . pi 1. pi .ci )
ci  4  g i 3  pi 3 .( g i  2  pi  2 .( g i 1  pi 1.g i ))  pi 3 . pi  2 . pi 1. pi .ci
• So for example to generate c4, i.e., i = 0,
c4  g3  p3.( g 2  p2 .( g1  p1.g 0 ))  p3. p2 . p1. p0 .c0
c4  G  Pc0
where,
G  g3  p3.( g 2  p2 .( g1  p1.g 0 ))
P  p3. p2 . p1. p0
• See it is quick to evaluate this function
• We could generate all the carrys within an
adder block using the previous equations
• However, in order to reduce complexity, a
suitable approach is to implement say 4-bit
adder blocks with only c4 generated using
fast generation.
– This is used as the carry-in to the next 4-bit
adder block
– Within each 4-bit adder block, conventional RCA
is used
c0 a0 b0 a1 b1 a2 b2 a3 b3
a b a b a b a b
c0 cin cout cin cout cin cout cin cout
sum sum sum sum
s0 s1 s2 s3 c4
Other Ways to Implement
Combinational Logic
• We have seen how combinational logic
can be implemented using logic gates,
e.g., AND, OR etc.
• However, it is also possible to generate
combinational logic functions using
memory devices, e.g., Read Only
Memories (ROMs)
ROM Overview
• A ROM is a data storage device:
– Usually written into once (either at manufacture or
using a programmer)
– Read at will
– Essentially is a look-up table, where a group of
input lines (say n) is used to specify the address
of locations holding m-bit data words
– For example, if n = 4, then the ROM has 24 = 16
possible locations. If m = 4, then each location
can store a 4-bit word
– So, the total number of bits stored is m  2 n
, i.e.,
64 in the example (very small!) ROM
ROM Example
address data Design amounts to putting
z A0 D0 minterms in the appropriate
y A1 64-bit D1 address location
x A2 ROM D2
'0' A3 D3 No logic simplification
required
address data
(decimal) x y z f D3 D2 D1 D0 Useful if multiple Boolean
functions are to be
0 0 0 0 1 X X X 1
1 0 0 1 1 X X X 1 implemented, e.g., in this
2 0 1 0 1 X X X 1 case we can easily do up to
3 0 1 1 1 X X X 1 4, i.e., 1 for each output line
4 1 0 0 0 X X X 0
5 1 0 1 0 X X X 0 Reasonably efficient if lots of
6 1 1 0 0 X X X 0 minterms need to be
7 1 1 1 1 X X X 1 generated
ROM Implementation
• Can be quite inefficient, i.e., become large in
size with only a few non-zero entries, if the
number of minterms in the function to be
implemented is quite small
• Devices which can overcome these problems
are known as programmable array logic (PAL)
• In PALs, only the required minterms are
generated using a separate AND plane. The
outputs from this plane are ORed together in
a separate OR plane to produce the final
output
Basic PAL Structure
a
b
c
AND plane
f0
Programmed by
OR plane
selectively removing
connections in the AND f1
and OR planes –
controlled by fuses or
memory bits f2
Other Memory Devices
• Non-volatile storage is offered by ROMs (and
some other memory technologies, e.g.,
FLASH), i.e., the data remains intact, even
when the power supply is removed
• Volatile storage is offered by Static Random
Access Memory (SRAM) technology
– Data can be written into and read out of the
SRAM, but is lost once power is removed
Memory Application
• Memory devices are often used in computer
systems
• The central processing unit (CPU) often
makes use of busses (a bunch of wires in
parallel) to access external memory devices
• The address bus is used to specify the
memory location that is being read or written
and the data bus conveys the data too and
from that location
• So, more than one memory device will often
be connected to the same data bus
Bus Contention
• In this case, if the output from the data pin of
one memory was a 0 and the output from the
corresponding data pin of another memory
was a 1, the data on that line of the data bus
would be invalid
• So, how do we arrange for the data from
multiple memories to be connected to the
some bus wires?
Bus Contention
• The answer is:
– Tristate buffers (or drivers)
– Control signals
• A tristate buffer is used on the data output of
the memory devices
– In contrast to a normal buffer which is either 1
or 0 at its output, a tristate buffer can be
electrically disconnected from the bus wire, i.e.,
it will have no effect on any other data currently
on the bus – known as the ‘high impedance’
condition
Tristate Buffer
Symbol Functional
Bus line Bus line
analogy
OE = 1
Output Enable
(OE) = 1 OE = 0
OE = 0
Control Signals
• We have already seen that the memory
devices have an additional control input (OE)
that determines whether the output buffers are
enabled.
• Other control inputs are also provided:
– Write enable (WE). Determines whether data is
written or read (clearly not needed on a ROM)
– Chip select (CS) – determines if the chip is
activated
• Note that these signals can be active low,
depending upon the particular device
Sequential Logic
Flip-flops and Latches

Sequential Logic
• The logic circuits discussed previously
are known as combinational, in that the
output depends only on the condition of
the latest inputs
• However, we will now introduce a type
of logic where the output depends not
only on the latest inputs, but also on the
condition of earlier inputs. These circuits
are known as sequential, and implicitly
they contain memory elements
Memory Elements
• A memory stores data – usually one bit per
element
• A snapshot of the memory is called the state
• A one bit memory is often called a bistable,
i.e., it has 2 stable internal states
• Flip-flops and latches are particular
implementations of bistables
RS Latch
• An RS latch is a memory element with 2
inputs: Reset (R) and Set (S) and 2
outputs: Q and Q .
R Q S R Q Q  comment
0 0 Q Q hold
0 1 0 1 reset
1 0 1 0 set
Q 1 1 0 0 illegal
S
Where Q is the next state
and Q is the current state
RS Latch - Operation
R NOR truth table
1 Q
a b y
0 0 1 b complemented
0 1 0
2 Q 1 0 0 always 0
S 1 1 0
• R = 1 and S = 0
– Gate 1 output in ‘always 0’ condition, Q  0
– Gate 2 in ‘complement’ condition, so Q  1
• This is the (R)eset condition
R NOR truth table
1 Q
a b y
0 1 0
2 Q 1 0 0 always 0
S 1 1 0
• S = 0 and R to 0
– Gate 2 remains in ‘complement’ condition, Q  1
– Gate 1 into ‘complement’ condition, Q  0
• This is the hold condition
R NOR truth table
1 Q
a b y
0 1 0
2 Q 1 0 0 always 0
S 1 1 0
• S = 1 and R = 0
– Gate 1 into ‘complement’ condition, Q  1
– Gate 2 in ‘always 0’ condition, Q  0
• This is the (S)et condition
R NOR truth table
1 Q
a b y
0 1 0
2 Q 1 0 0 always 0
S 1 1 0
• S = 1 and R = 1
• This is the illegal condition
RS Latch – State Transition Table
• A state transition table is an alternative
way of viewing its operation
Q S R Q comment
0 0 0 0 hold
0 0 1 0 reset
0 1 0 1 set
0 1 1 0 illegal
1 0 0 1 hold
1 0 1 0 reset
1 1 0 1 set
1 1 1 0 illegal
• A state transition table can also be
expressed in the form of a state diagram
RS Latch – State Diagram
• A state diagram in this case has 2
states, i.e., Q=0 and Q=1
• The state diagram shows the input
conditions required to transition
between states. In this case we see that
there are 4 possible transitions
• We will consider them in turn
Q  0 Q  0
Q S R Q comment From the table we can see:
0 0 0 0 hold S .R  S .R  S .R 
0 0 1 0 reset
0 1 0 1 set S .( R  R )  S .R  S  S .R 
illegal
0 1 1 0 ( S  S ).( S  R )  S  R
1 0 0 1 hold
1 0 1 0 reset Q 1 Q  1
1 1 0 1 set
illegal From the table we can see:
1 1 1 0
S .R  S .R  R .( S  S ) 
R
Q 1 Q  0
Q S R Q comment
From the table we can see:
0 0 0 0 hold
0 0 1 0 reset S .R  S .R 
set
0 1 0 1
illegal R.( S  S )  R
0 1 1 0
1 0 0 1 hold
1 0 1 0 reset Q0 Q  1
1 1 0 1 set From the table we can see:
1 1 1 0 illegal
S.R
• Which gives the following state diagram:
S.R
S R Q0 Q 1 R
R
• A similar diagram can be constructed for the
Q output
• We will see later that state diagrams are a
useful tool for designing sequential systems
Clocks and Synchronous Circuits
• For the RS latch we have just described, we
can see that the output state changes occur
directly in response to changes in the inputs.
This is called asynchronous operation
• However, virtually all sequential circuits
currently employ the notion of synchronous
operation, that is, the output of a sequential
circuit is constrained to change only at a time
specified by a global enabling signal. This
signal is generally known as the system clock
Clocks and Synchronous Circuits
• The Clock: What is it and what is it for?
– Typically it is a square wave signal at a
particular frequency
– It imposes order on the state changes
– Allows lots of states to appear to update
simultaneously
• How can we modify an asynchronous
circuit to act synchronously, i.e., in
synchronism with a clock signal?
Transparent D Latch
• We now modify the RS Latch such that its
output state is only permitted to change when
a valid enable signal (which could be the
system clock) is present
• This is achieved by introducing a couple of
AND gates in cascade with the R and S inputs
that are controlled by an additional input
known as the enable (EN) input.
Transparent D Latch
R Symbol
Q
D Q
EN S Q
EN
D
AND truth table
• See from the AND truth table:
a b y
– if one of the inputs, say a is 0, the output
is always 0 0 0 0
– Output follows b input if a is 1 0 1 0
1 0 0
• The complement function ensures 1 1 1
that R and S can never be 1 at the
same time, i.e., illegal avoided
Transparent D Latch
R
Q
EN S Q
D
D EN Q Q  comment
X 0 Q Q RS hold
0 1 0 1 RS reset
1 1 1 0 RS set
• See Q follows D input provided EN=1.

If EN=0, Q maintains previous state
Master-Slave Flip-Flops
• The transparent D latch is so called ‘level’
triggered. We can see it exhibits transparent
behaviour if EN=1. It is often more simple to
design sequential circuits if the outputs
change only on the either rising (positive
going) or falling (negative going) ‘edges’ of
the clock (i.e., enable) signal
• We can achieve this kind of operation by
combining 2 transparent D latches in a so
called Master-Slave configuration
Master-Slave D Flip-Flop
Master Slave Symbol
Qint
D D Q D Q Q D Q
CLK
• To see how this works, we will use a timing diagram

• Note that both latch inputs are effectively connected
to the clock signal (admittedly one is a complement
of the other)
Master-Slave D Flip-Flop
Master Slave
Qint
D D Q D Q Q
See Q changes on rising

CLK edge of CLK
CLK
CLK
Note propagation delays
D have been neglected in
the timing diagram
Qint
Q
D Flip-Flops
• The Master-Slave configuration has
now been superseded by new F-F
circuits which are easier to implement
and have better performance
• When designing synchronous circuits it
is best to use truly edge triggered F-F
devices
• We will not consider the design of such
F-Fs on this course
Other Types of Flip-Flops
• Historically, other types of Flip-Flops
have been important, e.g., J-K Flip-
Flops and T-Flip-Flops
• However, J-K FFs are a lot more
complex to build than D-types and so
have fallen out of favour in modern
designs, e.g., for field programmable
gate arrays (FPGAs) and VLSI chips
Other Types of Flip-Flops
• Consequently we will only consider
synchronous circuit design using D-type
FFs
• However for completeness we will
briefly look at the truth table for J-K and
T type FFs
J-K Flip-Flop
• The J-K FF is similar in function to a
clocked RS FF, but with the illegal state
replaced with a new ‘toggle’ state
J K Q Q  comment Symbol
0 0 Q Q hold J Q
0 1 0 1 reset
1 0 1 0 set K Q
1 1 Q Q toggle
T Flip-Flop
• This is essentially a J-K FF with its J
and K inputs connected together and
renamed as the T input
Symbol
T Q Q  comment Q
0 Q Q hold T
1 Q Q toggle Q

Asynchronous Inputs
• It is common for the FF types we have mentioned
to also have additional so called ‘asynchronous’
inputs
• They are called asynchronous since they take
effect independently of any clock or enable inputs
• Reset/Clear – force Q to 0
• Preset/Set – force Q to 1
• Often used to force a synchronous circuit into a
known state, say at start-up.
Timing
• Various timings must be satisfied if a FF
is to operate properly:
– Setup time: Is the minimum duration that
the data must be stable at the input before
the clock edge
– Hold time: Is the minimum duration that the
data must remain stable on the FF input
after the clock edge
Applications of Flip-Flops
• Counters
– A clocked sequential circuit that goes through a
predetermined sequence of states
– A commonly used counter is an n-bit binary
n
counter. This has n FFs and 2 states which are
n
passed through in the order 0, 1, 2, ….2 -1, 0, 1, .
– Uses include:
• Counting
• Producing delays of a particular duration
• Sequencers for control logic in a processor
• Divide by m counter (a divider), as used in a digital
watch
Applications of Flip-Flops
• Memories, e.g.,
– Shift register
• Parallel loading shift register : can be used for
parallel to serial conversion in serial data
communication
• Serial in, parallel out shift register: can be used
for serial to parallel conversion in a serial data
communication system.
Counters
• In most books you will see 2 basic types
of counters, namely ripple counters and
synchronous counters
• In this course we are concerned with
synchronous design principles. Ripple
counters do not follow these principles
and should generally be avoided if at all
possible. We will now look at the
problems with ripple counters
Ripple Counters
• A ripple counter can be made be cascading
together negative edge triggered T-type FFs
operating in ‘toggle’ mode, i.e., T =1
Q0 Q1 Q2
‘1’ ‘1’ ‘1’
Q Q Q
T T T
Q Q Q
CLK
• See that the FFs are not clocked using the

same clock, i.e., this is not a synchronous
design. This gives some problems….
Ripple Counters
• We will now draw a timing diagram
CLK
Q0
Q1
Q2
0 1 2 3 4 5 6 7 0
• Problems:
See outputs do not change at the same time, i.e., synchronously.
So hard to know when count output is actually valid.
Propagation delay builds up from stage to stage, limiting
maximum clock speed before miscounting occurs.
Ripple Counters
• If you observe the frequency of the counter
output signals you will note that each has half
the frequency, i.e., double the repetition
period of the previous one. This is why
counters are often known as dividers
• Often we wish to have a count which is not a
power of 2, e.g., for a BCD counter (0 to 9).To
do this:
– use FFs having a Reset/Clear input
– Use an AND gate to detect the count of 10 and
use its output to Reset the FFs
Synchronous Counters
• Owing to the problems identified with ripple
counters, they should not usually be used to
implement counter functions
• It is recommended that synchronous counter
designs be used
• In a synchronous design
– all the FF clock inputs are directly connected to the clock
signal and so all FF outputs change at the same time, i.e.,
synchronously
– more complex combinational logic is now needed to
generate the appropriate FF input signals (which will be
different depending upon the type of FF chosen)
• We will now investigate the design of
synchronous counters
• We will consider the use of D-type FFs
only, although the technique can be
extended to cover other FF types.
• As an example, we will consider a 0 to 7
up-counter
• To assist in the design of the counter we will make
use of a modified state transition table. This table
has additional columns that define the required FF
inputs (or excitation as it is known)
– Note we have used a state transition table previously
when determining the state diagram for an RS latch
• We will also make use of the so called ‘excitation
table’ for a D-type FF
• First however, we will investigate the so called
characteristic table and characteristic equation for a
D-type FF
Characteristic Table
• In general, a characteristic table for a FF
gives the next state of the output, i.e.,Q in
terms of its current state Q and current inputs
Q D Q Which gives the characteristic equation,
0 0 0 Q'  D
0 1 1 i.e., the next output state is equal to the
1 0 0 current input value
1 1 1
Since Q is independent of Q D Q
the characteristic table can 0 0
be rewritten as 1 1
Excitation Table
• The characteristic table can be modified to
give the excitation table. This table tells us
the required FF input value required to
achieve a particular next state from a given
current state
As with the characteristic table it can
Q Q D be seen that Q, does not depend
0 0 0 upon, Q , however this is not
0 1 1 generally true for other FF types, in
1 0 0 which case, the excitation table is
1 1 1 more useful. Clearly for a D-FF,
D  Q'
Characteristic and Excitation
Tables
• Characteristic and excitation tables can
be determined for other FF types.
• These should be used in the design
process if D-type FFs are not used
• We will now determine the modified
state transition table for the example 0
to 7 up-counter
Modified State Transition
Table
• In addition to columns representing the
current and desired next states (as in a
conventional state transition table), the
modified table has additional columns
representing the required FF inputs to
achieve the next desired FF states
Modified State Transition Table
• For a 0 to 7 counter, 3 D-type FFs are needed
Current Next FF The procedure is to:
state state inputs Write down the desired
Q2 Q1Q0 Q2' Q1' Q0' D2 D1D0 count sequence in the
0 0 0 0 0 1 0 0 1 current state columns
0 0 1 0 1 0 0 1 0 Write down the required
0 1 0 0 1 1 0 1 1
next states in the next
0 1 1 1 0 0 1 0 0 state columns
1 0 0 1 0 1 1 0 1
1 0 1 1 1 0 1 1 0 Fill in the FF inputs
1 1 0 1 1 1 1 1 1 required to give the
1 1 1 0 0 0 0 0 0 defined next state
Note: Since Q '  D (or D  Q ' ) for a D-FF, the
required FF inputs are identical to the Next state
Synchronous Counter Example
• Also note that if we are using D-type FFs, it
is not necessary to explicitly write out the
FF input columns, since we know they are
identical to those for the next state
• To complete the design we now have to
determine appropriate combinational logic
circuits which will generate the required FF
inputs from the current states
• We can do this from inspection, using
Boolean algebra or using K-maps.
Current Next FF By inspection,
state state inputs
D0  Q0
Q2 Q1Q0 Q2' Q1' Q0' D2 D1D0
Note: FF0 is toggling
0 0 0 0 0 1 0 0 1 Also, D1  Q0  Q1
0 0 1 0 1 0 0 1 0
0 1 0 0 1 1 0 1 1 Use a K-map for D2 ,
0 1 1 1 0 0 1 0 0 Q1Q0
Q0
1 0 0 1 0 1 1 0 1 Q2 00 01 11 10
1 0 1 1 1 0 1 1 0 0 1
1 1 0 1 1 1 1 1 1 Q2 1 1 1 1
1 1 1 0 0 0 0 0 0
Q1
Q0 .Q2 Q1.Q2 Q0 .Q1.Q2
Q0
Q1Q0
Q2 00 01 11 10
So,
0 1
Q2 1 1 1 1
D2  Q0 .Q2  Q1.Q2  Q0 .Q1.Q2
Q1 D2  Q2 .(Q0 .  Q1 )  Q0 .Q1.Q2
Q0 .Q2 Q1.Q2 Q0 .Q1.Q2
Q0 Q1 Q2
Q0
Q0
Q1 Combinati-
Q Q onal logic Q
D0 D1 Q1 D2
D D Q2 D
Q Q Q2 Q
CLK
Synchronous Counter
• A similar procedure can be used to design
counters having an arbitrary count sequence
– Write down the state transition table
– Determine the FF excitation (easy for D-types)
– Determine the combinational logic necessary to
generate the required FF excitation from the
current states – Note: remember to take into
account any unused counts since these can be
used as don’t care states when determining the
combinational logic circuits
Shift Register
• A shift register can be implemented
using a chain of D-type FFs
Q0 Q1 Q2
Q Q Q
Din D D D
Q Q Q
CLK
• Has a serial input, Din and parallel

output Q0, Q1 and Q2.
• See data moves one position to the
right on application of clock edge
Shift Register
• Preset and Clear inputs on the FFs can
be utilised to provide a parallel data
input feature
• Data can then be clocked out through
Q2 in a serial fashion, i.e., we now have
a parallel in, serial out arrangement
• This along with the previous serial in,
parallel out shift register arrangement
can be used as the basis for a serial
data link
Serial Data Link
Q0 Q1 Q2 Q0 Q1 Q2
Parallel in Serial Data Serial in

serial out parallel out
CLK
• One data bit at a time is sent across the serial

data link
• See less wires are required than for a parallel
data link
Synchronous State Machines
Synchronous State Machines
• We have seen how we can use FFs (D-types
in particular) to design synchronous counters
• We will now investigate how these principles
can be extended to the design of synchronous
state machines (of which counters are a
subset)
• We will begin with some definitions and then
introduce two popular types of machines
Definitions
• Finite State Machine (FSM) – a deterministic
machine (circuit) that produces outputs which
depend on its internal state and external inputs
• States – the set of internal memorised values,
shown as circles on the state diagram
• Inputs – External stimuli, labelled as arcs on the
state diagram
• Outputs – Results from the FSM
Types of State Machines
• Two types of state machines are in
general use, namely Moore machines
and Mealy machines
• In this course we will only look in detail
at FSM design using Moore machines,
although for completeness we will
briefly describe the structure of Mealy
machines
Machine Schematics
Moore Current state
Machine
Next state Q Optional
Outputs
Inputs combinational D combinational
n logic m Q m logic
CLK
Mealy
Current state
Machine
Next state Q
combinational Outputs
Inputs combinational D
n m m logic
logic Q
CLK
Moore vs. Mealy Machines
• Outputs from Mealy Machines depend upon
the timing of the inputs
• Outputs from Moore machines come directly
from clocked FFs so:
– They have guaranteed timing characteristics
– They are glitch free
• Any Mealy machine can be converted to a
Moore machine and vice versa, though their
timing properties will be different
Moore Machine - Example
• We will design a Moore Machine to implement
a traffic light controller
• In order to visualise the problem it is often
helpful to draw the state transition diagram
• This is used to generate the state transition
table
• The state transition table is used to generate
– The next state combinational logic
– The output combinational logic (if required)
Example – Traffic Light Controller
R See we have 4 states
So in theory we could
use a minimum of 2 FFs
However, by using 3 FFs
R
we will see that we do not
A A
need to use any output
combinational logic
So, we will only use 4 of
the 8 possible states
G
In general, state assignment is a
difficult problem and the optimum
choice is not always obvious
State By using 3 FFs (we will use
100 R D-types), we can assign one
to each of the required
outputs (R, A, G), eliminating
State
the need for output logic
010
R
State We now need to write down
A A
110 the state transition table
We will label the FF outputs
R, A and G
Remember we do not need to
G explicitly include columns for FF
State excitation since if we use D-types
001
these are identical to the next state
Current Next
State
100 R state state
R AG R ' A' G '
State 1 0 0 1 1 0
010 1 1 0 0 0 1
R 0 0 1 0 1 0
State
A
110
A 0 1 0 1 0 0
Unused states, 000, 011, 101 and
111. Since these states will never
occur, we don’t care what output
the next state combinational logic
G gives for these inputs. These don’t
State care conditions can be used to
001 simplify the required next state
combinational logic
Current Next We now need to determine the next
state state state combinational logic
R AG R ' A' G ' For the R FF, we need to determine DR
1 0 0 1 1 0 To do this we will use a K-map
1 1 0 0 0 1
0 0 1 0 1 0 AG G
0 1 0 1 0 0 R 00 01 11 10
0 X X 1
Unused states, 000, R 1 1 X X
R. A
011, 101 and 111.
R. A A
DR  R. A  R.A  R  A
Current Next By inspection we can also see:
state state
' ' ' DA  A
R AG R AG
1 0 0 1 1 0 and,
1 1 0 0 0 1 DG  R. A
0 0 1 0 1 0
0 1 0 1 0 0
Unused states, 000,

011, 101 and 111.
R A G
Q Q Q
DR DA DG
D D D
Q Q Q
CLK
FSM Problems
• Consider what could happen on power-up

• The state of the FFs could by chance be in
one of the unused states
– This could potentially cause the machine to
become stuck in some unanticipated sequence of
states which never goes back to a used state
FSM Problems
• What can be done?
– Check to see if the FSM can eventually
enter a known state from any of the
unused states
– If not, add additional logic to do this, i.e.,
include unused states in the state transition
table along with a valid next state
– Alternatively use asynchronous Clear and
Preset FF inputs to set a known (used)
state at power up
• Does the example FSM self-start?
• Check what the next state logic outputs
if we begin in any of the unused states
• Turns out:
Start Next state
state logic output
000 010
011 100 Which are all So it does
101 110 valid states self start
111 001
Example 2
• We extend Example 1 so that the traffic
signals spend extra time for the R and G
lights
• Essentially, we need 2 additional states, i.e.,
6 in total.
• In theory, the 3 FF machine gives us the
potential for sufficient states
• However, to make the machine combinational
logic easier, it is more convenient to add
another FF (labelled S), making 4 in total
Example 2
State State See that new FF
1000 R 1001 R
toggles which
makes the next
State
0101
state logic easier
FF labels R
State
A 1100 A
RAGS
As before, the first

step is to write
G G down the state
State State transition table
0010 0011
Example 2
State State Current Next
1000 R 1001 R state state
State
R AG S R ' A' G ' S '
0101 1 0 0 0 1 0 0 1
FF R 1 0 0 1 1 1 0 0
labels State
A 1100 A 1 1 0 0 0 0 1 1
RAGS 0 0 1 1 0 0 1 0
0 0 1 0 0 1 0 1
0 1 0 1 1 0 0 0
G G Clearly a lot of unused states.
State State When plotting k-maps to determine
0010 0011 the next state logic it is probably
easier to plot 0s and 1s in the map
and then mark the unused states
Example 2
Current Next
state state We will now use k-maps to determine
R AG S R ' A' G ' S ' the next state combinational logic
1 0 0 0 1 0 0 1 For the R FF, we need to determine DR
1 0 0 1 1 1 0 0 G
GS
1 1 0 0 0 0 1 1 R A 00 01 11 10
0 0 1 1 0 0 1 0 00 X X 0 0
0 0 1 0 0 1 0 1 01 X 1 X X
0 1 0 1 1 0 0 0 A
11 0 X X X
R R. A
10 1 1 X X
R. A
S
DR  R. A  R.A  R  A
Example 2
Current Next
state state We can plot k-maps for DA and DG
R AG S R ' A' G ' S ' to give:
1 0 0 0 1 0 0 1 DA  R.S  G.S or
1 0 0 1 1 1 0 0 DA  R.S  R.S  R  S
1 1 0 0 0 0 1 1
0 0 1 1 0 0 1 0 DG  R. A  G.S or
0 0 1 0 0 1 0 1 DG  G.S  A.S
0 1 0 1 1 0 0 0
By inspection we can also see:
DS  S
State Assignment
• As we have mentioned previously, state
assignment is not necessarily obvious or
straightforward
– Depends what we are trying to optimise, e.g.,
• Complexity (which also depends on the
implementation technology, e.g., FPGA, 74 series
logic chips).
– FF implementation may take less chip area than you may
think given their gate level representation
– Wiring complexity can be as big an issue as gate complexity
• Speed
– Algorithms do exist for selecting the ‘optimising’
state assignment, but are not suitable for manual
execution
State Assignment
• If we have m states, we need at least log 2 m
FFs (or more informally, bits) to encode the
states, e.g., for 8 states we need a min of 3
FFs
• We will now present an example giving
various potential state assignments, some
using more FFs than the minimum
Example Problem
• We wish to investigate some state
assignment options to implement a divide by
5 counter which gives a 1 output for 2 clock
edges and is low for 3 clock edges
CLK
Output
Sequential State Assignment
• Here we simply assign the states in an
increasing natural binary count
• As usual we need to write down the
state transition table. In this case we
need 5 states, i.e., a minimum of 3 FFs
(or state bits). We will designate the 3
FF outputs as c, b, and a
• We can then determine the necessary
next state logic and any output logic.
Current Next By inspection we can see:
state state
The required output is from FF b
c b a c b a Plot k-maps to determine the
0 0 0 0 0 1 next state logic:
0 0 1 0 1 0
0 1 0 0 1 1 For FF a:
a
0 1 1 1 0 0 ba a.c
1 0 0 0 0 0 c 00 01 11 10
0 1 1
c 1 X X X
Unused states, 101,
110 and 111. b
Da  a .c
For FF b:
a
Current Next ba
c 00 01 11 10 a.b
state state
0 1 1
c b a c b a c 1 X X X
0 0 0 0 0 1 a.b
0 0 1 0 1 0 b
0 1 0 0 1 1 Db  a .b  a.b  a  b
0 1 1 1 0 0 For FF c:
1 0 0 0 0 0 ba
a
c 00 01 11 10 a.b
Unused states, 101, 0 1
110 and 111. c 1 X X X
b
Dc  a.b
Sliding State Assignment
Current Next By inspection we can see that
state state we can use any of the FF
c b a c b a outputs as the wanted output
0 0 0 0 0 1 Plot k-maps to determine the
0 0 1 0 1 1 next state logic:
0 1 1 1 1 0
1 1 0 1 0 0 For FF a:
a
1 0 0 0 0 0 ba b.c
c 00 01 11 10
0 1 1 X
Unused states, 010, c 1 X X
101, and 111.
b
Da  b .c
Sliding State Assignment
Current Next By inspection we can see that:
state state For FF b:
c b a c b a Db  a
0 0 0 0 0 1 For FF c:
0 0 1 0 1 1
0 1 1 1 1 0 Dc  b
1 1 0 1 0 0
1 0 0 0 0 0
Unused states, 010,

101, and 111.
Shift Register Assignment
• As the name implies, the FFs are connected
together to form a shift register. In addition,
the output from the final shift register in the
chain is connected to the input of the first
FF:
– Consequently the data continuously cycles
through the register
Shift Register Assignment
Current Next Because of the shift register
state state configuration and also from the
e d c b a e d  c b a state table we can see that:
0 0 0 1 1 0 0 1 1 0 Da  e
0 0 1 1 0 0 1 1 0 0 Db  a
0 1 1 0 0 1 1 0 0 0 Dc  b
1 1 0 0 0 1 0 0 0 1 Dd  c
1 0 0 0 1 0 0 0 1 1 D d
e
By inspection we can see that
Unused states. Lots! we can use any of the FF
outputs as the wanted output
See needs 2 more FFs, but no logic and simple wiring

One Hot State Encoding
• This is a shift register design style where only
FF at a time holds a 1
• Consequently we have 1 FF per state,
compared with log 2 m for sequential assignment
• However, can result in simple fast state
machines
• Outputs are generated by ORing together
appropriate FF outputs
One Hot - Example
• We will return to the traffic signal example,
which recall has 4 states
R
For 1 hot, we need 1 FF for
each state, i.e., 4 in this case
The FFs are connected to form
a shift register as in the
R
A A previous shift register example,
however in 1 hot, only 1 FF
holds a 1 at any time
We can write down the state
G transition table as follows
One Hot - Example
R
Current Next
state state
r ra g a r  ra g  a
R 10 0 0 0 1 0 0
A A 01 0 0 0 0 1 0
00 1 0 0 0 0 1
00 0 1 1 0 0 0
Unused states. Lots!
G
Because of the shift register configuration
and also from the state table we can see
that: Da  g Dg  ra Dra  r Dr  a
To generate the R, A and G outputs we do the following ORing:
R  r  ra A  ra  a Gg
One Hot - Example
Da  g Dg  ra Dra  r Dr  a
R  r  ra A  ra  a Gg
r ra g Q a
Q Q Q
Dr Dra Dg Da
D D D D
Q Q Q Q
CLK
R A G
Tripos Example
• The state diagram for a synchroniser is shown.
It has 3 states and 2 inputs, namely e and r.
The states are mapped using sequential
assignment as shown.
e e.r r FF labels
[s1 s0]
Sync Hunt
[10] [00]
e.r
e.r e.r An output, s should be
r true if in Sync state
Sight
[01]
e
Tripos Example
Current Input Next
r state state
e e.r
s1 s0 e r s1' s0'
Sync Hunt
[10] [00] 0 0 X 0 0 0
e.r 0 0 X 1 0 1
e.r e.r 0 1 0 X 0 1
r 0 1 1 0 0 0
Sight
[01] 0 1 1 1 1 0
e 1 0 0 X 1 0
1 0 1 0 0 0
Unused state 11 1 0 1 1 1 0
1 1 X X X X
From inspection, s  s1
Tripos Example
Current Input Next Plot k-maps to determine the
state state next state logic
s1 s0 e r s1' s0' For FF 1:
e
0 0 X 0 0 0 er
0 0 X 1 0 1 s1 s0 00 01 11 10 s0 .e.r
0 1 0 X 0 1 00
0 1 1 0 0 0 01 1 s0
0 1 1 1 1 0
11 X X X X
1 0 0 X 1 0 s1
1 0 1 0 0 0 10 1 1 1
1 0 1 1 1 0 r
s1.e s1.r
1 1 X X X X
D1  s1.e  s1.r  s0 .e.r
Tripos Example
Current Input Next Plot k-maps to determine the
state state next state logic
s1 s0 e r s1' s0' For FF 0:
e
0 0 X 0 0 0 er
0 0 X 1 0 1 s1 s0 00 01 11 10 s1.s0 .r
0 1 0 X 0 1 00 1 1
0 1 1 0 0 0 01 1 1 s0
0 1 1 1 1 0 11 X X X X
1 0 0 X 1 0 s1
10
1 0 1 0 0 0
1 0 1 1 1 0 s0 .e r
1 1 X X X X
D0  s0 .e  s1.s0 .r
Tripos Example
• We will now re-implement the synchroniser
using a 1 hot approach
• In this case we will need 3 FFs
e e.r r FF labels
[s2 s1 s0]
Sync Hunt
[100] [001]
e.r An output, s should be
e.r e.r true if in Sync state
r
Sight From inspection, s  s2
[010]
e
Tripos Example
Current Input Next
state state
e e.r r
s2 s1 s0 e r s2' s1' s0'
Sync Hunt 0 0 1 X 0 0 0 1
[100] [001]
e.r 0 0 1 X 1 0 1 0
0 1 0 0 X 0 1 0
e.r e.r r 0 1 0 1 0 0 0 1
Sight 0 1 0 1 1 1 0 0
[010] 1 0 0 0 X 1 0 0
e 1 0 0 1 0 0 0 1
1 0 0 1 1 1 0 0
Remember when interpreting this table, because of the 1-
hot shift structure, only 1 FF is 1 at a time, consequently it
is straightforward to write down the next state equations
Tripos Example
Current Input Next For FF 2:
state state D2  s1.e.r  s2 .e  s2 .e.r
s2 s1 s0 e r s2' s1' s0' For FF 1:
0 0 1 X 0 0 0 1 D1  s0 .r  s1.e
0 0 1 X 1 0 1 0 For FF 0:
0 1 0 0 X 0 1 0
0 1 0 1 0 0 0 1 D0  s0 .r  s1.e.r  s2 .e.r
0 1 0 1 1 1 0 0
1 0 0 0 X 1 0 0
1 0 0 1 0 0 0 1
1 0 0 1 1 1 0 0
Tripos Example
r Note that it is not strictly
e e.r
necessary to write down the
Sync Hunt state table, since the next state
[100]
e.r [001] equations can be obtained from
the state diagram
e.r e.r r It can be seen that for each
Sight
[010] state variable, the required
e equation is given by terms
representing the incoming arcs
on the graph
For example, for FF 2: D2  s1.e.r  s2 .e  s2 .e.r
Also note some simplification is possible by noting that:
s2  s1  s0  1 (which is equivalent to e.g., s2  s1  s0 )
Tripos Example
• So in this example, the 1 hot is easier to
design, but it results in more hardware
compared with the sequential state
assignment design
Implementation of FSMs
• We saw previously that programmable logic
can be used to implement combinational logic
circuits, i.e., using PAL devices
• PAL style devices have been modified to
include D-type FFs to permit FSMs to be
implemented using programmable logic
• One particular style is known as Generic
Array Logic (GAL)
GAL Devices
• They are similar in concept to PALs, but
have the option to make use of a D-type flip-
flops in the OR plane (one following each OR
gate). In addition, the outputs from the D-
types are also made available to the AND
plane (in addition to the usual inputs)
– Consequently it becomes possible to build
programmable sequential logic circuits
AND plane
Q
OR plane D
Q
GAL
Device Q
D
Q
FPGA
• Field Programmable Gate Array (FPGA)
devices are the latest type of programmable
logic
• Are a sea of programmable wiring and
function blocks controlled by bits downloaded
from memory
• Function units contain a 4-input 1 output look-
up table with an optional D-FF on the output
3 Flip-Flops
Flip-flops and latches are digital memory circuits that can remain in the
state in which they were set even after the input signals have been
removed. This means that the circuits have a memory function and will
hold a value ( 0 or 1 ) until the circuit is forced to change state.
A latch is a memory device that samples and acts upon its input lines
immediately the input lines change. It does not require any external
timing signals.
A flip-flop is a memory device that samples and acts upon its input lines
only when it is told to do so with a special timing signal called the clock.
This may be in the form of a level or an edge. A level trigger means that
the flip-flop samples its inputs depending upon the voltage level of the
trigger input. An edge trigger means that the flip-flop samples its inputs
depending on a LOW-to-HIGH transition on the trigger line or a HIGH-
to-LOW transistion on a trigger line.
3.1 RS Latches
The latch is a logic block that has 2 stable states (0) or (1).
The RS latch can be forced to hold a 1 when the Set line is asserted.
The RS latch can be forced to hold a 0 when the Reset line is asserted.
The RS latch will hold it current value (state) if the Set and Reset lines
are not asserted.
The circuit for he RS latch can be seen below.
_
R S
Q Q
_ _
Q _ Q
S R
Cross-coupled NOR RS latch Cross-coupled NAND RS latch
45
The most noticeable thing about the latch is that it has a feedback path
from the output to the inputs. It is this feedback path which enables it to
hold a value even when the inputs are not asserted.
There are two types of RS latch. Cross-coupled NOR and cross-coupled

NAND.
The NOR type has high active R and S inputs. This means they perform
their prescribed action when the lines are high.
The NAND type has low active R and S inputs. This means they perform
their prescribed action when the lines are low.
The symbols for the RS latches are shown below:
S Q S Q
R /Q R /Q
Active High Active Low
Active High indicates that a high (1) will activate the line.
Active Low indicates that a low (0) will activate the line.
To understand the operation of the RS it is instructive to trace through the

logic signals when different values are placed on the R and S lines. Due
to the feedback, this may require tracing the lines at least twice until the
latch is in a stable state.
For simplicity we will examine the cross-coupled NOR latch since it is

high active.
46
3.1.1 Reset Condition
R 1 R 1 1 -> 0
Q Q
A 0 A 0
_ _
B 1 Q B 1 Q
S S
0 0 1 -> 0
Q = 0, /Q = 1 Q = 1, /Q = 0
Analysis:
Initial Q=0, /Q=1
• Q and /Q must be different values.

• When R is set to 1
• Gate A has a 1,0 input, therefore output Q=0,
• Gate B has a 0,0 input, therefore output /Q=1
Initial Q=1, /Q=0

47
3.1.2 Set Condition
R 0 0->1 R 0
Q Q
A A 1
_ _
B Q B 0 Q
S S
1 1->0 1
Q = 0, /Q = 1 Q = 1, /Q = 0
Analysis:
Initial Q=0, /Q=1

• When S is set to 1
• Gate B has a 1,0 input, therefore output /Q=0,
• Gate A has a 0,0 input, therefore output Q=1
Initial Q=1, /Q=0

• When S is set to 1
• Gate B has a 1,1 input, therefore output /Q=0,
48
3.1.3 Hold Condition
R 0 R 0
Q Q
A 0 A 1
_ _
B 1 Q B 0 Q
S S
0 0
Q = 0, /Q = 1 Q = 1, /Q = 0
Analysis:
Initial Q=0, /Q=1

Initial Q=1, /Q=0

49
3.1.4 Disallowed Condition
R 1 R 1 1->0
Q Q
A 0 A
_ _
B Q B 0 Q
S S
1 1->0 1
Q = 0, /Q = 1 Q = 1, /Q = 0
Analysis:
Initial Q=0, /Q=1

• When R is set to 1, S is set to 1
Initial Q=1, /Q=0

• When R is set to 1, S is set to 1
ALARM BELLS SHOULD BE RINGING.
This violates our logic rules.

Q and NOT Q cannot both be 0.
Therefore R=1, S=1 cannot not be allowed to happen.
We avoid these inputs at all costs.
50
3.1.5 Truth Table for Set – Reset Latch
S R Q /Q Comment
1 0 1 0 Sets latch to 1
0 1 0 1 Resets latch to 0
0 0 hold hold Retains Q & /Q values
1 1 - - Disallowed
Timing Diagram
Initial Q=0, then a momentary Set Pulse, then a momentary Reset Pulse
/Q
A B C D E
Region S R Description Q
A 0 0 Hold 0
B 1 0 Set Latch 1
C 0 0 Hold previous 1
D 0 1 Reset Latch 0
E 0 0 Hold previous 0
51
3.2 Gated RS Latch
0 when Enable = 0
Set
S Q Q
Enable
R /Q /Q
Reset
0 when Enable = 0
The AND gates are used to pass the Set and Reset signals to the latch
when the Enable line is asserted.
The latch will operate normally when the Enable is HIGH.
The latch will not respond when the Enable is LOW.
The following truth table for the gated SR latch can be constructed using
the following properties of AND gates
X.0=0
X.1=X
Enable Set Reset S R Result

(Set . Enable) (Reset . Enable)
0 0 0 0 0 No change
0 1 0 0 0 No change
0 0 1 0 0 No change
1 0 0 0 0 No change
1 1 0 1 0 Q=1
1 0 1 0 1 Q=0
1 1 1 1 1 Disallowed
52
Timing Diagram
En
Set
Reset
A B C D E
Region En Set Reset S R Description Q

A 0 0 0 0 0 Unchanged 0
B 1 1 0 1 0 Set Latch 1
C 0 0 1 0 0 Unchanged 1
D 1 0 1 0 1 Reset Latch 0
E 0 1 0 1 0 Unchanged 0
Regions B & D, set and reset the latch since Enable is HIGH.
Regions A & C & E, do nothing since Enable is LOW.
Symbol
S Q
R /Q
En
S is the Set.
R is the Reset.
En is the Enable (Gate).
Q is the output.
53
3.2.1 Integrated Circuit RS Latch (74279)
This contains 4 low active RS latches.
This is called the Quad Set-Reset Latch
Each latch has a R and S input, with only the Q output.
It should be noted that the R and S lines are low active.
Two of the latches are unusual in that they have 2 set lines. For most
applications it is best to tie these lines together.
This device is NOT gated.
54
3.3 Gated D Latch
A D latch stands for Data Latch.
A D latch uses only one input to set and reset the latch.
This is achieved by placing a NOT gate between the S and R inputs of a

gated SR latch.
The NOT guarantees that the unwanted R=S=1 does not occur.
The enable controls the latching of the data.

S Q Q
Data
R /Q /Q
En
Enable
Truth Table
Enable Data Result

0 0 No change
0 1 No change
1 0 Q=0
1 1 Q=1
55
Timing Diagram
En
Data
A B C D E
Region En Data Description Q

A 0 0 Unchanged 0
B 1 1 Load Data 1
C 0 1 Unchanged 1
D 1 0 Load Data 0
E 0 1 Unchanged 0
The data is loaded into the latch in regions B & D since Enable is HIGH.
Regions A & C & E, do nothing since Enable is LOW.
Symbol
D Q
En /Q
D is the Data.
En is the Enable (Gate).
Q is the output.
56
3.3.1 Integrated Circuit D Latch (7475)
This contains 4 D latches.
It is called the 4-bit bistable latch.
Latches 0,1 share the same enable.
Latches 2,3 share the same enable.
Information present at a dat input (D) is transferred to the Q output when

the enable is HIGH and the Q output will follow the D input as long as
the enable is HIGH.
There are Q and /Q outputs for all the latches.
57
3.4 Triggering & Clocking
A trigger is a control signal used to initiate an action.
In the gated latches, the trigger is the enable line. Setting the enable
HIGH allows the latch to be set or reset.
Triggers can be of two forms

1. Level Triggers (HIGH or LOW levels)
2. Edge Triggers (+ve or –ve going transitions)
Examining a pulse, indicates all the possible levels and edges
A B
C D
Letter Comment
A LOW level
B HIGH level
C Positive Edge (LOW -> HIGH Transition)
D Negative Edge (HIGH -> LOW Transition)
A level trigger means that an action is initiated on either a LOW or HIGH

level.
An edge trigger means that an action is initiated on either a positive or

negative transition.
A clock is a series of pulses (Square Waves) used to synchronise actions.

Generally the triggers are taken from the edges of the clock.
58
3.4.1 Edge Triggering
The positive edge triggering circuit is given below
P
X
/P
The propagation delay of the inverter causes a delay of a few

nanoseconds between P and /P. The AND gate translates this into a
narrow pulse (X) of the order of a few nanoseconds in duration.
Pulse X is long enough to trigger a change in the state of the latches.
Q. How do you make a negative edge detector?

A. Invert the pulse P before applying to the circuit above.
Q. How do you make an edge triggered SR latch or D latch?

A. Add the edge detector to the enable line.
S S Q Q
R R /Q /Q
Edge
CLK Detector En
D D Q
Edge
CLK Detector En /Q
59
3.4.2 Symbols
Positive Level Triggered Negative Level Triggered
Positive Edge Triggered Negative Edge Triggered
3.4.3 Truth Table
Positive Edge Triggered RS Flip-Flop
Edge Set Reset Result

X 0 0 No change
0 0 No change
1 0 Q=1
0 1 Q=0
1 1 Invalid
Note:
X is don’t care. (Can be either 0 or 1)
indicates a LOW to HIGH (positive) transition.
Positive Edge Triggered D Flip-Flop
Edge Data Result

X X No change
0 Q=0
1 Q=1
Note:
X is don’t care. (Can be either 0 or 1)
indicates a LOW to HIGH (positive) transition.
60
3.4.4 Integrated Circuit D Flip-Flop (7474)
This contains 2 D-type flip-flops.
This is called the Dual D-Type Positive Edge-Triggered Flip-Flop.
There is an asynchronous preset and clear for these flip-flops to allow the
initial state to be set.
There is a CP (clock pulse) input which requires the synchronising clock

signal.
Information at the input is transferred to the outputs on the positive edge

of the clock pulse. After the clock pulse input threshold has been passed,
the Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the clock pulse
input.
3.4.5 Integrated Circuit Octal D Latch (74273)
This is called an 8-bit Register.
This contains 8 x D latches which is ideal for computer applications.
Each latch contains 1 bit and 8 bits make one byte.
All 8 latches are controlled by a common clock signal.
Data is latched in on the positive edge of the clock.
All 8 latches can be simultaneously reset (cleared) by asserting the

Master Reset (/MR) line.
This is a high-speed 8 bit register, consisting of 8 D-type flip-flops with a

common clock and an asynchronous active LOW Master Reset.
61
3.5 Edge Triggered JK Flip-Flop
The JK is a widely used flip-flop.
J & K do not mean anything special.
The J is equivalent to a set.
The K is equivalent to a reset.
A JK flip-flop acts like a RS flip-flop except that it does not have a

invalid state.
The R=S=1 state has been replaced with a toggle state.
Toggle means that the output (Q) will change to the opposite state (0 to 1
or 1 to 0) after every clock transition.
The JK is an RS flip-flop with feed back from Q and /Q.
J
S /Q /Q
Edge
Detector
CLK R Q Q
Truth Table
CLK J K Result
X 0 0 No change
0 0 No change
1 0 Q=1
0 1 Q=0
1 1 Toggle
62
3.5.1 Illustration of Toggle
CLK
A B C D E F
Region En J K Description Q
A 0 0 0 Initial 1
B 1 1 Toggle 0
C 1 1 Toggle 1
D 1 1 Toggle 0
E 1 1 Toggle 1
F 1 1 Toggle 0
Symbol
J Q
Clk /Q
63
3.5.2 Asynchronous Preset and Clear Inputs
The previous flip-flops are synchronous because data is transferred to the

flip-flops output on the clock signal.
Asynchronous inputs change the state of the flip-flop without requiring a

clock pulse.
The asynchronous inputs are normally preset and clear, which allows the
flip-flop to be set and reset.
The preset and clear are level triggered, generally LOW active.
CLK
PRE
CLR
A B C D E F
64
3.5.3 Other types of flip-flops from JK Flip-Flops
JK flip-flops are widely used because of their versatility. They can be

easily adapted for use as a RS flip-flop, D flip-flop, and T flip-flop.
Edge Triggered RS flip-flop
The RS flip-flop can be constructed out of a JK flip-flop by setting S=J

and R=K. S Q
J Q
CLK Clk /Q /Q
R K
Edge Triggered D flip-flop
A D flip-flop can be constructed out of a JK flip-flop by connecting an

inverter between J and K.
D J Q Q
CLK Clk /Q /Q
Edge Triggered T flip-flop
A Toggle flip-flop can be constructed out of a JK flip-flop by connecting

J and K to HIGH.
1 J Q Q
CLK Clk /Q /Q
1 K
65
3.5.4 Integrated Circuit JK Flip-Flop (7476)
This contains 2 JK-type flip-flops.
This is called the Dual JK Flip-Flop.
There is an asynchronous low active preset (/SD) and clear (/CD) for
these flip-flops to allow the initial state to be set.
There is are 2 CP (clock pulse) inputs which synchronises the flip-flops to

the clock.
When the Clock Pulse input is HIGH, the JK inputs are enabled and data
is accepted. This data will be transferred to the outputs according to the
Truth Table on the HIGH-to-LOW clock transitions.
66
3.6 Master – Slave Flip-Flops
A master-slave flip-flop is a flip-flop that responds to a pulse rather than

an edge or a level.
It consists of two flip-flops called the master and the slave.
The master flip-flop latches the inputs on the positive edge of the clock
and transfers them to the slave on the negative edge of the clock.
A B
Region Description
A Inputs gated into the Master
B Master transfers inputs to Slave
Eg
RS Master Slave Flip-Flop
MASTER SLAVE
S R Q R Q Q
MR
S /Q S /Q /Q
R MS
En En
CLK
The Master latches the SR inputs on the positive edge of the clock.
The Slave latches the MR and MS inputs and generates the Q and /Q on
the negative edge of the clock.
67
3.7 AC Characteristics
Propagation Delay Time (tPLH, tPHL)
The time taken from the triggering input transition to the corresponding
output transition.
The transitions are measured from the 50% point.
The output (Q) is measured relative to the:

1. Clock Pulse input.
2. Preset and Clear inputs.
tPLH
50%
INPUT
Q 50%
tPLH
The input is either the Clock or the Preset inputs.
68
tPHL
50%
INPUT
50%
tPHL
The input is either the Clock or the Preset inputs.
Set-up Time (ts)
The minimum time that the logic levels must be maintained on the inputs
prior to the clock transition.
This guarantees that the inputs are reliably clocked into the flip-flop.
50%
INPUT
CLK
50%
tS
69
Hold Time (th)
The minimum time that the logic levels must be maintained on the inputs
after the clock transition.
This guarantees that the inputs are reliably clocked into the flip-flop.
INPUT 50%
50%
CLK
th
Maximum Clock Frequency (fmax)
The highest frequency which can reliably be used as a clock.
Pulse Width (tw)
The minimum pulse width for the preset, clear, and clock inputs.
3.8 DC Characteristics
Power Dissipation
The total power consumption of the device.
70
3.9 Propagation Delay
Propagation delays can cause timing problems with flip-flop circuits. The
propagation delay is the time taken for the flip-flop to respond after
receiving the active clock edge.
CLK
tprop
The following circuit illustrates a potential timing problem with

triggering flip-flops off the same clock pulse.
Vcc
CLK
D Q D Q
CLK CLK
FF1 FF2 Q1
tprop
Q2
The idea is that when the negative edge of the clock pulse occurs, the
output of FF1 is latched in FF2.
This will not happen as expected due to the propagation delay of the FF1.
Instead FF2 will latch output of FF1 before FF1 has had time to change
its output.
We use this effect to our advantage when we make ripple counters in

module 3.
The way to fix the timing problem is to make FF1 latch the data on the
positive edge and make FF2 latch the data on the negative edge.
71
3.10 RS Latch circuit to remove contact bounce
A switch circuit is shown below. It is expected that when the when the
switch makes contact with pole 1 the line will go low. However, this is
not the case. Switch bounce can cause the voltage to randomly fluctuate
between Vcc and ground until it finally settles at ground. This can cause
false triggering in digital circuits.
VCC
Vcc
1
Sw
Gnd
The contact bounce can be eliminated using an RS latch as in the

following circuit.
VCC
1
S Q Sw
R Q
2
When the switch is connected to pole 1, the set line is LOW and the reset
line is HIGH. This sets the latch forcing Sw HIGH. When the switch is
connected to pole 2, the reset line is LOW and the set line is HIGH. This
resets the latch forcing Sw LOW. Contact bounce will not affect this
circuit as long as the initial contact with pole 2 is long enough to assert
the reset.
72

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4 BOOLEAN ALGEBRA

At the end of the lesson, students should be able to:

NOT, AND, OR, NAND AND NOR GATES USING

Boolean algebra is the mathematics of digital systems. A basic knowledge of Boolean

► Variable, complement and literal

i. Variable - Symbol (usually an italic uppercase letter to

ii. Complement - Is the inverse of a variable and is indicated by a

iii. Literal - A literal is a variable or the complement of a

Fatma Syazana Zaini

Determine the values of A, B, C and D that make the sum term

Fatma Syazana Zaini

In Boolean algebra, a product term is the product of literals. Some examples of

AB, AB, ABCandABCD

A product term is equal to 1 only if each of the literals in the term is 1.

ABC D  1.0.1.0  1.1.1.1  1

► Laws And Rules Of Boolean Algebra

 Laws of Boolean Algebra

The basic of Boolean algebra: -

Fatma Syazana Zaini

 Twelve Basic Rules of Boolean Algebra

Fatma Syazana Zaini

Fatma Syazana Zaini

Fatma Syazana Zaini

  A  B - rule 4: drop the 1

Rule 12. (A + B)(A + C) = A + BC

Fatma Syazana Zaini

4.2 DEMORGAN’S THEOREMS

► State DeMorgan’s Theorem

Two DeMorgan’s theorem are: -

Sign ‘.’ Change to ‘+’, breaks the bar

Sign ‘+’ Change to ‘.’, breaks the bar

► Relate DeMorgan’s Theorem to the equivalency of the: -

i. NAND and negative-OR gates

ii. NOR and negative-AND gates

Fatma Syazana Zaini

Apply DeMorgan’s theorems to the expression XYZ and X  Y  Z

► Applying DeMorgan’s Theorem

Applying DeMorgan’s theorem to the expression below:

From DeMorgan rule (b):

Insert (2) into (1)

Fatma Syazana Zaini

Simplify the expression

Step 1: DeMorgan Rule (a) :

Step 2: DeMorgan Rule (b) :

Simplify the expression

Step 1 : … … Rule 1: A+(B+C)=(A+B)+C

Step 2 : DeMorgan Rule (b) :

Fatma Syazana Zaini

SIMPLIFICATION USING BOOLEAN ALGEBRA INTO SUM – OF –

Also an SOP expression can contain a single-variable term as in A + A B C + B C D. In an

► Domain of a Boolean expression

i. AB  ABC is the set of variables A, B and C

► Implementation of an SOP expression.

Fatma Syazana Zaini

Figure 4.1: Implementation of the SOP expression AB + BCD + AC

 Convert a General Expression to SOP Form

Convert each of the following Boolean expression to SOP form:

Fatma Syazana Zaini

► The Standard SOP Form

ABCD  ABC D  ABC D is a standard SOP expression.

 Convert Product Terms to Standard SOP

Step 1: multiply each nonstandard product term by made up of the sum of a

Convert the following Boolean expression into standard SOP form: