17th January: Lecture#6: 2nd Slot

By, Nirav Joshi 6th Electrical, Summer 2023

4. Microcontrollers

By, Nirav Joshi 6th Electrical, Summer 2023

4.1 Microprocessor vs Microcontrollers
Sr.
Microprocessor Microcontroller
No.
1 Microprocessor acts as a heart of computer system. Microcontroller acts as a heart of embedded system.
It is a processor in which memory and I/O It is a controlling device in which memory and I/O
2
output component is connected externally. output component is present internally.
Since memory and I/O output is to be connected Since on chip memory and I/O output component is
3
externally. Therefore the circuit is more complex. available. Therefore the circuit is less complex.

4 It cannot be used in compact system. It can be used in compact system.

Microprocessor has less number of registers.

Microcontroller has more number of registers.
5 Therefore most of the operations are memory
Therefore a program is easier to write.
based.

6 A microprocessor having a zero status flag. A microcontroller has no zero flag.

It is mainly used in washing machines, air conditioners

7 It is mainly used in personal computers.
etc.
By, Nirav Joshi 6th Electrical, Summer 2023
5. Von Neumann and Harvard Architecture
5.1 Von Neumann Architecture
• The Von Neumann architecture was first proposed by a computer scientist John von Neumann.
• In this architecture,
• one data path or bus exists for both instruction and data.
• As a result, the CPU does one operation at a time.

• It either fetches an instruction from memory, or performs read/write operation on data.

• So, an instruction fetch and a data operation cannot occur simultaneously, sharing a common
bus.

By, Nirav Joshi 6th Electrical, Summer 2023

5. Von Neumann and Harvard Architecture
5.1 Von Neumann Architecture

By, Nirav Joshi 6th Electrical, Summer 2023

5. Von Neumann and Harvard Architecture
5.2 Harvard Architecture
• The Harvard architecture offers separate storage and signal buses for instructions and data.
• In this architecture
• Data storage entirely contained within the CPU, and
• there is no access to the instruction storage as data.

• Computers have
• separate memory areas for program instructions and data using internal data buses,
• allowing simultaneous access to both instructions and data.

By, Nirav Joshi 6th Electrical, Summer 2023

5. Von Neumann and Harvard Architecture
5.2 Harvard Architecture
• In a Harvard architecture, there is no need to make the two memories share properties.

By, Nirav Joshi 6th Electrical, Summer 2023

5.3 Difference between Von Neumann and Harvard Architectures

• The major difference between the two architectures is that

• In a Von Neumann architecture all memory is capable of storing all program elements, data
and instructions;
• In a Harvard architecture the memory is divided into two memories, one for data and one
for instructions.

By, Nirav Joshi 6th Electrical, Summer 2023

5.3 Difference between Von Neumann and Harvard Architectures

By, Nirav Joshi 6th Electrical, Summer 2023

5.3 Difference between Von Neumann and Harvard Architectures

• In Von Neumann architecture

• at least two clock cycles required to execute an instruction, whereas
• In a Harvard architecture
• At least one cycle required to execute an instructions.

• The ability in a Harvard architecture to execute an instruction in a single instruction leads to a

much simpler and cleaner design for a CPU than one implemented using a Von Neumann
architecture.

By, Nirav Joshi 6th Electrical, Summer 2023

6. CISC and RISC Processors
• The architectural design of the CPU is
• A: Reduced instruction set computing (RISC) and
• B: Complex instruction set computing (CISC).

By, Nirav Joshi 6th Electrical, Summer 2023

6. CISC and RISC Processors

• RISC is the CPU design based on the vision that a

• basic instruction set gives great performance when combined with a microprocessor.

By, Nirav Joshi 6th Electrical, Summer 2023

6. CISC and RISC Processors
6.1 CISC Processors
• CISC was developed by the Intel Corporation.
• This processor includes a huge collection of simple to complex instructions.
• These instructions are specified in the level of assembly language level and the execution of
these instructions takes more time.

By, Nirav Joshi 6th Electrical, Summer 2023

6. CISC and RISC Processors
6.1 CISC Processors
• A CISC is a computer where
• single instructions can perform numerous low-level operations like
• a load from memory, an arithmetic operation, and a memory store in single instructions,
as its name proposes “Complex Instruction Set ”.

• So, this processor moves to decrease the number of instructions on every program & ignore the
number of cycles for each instruction.

By, Nirav Joshi 6th Electrical, Summer 2023

6. CISC and RISC Processors
6.1 CISC Processors
• It highlights to assemble complex instructions.
• However, CISC chips are relatively slower as compared to RISC chips but utilize small
instruction as compare with RISC.
• The best examples of the CISC processor include AMD, VAX, System/360 & Intel x86.

By, Nirav Joshi 6th Electrical, Summer 2023

6. CISC and RISC Processors
6.2 RISC Processors
• A RISC is a computer that only uses simple commands
• that can be divided into several instructions
• that achieve low-level operation within a single CLK cycle,
• as its name proposes “Reduced Instruction Set”.

By, Nirav Joshi 6th Electrical, Summer 2023

6. CISC and RISC Processors
6.2 RISC Processors
• The main function of this is to reduce the time of instruction execution by limiting as well as
optimizing the number of commands.
• So each command cycle uses a single clock cycle where every clock cycle includes three
parameters namely fetch, decode & execute.

• The best examples of RISC processors include PowerPC, SUN’s SPARC, RISC-V, Microchip
PIC processors, etc.

By, Nirav Joshi 6th Electrical, Summer 2023

6. CISC and RISC Processors
6.3 CISC vs RISC Processors
Parameters CISC RISC

Instruction Size Varies Fixed

Instruction Length 1,2,3 or 4 bytes 4 bytes

Number of Instructions More Less

Instruction Decoding Serial (slow to decode) Easy (fast) to decode

Instruction Semantics
Addressing Modes
Instruction execution speed
By, Nirav Joshi
Varies from simple to complex
Supports complex addressing
modes
Slow
Almost always one simple
operation
Complex addressing modes are
synthesized in software
Medium
6th Electrical, Summer 2023
6. CISC and RISC Processors
6.3 CISC vs RISC Processors
Parameters CISC RISC

Registers Few, may be special purpose Many, general purpose

Memory References Combined with operations in Not combined with operations

many different types of i.e. load/store architecture
instructions
Hardware Complicated Simple

Memory Access Frequently Rarely

Pipelined No Yes

Compiler Simple Complicated

Example
By, Nirav Joshi 6th Electrical, Summer 2023
 Thank
You
Find me on:
Nirav Joshi
nirav.joshi@marwadieducation.edu.in
9909350982