Xilinx ISE 9.

2i Manual

1. Click Xilinx ISE 8.2i icon or execute the software from Program Files.

2. Select “File” and choose “New Project” to generate new project.

3. Input project name and select folder path. The sample is written in VHDL so select “DHL” in Top-
Level Source Type column and then press “Next”.
4. Select IC type. The IC on LP-2900 chip board is Spartan2 series. The package of XC2S50 is PQ208
and it’s speed level is -5. Select “VHDL” in preferred language column.
5. User can select “Create a new source” in the next page. If user already has a source, press
“Next” to enter the next window and then load VHDL program to project.
6. Press “Add Source” to load sample program-ring and emulation test file-
ring_testbench
7. Press “Finish” and “OK”. Programs are loaded to project.
8. Enter main page and select “Synthesis/Implementation” in “Sources for” column. User can see IC
number and the loaded programs. User can do edit, synthesis Implementation, design and generate
programming File in this column.
9. Double click the loaded files and then the content of program appears in the right window.
User can directly edit the content .
10. After editing, user can double click “Assign Package Pins” to set the pins.
11. User can drag the I/O pin from left window to IC pins. User also can do I/O setting and constraint
in “Design Object List”.
12. Besides, use can double click “Edit Constraints(Text)” to directly edit .UCF file, set pins and
set constraints.
13. After editing the pins, start synthesis, implement design and generating programming file. If there is
an error in the process, there will be a red X on the item. The detail of each process appears in the right
column.

FP GA 內部資源所用的百分比
14. User can select” Floorplanner” or “FPGA Editor” to adjust CLB (Configurable Logic Block).
15. In “Floorplanner” page, user can see output pins and CLB address.
16. In “FPGA Editor” page, user can see the circuit of the internal IC. Please refer to HELP to get
detailed procedures.
17. Zoom out the figure and select a CLB line. Double click the CLB line to see the internal
connection. Please refer to HELP to get detailed procedures.
Simulation
After synthesis, user can start emulation. There are two kind s of emulation.
1. Behavioral simulation: only simulate function of the program and not to simulate winding and
delay of the IC.
2. Post- route simulation: simulate delay of the IC.

18. Execute implement Design\place & route\generate post-placed &Route Simulation Model
19. Behavioral simulation: Select “behavioral simulation” in “source for” column. User can see
ring_testbench file and ring sample in the window.
20. Select ring and execute Check Syntax.
21. Select ring_testbench and execute check Syntax. Then, execute simulate Behavioral Model. After
that, software generates simulation waveform.
22. Select the signal and drag it to simulation window. Software generates simulation waveform after
user sets “run for specified time”.
23.Post-route simulation is similar to behavioral simulation but it simulates better.
24. Download program
(1) Turn on LP-2900 and connect it to PC.
(2) Execute Configure Device (iMACT) and then software automatically generates . bit file and
then enters “Boundary Scan” page.
25. Move the cursor on the IC and right click to select “Program”.
26. Do not mark any item in this page. Press”OK” to start program.
27. Program succeeded. .