CS220: Computer Organization

Quiz#2 Solution Sketch

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1. A register file has 32 registers each of width 64 bits. The register file has two read ports and a write port. For
each port, there is a decoder which drives the wordlines. The read data appears on a set of bitlines and the data to
be written must be launched on a set of bitlines. The ports are designed in such a way that a read operation and a
write operation can be done at the same time. Further, the design is such that the environment can read from and
write to the same register simultaneously. Calculate the number of input bits to each decoder, the total number of
wordlines, and the total number of bitlines in the register file. (0.5+0.5+0.5 points)

Solution: There are 32 registers. So, the number of input lines to each decoder is log of that i.e., 5. Each port
requires a wordline for each row. The read and write ports cannot share wordlines. So, there are 32 × 3 or 96
wordlines. Each port requires a bitline per column. The read and write ports cannot share bitlines. So, the total
number of bitlines is 64 × 3 or 192.

2. A finite state machine (FSM) having 100 states is implemented using a state sequencer, a microcode ROM, five
dispatch ROMs, and a next state selection multiplexer. The FSM takes a seven-bit input. There are six states S
in the FSM for which the next state S ′ does not depend on the input and S ′ ̸= S + 1. Compute the minimum
width (in bits) of the microinstructions and the number of entries in each dispatch ROM. (1+0.5 points)

Solution: Each microinstruction (stored in a row of the microcode ROM) provides the selection input of the next
state selection multiplexer. There are twelve inputs to the next state selection multiplexer: (current state + 1),
six constant next states S ′ , and the five dispatch ROM outputs. So the selection input needs to be at least four
bits wide. This is the minimum width of the microinstructions. The dispatch ROM is indexed using the input.
Therefore, the number of entries in the dispatch ROM is 27 .

3. Consider a 1 GB DIMM card with one channel. The DIMM card has 64 chips. The interface between the
DIMM card and the SRAM cache is 128 bytes. The channel width is such that the best performing burst length is
eight. Each chip has several banks and the row buffer size in each bank in a chip is 2 KB. Each bank has 2048 rows
and 4096 columns. A computer has installed four such DIMM cards to have a total 4 GB of memory and each
DIMM card has its own channel. Write down the length (in number of bits) of different portions of an address as
decoded by the DRAM controller below. (1×7 points)

-----------,-------,-------,-----------,-----------,-----------,-----------.
Row number Rank Bank Column-high Channel Column-low

Solution: Since the best performing burst length is eight, the channel width must be exactly one-eighth of the
interface between the DIMM card and the SRAM cache. Therefore, the channel width is 128 bits or 16 bytes.
Thus, log2 (channelwidth) is the least significant four bits of the address. Since the interface between the DIMM

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card and the SRAM cache is 128 bytes, the channel bits (to select one of the four channels) would be placed after
seven bits from the least significant side. The width of column-low is same as log2 (BL) i.e., 3 because column-
low is incremented internally during the bursts of a burst length. Since the row buffer size is 2 KB or 16 Kb and
there are 4096 columns, the width of each column is (16 K)/4096 bits or 4 bits meaning that the chips are x4.
Column-high is 9 bits long so that the sum of Column-high and Column-low covers all the columns. The capacity
of a bank is 2 KB×2048 = 225 bits. The capacity of a chip is 1 GB/64 = 227 bits. So, the number of banks per chip
= 227 /225 = 4. So, the number of bits needed for bank number is 2. Since the channel width is 128 bits and the
chips are x4, 32 chips are needed in a rank. Therefore, there are two ranks in each channel and the rank number
needs one bit. The row number needs 11 bits to be able to cover 2048 rows. The total number of address bits is
32 (covering 4 GB of installed memory) as shown below.

11 1 2 9 2 3 4
-----------,-----------,-----------,-----------,-----------,-----------,-----------.
Row number Rank Bank Column-high Channel Column-low