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Processor Architectures – Von Neumann vs Harvard
Processor Architectures – Von Neumann vs Harvard
VON NEUMANN ARCHITECTURE HARVARD ARCHITECTURE
It is ancient computer architecture based on stored It is modern computer architecture based on
program computer concept. Harvard Mark I relay based model.
Same physical memory address is used for Separate physical memory address is used for
instructions and data. instructions and data.
There is common bus for data and instruction Separate buses are used for transferring data and
transfer. instruction.
Two clock cycles are required to execute single
An instruction is executed in a single cycle.
instruction.
It is cheaper in cost. It is costly than Von Neumann Architecture.
CPU can not access instructions and read/write at CPU can access instructions and read/write at the
the same time. same time.
It is used in personal computers and small
It is used in micro controllers and signal processing.
computers.
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ILP Example Problems
• Calculate ILP (Instruction Level Parallelism) for the following
operations, and also calculate the number of cores required to
achieve that ILP.
• i) C = A + B where A,B,C are 2x2 matrices.
• ii) C = A*B, where A,B,C are 2x2 matrices.
• iii) C = A*B, where A,B,C are 3x3 matrices.
• iv) Y = |A|, where A is 3x3 matrix and | | denotes determinant.
• v) Y = inverse(A), where A is 3x3 matrix.
ILP Example Problems (Contd.)
ILP vs No. of Cores
No. of Cores ILP
• Solutions: 1 1
2 2
i) C = A + B, where A,B,C are 2x2 matrices 3 2
4 4
Lets take A = , = , = 8 4
16 4
 The equations are = + ; = + ; =
+ ; = + ;
ILP vs No. of Cores
5
 Sequential execution Time = =1+1+1+1=4 _
4
 Maximum Parallel execution Time = =
1 _ ( ! ) 3

ILP
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'()

 Number of parallel Cores required (for ILP = 4) = 4 (since 4 additions 1

are running independently in parallel) 0


0 2 4 6 8 10 12 14 16 18 20
No. of Cores
ILP Example Problems (Contd.) ILP vs No. of Cores
No. of Cores ILP
1 1
• Solutions:
2 1.5
i) C = A x B, where A,B,C are 2x2 matrices 3 2
4 3
Lets take A = , = , = 8 6
16 6
 The equations are = + ; = + ;
= + ; = + ;
 Sequential execution Time = =3+3+3+3=
12 _ No. of Cores vs ILP
7
 Maximum Parallel execution Time = 1 time unit for mult. and 1 for 6
addition., and all four elements of matrix ‘C’ can run in parallel. 5
Hence total 2 time units. 4

ILP
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'() 2

 Number of parallel Cores required (for ILP=6) = (1 core for mult. 1

+ 1 core for addition) x 4 elements of matrix C = 2x4 = 8 cores. 0


0 2 4 6 8 10 12 14 16 18 20
No. of Cores
Speedup
• speedup is a number that measures the relative
performance of two systems processing the same problem
• Let total time taken in architecture 1 is T1 and
• after improvement of the architecture due to parallelism or
pipelining or any other technique, the time is reduced to T2
• Now the speedup in latency is given by:

#4
./ 0 123 = #5
Amdahl’s Law
• it states that "the overall performance improvement gained by optimizing a
single part of a system is limited by the fraction of time that the improved part
is actually used”
Amdahl’s Law - derivation
• Let the total time of the program is T which is divided into two parts,
• the part of program that cannot be parallelised or sequential time Tseq
• and the part of the time that can be parallelised Tpar
• Where the total time is T = Tseq + Tpar
• The sequential fraction of time sq = Tseq/T and the parallelisable fraction of time is p = Tpar/T
• sq + p = Tseq/T + Tpar/T = 1, or sq = 1 - p
• Let the speedup of parallelisable part is ‘s’, due to parallel processing
• Where Tpar,new = Tpar/s
• Now, the total speedup in latency is
Slatency = Told/Tnew
= T/(Tseq + Tpar,new)
= T/(Tseq + (Tpar/s))
= 1/(sq+(p/s))
= 1/((1-p)+(p/s)
Amdahl's law - Examples
• For a certain task in a computer, 30% of the execution time can be
subjected to speedup. If the improvement makes the affected part twice
as fast. Calculate the overall speedup improvement of the program.

Here fractioion of time of the program that can be parallelised = 30%


=> p = 0.3
Speed improvement for that fraction of time = 2 => s = 2
According to Amdahl's law
Slatency = 1/((1-P)+(p/s)) = 1/((1-0.3) + (0.3/2)) = 1/(0.7+0.15) = 1.18
Hence the overall system is improved by only 1.18 times
Amdahl's law – Examples (contd.)
• For a certain program, a serial task can be split into four consecutive
parts, whose percentages of execution time are p1 = 0.11, p2 = 0.18, p3
= 0.23, and p4 = 0.48 respectively. The 1st part is not speedup up, the
2nd part is sped up 5 times, the 3rd part is sped up 20 times, the 4th
part is sped up 1.6 times. Calculate the overall speedup of the program.
Sol. Given s1 = 1, s2 = 5, s3 = 20, and s4 = 1.6.
By using Amdahl's law, the overall speedup is
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IF ID AG DF EX WB
1 1 1 1 1 1

Time 1 2 3 4 5 6
6+1-1 INS1 IF1 ID1 AG1 DF1 EX1 WB1
6+2-1 INS2 IF2 ID2 AG2 DF2 EX2
6+3-1 INS3 IF3 ID3 AG3 DF3
6+4-1 INS4 IF4 ID4 AG4

105 6+100-1 INS100


Freq = 1 GHz
T = 1 ns

7 8 9 10 11 12 13 14

WB2
EX3 WB3 P=6
DF4 EX4 WB4
IXP P+I-1
Without With
4 24 9
100 600 105

600 ns 105 ns
clk freq = 1.6 GHz, single core
IF ID AG DF EX WB
1 2 1 3 3 2 T = 13.125 ns

clock
1 2 3 4 5 6 7 8 9 10 11 12 13
cycles
INS1 IF1 ID1 ID1 AG1 DF1 DF1 DF1 EX1 EX1 EX1 WB1 WB1
INS2 IF2 ID2 ID2 AG2 DF2 DF2 DF2 EX2 EX2 EX2
INS3 IF3 ID3 ID3 AG3 DF3 DF3 DF3
INS4 IF4 ID4 ID4 AG4

IF ID AG DF EX WB
1 2 1 3 3 2

clock
1 2 3 4 5 6 7 8 9 10 11 12 13
cycles
INS1 IF1 ID1 ID1 AG1 DF1 DF1 DF1 EX1 EX1 EX1 WB1 WB1
INS2 IF2 ID2 ID2 AG2 DF2 DF2 DF2 EX2 EX2 EX2
INS3 IF3 ID3 ID3 AG3 DF3 DF3 DF3
INS4 IF4 ID4 ID4 AG4

IF ID AG DF EX WB
1 2 1 3 4 2 5 instructions
frequency = 2 GHz
GHz, single core
21

14 15 16 17 18 19 20 21 22

WB2 WB2
EX3 EX3 EX3 WB3 WB3
DF4 DF4 DF4 EX4 EX4 EX4 WB4 WB4

14 15 16 17 18 19 20 21 22

WB2 WB2
EX3 EX3 EX3 WB3 WB3
DF4 DF4 DF4 EX4 EX4 EX4 WB4 WB4
C=4

IF ID AG DF EX WB
1 1 1 1 1 1

Time 1 2 3 4 5 6
INS1 IF1_C1 ID1_C1 AG1_C1 DF1_C1 EX1_C1 WB1_C1
INS2 IF2_C2 ID2_C2 AG2_C2 DF2_C1 EX2_C2 WB2_C2
INS3 IF3_C3 ID3_C3 AG3_C3 DF3_C2 EX3_C3 WB3_C3
INS4 IF4_C4 ID4_C4 AG4_C4 DF4_C3 EX4_C4 WB4_C4
INS5 IF5_C1 ID5_C1 AG5_C1 DF5_C1 EX5_C1
INS6 IF6_C2 ID6_C2 AG6_C2 DF6_C1 EX6_C2
INS7 IF7_C3 ID7_C3 AG7_C3 DF7_C2 EX7_C3
INS8 IF8_C4 ID8_C4 AG8_C4 DF8_C3 EX8_C4
INS9 IF9_C1 ID9_C1 AG9_C1 DF9_C1
INS10 IF10_C2 ID10_C2 AG10_C2 DF10_C1
INS11 IF11_C3 ID11_C3 AG11_C3 DF11_C2
INS12 IF12_C4 ID12_C4 AG12_C4 DF12_C3

P + I/C - 1
4C 8 cycles
2C 11 cycles
1C 17 cycles

IF ID AG DF EX WB
1 1 1 1 1 1
C=2

Time 1 2 3 4 5 6
INS1 IF1_C1 ID1_C1 AG1_C1 DF1_C1 EX1_C1 WB1_C1
INS2 IF2_C2 ID2_C2 AG2_C2 DF2_C2 EX2_C2 WB2_C2
INS3 IF3_C1 ID3_C1 AG3_C1 DF3_C1 EX3_C1
INS4 IF4_C2 ID4_C2 AG4_C2 DF4_C2 EX4_C2
INS5 IF5_C1 ID5_C1 AG5_C1 DF5_C1
INS6 IF6_C2 ID6_C2 AG6_C2 DF6_C2
INS7 IF7_C1 ID7_C1 AG7_C1
INS8 IF8_C2 ID8_C2 AG8_C2
INS9 IF9_C1 ID9_C1
INS10 IF10_C2 ID10_C2
Freq = 1 GHz
T = 1 ns

7 8 9 10 11 12 13 14

WB5_C1
WB6_C2
WB7_C3
WB8_C4
EX9_C1 WB9_C1
EX10_C2 WB10_C2
EX11_C3 WB11_C3
EX12_C4 WB12_C4

IF2 ID2 AG2 DF2 EX2 WB2


IF3 ID3 AG3 DF3 EX3 WB3
IF4 ID4 AG4 DF4 EX4

7 8 9 10 11 12 13 14

WB3_C1
WB4_C2
EX5_C1 WB5_C1
EX6_C2 WB6_C2
DF7_C1 EX7_C1 WB7_C1
DF8_C2 EX8_C2 WB8_C2
AG9_C1 DF9_C1 EX9_C1 WB9_C1
AG10_C2 DF10_C2 EX10_C2 WB10_C2
P=6

IXP P+I-1
Without With
4 24 9
100 600 105

600 ns 105 ns

WB4
C=2

IF ID AG DF EX WB
1 2 1 3 3 2

clock
1 2 3 4 5 6 7 8
cycles
INS1 IF1_C1 ID1_C1 ID1_C1 AG1_C1 DF1_C1 DF1_C1 DF1_C1 EX1_C1
INS2 IF2_C2 ID2_C2 ID2_C2 AG2_C2 DF2_C2 DF2_C3 DF2_C2 EX2_C2
INS3 IF3_C1 ID3_C1 ID3_C1 AG3_C1 DF3_C1
INS4 IF4_C2 ID4_C2 ID4_C2 AG4_C2 DF4_C2

T
C=4 12 cycles 7.5 ns
C=2 15 cycles 9.3 ns
C=1 21 cycles 13.125 ns

IF ID AG DF EX WB
1 2 1 3 3 2

C=2

clock
1 2 3 4 5 6 7 8
cycles
INS1 IF1_C1 ID1_C1 ID1_C1 AG1_C1 DF1_C1 DF1_C1 DF1_C1 EX1_C1
INS2 IF2_C2 ID2_C2 ID2_C2 AG2_C2 DF2_C2 DF2_C2 DF2_C2 EX2_C2
INS3 IF3_C1 ID3_C1 ID3_C1 AG3_C1 DF3_C1
INS4 IF4_C2 ID4_C2 ID4_C2 AG4_C2 DF4_C1

IF ID AG DF EX WB
1 3 2 2 3 2
C=4
N=8
f=1GHz
clk freq = 1.6 GHz, single core

T = 13.125 ns

9 10 11 12 13 14 15 16 17 18 19
EX1_C1 EX1_C1 WB1_C1 WB1_C1
EX2_C2 EX2_C2 WB2_C2 WB2_C2
DF3_C1 DF3_C1 EX3_C1 EX3_C1 EX3_C1 WB3_C1 WB3_C1
DF4_C2 DF4_C2 EX4_C2 EX4_C2 EX4_C2 WB4_C2 WB4_C2

9 10 11 12 13 14 15 16 17 18 19
EX1_C1 EX1_C1 WB1_C1 WB1_C1
EX2_C2 EX2_C2 WB2_C2 WB2_C2
DF3_C1 DF3_C1 EX3_C1 EX3_C1 EX3_C1 WB3_C1 WB3_C1
DF4_C1 DF4_C1 EX4_C2 EX4_C2 EX4_C2 WB4_C2 WB4_C2
21

20 21 22

IF2 ID2
IF3
IF4

20 21 22
ID2 AG2 DF2 DF2 DF2 EX2 EX2 EX2 WB2 WB2
ID3 ID3 AG3 DF3 DF3 DF3 EX3 EX3
ID4 ID4 AG4 DF4 DF4
EX3 WB3 WB3
DF4 EX4 EX4 EX4 WB4 WB4
Cores = 1
IF ID AG DF EX WB
1 2 1 3 4 2

1 1 1 2 3 2 6 Ins

Cycle -> 1 2 3 4 5 6 7 8 9 10
INS1 IF1 ID1 ID1 AG1 DF1 DF1 DF1 EX1 EX1 EX1
INS2 IF2 ID2 ID2 AG2 DF2 DF2 DF2
INS3 IF3 ID3 ID3 AG3
INS4 IF4 ID4 ID4 AG4

IF ID AG DF EX WB
1 2 1 3 4 2

Cycle -> 1 2 3 4 5 6 7 8 9 10
INS1 IF1_1 ID1_1 ID1_1 AG1_1 DF1_1 DF1_1 DF1_1 EX1_1 EX1_1 EX1_1
INS2 IF2_2 ID2_2 ID2_2 AG2_2 DF2_2 DF2_2 DF2_2 EX2_2 EX2_2 EX2_2
INS3 IF3_1 ID3_1 ID3_1 AG3_1 DF3_1 DF3_1 DF3_1
INS4 IF3_2 ID3_2 ID3_2 AG3_2 DF3_2 DF3_2 DF3_2
11 12 13 14 15 16 17 18 19 20 21 22 23 24
EX1 WB1 WB1
EX2 EX2 EX2 EX2 WB2 WB2
DF3 DF3 DF3 EX3 EX3 EX3 EX3 WB3 WB3
DF4 DF4 DF4 EX4 EX4 EX4 EX4 WB4

11 12 13 14 15 16 17 18 19 20 21 22 23 24
EX1_1 WB1_1 WB1_1
EX2_2 WB2_2 WB2_2
EX3_1 EX3_1 EX3_1 EX3_1 WB3_1 WB3_1
EX3_2 EX3_2 EX3_2 EX3_1 WB3_2 WB3_2
25

WB4

25
C=2 IF ID AG DF EX WB
1 2 1 3 4 2

Cycle -> 1 2 3 4 5 6 7
INS1 IF1_C1 ID1_C1 ID1_C1 AG1_C1 DF1_C1 DF1_C1 DF1_C1
INS2 IF2_C2 ID2_C2 ID2_C2 AG2_C2 DF2_C2 DF2_C2 DF2_C2
INS3 IF3_C1 ID3_C1 ID3_C1 AG3_C1
INS4 IF4_C2 ID4_C2 ID4_C2 AG4_C2

C=1 25
C=2 17
C=4 13
8 9 10 11 12 13 14 15 16 17 18 19
EX1_C1 EX1_C1 EX1_C1 EX1_C1 WB1_C1 WB1_C1
EX2_C2 EX2_C2 EX2_C2 EX2_C2 WB2_C2 WB2_C2
DF3_C1 DF3_C1 DF3_C1 EX3_C1 EX3_C1 EX3_C1 EX3_C1 WB3_C1 WB3_C1
DF4_C2 DF4_C2 DF4_C2 EX4_C2 EX4_C2 EX4_C2 EX4_C2 WB4_C2 WB4_C2
20 21 22 23 24 25

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