AMBA: Advanced Microcontroller Bus Architecture

AHB: AMBA High-performance Bus

APB: Advanced Peripheral Bus
AXI: Advanced eXtensible Interface

1
 Busses: the glue that connects the pieces

C
Assembly
Software Central Machine Code
ISA Hardware
Processing
Unit
ldr (read)
bl (int) str (write)

System Buses
AHB/APB
Interrupts

Internal &
GPIO/INT Timers USART DAC/ADC External
Memory

Internal
External

2
Today…

MMIO: Memory-Mapped I/O review

AMBA: Advanced Microcontroller Bus Architecture

APB: Advanced Peripheral Bus

AHB: AMBA High-performance Bus

AXI: Advanced eXtensible Interface

3
Memory-Mapped I/O (MMIO)

• I/O model in which the same address bus/space

is used to
– Do memory accesses (e.g. to RAM)
– Do I/O operations (e.g. to I/O pins or peripheral
registers)
• Reading and writing memory addresses allows us
to
– Read peripheral state (e.g. value of an I/O pin or FSM’s
DFF)
– Issue peripheral commands (e.g. set an I/O pin or FSM’s
state)
• How?
– Memory has an address and value
– Can equate a pointer to desired address
– Can set/get de-referenced value to change memory
– Can control peripheral state in this way
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Reading register bits with MMIO

• How?
– Let’s say that red, green, and blue pushbuttons are mapped to
memory address 0xB0000003 at bits 0, 1, and 2, respectively
– When pushed, we will read a ‘1’ from the corresponding bit
– When released, we will read a ‘0’ from the corresponding bit

Address \ Bit 31 24 23 16 15 8 7 210

0xB0000003-------- -------- -------- -----

– Must mask (and perhaps shift) to select target bits for reading

#define PBS_REG 0xB0000003

int isBlueButtonPressed() {
return (*((uint32_t *)PBS_REG) & 0x00000004) >> 2;
}

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Writing register bits with MMIO

• How?
– Let’s say that red, green, and blue LEDs are mapped to memory
address 0xB0000004 at bits 0, 1, and 2, respectively
– Writing a ‘1’ (‘0’) to the corresponding bit turns on (off) the LED

Address \ Bit 31 24 23 16 15 8 7 210

0xB0000004-------- -------- -------- -----

– When updating (set/clear) bits, must preserve remaining contents

– Use bitmask to select target bits for manipulation, e.g.
#define LED_REG 0xB0000004 #define LED_REG 0xB0000004

void setRedLed() { void clearRedLed() {

*((uint32_t *)LED_REG) |= 0x1; *((uint32_t *)LED_REG) &= ~(0x00000001);
} }

void setGreenLed() { void clearBlueLed() {

*((uint32_t *)LED_REG) |= 0x2; *((uint32_t *)LED_REG) &= ~(0x00000004);
} }
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Some useful C keywords

• const
– Makes variable value or pointer parameter unmodifiable
– const x = 32;
• register
– Tells compiler to locate variables in a CPU register if possible
– register int x;
• static
– Preserve variable value after its scope ends
– Does not go on the stack
– static int x;
• volatile
– Opposite of const
– Can be changed in the background
– volatile int I;
7
Today…

MMIO: Memory-Mapped I/O review

AMBA: Advanced Microcontroller Bus Architecture

APB: Advanced Peripheral Bus

AHB: AMBA High-performance Bus

AXI: Advanced eXtensible Interface

8
AMBA: Advanced Microcontroller Bus Architecture

APB: Advanced Peripheral Bus

AHB: AMBA High-performance Bus

AXI: Advanced eXtensible Interface

9
 Busses: the glue that connects the pieces

C
Assembly
Software Central Machine Code
ISA Hardware
Processing
Unit
ldr (read)
bl (int) str (write)

System Buses
AHB/APB
Interrupts

Internal &
GPIO/INT Timers USART DAC/ADC External
Memory

Internal
External

10
Actel SmartFusion system/bus architecture

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Advanced Microcontroller Bus Architecture (AMBA)
- Advanced/AMBA High-performance Bus (AHB)
- Advanced Peripheral Bus (APB)

AHB APB
• High performance • Low power
• Pipelined operation • Latched address/control
• Burst transfers • Simple interface
• Multiple bus masters • Suitable of many
• Split transactions peripherals

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AMBA: Advanced Microcontroller Bus Architecture

APB: Advanced Peripheral Bus

AHB: AMBA High-performance Bus

AXI: Advanced eXtensible Interface

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APB: a simple bus that is easy to work with

• Low-cost

• Low-power

• Low-complexity

• Low-bandwidth

• Non-pipelined

• Ideal for peripherals

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Notation

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APB
APB States:

IDLE:
PSELx = 0;
PENABLE = 0;
Transfer = OFF;

SETUP:
PSELx = 1;
PENABLE = 0;
Transfer = START;

ACCESS:
PSELx = 1;
PENABLE = 1;
Transfer = ON;

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APB bus state machine

• IDLE
– Default APB state
• SETUP
– When transfer required
– PSELx is asserted Setup phase begins
with this rising edge
– Only one cycle
• ACCESS
– PENABLE is asserted
– Addr, write, select, and
write data remain stable
– Stay if PREADY = L
– Goto IDLE if PREADY = H
and no more data
– Goto SETUP is PREADY = H
and more data pending Setup Access
Phase Phase
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APB Master-Slave Interface

• PADDR: Master -> Slave

• PWRITE: Master -> Slave
• PSEL: Master -> Slave
• PENABLE: Master -> Slave
• PWRITE: Master -> Slave
• PREADY: Slave -> Master
• PSLAVERR: Slave -> Master
• PRDATA: Slave -> Master

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APB Master

• PADDR: Master -> Slave

• PWRITE: Master -> Slave
• PSEL: Master -> Slave
• PENABLE: Master -> Slave
• PWRITE: Master -> Slave
• PREADY: Slave -> Master
• PSLAVERR: Slave -> Master
• PRDATA: Slave -> Master

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APB Slave

• PADDR: Master -> Slave

• PWRITE: Master -> Slave
• PSEL: Master -> Slave
• PENABLE: Master -> Slave
• PWRITE: Master -> Slave
• PREADY: Slave -> Master
• PSLAVERR: Slave -> Master
• PRDATA: Slave -> Master

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APB Write transfer Signals direction

• PADDR: Master -> Slave

• PWRITE: Master -> Slave
• PSEL: Master -> Slave
• PENABLE: Master -> Slave
• PWRITE: Master -> Slave
• PREADY: Slave -> Master
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APB signal definitions

• PCLK: the bus clock source (rising-edge triggered)

• PRESETn: the bus (and typically system) reset signal (active low)
• PADDR: the APB address bus (can be up to 32-bits wide)
• PSELx: the select line for each slave device
• PENABLE: indicates the 2nd and subsequent cycles of an APB xfer
• PWRITE: indicates transfer direction (Write=H, Read=L)
• PWDATA: the write data bus (can be up to 32-bits wide)
• PREADY: used to extend a transfer
• PRDATA: the read data bus (can be up to 32-bits wide)
• PSLVERR: indicates a transfer error (OKAY=L, ERROR=H)

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APB bus signals in action

• PCLK
– Clock
• PADDR
– Address on bus
• PWRITE
– 1=Write, 0=Read
• PWDATA
– Data written to the I/O
device. Supplied by the bus
master/processor.

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APB bus signals

• PSEL
– Asserted if the current bus
transaction is targeted to
this device
• PENABLE
– High during entire
transaction other than the
first cycle.
• PREADY
– Driven by target. Similar to
ACKNOWLEDGE signal.
Indicates if the target is
ready to do transaction.
Each target has it’s own
PREADY

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A write transfer with no wait states

Setup phase begins

with this rising edge

Setup Access
Phase Phase

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A write transfer with no wait states

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A write transfer with wait states

Setup phase begins

with this rising edge

Setup Wait Wait Access

Phase State State Phase

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APB Multiple Write Transfers

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A read transfer with no wait states

Setup phase begins

with this rising edge

Setup Access
Phase Phase

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A read transfer with wait states

Setup phase begins

with this rising edge

Setup Wait Wait Access

Phase State State Phase

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APB Multiple Read Transfers

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APB Back to Back Transfers

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Error response

• PSLVERR can be used to indicate an error condition on an

APB transfer.
– Error conditions can occur on both read and write transactions.

• PSLVERR is only considered valid during the last cycle of an

APB transfer
– when PSEL, PENABLE, and PREADY are all HIGH.

• Drive PSLVERR LOW when it is not being sampled

– when any of PSEL, PENABLE, or PREADY are LOW.
– recommended, but not mandatory

• Transactions that receive an error, might or might not

have changed the state of the peripheral
– peripheral-specific and either is acceptable

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Error response

• When a write transaction receives an error

– does not mean that the register within the peripheral has not been
updated

• Read transactions that receive an error can return invalid

data

• There is no requirement for the peripheral to drive the

data bus to all 0s for a read error.

• APB peripherals are not required to support the PSLVERR

pin.
– true for both existing and new APB peripheral designs
– If a peripheral does not include this pin then the appropriate input to
the APB bridge is tied LOW

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Failing write transfer

 a failing write transfer that completes with an error

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Failing read transfer

 read transfer can also complete with an error response

 indicates that there is no valid read data available

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APB 2.0 and 3.0 add-ons

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Write strobes

• The write strobe signals ‘PSTRB’ enable sparse data transfer on the write
data bus

• Each write strobe signal corresponds to one byte of the write data bus

• When asserted HIGH, a write strobe indicates that the corresponding byte
lane of the write data bus contains valid information

• There is one write strobe for each eight bits of the write data bus, so
PSTRB[n] corresponds to PWDATA[(8n+7):(8n)]

• For read transfers the bus master must drive all bits of PSTRB LOW

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Protection unit support

• To support complex system designs, it is often necessary for both the interconnect
and other devices in the system to provide protection against illegal transactions

• For the APB interface, this protection is provided by the PPROT[2:0] signals

• The primary use of PPROT is as an identifier for Secure or Non-secure transactions

• Three levels of access protection:

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Example setup

• We will assume we have one bus master

“CPU” and two slave devices (D1 and D2)
– D1 is mapped to 0x00001000-0x0000100F
– D2 is mapped to 0x00001010-0x0000101F
CPU stores to location 0x00001004 with no stalls

D1

D2

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Design
What ifawe
device
wantwhich writes
to have to a of
the LSB register whenever
this register
any address
control in its range is written
an LED?
PWDATA[31:0] PREADY

PWRITE
32-bit Reg

PENABLE D[31:0]
Q[31:0]
EN
PSEL
C LED
PADDR[7:0]

PCLK

We are assuming APB only gets lowest 8 bits of address here…

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Reg A should be written at address 0x00001000
Reg B should be written at address 0x00001004
PWDATA[31:0] PREADY
32-bit Reg A

PWRITE D[31:0]
Q[31:0]
EN

PENABLE C

PSEL

PADDR[7:0] 32-bit Reg B

D[31:0]
Q[31:0]
PCLK
EN

We are assuming APB only gets lowest 8 bits of address here…

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Reads…

The key thing here is that each slave device has its own read data (PRDATA) bus!
Recall that “R” is from the initiator’s viewpoint—the device drives data when read.
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Let’s say we want a device that provides data from
a switch on a read to any address it is assigned.
(so returns a 0 or 1)
PREADY

PRDATA[31:0]
PWRITE

PENABLE

Switch1
PSEL

PADDR[7:0]

PCLK

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Device provides data from switch A if address
0x00001000 is read from. B if address 0x00001004
is read from
PREADY

PRDATA[31:0]
PWRITE

PENABLE

PSEL Switch1

PADDR[7:0] Switch2

PCLK

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All reads read from register, all writes write…

PWDATA[31:0] PREADY

PRDATA[31:0]
PWRITE

32-bit Reg
PENABLE
D[31:0]
Q[31:0]
PSEL EN

C
PADDR[7:0]

PCLK

PREADY

We are assuming APB only gets lowest 8 bits of address here…

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Things left out…

• There is another signal, PSLVERR (APB Slave

Error) which we can drive high if things go bad.
– We’ll just tie that to 0.

• PRESETn
– Active low system reset signal
– (needed for stateful peripherals)

• Note that we are assuming that our device need

not stall.
– We could stall if needed.

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Verilog!

/*** APB3 BUS INTERFACE ***/

input PCLK, // clock
input PRESERN, // system reset
input PSEL, // peripheral select
input PENABLE, // distinguishes access phase
output wire PREADY, // peripheral ready signal
output wire PSLVERR, // error signal
input PWRITE, // distinguishes read and write cycles
input [31:0] PADDR, // I/O address
input wire [31:0] PWDATA, // data from processor to I/O device (32 bits)
output reg [31:0] PRDATA, // data to processor from I/O device (32-bits)

/*** I/O PORTS DECLARATION ***/

output reg LEDOUT, // port to LED
input SW // port to switch
);

assign PSLVERR = 0;
assign PREADY = 1;

reg [31:0] regA;

assign LEDOUT = sw ? regA[0] : 1’bz;

// regA is updated with APB slave interface register read and write always blocks
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Actel/Microsemi implementation of CoreAPB3

• ARM APB spec is silent about sharing signals

– PSEL, PREADY, PRDATA are shared
– Hence, every peripheral needs its own
decode logic…which is cumbersome
• Actel CoreAPB3 (and other) module(s) help
• Allocates per-slave signals
– PSEL, PREADY, PRDATA, PSLVERR broken out
– CoreAPB3 supports 16 slaves
– Performs address decoding for PSEL
– De-multiplexes PSEL signal
– Multiplexes PREADY, PRDATA, PSLVERR

50
Today…

MMIO: Memory-Mapped I/O review

AMBA: Advanced Microcontroller Bus Architecture

APB: Advanced Peripheral Bus

AHB: AMBA High-performance Bus

AXI: Advanced eXtensible Interface

51
 AHB-Lite supports single bus master and provides high-
bandwidth operation

• AHB Lite is a reduced version

of AHB protocol.
• AHB Lite essentially means
that there is only 1 master.
• Burst transfers
• Single clock-edge operation
(rising edge)
• Non-tristate implementation
(no enable)
• Configurable bus width

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AHB-Lite bus master/slave interface

• Global signals
– HCLK
– HRESETn
• Master out/slave in
– HADDR (address)
– HWDATA (write data)
– Control
• HWRITE
• HSIZE
• HBURST
• HPROT
• HTRANS
• HMASTLOCK
• Slave out/master in
– HRDATA (read data)
– HREADY
– HRESP

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AHB-Lite signal definitions

• Global signals
– HCLK: the bus clock source (rising-edge triggered)
– HRESETn: the bus (and system) reset signal (active low)
• Master out/slave in
– HADDR[31:0]: the 32-bit system address bus
– HWDATA[31:0]: the system write data bus
– Control
• HWRITE: indicates transfer direction (Write=1, Read=0)
• HSIZE[2:0]: indicates size of transfer (byte, halfword, or word)
• HBURST[2:0]: indicates single or burst transfer (1, 4, 8, 16 beats)
• HPROT[3:0]: provides protection information (e.g. I or D; user or handler)
• HTRANS: indicates current transfer type (e.g. idle, busy, nonseq, seq)
• HMASTLOCK: indicates a locked (atomic) transfer sequence
• Slave out/master in
– HRDATA[31:0]: the slave read data bus
– HREADY: indicates previous transfer is complete
– HRESP: the transfer response (OKAY=0, ERROR=1)

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Key to timing diagram conventions

• Timing diagrams
– Clock
– Stable values
– Transitions
– High-impedance

• Signal conventions
– Lower case ‘n’ denote
active low (e.g. RESETn)
– Prefix ‘H’ denotes AHB
– Prefix ‘P’ denotes APB

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Basic read and write transfers with no wait states

Pipelined
Address
& Data
Transfer

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Read transfer with two wait states

Two wait states Valid data

added by slave produced
by asserting
HREADY low

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Write transfer with one wait state

One wait state Valid data

added by slave held stable
by asserting
HREADY low

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Wait states extend the address phase of next transfer

Address stage of
the next transfer
is also extended

One wait state

added by slave
by asserting
HREADY low

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MMIO: Memory-Mapped I/O review

AMBA: Advanced Microcontroller Bus Architecture

APB: Advanced Peripheral Bus

AHB: AMBA High-performance Bus

- Low-level details included for completeness

AXI: Advanced eXtensible Interface

60
Burst transfer

• The main advantage of burst mode over single mode is that the burst
mode typically increases the throughput of data transfer.
• Any bus transaction is typically handled by an arbiter, which decides
when it should change the granted master and slaves.
• In case of burst mode, it is usually more efficient if you allow a master to
complete a known length transfer sequence.
• The total delay in a data transaction can be typically written as a sum of
initial access latency plus sequential access latency.

• Here the sequential latency is same in both single mode and burst mode,
but the total initial latency is decreased in burst mode, since the initial
delay (usually depends on FSM for the protocol) is caused only once in
burst mode. Hence the total latency of the burst transfer is reduced, and
hence the data transfer throughput is increased.
• It can also be used by slaves that can optimize their responses if they
know in advance how many data transfers there will be.
• The typical example here is a DRAM which has a high initial access
latency, but sequential accesses after that can be performed with fewer
wait states.
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Transfers can be of four types (HTRANS[1:0])

• IDLE (b00)
– No data transfer is required
– Slave must OKAY w/o waiting
– Slave must ignore IDLE
• BUSY (b01)
– Insert idle cycles in a burst
– Burst will continue afterward
– Address/control reflects next transfer in
burst
– Slave must OKAY w/o waiting
– Slave must ignore BUSY
• NONSEQ (b10)
– Indicates single transfer or first transfer of
a burst
– Address/control unrelated to prior
transfers
• SEQ (b11)
– Remaining transfers in a burst
– Addr = prior addr + transfer size

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A four beat burst with master busy and slave wait

Master busy
indicated by
HTRANS[1:0]

One wait state

added by slave
by asserting
HREADY low

63
Controlling the size (width) of a transfer

• HSIZE[2:0] encodes the size

• The cannot exceed the data bus

width (e.g. 32-bits)

• HSIZE + HBURST is determines

wrapping boundary for wrapping
bursts

• HSIZE must remain constant

throughout a burst transfer

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Controlling the burst beats (length) of a transfer

• Burst of 1, 4, 8, 16, and undef

• HBURST[2:0] encodes the type

• Incremental burst

• Wrapping bursts
– 4 beats x 4-byte words wrapping
– Wraps at 16 byte boundary
– E.g. 0x34, 0x38, 0x3c, 0x30,…

• Bursts must not cross 1KB

address boundaries

65
A four beat wrapping burst (WRAP4)

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A four beat incrementing burst (INCR4)

67
An eight beat wrapping burst (WRAP8)

68
An eight beat incrementing burst
(INCR8) using half-word transfers

69
An undefined length incrementing burst (INCR)

70
Multi-master AHB-Lite
requires a multi-layer interconnect

• AHB-Lite is single-master

• Multi-master operation
– Must isolate masters
– Each master assigned to layer
– Interconnect arbitrates slave
accesses

• Full crossbar switch often

unneeded
– Slaves 1, 2, 3 are shared
– Slaves 4, 5 are local to Master 1

71
unaligned data transfers

72
AXI features

73
74
Architecture

75
Key Features of AXI Protocol

76
Channel Definition

77
Flexible Interconnect

Shared address and

data
buses
Shared address
buses and
multiple data buses
Multilayer, with
multiple
address and data
buses

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Basic AXI Transactions

79
AXI Transaction Handshake Dependencies

80
AXI Channel Handshaking

81
AXI Signals

82
AHB/AXI Burst Transfer

83
AHB/AXI Burst Transfer

84
85