IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO.
9, SEPTEMBER 2010 2353
Analysis and Optimization of Direct-Conversion
Receivers With 25% Duty-Cycle Current-Driven
Passive Mixers
Ahmad Mirzaei, Member, IEEE, Hooman Darabi, Senior Member, IEEE, John C. Leete, and Yuyu Chang
Abstract—The performance of zero-IF receivers with cur-
rent-driven passive mixers driven by 25% duty-cycle quadrature
clocks is studied and analyzed. It is shown that, in general,
these receivers outperform the ones that utilize passive mixers
with 50% duty-cycle clocks. The known problems in receivers
with 50% duty-cycle mixers, such as having unequal high- and
low-side conversion gains, unexpected IIP2 and IIP3 numbers,
and IQ crosstalk, are significantly lowered due to the operating
principles of the 25% duty-cycle passive mixer. It is revealed
that with an intelligent sizing of the design parameters, the
25%-duty-cycle-mixer-based receiver is superior in terms of
linearity, noise, and elimination of IQ crosstalk.
Index Terms—Conversion gain, current-driven, down-conver-
sion, impedance transformation, mixer, noise figure, receiver.
I. INTRODUCTION
T HE direct-conversion receiver (DCR) has attracted wide-
spread attention among IC designers due to its architec-
tural simplicity and ease of integration, particularly in multiband
applications where RF and baseband circuits can be highly inte-
grated and conveniently reconfigured [1]–[4]. There have been
tremendous advancements on alleviating the well-known prob-
lems of the DCR, such as dc offset, flicker noise, and even-order
intermodulation products. In the circuit level, various circuit
techniques have been proposed to lower the flicker noise corner
of downconversion mixers [5]–[7]. Similarly, even-order dis-
tortion in mixers has been extensively studied, and numerous
circuit techniques have been devised [8]–[10]. On the software
side, powerful calibration algorithms have been developed to
not only calibrate receiver front-end circuits but also perform
smart signal processing to extract the original desired signal
from the one contaminated by RF impairments [11]–[13].
It has been shown that a current-driven passive mixer is a
very suitable choice in a DCR, specifically in low-voltage ap-
plications [14]–[18]. Because, in general, there is no dc current
passing through the switches, the flicker noise corner can be ex-
ceptionally low [19], [20]. The mixer also exhibits good lin-
earity (low intermodulation) and is highly capable of handling
large signal swings [21], [22].
Manuscript received October 06, 2009; revised December 09, 2009 and Jan-
uary 25, 2010; accepted January 25, 2010. Date of publication March 11, 2010;
date of current version October 01, 2010. This paper was recommended by As-
sociate Editor E. A. M. Klumperink.
The authors are with Broadcom Corporation, Irvine, CA 92617 USA (e-mail:
ahmadm@broadcom.com).
Digital Object Identifier 10.1109/TCSI.2010.2043014
1549-8328/$26.00 © 2010 IEEE
It is known that applying 25% duty-cycle quadrature clocks
(as opposed to 50%) to the passive mixer increases the down-
conversion gain by 3 dB, which lowers the noise contribution
of the following stages [23]–[27]. It is also known that in IQ
receivers with a 25% passive mixer, because the switches of the
passive mixer in two quadrature channels are not simultane-
ously ON, the two channels do not load each other. This lowers
the noise contribution of transimpedance amplifiers (buffers
after the passive mixers) compared to the same receiver but
with a 50% duty-cycle passive mixer[23]. Although the afore-
mentioned properties of receivers with a 25% passive mixer are
known, in the literature, they are explained mostly intuitively
with no mathematical basis. Therefore, in this paper, we intro-
duce novel mathematical tools along with intuition in order to
analyze and understand the operation of the downconversion
passive mixer clocked with 25% duty-cycle local oscillator
(LO) clocks. This way, by deriving the transfer function of the
downconversion, the front end is optimized for maximum gain
and minimum noise figure. This paper also reveals how the
potential problems of the 50% duty-cycle mixer [28], such as
unequal high- and low-side conversion gains, unexpected IIP2
and IIP3 numbers, and IQ crosstalk, are significantly lowered
with this approach.
Section II highlights the problems associated with the 50%
duty-cycle mixer. InSection III, after briefly introducing the
25% duty-cycle downconversion mixer, we develop the re-
quired mathematical tools to derive the frequency response of
the downconversion and optimize the receiver for the best per-
formance.Section IV demonstrates the underlying mechanism
by which the nonlinearity in the transimpedance amplifier of
one quadrature channel can contaminate the outputs of both I
and Q channels and reveals that, in a 25% duty-cycle mixer,
the effect is significantly lower. Noise and IIP2 are discussed
inSection V, and Section VII concludes this paper.
II. QUADRATURE DOWNCONVERSION WITH
50% DUTY-CYCLE CLOCKS
Fig. 1(a) shows a simple model of a typical IQ receiver
front end with current-driven passive downconversion mixers
driven by 50% duty-cycle quadrature clocks. The low-noise
amplifier (LNA) is, in fact, a transconductor, which supplies
the RF current and is modeled by a current source with an
output impedance . Each of the I and Q paths is directly
coupled to the LNA with a capacitor of size , and there are
no intermediate transconductance stages between the LNA
and the IQ mixers, such as the one in [18]. Otherwise, these
2354 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 9, SEPTEMBER 2010
Fig. 1. (a) Simple model of a typical IQ receiver front end with current-driven passive mixers driven by 50% duty-cycle clocks. (b) Circulation of the image
current.
transconductance stages would hurt the receiver linearity due to
current-to-voltage and voltage-to-current conversions, although
they would isolate the I and Q channels and eliminate the IQ
crosstalk that will be discussed shortly. The series capacitors
not only block the second-order intermodulation products gen-
erated inside the LNA but also prevent any unwanted current
circulating through the switches from the I channel to the Q
one due to random offsets in the transimpedance amplifiers.
Otherwise, the flicker noise corner may go up[5]. is the
input impedance of the transimpedance amplifier, which is also
referred to as a current buffer.
Let us assume that the input RF signal is a tone at . conversion gain. In [28], it has been shown that for narrow-
In [28], it is shown that, depending on the LNA load, , series
capacitors ’s, switch resistance , and current buffer
impedance , a portion of the signal current coming from
the LNA output flows to . The remaining is equally split
between the two downconversion channels, and after being
downconverted, they become baseband currents at . It can be
shown that due to the lack of reverse isolation between the RF
and baseband sides of the passive mixers, the RF voltages at
points and are composed of two frequency components1:
(a) at the main RF frequency , (b) at the image
frequency . Mirzaei et al. [28] prove that the voltage
components at the main RF frequency are equal; however,
the image components are antiphase with equal magnitudes.
As shown in Fig. 1(b), these antiphase voltages at the image
frequency initiates an RF current at circulating
from node to node . The out-of-phase image currents in
the I and Q channels are downconverted and become additional
baseband currents at . The creation of this image current
that stems from the absence of reverse isolation between the
two I and Q channels is called IQ interaction and, overall, is not
desirable and must be minimized. This IQ interaction degrades
the receiver performance through the following ways: 1) The
high- and low-side conversion gains become unequal; 2) the
high- and low-side IIP2 and IIP3 numbers are different; 3) the
1Components at around higher harmonics of the clock are ignored.
nonlinearity-induced low-frequency components in the input
voltage of the current buffer in one channel leak to the other
quadrature channel; this phenomenon transfers the nonlinearity
into the baseband currents, resulting in unexpected IIP2 and
IIP3 numbers; and 4) due to the IQ interaction, the noise of the
current buffers can be boosted, increasing the overall receiver
noise figure.
The magnitude of the image current and, thus, the intensity
of the IQ interaction in Fig. 1(b) can be significantly lowered
by increasing the series-capacitor impedance or, equivalently,
lowering [29]. However, care must be taken to not lower the
band applications, there is an optimum value for to achieve
a maximum conversion gain. Fortuitously, this value of is
low enough to lower the IQ interaction by a factor of 10–15 dB
versus the conventional design where large series capacitors are
chosen.
III. QUADRATURE DOWNCONVERSION WITH 25%
DUTY-CYCLE CLOCK
A. Operation of the 25% Duty-Cycle Mixing System
First, let us consider Fig. 2(a) in which an RF current
is passing to a quadrature mixing system whose switches are
clocked by rail-to-rail 25% duty-cycle clocks. The clock phases
are also shown in Fig. 2(a). The other side of the switches
is terminated to four identical baseband loads . The
I-channel switches are clocked by 25% duty-cycle and
clocks, which are time shifted by ( is the
LO period) with respect to each other. The switches of the
Q channel are clocked by and clocks that are
the same as and , respectively, except that they
are time shifted by . For the purpose of this analysis,
we assume that the switches are ideal, except that they have
nonzero ON resistance that is equal to . The parasitic
capacitors of the switches can be easily lumped into the RF
or baseband impedances; therefore, they are ignored in this
MIRZAEI et al.: ANALYSIS AND OPTIMIZATION OF DCRs WITH CURRENT-DRIVEN PASSIVE MIXERS 2355

Fig. 2. (a) Current-driven passive mixer driven by 25% duty-cycle quadrature clocks. is the baseband impedance. (b) Simulated input impedance versus
prediction.

analysis. The baseband currents2 in the I channel are called in which is the convolution integral [30]. In order to find the
and , and those in the Q channel are called resulting voltage at the RF side of the switches, we observe
and . From the clock phases, it is observed that, at any given moment, only one switch is ON, and thus, the
that over a period of , only one of the four switches is RF voltage is equal to the corresponding baseband voltage plus
ON and that the RF current flows to the corresponding baseband the voltage drop across that switch, i.e., . Conse-
impedance. Then over the next period of length , another quently, the RF voltage is equal to
switch from the other quadrature channel turns on and so on. To
analyze this mixing system, let us define the following periodic
functions corresponding to the four LOs:

(1)
(7)
(2)
To simplify (7), let us write the Fourier series of , ,
(3) , and

(4) (8)

Therefore, is one when is high and the corre-

sponding switch is ON; otherwise, it is zero. The other functions
were defined in a similar way. (9)
Now, let us focus on one of the four paths, for example, the
path. The corresponding baseband current can be
written as

(5)
(10)
meaning that it is equal to either the RF current when the switch
is ON or zero when it is OFF. This baseband current flows into
the corresponding baseband impedance , producing the
following baseband voltage:

(6) (11)
2For now, by baseband current, it does not mean the low-frequency part only;
it means the total current through . where .
2356 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 9, SEPTEMBER 2010

Now, in order to find the Fourier transform of in(7)
, we need to know the Fourier transform of its last
four terms. Using the properties of the Fourier transform [30],
it can be shown that
(12)
in which and are the coefficients of the Fourier series
in (8). Similarly, by utilizing the Fourier series in (9)–(11), the
Fourier transforms of the other three terms in (7) are found
ignore higher order harmonics, and it will be revealed that this
approximation introduces insignificant errors between the pre-
dicted and simulated actual transfer functions.
The most important observation here is that, unlike the 50%
duty-cycle passive mixer, there is no voltage component gener-
ated at the image frequency . In other words, the
image problem of the 50% duty-cycle mixer no longer exists.
By ignoring those frequency components at around the third
and higher odd harmonics of the LO, becomes a func-
tion of only , and we can define the following input
impedance seen from the RF side of the 25% duty-cycle mixing
system
(17)

Equation (17) can be written in the following format:

(13)

(14) (18)

According to (17), the input impedance seen from the mixing

system in Fig. 2(a) is actually the baseband impedance
shifted to the integer harmonics of the LO along with a scaling
(15) factor. If the baseband impedance is a simple low-pass filter,
becomes the same low-pass filter at dc but high- bandpass
Finally, from (7) and (12)–(15), the Fourier transform of filter at LO and its harmonics. Because the desired signal is at
is obtained around , for the purpose of receiver analysis, in the vicinity
of , we can simplify the input impedance as the following:

(16)
Thus, for a sinusoidal incident RF current at a frequency ,
the voltage response at the RF side of the switches is composed
of frequency components at , , , etc. This
means that for an RF current at , where is a small
frequency offset, has its major frequency component at the
main frequency , and the rest reside at
and . In a receiver, these harmonics of the voltage
at the RF side of the switches appear across the overall RF
impedance seen from that side (looking into the RF side) and ini-
tiate RF currents at those frequencies. The resulting RF currents
are harmonically downconverted back to the baseband at ,
which can modify the receiver downconversion gain. Taking
into account these harmonics leads to complicated and counter-
intuitive equations. Therefore, unless otherwise stated, we will
(19)
Therefore, the input impedance is simply the switch resis-
tance in series with an RF impedance which is the base-
band impedance that is frequency shifted to . In other
words, the aforementioned mixing system, which is composed
of four baseband impedances and four switches each driven by
four nonoverlapped 25% duty-cycle clocks, holds a property
called impedance transformation. By holding this property, this
system transfers a low quality-factor baseband impedance
to a high- RF impedance simply by frequency shifting. This
makes such a mixing structure very suitable to be utilized as
an on-chip high- RF bandpass filter in a variety of applica-
tions such as cellular receivers. Fig. 2(b) compares the simu-
lated input impedance versus the prediction [(19)], which are
quite well matched.
Now, let us find the downconverted baseband currents versus
the incident RF current. The baseband currents of interest for
the I and Q channels are and
, respectively. From (5), (8)–(11), these baseband
MIRZAEI et al.: ANALYSIS AND OPTIMIZATION OF DCRs WITH CURRENT-DRIVEN PASSIVE MIXERS 2357

Fig. 3. (a) Simple model of a typical IQ receiver front end with current-driven passive mixers driven by 25% duty-cycle clocks. (b) LNA load.

currents are calculated to be
A useful equation that is repeatedly utilized across this paper
is the phasor of the downconverted currents at versus
the corresponding phasor of the RF current
at . From (20) and (21), depending on whether the RF
frequency is above or below , the phasor of the baseband
currents is found
The baseband currents flow into the current buffers to gen-
erate the final output voltages; thus, it is appropriate to define the
conversion gain as . From (22) and (23), it is deduced
that the conversion gain for this 25% duty-cycle current-driven
passive mixer is ( 3 dB) times larger than that of its 50%
duty-cycle counterpart.3
To analyze the 25% duty-cycle passive mixer, we assumed
that the clocks are rail to rail with sharp rise and fall times. This
way, the overdrive voltage (gate–source voltage) of an ON mixer
switch becomes very large, which allows us to model it with a
constant resistor of size during the time it is ON. In the ad-
vent of submicrometer CMOS technology, for applications like
cellular receivers, such sharp4 clocks can be easily generated
with on-chip inverters. However, at very high frequencies due
to the layout and bondwire limitations, such a requirement may
not be met. In that case, the resistance of the mixer switch is
modulated during the time the switch is ON. It can be shown
that (19) is still valid, provided that switch resistance
replaced with its average value during the ON time. Thus, the
impedance transformation property [the second part of (19)] re-
(20) mains intact. Similarly, for the remaining equations, all that is
needed is to replace the switch resistance with its average value.
(21) B. Optimization of the Receiver for Maximum Gain
Fig. 3(a) shows a simple model of a typical IQ receiver front
end with a 25% duty-cycle current-driven passive mixer. The
LNA is a transconductor, which supplies the RF current and is
modeled by an RF current with an output impedance of .
The common node of the switches of the IQ mixer is connected
to the LNA through a capacitor of size . This way, the dc
voltage at the drain and source of the switches is set by the
(22) baseband loads (current buffers). This series capacitor blocks
the low-frequency intermodulation products and any low-fre-
quency components created inside the LNA due to the second-
(23) order nonlinearity. Otherwise, these products can leak into the
baseband due to mismatches in the switches of the mixer. Unlike
the receiver with a 50% passive mixer in Fig. 1, only one series
capacitor is needed. This is because, in the 50% passive mixer,
at any given moment, one switch from the I channel and one
switch from the Q channel are simultaneously ON. If nodes A
and B (Fig. 1) are shorted together, any random offset voltages
at the inputs of the two transimpedance amplifiers will create a
current between the two channels whose size would be inversely
proportional to the resistance of the series combination of the
two switches. Because the switch resistance is small, this cur-
rent can be even on the order of milliamperes. The effect can not
only disturb the bias points but also drastically raise the flicker
noise contribution of the switches. That is why, in the receiver
with a 50% duty-cycle passive mixer, two series capacitors must
be utilized to isolate nodes A and B at dc.
Now, the input RF current is assumed to be at .
From the input-impedance expression in (19), the RF current
through the series capacitor (the RF current that is provided to
is the mixer) is equal to

3The conversion gain in the 50% duty-cycle current-driven passive mixer is

about .
4By sharp, it is meant to have rise and fall times that are much lower than the
clock period. (24)
2358 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 9, SEPTEMBER 2010

Fig. 4. (a) Simulated and predicted high- and low-side conversion gains. (b) Simulated high- and low-side conversion gains for the optimum and conventional
designs.

in which is the series-capacitor impedance, i.e., . Because

Thus, from (22) to (24), the downconverted baseband currents , in general,
are obtained (shown in (25) at the bottom of the page). the high- and low-side conversion gains can be different. Equiv-
With a similar analysis, for an input RF current alently, converting into in (27) could change the con-
at , the baseband currents are calculated to be (26), version gain but would be much smaller than that of a 50%
shown at the bottom of the page. duty-cycle mixer [28] because of the nature of this equation.
The corresponding conversion gain obtained in (25) and (26) This is because the coefficient of in the de-
are called high- and low-side conversion gains, respectively. nominator of (27) is real, as opposed to that of the 50% duty-
Fig. 4(a) compares the SpectreRF simulation results against the cycle mixer [28, eq. (25)], which is a complex number that
predictions of (25) and (26), which are well matched over the is a function of and . Therefore, a complex baseband
100-MHz frequency offset from the LO frequency. As it is impedance can potentially cause a larger difference
observed, in general, the high- and low-side gains are different. between the high- and low-side gains. Conventionally, series
We can simplify (25) and (26) using the fact that unlike base- capacitor is selected to be large enough to have very
band impedance , RF impedances and are small at , and is selected to be a tuned LC load at
almost constant from to . That means [Fig. 3(b)]. With this selection, because both and
that and are much smaller than , the conversion gain in (27) ap-
. This way, proaches to a constant value of , making the high- and
the equation for the baseband currents in (25) and (26) are sim- low-side conversion gains identical.
plified into Now, let us look for a solution to maximize the conversion
gain yet retain the equality of the high- and low-side conversion
gains. in(27) is a complex impedance that
is equal to , where and are real numbers. Over the
(27) desired channel, impedance is assumed to be purely resis-
tive and equal to . To have a maximum conversion gain, the
magnitude of the denominator in (27) must be minimum, so
must be zero. That means that and must resonate at .
Let us assume that is selected to be a parallel LC similar to
the one in Fig. 3(b), in which resistor models the inductor
(28) loss. With and considering the fact

(25)

(26)
MIRZAEI et al.: ANALYSIS AND OPTIMIZATION OF DCRs WITH CURRENT-DRIVEN PASSIVE MIXERS 2359

changes the conversion gain. This is why the simulated and pre-
dicted conversion gains in Fig. 4(a) are slightly different (less
than 0.1 dB).

IV. LEAKAGE OF BASEBAND NONLINEARITY FROM ONE

CHANNEL TO THE OTHER

In this section, the leakage of nonlinearity-induced low-fre-

quency components at the input of the current buffer from one
quadrature channel to the other will be discussed. Let us assume
that the baseband loads in the I and Q paths are identical, ex-
cept that the one in the I channel has second- and third-order
nonlinear terms (Fig. 5). The RF section is assumed to be per-
Fig. 5. Leakage of nonlinearity in the current buffer of one channel to the other. fectly linear. The input RF current is composed of two tones at
and with equal strengths. In order to
find the baseband currents at and , we can ignore the
that resonates with , it can be concluded that nonlinear terms of the baseband load in the I channel. Baseband
and . Thus, from (27), the conversion gain can be currents and for each of the frequency components
written as ( and ) are calculated from (25). The total baseband
currents for these two components are found from the superposi-
tion.5 However, due to the third- and second-order nonlinearities
of the baseband load in the I channel, baseband current
conversion gain (29) creates voltage components at or
and . Let us call one of these frequencies as
and the corresponding voltage at the input of the current buffer
Consequently, it can be shown that the maximum conversion as .Appendices A–C calculate the resulting base-
gain takes place when capacitor has an impedance that is band currents, which are equal to
equal to at , and the maximum
conversion gain is equal to

maximum conversion gain (30)

For this optimum design, the baseband currents in(27) can be

approximated to

(31)

Because changing to does not change the con- (32)

version gain, the high- and low-side gains are also identical for
the optimum design.Fig. 4(b) compares the simulated high- and
low-side conversion gains (with SpectreRF) for the two conven-
tional and optimum designs. Evidentally, the optimum design
results in a higher gain that is close to 5.5 dB in this particular
example.
In deriving the conversion gain, we assumed that the main fre-
quency component of the current of series capacitor is mainly
at the incident RF frequency. However, as is revealed from
(16), when an RF current that is close to passes through
the switching mixers, the voltage of the common node of the
mixers contains other frequency components at around the third, (33)
fifth, seventh, harmonics of the LO. These voltage compo-
nents appear across the series combination of and and in- Equations (32) and (33) indicate that, in general, the nonlin-
evitably induce RF currents at around the odd harmonics of the earity-induced baseband components in one channel leak to the
clock. Due to the harmonic downconversion of the mixer, these 5The mixing system with linear loads is linear time-variant (LTV), and the
currents are downconverted back to the baseband and slightly nonlinearity of the I channel has not been included so far.
2360 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 9, SEPTEMBER 2010

Fig. 6. Simulated and predicted conversion gains from a differential voltage in series with the baseband impedance in the I channel to the currents of the I and Q
channels. (a) Conventional design. (b) Design for the maximum front-end gain.

other channel and vice versa. They also reveal that the nonlin- V. NOISE AND IIP2 OF A DCR RECEIVER WITH THE 25%
earity seen at the input voltage of the current buffer is transferred DUTY-CYCLE MIXER
to the baseband currents and eventually appears in the final out-
puts of both channels as these currents pass through the current A. Noise Performance of the 25% Duty-Cycle Mixer
buffers.
The results of the previous section can be utilized to study the
Fig. 6(a) and (b) compares the SpectreRF simulations
noise performance of a receiver with the 25% duty-cycle passive
(pss+pac) with the predictions [(32) and (33)] for the two
mixer. Of interest is the noise contribution of the current buffers
conventional and optimum designs, respectively. The design
to the receiver noise figure. Because, in the 50%s duty-cycle
parameters are the same as the ones in Fig. 4(b). For this
mixer, the two I and Q channels are simultaneously ON, the
purpose, a differential ac voltage is placed in series with the
output impedance seen through the baseband side of each mixer
baseband impedance in the I channel, and the resulting base-
is lowered due to the loading of the other channel, which causes
band ac currents in the I and Q channels are monitored. Also,
the noise of the current buffers to be boosted [28]. In contrast, in
to plot the prediction, only six terms in the infinite summa-
the 25% duty-cycle mixer, only one channel is ON at any given
tions of (32) and (33) have been retained, which means that
moment. That is why, in terms of noise figure, a receiver with the
only frequency components at around , and
25% duty-cycle passive mixer outperforms. Thus, all that is left
of the series-capacitor current have been considered. From
is to compare the noise performances of the two conventional
Fig. 6(a) and (b), it is observed that in the optimum design (the
and optimum (proposed) designs, where the downconversion is
design for the maximum front-end gain), the conversion gain
performed by the 25% duty-cycle passive mixer. Let us con-
from the baseband voltage in the I channel to the baseband
sider a noise component at of the equivalent input-referred
current of the same channel is about 5 dB larger with respect
noise of the current buffer. This noise voltage is transferred to
to that in the conventional design. However, because the re-
the baseband current, as predicted by (32). We observed that
ceiver gain in the optimum design is also larger by 5 dB, when
the transfer gain in the optimum design was larger compared to
referred to the receiver input, the two designs exhibit the same
that in its conventional counterpart. However, considering the
performance. On the contrary, in terms of the leakage gain from
fact that the receiver conversion gain is also larger by the same
one channel to the other quadrature one, the optimum design
amount, the equivalent input-referred noise is almost the same
outperforms by about 6 dB.
for both designs.6 Therefore, unlike the receiver with the 50%
In summary, compared to that in the 50%s duty-cycle cur-
duty-cycle passive mixer where the optimum design was supe-
rent-driven passive mixer, the IQ crosstalk in its 25% duty-cycle
rior, with the 25% duty-cycle mixer, the two designs perform
counterpart is significantly lowered. Intuitively, this can be at-
pretty much the same. Of course, due to the higher gain of the
tributed to the loading of one channel by the other quadrature
optimum design, the noise contribution of the following stages,
channel and vice versa because, in the 50% duty-cycle mixer,
i.e., baseband filter and analog-to-digital converter, will be less.
both I and Q channels are simultaneously ON. However, this is
not the case in the 25% duty-cycle mixer, in which, at any mo- 6In fact, this is not a coincidence, and from (25), (26), and (32), it can be

ment, only one channel is ON. Moreover, when a receiver with shown that for a receiver with the 25% passive mixer, the noise of the receiver
referred to the LNA input is almost independent of size selection of the series
the 25% duty-cycle mixer is designed for a maximum conver- capacitor and the LNA load as far as the LNA+mixer noise and the
sion gain, the IQ crosstalk is lowered even further. transimpedance amplifier input-referred noise are considered.
MIRZAEI et al.: ANALYSIS AND OPTIMIZATION OF DCRs WITH CURRENT-DRIVEN PASSIVE MIXERS
Fig. 7. Simulated IIP2 of two receivers with the 25% and 50% duty-cycle passive mixers. (a) IIP2 from mismatch in . (b) IIP2 from mismatch in
from RF-to-LO feedthrough.
B. Second-Order Nonlinearity Performance of the 25%
Duty-Cycle Mixer
The major sources of the second-order nonlinearity in a DCR
receiver are well known [8]–[10]. Because the second-order
nonlinearity of the mixer is generally dominant in the receiver
IIP2 number, in this section, we briefly compare the IIP2 perfor-
mances of the two 25% and 50% current-driven passive mixers.
The sources of the second-order nonlinearity in anonquadrature
50% current-driven downconversion passive mixer have been
studied, which can be summarized as follows: 1) direct leakage
of the IM2 components created inside the LNA [Fig. 1(a)] to
the baseband in the presence of mismatches among the switches
of the passive mixer; 2) RF-to-LO and LO-to-RF coupling in
the downconversion mixer; and 3) nonlinearity of the mixer
switches in the presence of and threshold-voltage mismatches.
The series capacitor between the LNA and the switches of
the passive mixer (both the 25% and 50% duty-cycle mixers)
blocks those IM2 components generated inside the LNA; there-
fore, they do not contribute to the IIP2 of the receiver. The rest
of the IM2 sources mentioned earlier can contribute to the IIP2
throughout the following two ways: 1) by modulating the resis-
tance of the switches of the passive mixer and 2) by modulating
the ON/OFF instants of the mixer switches. Fortuitously, it ap-
pears that the modulation of the window duration in which the
switches are ON does not contribute much to the IM2 products
compared to the resistance modulation of the switches [21]. This
is because the switches are clocked by rail-to-rail clocks with
fast rise and fall times.
Now, we intuitively explain that the 25% current-driven pas-
sive mixer should outperform the 50% one when it comes to
the IIP2. Once again, the LNA is modeled as an RF current
source with a relatively large output impedance. In the case of
quadrature downconversion with the 50% duty-cycle mixer and
without an intermediate transconductance stage [Fig. 1(a)], at
any given moment, one switch from the I channel and one switch
from the Q channel are simultaneously ON. Ideally, the RF cur-
rent is supposed to be equally divided between the two channels.
However, the resistance modulation of the mixer switches dis-
turbs this equipartition of the RF current between the two down-
conversion channels. Any unequal distribution arising from a
mismatch (together with the second-order nonlinearity) in one
channel would lead to IM2 components in both I and Q chan-
nels. In other words, the transfer functions in which the RF
2361
. (c) IIP2
current must be divided between the two channels are modu-
lated due to the presence of mismatch/nonlinearity. In fact, in
[28], it is proved that in an IQ receiver with a 50% passive
mixer and no intermediate transconductance stage between the
LNA and the passive mixers, any low-frequency intermodula-
tion components created at the baseband of one channel strongly
transfer to the other quadrature channel. In contrast, as observed
from Fig. 3, at any moment, only one switch is ON, and the RF
current passes through this switch without being significantly
modulated. This is why the 25% mixer is expected to exhibit
a superior IIP2 performance compared to its 50% counterpart.7
Fig. 7 shows the simulated IIP2 numbers of two receivers, i.e.,
one with 50% duty-cycle passive mixer and another with 25%
duty-cycle passive mixer. For both receivers, the rise and fall
times of the clocks are set to be 0.5 ps in order to lower the IM2
components created through modulation of the ON/OFF instants
of the mixer switches. Except their downconversion mixers, the
two receivers are identical. The simulated IIP2 numbers for mis-
match in the or the threshold voltage of one of the mixer
switches are shown in Fig. 7(a) and (b), respectively. The IIP2
performances of the two receivers due to RF-to-LO feedthrough
are shown in Fig. 7(c), in which the horizontal axis is the leakage
gain of the LNA input to one of the LOs. Evidentally, the 25%
mixer presents a superior IIP2.
VI. MEASUREMENT RESULTS
To verify the theory, a zero-IF receiver front end was designed
and implemented at around the 1.9-GHz range (Fig. 8). The ac-
tual implementation is differential, and for simplicity, a single-
ended version is drawn in Fig. 8. The LNA has a large transcon-
ductance to lower the noise contribution of the following stages.
The LNA load is a tuned LC load, in which the loading inductor
is differential with a single-ended size of 8 nH and a of 11.5
. Special care has been taken in the layout to
not degrade the of the LNA load due to the ohmic loss of the
signal traces.
The transimpedance amplifier is a common-gate one (Fig. 8),
and the design parameters are selected based on the optimum
method. The degeneration resistor of the common gate is
chosen to be 1 k , and the common-gate devices of the current
7Assuming that there are no intermediate transconductor stages placed be-
tween the LNA and the mixers to isolate the I and Q channels. Otherwise, with
no IQ crosstalk, the two 50% and 25% passive mixers would show the same
IIP2 performances.
2362 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 9, SEPTEMBER 2010
Fig. 8. Receiver of 1.9 GHz with 25% duty-cycle current-driven passive mixers
designed in 65-nm CMOS.
Fig. 9. Generation of 25% duty-cycle quadrature clocks.
buffer are sized large enough to lower the flicker noise corner
down to a very low frequency. The simulated single-ended input
impedance seen from each input of the current buffer is around
60 . Each of the differential outputs of the common-gate buffer
is buffered by an N-type source follower. The buffer consumes
1.16 mA and exhibits a loss of 0.6 dB.
The ON resistance of the passive mixer switches is about 23
for a typical process corner and room temperature. Due to
the 60- single-ended input impedance of the current buffer,
lowering the switch resistance further will not help much in the
conversion gain and may even decrease it because of excessive
junction and parasitic capacitance at the RF side. Moreover, it
will require stronger LO buffers and, as a result, more power
consumption. In this design, they have been sized just to achieve
an acceptable IIP2. As shown inFig. 8, switchable capacitors are
placed in parallel with the resistive loads of the current buffers
to embed a first-order low-pass filter with a controllable 3-dB
bandwidth. The simulated noise figure of the receiver at the an-
tenna measured from the differential outputs of the source fol-
lower is about 2.7 dB.
There is an on-chip synthesizer operating at double fre-
quency, and an on-chip divide-by-two provides 50% duty-cycle
rail-to-rail quadrature clocks at the desired LO frequency (see
Fig. 9). Using four AND gates, these 50% duty-cycle quadra-
ture signals are converted into 25% duty-cycle quadrature
clocks, and after being buffered, they feed the switches of the
current-driven passive mixer. The AND gates, including their
buffers, dissipate 6.5 mA from 1.2-V supply. The simulated rise
TABLE I
MEASURED PERFORMANCE OF THE RECEIVER
Tones are at 0.8- and 1.6-MHz offsets.
Fig. 10. Simulated and measured conversion gain difference between the high
and low sides.
and fall times (the bondwires and other parasitics are included)
are both about 15 ps for the typical process corner.
Table I shows the measured performance of the receiver. As
we had predicted from the analysis, the IIP3 values measured at
any frequency offsets are equal for both I and Q channels (not
shown in the table). Moreover, the measured high- and low-side
IIP3 numbers are almost the same. For example, the measured
in-band IIP3 values (tones at 0.8- and 1.6-MHz offsets) at high-
and low-side frequencies are different by only 0.06 dB.
Fig. 10 shows the measured and simulated high- and low-side
conversion gain differences over a 10-MHz range. The mea-
sured high- and low-side gain difference is about 0.25 dB up
to 5 MHz, which is quite low. At the baseband side of the mixer
switches of each quadrature channel, a capacitor has been put
between the two differential outputs of the passive mixer (
and in Fig. 8). This capacitor paralleled with the input re-
sistance of the current buffer makes a low-pass filter with a
cutoff frequency of about 14 MHz. This low-pass filter attenu-
ates blockers at offset frequencies beyond its 3-dB cutoff, which
lowers the voltage swing and, as a result, improves the linearity.
In order to find the transfer function from the LNA input to the
differential voltage across the common-gate inputs, all that is
needed is to simply multiply the transfer function of the base-
band current [(25)] to baseband impedance . The predicted
conversion gain is shown in Fig. 11(a), which is normalized to
the dc gain. Evidentally, the conversion gain is predicted to be-
come 8 dB lower when offset frequency sweeps from 10 to
50 MHz. Because the common-gate inputs are not available for
the measurement, it has been measured indirectly by applying a
blocker tone at to the receiver and adjusting its power
in a way to compress the receiver gain at the desired channel
MIRZAEI et al.: ANALYSIS AND OPTIMIZATION OF DCRs WITH CURRENT-DRIVEN PASSIVE MIXERS
Fig. 11. (a) Predicted conversion gain from the LNA input to the differential inputs of the current buffer versus offset frequency
(measured) versus offset frequency from the LO in which the receiver gain is desensitized by 1 dB. (b) Measured IIP3 versus frequency offset
tone to the LO is located at .
Fig. 12. Die photograph.
around dc by 1 dB. Knowing that, for the high-frequency off-
sets of the blocker, the inputs of the common gate are the prime
factors of compression, the adjusted blocker power must follow
the same predicted trend of the conversion transfer function. As
shown in Fig. 11(a), the blocker power is relaxed by about 8
dB when its frequency is swept from 10 to 50 MHz, confirming
the theory. Also,Fig. 11(b) shows IIP3 versus frequency offset
, in which one of the two test tones is located at , tance amplifier, followed by a current-driven passive mixer in
and the other is located at around . Evidentally, IIP3
improves as increases again because of the RC low-pass fil-
tering at the inputs of the current buffer. The measured IIP2 is
better than 45 dBm at the maximum gain of the front end.
The test chip was fabricated in a 65-nm digital CMOS
process, and the die photograph of the receiver section is shown
in Fig. 12.
VII. CONCLUSION AND DISCUSSION
The performance of receivers with 25% duty-cycle current-
driven passive mixers has been studied and analyzed. It has
been shown that, in general, these receivers outperform the ones
with 50% duty-cycle passive mixers. The problems, such as un-
equal high- and low-side conversion gains and different high-
and low-side IIP2 and IIP3 values, are significantly lowered
due to the operating principles of this passive mixer and can
be solved by sizing the design parameters carefully. Addition-
ally, the leakage amount of low-frequency components from the
2363
, plus the blocker power
. The closest
baseband of one quadrature channel to the other has been signif-
icantly lowered compared to that with a 50% duty-cycle mixer.
Also, due to the lower conversion gain from a low-frequency
voltage source in series with the baseband impedance to the
baseband current, with the 25% duty-cycle mixer, the receiver
linearity has been degraded less from the nonlinearity of the cur-
rent buffer.
This paper clarifies the main reason by which the aforemen-
tioned issues are stronger with the 50% duty-cycle mixer, and
that is the circulation of the image current between the two
quadrature channels. Although Mirzaei et al. [28] have demon-
strated that even that design can be optimized to minimize the
IQ crosstalk by lessening the image current, the 25% duty-cycle
mixer solves the problem by eliminating the existence of the
image current itself. The main objective could be generation of
25% duty-cycle quadrature clocks with relatively sharp rise and
fall times at gigahertz frequencies. This will add to the power
consumption.
Finally, it should be highlighted that receivers with current-
driven passive mixers exhibit higher linearity compared with
other mixing schemes. This is because a low-noise transconduc-
which its load is a low-input-impedance transimpedance ampli-
fier, can be optimized to produce less voltage swings at both RF
and baseband sides of the mixer switches [14],[28], [29], [31].
In other words, all the internal nodes, including the transconduc-
tance amplifier output and the transimpedance amplifier inputs,
are low-impedance nodes. The lower voltage swings in the in-
ternal nodes improve the linearity [31].
APPENDIX A
In this Appendix, we aim to find the Thévenin equiva-
lent of the mixing systems shown in Fig. 13(a) and (b). The
mixers are driven by 25% duty-cycle quadrature clocks. In
the baseband section of the I channel of both circuits, there
is a low-frequency differential voltage of
( single-ended) in series with the base-
band impedances. There is a differential baseband voltage in
the Q channel too, which is orthogonal to that of the I channel.
2364 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 9, SEPTEMBER 2010
Fig. 13. Finding the Thévenin equivalent. (a) Quadrature baseband voltages are in series with the baseband impedances. (b) Quadrature sequence of baseband
excitations is changed. (c) Thévenin equivalent.
Thus, there are two possibilities: having
in Fig. 13(a) or in Fig. 13(b).
The Thévenin equivalent [32] of Fig. 13(a) and (b) is shown
in Fig. 13(c). The Thévenin equivalents are, in fact, the same
mixing system, with all its independent sources being set to
zero,8 in series with a voltage called the Thévenin voltage
[ in Fig. 13(c)]. The Thévenin voltage also is
called an open-circuit voltage because it is the voltage observed
when the original circuit is not connected to any other circuit.
Therefore, the Thévenin equivalents of Fig. 13(a) and (b) are
different only in . According to Thévenin’s theorem for
linear circuits [32], when any of the circuits in Fig. 13(a) and (b)
is connected to another system, the currents and voltages of all
branches in that system would not alter if it is connected to the
Thévenin equivalent.
Now, let us find the Thévenin voltage of Fig. 13(a),
and that of Fig. 13(b) can be found in a similar way. All that is
needed is to find the open-circuit voltage. It is obvious that
(34)
By utilizing the Fourier series in (8)–(11), is found
(35)
8Voltage sources become short circuit, and current sources become open cir-
cuit.
In other words, the two baseband inputs at with phasors
and in the I and Q channels,
respectively, can be removed and instead replaced with
at the RF side of the switches in order to solve any arbitrary
system connected to the original mixing system.
If we do similar analysis for the circuit in Fig. 13(b), the
equivalent Thévenin voltage is found
(36)
APPENDIX B
Now, assume that the circuits of Fig. 13(a) and (b) in
Appendix A are placed in the receiver of Fig. 3, and we would
like to find the resulting baseband currents. We analyze the
case of Fig. 13(a), and the case in Fig. 13(b) is quite similar.
The Thévenin equivalent in Fig. 13(c) can now be utilized to
find the current of series capacitor . The capacitor current is
readily found, observing the fact that the input impedance seen
from the RF side of the switches is given by (17). Because the
equivalent Thévenin voltage is composed of frequency com-
ponents at , the capacitor current
contains only these frequencies too. From (17) and (35), the
phasor of the capacitor current at is
obtained (see (37) at the bottom of the page). Impedance
is defined as in (37). Also, to calculate at
(37)
MIRZAEI et al.: ANALYSIS AND OPTIMIZATION OF DCRs WITH CURRENT-DRIVEN PASSIVE MIXERS 2365

from (17), the following approximation

was taken:
(42)

Because is a baseband frequency, and do not

(38) change much from to .
Finally, from (20) and (21), the phasors of the resulting base- Hence,(41) and (42) are approximated to
band currents at are found

(39)

By performing similar analysis, the resulting baseband cur-

(43)
rents are found if the circuit of Fig. 13(b) is used

(40)

(44)
APPENDIX C
Now, let us consider the case when there is, for example, only
one baseband excitation voltage in the I channel and there is REFERENCES
no excitation voltage in the Q channel. A differential baseband [1] A. Abidi, “RF CMOS comes of age,” IEEE J. Solid-State Circuits, vol.
voltage at is in series with the baseband impedance and is 39, no. 4, pp. 549–561, Apr. 2004.
[2] B. Razavi, “Design considerations for direct-conversion receivers,”
represented by phasor . To find the baseband cur- IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44,
rents, because the system is LTV, we can decompose this into no. 6, pp. 428–435, Jun. 1997.
two pairs of differential quadrature baseband voltages in series [3] F. Agnelli, G. Albasini, I. Bietti, A. Gnudi, A. Lacaita, D. Manstretta,
R. Rovatti, E. Sacchi, P. Savazzi, F. Svelto, E. Temporiti, S. Vitali, and
with the baseband loads: 1) in the I channel and R. Castello, “Wireless multi-standard terminals: System analysis and
in the Q channel, and 2) in design of a reconfigurable RF front-end,” IEEE Circuits Syst. Mag.,
the I channel and in the Q channel. From vol. 6, no. 1, pp. 38–59, Mar. 2006.
[4] A. Abidi, “The path to the software-defined radio receiver,” IEEE J.
Appendix B, the baseband currents are given by these expres- Solid-State Circuits, vol. 42, no. 5, pp. 954–966, May 2007.
sions: [5] H. Darabi and A. Abidi, “Noise in RF-CMOS mixers: A simple phys-
ical model,” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 15–25, Jan.
2000.
[6] H. Darabi and J. Chiu, “A noise cancellation technique in active
RF-CMOS mixers,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp.
2628–2632, Dec. 2005.
[7] R. Pullela, T. Sowlati, and D. Rozenblit, “Low flicker-noise quadrature
mixer topology,” in Proc. IEEE Int. Solid-State Circuits Conf., 2006,
pp. 1870–1879.
[8] K. Dufrêne, “Analysis and cancellation methods of second order inter-
modulation distortion in RFIC downconversion mixers,” Ph.D. disser-
tation, Universität Erlangen-Nürnberg, Franconia, Germany, 2007.
[9] D. Manstretta, M. Brandolini, and F. Svelto, “Second-order intermod-
ulation mechanisms in CMOS downconverters,” IEEE J. Solid-State
(41) Circuits, vol. 38, no. 3, pp. 394–406, Mar. 2003.
[10] M. Brandolini, P. Rossi, D. Sanzogni, and F. Svelto, “A 78 dBm
IIP2 CMOS direct downconversion mixer for fully integrated UMTS
receivers,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 552–559,
Mar. 2006.
[11] J. H. Reed, Software Radio: A Modern Approach to Radio Engineering,
1st ed. Englewood Cliffs, NJ: Prentice-Hall, 2002.
[12] A. Schoonen, T. Schenk, and P. Baltus, “Impact and digital estimation
of nonlinear impairments in analog baseband processing stages,” in
Proc. IEEE Eur. Conf. Wireless Technol., 2008, pp. 73–76.
2366 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 9, SEPTEMBER 2010
[13] E. Acar and S. Ozev, “Digital calibration of RF transceivers for I–Q
imbalances and nonlinearity,” in Proc. IEEE Int. Conf. Comput. Des.,
2007, pp. 512–517.
[14] E. Sacchi, I. Bietti, S. Erba, L. Tee, P. Vilmercati, and R. Castello, “A
15 mW, 70 kHz corner direct conversion CMOS receiver,” in Proc.
IEEE Custom Integr. Circuits Conf., 2003, pp. 459–462.
[15] M. Valla, G. Montagna, R. Castello, R. Tonietto, and I. Bietti, “A
72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF
and 200-kHz noise corner,” IEEE J. Solid-State Circuits, vol. 40,
no. 4, pp. 970–977, Apr. 2005.
[16] N. Poobuapheun, C. Wei-Hung, Z. Boos, and A. Niknejad, “A 1.5-V
0.7 to 2.5 GHz CMOS quadrature demodulator for multiband direct-
conversion receivers,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp.
1669–1677, Aug. 2007.
[17] R. Bagheri, A. Mirzaei, S. Chehrazi, E. Heidari, M. Lee, M. Mikhemar,
W. Tang, and A. Abidi, “An 800 MHz to 6 GHz software-defined wire-
less receiver in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 41,
no. 12, pp. 2860–2876, Dec. 2006.
[18] T. Nguyen, N. Oh, V. Le, and S. Lee, “A low-power CMOS direct
conversion receiver with 3-dB NF and 30-kHz flicker-noise corner for
915-MHz band IEEE 802.15.4 ZigBee standard,” IEEE Trans. Microw.
Theory Tech., vol. 54, no. 2, pp. 735–741, Jun. 2006.
[19] S. Chehrazi, A. Mirzaei, and A. Abidi, “Noise in current-commutating
passive FET,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 2,
pp. 332–344, 2010.
[20] D. Leenaerts and W. Readman-White, “ noise in passive CMOS
mixers for low and zero IF receivers,” in Proc. Eur. Solid-State Circuits
Conf., 2001, pp. 41–44.
[21] S. Chehrazi, A. Mirzaei, and A. Abidi, “Second-order intermodula-
tion in current-commutating passive FET mixers,” IEEE Trans. Cir-
cuits Syst. I, Reg. Papers, vol. 56, no. 12, pp. 2556–2568, Dec. 2009.
[22] S. Zhou and M. F. Chang, “A CMOS passive mixer with low flicker
noise for low-power direct-conversion receiver,” IEEE J. Solid-State
Circuits, vol. 40, no. 5, pp. 1084–1093, May 2005.
[23] D. Kaczman, M. Shah, M. Alam, M. Rachedine, D. Cashen, L. Han, and
A. Raghavan, “A single-chip 10-band WCDMA/HSDPA 4-band GSM/
EDGE SAW-less CMOS receiver with DigRF 3G interface and 90
dBm IIP2,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 718–739,
Mar. 2009.
[24] B. Cook, A. Berny, A. Molnar, S. Lanzisera, and K. Pister, “Low-power
2.4-GHz transceiver with passive RX front-end and 400-mV supply,”
IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2757–2766, Dec. 2006.
[25] M. Soer, E. Klumperink, Z. Ru, F. van Vliet, and B. Nauta, “A
0.2-to-2.0 GHz 65 nm CMOS receiver without LNA achieving
dBm IIP3 and dB NF,” in Proc. IEEE Int. Solid-State Circuits
Conf., 2009, pp. 222–223.
[26] H. Khatri, L. Liu, T. Chang, P. Gudem, and L. Larson, “A SAW-less
CDMA receiver front-end with single-ended LNA and single-balanced
mixer with 25% duty-cycle LO in 65 nm CMOS,” in Proc. IEEE Radio
Frequency Integr. Circuits Symp., 2009, pp. 13–16.
[27] M. Camus, B. Butaye, L. Garcia, M. Sie, B. Pellat, and T. Parra, “A
5.4-mW/0.07 2.4 GHz front-end receiver in 90 nm CMOS for
IEEE 802.15.4 WPAN standard,” IEEE J. Solid-State Circuits, vol. 43,
no. 6, pp. 1372–1383, Jun. 2008.
[28] A. Mirzaei, H. Darabi, J. Leete, X. Chen, K. Juan, and A. Yazdi, “Anal-
ysis and optimization of current-driven passive mixers in narrowband
direct-conversion receivers,” IEEE J. Solid-State Circuits, vol. 44, no.
10, pp. 2678–2688, Oct. 2009.
[29] A. Mirzaei, X. Chen, A. Yazdi, J. Chiu, J. Leete, and H. Darabi, “A
frequency translation technique for SAW-less 3G receivers,” in Proc.
IEEE Symp. VLSI Circuits, 2009, pp. 280–281.
[30] A. V. Oppenheim, A. S. Willsky, and S. H. Nawab, Signals and Sys-
tems, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 1996.
[31] Z. Ru, N. Moseley, E. Klumperink, and B. Nauta, “Digitally-enhanced
software-defined radio receiver robust to out-of-band interference,”
IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3359–3375, Dec.
2009.
[32] C. A. Desoer and E. S. Kuh, Basic Circuit Theory. New York: Mc-
Graw-Hill, 1969.
Ahmad Mirzaei received the Ph.D. degree in elec-
trical engineering from the University of California,
Los Angeles, in 2006.
He is currently a Principal Scientist with
Broadcom Corporation, Irvine, CA. His interests
include analog and RF IC design for wireless com-
munications.
Hooman Darabi received the Ph.D. degree in elec-
trical engineering from the University of California,
Los Angeles, in 1999.
He is currently a Senior Director of Engineering
with Broadcom Corporation, Irvine, CA. His inter-
ests include analog and RF IC design for wireless
communications, including Bluetooth, wireless local
area network, and cellular applications.
John C. Leete received the B.S. degree in electrical
engineering from North Carolina State University,
Raleigh, in 1995 and the M.S. degree in electrical
engineering from the University of California, Los
Angeles, in 1999.
He is currently with Broadcom Corporation,
Irvine, CA. His research interests are in the area
of CMOS RF transceiver design and mixed-signal
simulation methods.
Yuyu Chang received the B.S. degree in electronics
engineering from Chung Yuan Christian University,
Chung Li, Taiwan, in 1992 and the M.S. and Ph.D.
degrees in electrical engineering from the University
of Southern California (USC), Los Angeles, in 1996
and 2002, respectively.
From 1996 to 2002, he was a Research Assistant
with the USC Information Sciences Institute. In
2002, he joined Advanced Design, Intel Corporation,
Hillsboro, OR, where he was mainly engaged in
radio frond-end design in both CMOS and SiGe.
Since 2005, he has been with Broadcom Corporation, Irvine, CA, as a Principal
Scientist. His current research interests are CMOS analog and RF ICs for
cellular and wireless local area network applications.