COMPUTER ORGANISATION

(SHORT ANSWERS)

Q1) Explain the principle of virtual memory.

Ans) Virtual memory creates the illusion of having more RAM than physically available. It
works like a tag team between your computer's hardware and software:
1. Larger Address Space: The software (operating system) creates a virtual address
space that's much larger than the actual RAM. Imagine it as a giant workspace for
your programs.
2. Divided into Pages: This virtual space is divided into fixed-size chunks called pages.
Think of them as sections in your workspace.
3. Only Active Pages in RAM: Only the most frequently used pages are loaded into the
physical RAM, acting as your active work area.
4. Swapping with Hard Drive: When a program needs a page not in RAM, the OS
swaps it with a less used page on the hard drive (slower but much larger). This
"backing store" holds inactive pages.
5. Transparent Swapping: The OS manages this swapping process transparently. You,
the user, don't notice the back-and-forth between RAM and the hard drive.
This allows multiple programs to run concurrently, even if their total memory needs exceed
physical RAM. It's like having a large workspace with clever storage to keep your active
projects at hand.

Q2) Discuss the general-purpose Registers in 8086

Ans) The 8086 microprocessor boasts eight general-purpose registers, each 16 bits wide.
These registers act as temporary storage locations for data during program execution. Let's
delve into some key ones:
• Accumulator (AX): This workhorse register holds operands for many arithmetic and
logical operations. It can be further divided into two 8-bit halves (AL and AH) for
handling byte-sized data.
• Data Registers (BX, CX, DX): These registers hold various kinds of data. BX is
often used as a base register for memory addressing, CX serves as a counter in loops,
and DX can participate in multiplication and division operations. Similar to AX, each
can be accessed in 8-bit halves (BL, CL, and DL, respectively).
 • Segment Registers (CS, DS, SS, ES): These 16-bit registers work differently. They
don't store data directly but hold segment addresses for accessing memory. CS points
to the current code segment, while DS, SS, and ES are used for data, stack, and
additional data segments, respectively.
• Pointer Registers (BP, SI, DI): These registers excel at memory addressing. BP (base
pointer) is often used to access data structures relative to the base of the stack
segment. SI (source index) and DI (destination index) come in handy for string
operations, keeping track of positions within string data.
By effectively utilizing these general-purpose registers, programmers can optimize their 8086
assembly code for faster execution and efficient memory usage.

Q3) In a single bus CPU what are the steps to fetch a word from the memory.
Ans) In a single bus CPU, fetching a word from memory involves a coordinated dance
between the processor and memory:
1. Instruction Register (IR) Prep: The processor starts by placing the address of the
desired word (obtained from the program counter) into a special register called the
Instruction Register (IR). Think of IR as a note holding the memory location you want
to visit.
2. Address Broadcast: The processor broadcasts the address from the IR onto the
address bus, which acts as a highway for memory locations. This address essentially
tells the memory where to look for the data.
3. Control Signal: Simultaneously, the processor sends a control signal (often called
"Read") on the control bus. This signal informs the memory that the processor intends
to read data.
4. Memory Access: The memory receives the address and control signal. It then locates
the requested word and prepares it for transfer.
5. Data Transfer: The memory places the data word onto the data bus, which acts as
another highway for data itself.
6. Data Register Load: Finally, the processor reads the data word from the data bus and
stores it in a dedicated register, often called the Memory Data Register (MDR). This
register holds the retrieved data ready for use.
These steps occur in rapid succession, with each bus carrying the necessary information for
the memory fetch operation. The single bus design simplifies the communication but might
become a bottleneck for high-performance processors.

Q4) What are the fundamental design issues in designing an instruction set.
Ans) Designing an instruction set (ISA) involves balancing power and efficiency. Here are
some key issues to consider:
 1. Instruction complexity:
o CISC (Complex): Offers powerful instructions that can do more in one go,
but can be slower to decode and less efficient.
o RISC (Reduced): Uses simpler instructions requiring multiple steps, but can
be faster to decode and allow for better pipelining.
2. Number of operands: How many data elements (registers or memory locations) an
instruction can handle at once. More operands might be convenient but could require
complex instructions.
3. Addressing modes: How instructions specify the location of data operands. More
options offer flexibility but can increase instruction complexity.
4. Instruction size: Fixed-length instructions simplify decoding for RISC processors,
while variable-length instructions in CISC can be more efficient for specific tasks.
5. Register usage: Emphasis on registers for operands (RISC) can speed up access
compared to relying heavily on memory (CISC).
The choice of design philosophy (CISC vs. RISC) depends on the target application. It's a
trade-off between instruction complexity, execution speed, and overall efficiency.