AEC Course Material

3REC01 Analog Electronic Circuits
III Semester B.E., Electronics & Communication Engg.
K. V. Jyothi Prakash
Assistant Professor
Department Of Electronics & Communication EngG.
SIDDAGANGA INSTITUTE OF TECHNOLOGY

TUMAKURU – 572 103
SYLLABUS
ANALOG ELECTRONIC CIRCUITS
Contact Hours/ Week : 3 (L) Credits :3

Total Lecture Hours : 39 CIE Marks : 50
Sub. Code : 3REC01 SEE Marks : 50
Course pre-requisite: Basic Electronics and Foundations of Electrical Engineering
Course Objectives: This subject enables the students to learn about:

 Applications of diode and special diodes
 Working of MOSFET, various configurations and their biasing.
 Small signal modelling and amplifiers design.
 Working and parameters of MOS Differential Amplifier.
 Concept of feedback and Power amplifiers.
Course Outcomes: At the end of the course the student should be able to
CO1 Design clipper, Clamper components to provide solutions for communication
problems, to design rectifier to meet the power supply requirement. (L3)
CO2 Analyze characteristics of MOSFET to design biasing circuit for Amplifiers. (L3)
CO3 Analyze characteristics of MOSFET amplifiers using small signal model at low and
high frequencies. (L2)
CO4 Analyze and evaluate MOS differential Amplifiers. (L2)
CO5 Compare different negative feedback topologies. (L1)
CO6 Analyze and evaluate the performance of power amplifiers. (L2)
Unit-1
Applications of Diode: Analysis of full wave rectifier with capacitor filter - approximate
method to calculate ripple factor, Two level clipping circuits, Clamping circuits, Voltage
doublers. Special Diode Types: The Schottky-Barrier Diode (SBD), Varactors, LED and
Photo diode. 7 Hrs
Unit-2
Device Structure & Physical Operation : Device structure, Operation, iD - vDS Relationship
(qualitative analysis), Symbol, iD –vDS characteristics, Output Resistance in saturation, The
body effect, Temperature effect, Breakdown & Input protection, MOSFET Circuit at DC.
MOSFET as an Amplifier and as a Switch: Large signal operation-transfer characteristics,
Operation as a switch, Operation as a Linear Amplifier (qualitative analysis).
Biasing in MOS Amplifier Circuits: Biasing by fixing VGS, Biasing by fixing VG and
connecting a resistance in the source, Biasing Using a Drain to Gate feedback Resistor,
Constant-Current-Source Biasing (using current mirror). 8 Hrs
Unit-3
Small-Signal Operation and Models: DC Bias Point, Signal Current in the Drain Terminal,
Voltage Gain, Small-Signal equivalent-Circuit Models, Trans conductance gm, The T
equivalent Circuit model.
Single-Stage MOS Amplifiers: The Basic structure, Characterizing MOS Amplifiers,
Common Source Amplifier, Common Source Amplifier with Source Resistance, Common
Gate Amplifier (qualitative analysis), Common Drain Amplifier (qualitative analysis),
Comparison.
The MOSFET Internal Capacitance & High-Frequency Model: Gate Capacitance Effect,
Junction Capacitance, High-Frequency Model, Unity Gain frequency-fT. Frequency
Response of CS Amplifier (qualitative analysis) 8 Hrs
Unit-4
The MOS Differential Pair: Operation with a Common-Mode Input Voltage and
Differential Input voltage. Small-Signal Operation of the MOS Differential Pair: Differential
Gain and Common Mode Rejection Ratio Other Non-ideal Characteristics of the Differential
Amplifier: Input Offset Voltage of the Differential Pair, Input Common-Mode Range.
The Differential Amplifier with Active Load: Differential-to-Single-Ended Conversion,
Active-Loaded MOS Differential Pair, Differential Gain of the Active-Loaded MOS Pair,
Common Mode Gain and CMRR. 8 Hrs
Unit-5
Feedback Amplifiers: General Feedback Structure, Properties of Negative Feedback, Four
Basic Feedback Topologies-Series-Shunt, Series-Series, Shunt-Shunt & Shunt-Series
Amplifier (Qualitative Analysis).
Power Amplifiers: Introduction, Classification, Class A - Operation, Transfer
Characteristics, Signal Waveforms, Power Dissipation, Power Conversion efficiency
(qualitative analysis), Transformer Coupled Power Amplifiers (qualitative analysis), Class B
– operation, Transfer Characteristics, Power Dissipation, Power Conversion efficiency,
Reducing Cross-Over Distortion, Class AB – Operation, Output Resistance 8 Hrs
TEXT BOOK
1 Adel S. Sedra Kenneth Microelectronic Circuits : Theory and Applications, 5th
C. Smith Edition, Oxford International Student Edition, 10th
impression 2012.
REFERENCE BOOKS
1 Behzad Razavi Fundamentals of Microelectronics, Wiley Student Edition,
Reprint 2012.
2 Robert L. Boylestad and Electronic Devices and Circuit Theory. 11th Edition, PHI,
Louis Nashelsky. 2013.
CONTENTS
Syllabus
Unit-1 Applications of Diode 1
1.1 Full wave rectifier with Capacitor filter 1
1.1.1 Expression for ripple factor 2
1.2 Clipping circuits 5
1.2.1 Two level series clippers 5
1.2.2 Two level shunt clippers 6
1.2.3 Design 8
1.3 Clamping circuits 13
1.3.1 Negative clampers 13
1.3.2 Positive clampers 17
1.3.3 Design 22
1.4 Voltage multiplier 24
1.4.1 Half wave voltage doubler 24
1.4.2 Full wave voltage doubler 25
1.5 Special diode types 27
1.5.1 Schottky barrier diode 27
1.5.2 Varactors 28
1.5.3 Photo diode 29
1.5.4 Light emitting diode 30
Questions 31
Unit-2 MOS Field Effect Transistor 33

2.1 Device structure and physical operation 33
2.1.1 Operation with no gate voltage 34
2.1.2 Creating a channel for conduction 35
2.1.3 Applying a small VDS 36
2.1.4 Operation as VDS is increased 37
2.1.5 Expression for drain current 38
2.1.6 Circuit symbol 39
2.2 ID-VDS characteristics / Output characteristics / Drain characteristics 39
2.2.1 Finite output resistance 42
2.2.2 The role of the substrate - the body effect 44
2.2.3 Temperature effect 44
2.2.4 Breakdown and input protection 44
2.3 MOSFET circuit at DC 45
2.4 MOSFET as an amplifier and as a switch 47
2.4.1 Large signal operation – the transfer characteristics 47
2.4.2 Graphical derivation of the transfer characteristics 48
2.5 Operation as a switch 49
2.6 Operation as a linear amplifier 49
2.7 Biasing in MOS amplifier circuits 50
2.7.1 Biasing by fixing VGS 50
2.7.2 Biasing by fixing VG and connecting a resistance in the 50
source
2.7.3 Biasing using a drain to gate feedback resistor 52
2.7.4 Biasing using constant current source 52
Questions 57
Unit-3 Small signal operations and models 59

3.1 DC bias point 59
3.1.1 The Signal current in the drain terminal 59
3.1.2 The voltage gain 61
3.1.3 Separating the DC analysis and signal analysis 61
3.1.4 Small signal equivalent circuit models 61
3.1.5 The Transconductance 62
3.1.6 The T equivalent circuit model 63
3.2 Common source (CS) amplifier 64
3.2.1 Common source (CS) amplifier with source resistance 66
3.3 Common gate (CG) amplifier 68
3.4 Common drain (CD) amplifier or Source follower 70
3.5 The MOSFET internal capacitances and high frequency model 71
3.5.1 The gate capacitive effect 72
3.5.2 The junction capacitances 73
3.5.3 The high frequency MOSFET model 73
3.5.4 The MOSFET unity gain frequency (fT) 74
3.6 Frequency response of the common source amplifier 76
3.6.1 High frequency response 77
3.6.2 Low frequency response 77
Questions 82
Unit-4 MOS differential amplifier 84

4.1 The MOS differential pair 84
4.1.1 Operation with a common mode input voltage 85
4.1.2 Operation with a differential input voltage 86
4.2 Small signal operation of the MOS differential pair 89
4.2.1 Differential gain 89
4.2.2 Common mode gain and common mode rejection ratio 92
(CMRR)
4.3 Other non ideal characteristics of the differential amplifier 96
4.3.1 Input offset voltage of the MOS differential pair 96
4.3.2 Input common mode range 99
4.4 The differential amplifier with active load 100
4.4.1 Differential to single ended conversion 100
4.4.2 The active loaded MOS differential pair 101
4.4.3 Differential gain of the active loaded MOS differential pair 102
4.4.4 Common mode gain and CMRR 105
Questions 109
Unit-5 Feedback amplifiers and Power amplifiers 111

5.1 The general feedback structure 111
5.2 Properties of negative feedback 112
5.3 Four basic feedback topologies 115
5.4 Series - Shunt feedback amplifier 117
5.5 Series - Series feedback amplifier 119
5.6 Shunt - Series feedback amplifier 119
5.7 Shunt - Shunt feedback amplifier 120
5.8 Classification of output stages 121
5.9 Class - A Output stage 123
5.10 Transformer coupled power amplifier 126
5.11 Class - B Transformer coupled amplifier 128
5.12 Class - B Output stage 129
5.13 Class - AB Output stage 131
Questions 135
3REC01 Analog Electronic Circuits III Semester E&C Engg.
Unit – 1 Applications of Diode
After studying this course the student should be able to

CO 1 : Design clipper, Clamper components to provide solutions for communication
problems, to design rectifier to meet the power supply requirement. (L3).
1.1 Full wave rectifier with capacitor filter

The centre tap full wave rectifier with ‘C’ filter is shown in Fig. 1.1 and the bridge
rectifier with ‘C’ filter is shown in Fig. 1.2.
A X +
+
Vi = Vm Sin t C
-
230 V
50 Hz
AC Supply Y -
Vi = Vm Sin t
Fig. 1.1 Centre tap full wave rectifier with ‘C’ filter
Working
During positive half cycle the diode D1 is forward biased in centre tap full wave
rectifier and diode D1 and D2 are forward biased in bridge rectifier. Hence the capacitor C
will charge from 0 V towards the peak value of input Vm. At , input Vi will be at Vm
and the charge on capacitor will also be equal to Vm, hence the diodes will turn off (since
both anode and cathode of diodes will be at same potential). Now the capacitor starts
discharging through the load RL, if the load is very light (load resistance is very high and load
current is low) the capacitor will discharge by a small amount, by that time next half cycle
charges the capacitor back to Vm. Thus the output voltage remains almost constant. The full
wave rectifier with ‘C’ filter waveform is shown in Fig. 1.3.
K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 1

D4 D1
230V
50 Hz X
Vi = Vm Sin t
AC Supply
D3 D2 C +
-
B
Y
Fig. 1.2 Bridge rectifier with ‘C’ filter
Vi
Vm
0 2 t
Vo with ‘C’
Vo filter
Vm
Vrp-p
VDC Vo without ‘C’ filter
0 2 3 t
Fig. 1.3 Full wave rectifier with ‘C’ filter waveform
1.1.1 Expression for ripple factor

Problems :
P1. Design a bridge rectifier with C filter to have an output dc voltage 12V at load current
100 mA and ripple less than 5%.
Solution :
A
D4 D1
230V
50 Hz X
Vi = Vm Sin t
AC Supply
D3 D2 C +
-
B
Y

P2. In a full wave rectifier if C = 1000 F and RL = 1 K , calculate ripple factor.

Solution :
P3. Calculate the ripple voltage of a full wave rectifier with a 120 F capacitor connected
to a load of 60 mA, frequency of ac source is 50 Hz.
i) If the peak voltage of the rectified wave is 60 V. Calculate the DC voltage at
the output.
ii) If the capacitor value is doubled what will be the modified ripple voltage.
Solution :
i)
ii)
P3. A full wave bridge rectifier with a 120 V rms sinusoidal input has a load resistor of 1
K . Determine the required PIV rating of each diode.
Solution :

P4. A full wave rectifier with C filter is fed by a 50 Hz sinusoidal waveform and delivers
a load current of 100 mA with a peak to peak ripple voltage of 1 V. What is the value
of capacitor used?
Solution :
1.2 Clipping circuits

Clipping circuit is one which eliminates unwanted portion of a signal.
Steps to be followed to analyse clipping circuit

1. Identify the state of each diode.
2. Replace the diode by its appropriate equivalent circuit.
3. Determine the applied that will determine the change of state of diode.
1.2.1 Two level Series clippers

If the clipping element (diode), load and source are in series, the circuit is said to be
series clipper.
1. To pass positive peak above (VR1+V) level and negative peak above -(VR2+V) level
The clipping circuit to pass positive peak above (VR1+V) level and negative peak above
-(VR2+V) level is shown in Fig. 1.4, the waveform and transfer characteristics are shown
in Fig. 1.5.
 , ,

Fig. 1.4 Clipping circuit to pass positive peak above (VR1+V) level and negative peak above
-(VR2+V) level
Vi
VO Slope = 1
(VR1+V) -(VR2+V)
-(VR2+V) t (VR1+V) Vi
Slope = 1
Vo
Fig. 1.5 Waveform and transfer characteristic of clipping circuit to pass positive peak above
(VR1+V) level and negative peak above -(VR2+V) level
i)
ii) 
iii)  
iv) 
v)  
1.2.2 Two level Shunt Clippers

If the clipping element (diode) is connected parallel to the source, the circuit is said to
be series clipper.
2. To pass waveform between (VR1+V) and –(VR2+V) level
The clipping circuit to pass waveform between (VR1+V) and –(VR2+V) level is shown in
Fig. 1.6, the waveform and transfer characteristics are shown in Fig. 1.7.

Fig. 1.6 Clipping circuit to pass between (VR1+V) and –(VR2+V) level
Vi
VO
VR1+V
VR1+V
t
-(VR2+V) -(VR2+V)
VR1+V Vi
Vo
VR1+V -(VR2+V)
Slope = 1
t
-(VR2+V)
Fig. 1.7 Waveform and transfer characteristic of clipping circuit to pass between (VR1+V)
and –(VR2+V) level
i)
ii) 
iii)  
iv) 
v)  
3. To pass portion of positive peak between (VR1-V) and (VR2+V) level

The clipping circuit to pass waveform between (VR1-V) and (VR2+V) level is shown in
Fig. 1.8, the waveform and transfer characteristics are shown in Fig. 1.9.

Fig. 1.8 Clipping circuit to pass waveform between (VR1-V) and (VR2+V)
Vi
VR2+V VO
VR1-V
VR2+V
t
Slope = 1
VR1-V
Vo
VR1-V VR2+V Vi
VR2+V
VR1-V
t
Fig. 1.9 Waveform and transfer characteristic of clipping circuit to pass between (VR1-V)
and (VR2+V) level
i)
ii) 
iii) 
iv)
v)
1.2.3 Design : Selection of resistance R

Consider an example clipping circuit shown in Fig. 1.10
Fig. 1.10 Example clipping circuit

When diode is ON the diode can be replaced by the forward resistance R f as shown in
Fig. 1.11.
Fig. 1.11 Equivalent circuit when diode is ON
When diode is ON, for ideal response entire input voltage Vi should fall across R
without any drop across Rf. This is possible only when
When diode is OFF the diode can be replaced by the reverse resistance R r as shown in
Fig. 1.12.
Fig. 1.12 Equivalent circuit when diode is OFF
When diode is OFF, for ideal response entire input voltage Vi should fall across Rr
without any drop across R. This is possible only when
Substituting for K in equation from equation
Problems :
P1. Design a clipping circuit to obtain the transfer characteristics shown in Fig. P1. Ad
sketch the input output waveform VO
Slope = 1
-2V
3V Vi
Slope = 1
Fig. P1

Solution :
Input / Output waveform

Vi
3V
-2 V t
Vo
P2. The input to a clipping circuit is a sine wave of peak value 25 V. Design the
components values such that the output should have its positive peak clipped at 15 V
and negative peak clipped at -18 V. Sketch the circuit, input/output waveform and
transfer characteristics.

Solution :
Input / output waveform and transfer characteristics
Vi
VO
15 V
15 V
t
-18 V
-18 V
15 V Vi
Vo
15 V -18 V
Slope = 1
t
-18 V
P3. Design a clipper to obtain the transfer characteristics shown in Fig. P3. Sketch the
input / output waveform. (Assume V = 0.7 V)

VO
4V
Slope = 1
3V
3V 4V Vi
Fig. P3
Solution :
Vi
4V
3V
Vo
4V
3V

1.3 Clamping circuits

A clamping circuit is one in which DC signal is added to an AC signal without
changing the shape of the AC signal. There are two types of clampers namely positive
clampers and negative clampers. In positive clampers negative DC voltage will be added to
the AC signal and in negative clampers positive DC voltage will be added.
1.3.1 Negative clampers

1. Positive peak clamped to V level
The clamping circuit to clamp positive peak to V level and the input / output
waveform are shown in Fig. 1.13.
Fig. 1.13 Circuit to clamp positive peak to V level and the input / output waveform
Circuit operation
i) When Vi = + Vm (during positive half cycle), diode D is forward biased and
the capacitor charges as shown in Fig. 1.14.
Fig. 1.14 Equivalent circuit during Vi = + Vm

ii) When Vi = -Vm (during negative half cycle), diode D is reverse biased and
the equivalent circuit is shown in Fig. 1.15.
Fig. 1.15 Equivalent circuit during Vi = - Vm

,
2. Positive peak clamped to positive reference level

The clamping circuit to clamp positive peak to VR + V level and the input / output
Fig. 1.16 Circuit to clamp positive peak to VR + V level and the input / output waveform

Circuit operation
i) When Vi = + Vm (during positive half cycle), diode D is forward biased and the
capacitor charges as shown in Fig. 1.17.
ii) When Vi = -Vm (during negative half cycle), diode D is reverse biased and the
equivalent circuit is shown in Fig. 1.18.

3. Positive peak clamped to negative reference level

The clamping circuit to clamp positive peak to -VR + V level and the input / output
Fig. 1.19 Circuit to clamp positive peak to –VR + V level and the input / output waveform
Circuit operation
i) When Vi = + Vm (during positive half cycle), diode D is forward biased and the

ii) When Vi = -Vm (during negative half cycle), diode D is reverse biased and the
1.3.2 Positive clampers

4. Negative peak clamped to -V level
The clamping circuit to clamp negative peak to -V level and the input / output
Fig. 1.22 Circuit to clamp negative peak to -V level and the input / output waveform

Circuit operation
i) When Vi = - Vm (during negative half cycle), diode D is forward biased and the
ii) When Vi = +Vm (during positive half cycle), diode D is reverse biased and the

5. Negative peak clamped to negative reference level

The clamping circuit to clamp negative peak to -VR-V level and the input / output
Fig. 1.25 Circuit to clamp negative peak to -VR-V level and the input / output waveform
Circuit operation

6. Negative peak clamped to positive reference level

The clamping circuit to clamp negative peak to VR-V level and the input / output
Fig. 1.28 Circuit to clamp negative peak to VR-V level and the input / output waveform

Circuit operation

1.3.3 Design : Selection of R and C

Consider a clamping circuit and input waveform shown in Fig. 1.31.
Fig. 1.31 Example clamping circuit and input waveform

When Vi = -Vm (negative half cycle) diode D is forward biased and the capacitor C
charges to Vm - Vγ. When Vi = +Vm (positive half cycle), the diode D is reverse biased and
for ideal responses of the clamping circuit the capacitor should not discharge through
resistance R
Problems
P1. Design clamping circuit to clamp negative peak to zero level. Assume V = 0.6 V.
Solution :

P2. Design a suitable circuit represented by the box shown in Fig. P2, which has the input
and output waveforms as indicated. (Assume V = 0.6 V)
Vi VO
10 V 2.7 V
Circuit using
silicon t
t diodes
-10 V
-17.3 V
Solution :
 ,

P3. Design a clamping circuit to obtain an output with positive peak at 20 V and negative
peak at –10 V. The input is a square wave of  15 V at 1 KHz. Assume silicon diode.
Solution :
 ,
1.4 Voltage Multipliers

Voltage multipliers will provide output voltage two or three of four times the peak
voltage of the input signal.
1.4.1 Half wave voltage doubler
The circuit of half wave voltage doubler is shown in Fig. 1.32.
Fig. 1.32 Half wave voltage doubler

Circuit operation
During the first negative half cycle diode D1 is forward biased and D2 is reverse
biased. Hence the capacitor C1 charges to Vm (Assuming ideal diode with V = 0) as shown in
Fig. 1.33.
Fig. 1.33 Equivalent circuit during negative half cycle
During the next positive half cycle diode D1 is reverse biased and D2 is forward
biased. Hence the input voltage Vi and the charge present on capacitor C1 together will
charge capacitor C2 to 2Vm, hence VO = 2 Vm as shown in Fig. 1.34. Hence the output voltage
is double of the input voltage.
Fig. 1.34 Equivalent circuit during positive half cycle
1.4.2 Full wave voltage doubler

The full wave voltage doubler circuit is shown in Fig. 1.35.
Fig. 1.35 Full wave voltage doubler

During the positive half cycle diode D1 is forward biased and D2 is reverse biased.
Hence the capacitor C1 charges to Vm (Assuming ideal diode with V = 0) as shown in Fig.
1.36.
Fig. 1.36 Equivalent circuit during positive half cycle
During the negative half cycle diode D1 is reverse biased and D2 is forward biased.
Hence the capacitor C2 charges to Vm (Assuming ideal diode with V = 0) as shown in Fig.
1.37.
Fig. 1.37 Equivalent circuit during negative half cycle
Hence the net output voltage, VO = 2 Vm as shown in Fig. 1.38.
Fig. 1.38 Net output voltage in full wave voltage doubler

1.5 Special diode types

1.5.1 Schottky barrier diode (SBD)
Schottky diode is a metal-semiconductor junction diode that has less forward voltage
drop than the P-N junction diode and can be used in high-speed switching applications.
In a normal p-n junction diode, a p-type semiconductor and an n-type
semiconductor are used to form the p-n junction. When a p-type semiconductor is joined with
an n-type semiconductor, a junction is formed between the P-type and N-type semiconductor.
This junction is known as P-N junction. Whereas in schottky diode, metals such as aluminum
or platinum replace the P-type semiconductor. Schottky diodes are widely used in radio
frequency (RF) applications. The P-N junction and M-S junction are shown in Fig.1.39.
Fig. 1.39 P-N junction and M-S junction

When aluminum or platinum metal is joined with N-type semiconductor, a junction is
formed between the metal and N-type semiconductor. This junction is known as a metal-
semiconductor junction or M-S junction. A metal-semiconductor junction formed between a
metal and n-type semiconductor creates a barrier or depletion layer known as a schottky
barrier. Schottky diode can switch on and off much faster than the p-n junction diode. Also,
the schottky diode produces less unwanted noise than p-n junction diode. These two
characteristics of the schottky diode make it very useful in high-speed switching power
circuits.
A silicon diode has a voltage drop of 0.6 to 0.7 volts, while a schottky diode has a
voltage drop of 0.2 to 0.3 volts. Hence, the schottky diode consumes less voltage to turn on.
The symbol and V-I characteristics of schottky diode is shown in Fig. 1.40.
Fig. 1.40 Symbol and V-I characteristics of schottky diode

Applications of schottky diodes

Schottky diodes are used in
 general-purpose rectifiers
 radio frequency (RF) applications
 power supplies
 detect signals
 logic circuits
1.5.2 Varactors (Voltage variable capacitors)

Varactor diode is a p-n junction diode whose capacitance is varied by varying the
reverse voltage. The term varactor is originated from a variable capacitor which operates only
in reverse bias and acts like a variable capacitor under reverse bias. Varactor diode is also
sometimes referred to as varicap diode.
When a p-type semiconductor is in contact with the n-type semiconductor, a p-n
junction is formed between them. This p-n junction separates the p-type and n-type
semiconductor and a depletion region is created where mobile charge carriers (free electrons
and holes) are not present. The symbol of a varactor diode is shown in Fig. 1.41, which is
almost similar to the normal p-n junction diode.
Fig. 1.41 Symbol of varactor

Two parallel lines at the cathode side represent two conductive plates and the space
between these two parallel lines represents dielectric.
The varactor diode should always be operated in reverse bias, because in reverse bias,
the electric current does not flow. When a forward bias voltage is applied, the electric current
flows through the diode and as a result, the depletion region becomes negligible. When a
reverse bias voltage is applied, the electrons from n-region and holes from p-region move
away from the junction. As a result, the width of depletion region increases and the
capacitance decreases, thus the capacitance can be varied by varying reverse voltage applied.
However, if the applied reverse bias voltage is very low the capacitance will be very large.
Varactor diodes are used in frequency multipliers and in voltage-controlled oscillators.
The capacitance is given by

1.5.3 Photo Diode

A photodiode is a p-n junction or pin semiconductor device that consumes light
energy to generate electric current. It is also sometimes referred as photo-detector, photo-
sensor, or light detector. Photodiodes are specially designed to operate in reverse bias
condition.
Photodiode is very sensitive to light so when light or photons falls on the photodiode
it easily converts light into electric current. Solar cell is also known as large area photodiode
because it converts solar energy or light energy into electric energy. The construction and
working of photodiode is almost similar to the normal p-n junction diode. PIN (p-type,
intrinsic and n-type) structure is mostly used for constructing the photodiode instead of p-n
(p-type and n-type) junction structure because PIN structure provide fast response time. PIN
photodiodes are mostly used in high-speed applications.
The symbol of photodiode shown in Fig. 1.42 is similar to the normal p-n junction
diode except that it contains arrows striking the diode which represent light or photons.
Fig. 1.42 Symbol of photo diode
A normal p-n junction diode allows a small amount of electric current under reverse
bias condition. To increase the electric current under reverse bias condition, we need to
generate more minority carriers. The external reverse voltage applied to the p-n junction
diode will supply energy to the minority carriers but not increase the population of minority
carriers. When external energy (light) is directly applied to the depletion region more charge
carriers are generated in depletion region.
The different materials used to construct photodiodes are Silicon (Si), Germanium,
(Ge), Gallium Phosphide (GaP), Indium Gallium Arsenide (InGaAs), Indium Arsenide
Antimonide (InAsSb), Extended Range Indium Gallium Arsenide (InGaAs), Mercury
Cadmium Telluride (MCT, HgCdTe).

Photodiode applications
 Compact disc players
 Smoke detectors
 Space applications
 Medical applications such as computed tomography, instruments to analyze
samples, and pulse oximeters
 Optical communications
1.5.4 Light emitting diodes (LED)

Light Emitting Diodes (LEDs) are the most widely used semiconductor diodes among
all the different types of semiconductor diodes available today. Light emitting diodes emit
either visible light or invisible infrared light when forward biased. The LEDs which emit
invisible infrared light are used for remote controls. When Light Emitting Diode (LED) is
forward biased, free electrons in the conduction band recombines with the holes in the
valence band and releases energy in the form of light.
The construction of LED is similar to the normal p-n junction diode except that
gallium, phosphorus and arsenic materials are used for construction instead of silicon or
germanium materials. The symbol of LED shown in Fig. 1.43 is similar to the normal p-n
junction diode except that it contains arrows pointing away from the diode indicating that
light is being emitted by the diode.
Fig. 1.43 Symbol of LED
LEDs are available in different colors and they are widely used in display devices

Questions (1 or 2 Marks)
1. In a full wave rectifier if C = 1000 F and RL = 1 K , calculate ripple factor.
2. Draw clamping circuit to clamp positive peak to +3 V (assume ideal diode).
3. Draw full wave voltage doubler circuit.
4. A full wave bridge rectifier with a 120V rms sinusoidal input has a load resistance of
1K . Determine the required PIV rating of each diode.
5. Mention about schottky barrier diode.
6. Discuss the working of voltage doubler.
7. A full wave rectifier with C filter is fed by a 50 Hz sinusoidal waveform and delivers
a load current of 100 mA with a peak to peak ripple voltage of 1 V. What is the value
of capacitor used?
8. Design a clamping circuit to clamp negative peak of a sine wave at +4V. Assume Si
diode.
9. The photo diode is operated under ____________ biased and LED is operated under
________ biased condition.
Questions (Descriptive) / Problems
1. Calculate the ripple voltage of a full wave rectifier with a 120 F capacitor connected
to a load of 60 mA, frequency of ac source is 50 Hz.
i) If the peak voltage of the rectified wave is 60 V. Calculate the DC voltage at
the output.
ii) If the capacitor value is doubled what will be the modified ripple voltage.
2. Design clamping circuit to clamp negative peak to zero level. (Assume V = 0.6 V).
3. With the help of circuit diagram and waveform, explain the working of full wave
rectifier with ‘C’ filter. Derive the expression for ripple factor.
4. Design a suitable circuit represented by the box shown in Fig. P2, which has the input
and output waveforms as indicated. (Assume V = 0.6 V)
Vi VO
10 V 2.7 V
Circuit using
silicon t
t diodes
-10 V
-17.3 V
5. Design a clamping circuit to obtain an output with positive peak at 20 V and negative
peak at –10 V. The input is a square wave of  15 V at 1 KHz. Assume silicon diode.

6. The input to a clipping circuit is a sine wave of peak value 25 V. Design the
7. Write short notes on SBD and varactor diodes.
8. Design a clipper circuit which limits the input ssignal Vi = 10 Sin t between +5V
and -3V. (Assume V = 0.7 V).
9. Design a clamper circuit which clamps positive peak of a input signal at -2 V. Input
signal is square wave with amplitude  5 V and frequency 1 KHz.
10. With the help of a neat circuit diagram, explain the working of a voltage doubler.
11. What is a light emitting diode? Explain its working and mention any one application
of it.
12. Design a clipping circuit to obtain the transfer characteristics shown in Fig. P1. Ad
sketch the input output waveform VO
Slope = 1
-2V
3V Vi
Slope = 1
Fig. P1
13. The input to a clipping circuit is a sine wave of peak value 25 V. Design the
14. Design a clipper to obtain the transfer characteristics shown in Fig. P3. Sketch the
input / output waveform. (Assume V = 0.7 V)
VO
4V
Slope = 1
3V
3V 4V Vi

Unit – 2 MOS Field Effect Transistor

CO 2 : Analyze characteristics of MOSFET to design biasing circuit for Amplifiers. (L3)
In this chapter one of the very important three terminal semiconductor device Metal
Oxide Semiconductor Field Effect Transistor (MOSFET) will be discussed. MOSFET is most
commonly used in the design of integrated circuits (ICs) both in analog and digital circuits.
MOSFET is a voltage controlled, unipolar device which can be used as switch and
amplifier. The classification of MOSFETs can be done as
MOSFET
Depletion MOSFET Enhancement MOSFET
N – Channel P – Channel N – Channel P – Channel

MOSFET MOSFET MOSFET MOSFET
2.1 Device structure and physical operation

The physical structure of the n-channel enhancement MOSFET is shown in Fig. 2.1.
SiO2 (Insulator) S G D Poly silicon / metal

thickness (tox) (Source) (Gate) (Drain)
n+ n+
p – Substrate
B
(a)
(Substrate / Bulk)
Fig. 2.1 Cross sectional view of n-channel enhancement MOSFET

The MOSFET is fabricated on a p-type substrate which is a single crystal silicon

wafer that provides physical support for the device. Two heavily doped n-type regions
indicated in the figure as n+ source and n+ drain regions are created in the substrate. A thin
layer of SiO2 of thickness (tox) which is an excellent electrical insulator is grown on the
surface of the substrate covering the area between the source and drain regions. Metal /
polysilicon is deposited on top of the oxide layer to form the gate electrode of the device.
Metal contacts are made to the source region, drain region and the substrate also known as
the body, thus four terminals are brought out the gate terminal (G), source terminal (S), drain
terminal (D) and the substrate or body (B).
The substrate forms pn-junction with the source and drain regions. In normal
operation these junctions are kept reverse biased which can be achieved by connecting the
substrate terminal to the source terminal, hence the MOSFET has only there terminal G, D
and S. For the normal operation of n-channel enhancement MOSFET, the drain and gate
terminals will be connected to positive terminal of the battery with respect to source.
2.1.1 Operation with no gate voltage

With no bias voltage applied to the gate two back to back diodes exist in series
between drain and source, one formed between n+ drain and p-substrate and the other formed
between n+ source and p-substrate. These back to back diodes prevent flow of current
between drain and source when a voltage VDS is applied. When VDS is applied between drain
and source, the drain to substrate P-N junction will be reverse biased and the depletion layer
around drain region will be enlarged as shown in Fig. 2.2, hence there will be no flow of
current.
VDS
S G D
Enlarged
n+ n+ depletion layer
p – Substrate
Fig. 2.2 When VGS = 0 and VDS is applied

2.1.2 Creating a channel for conduction

With the application of positive voltage to gate with respect to source (VGS) causes
the holes present in substrate to be repelled from the region under the gate. These holes are
pushed downward into the substrate leaving behind a carrier depletion region which is
populated by the bound negative charge associated with the acceptor atoms. The positive gate
voltage attracts electrons from the n+ source and drain regions in to the channel region. When
sufficient number of electrons accumulates near the surface of the substrate under the gate
region the source and drain will be connected as shown in Fig. 2.3. The value of VGS at
which a conducting channel is formed is called threshold voltage (Vt), for NMOSFET Vt is
positive.
VGS
S G D
Depletion layer
n+ n+
L
Induced n-type
p – Substrate channel
Fig. 2.3 Channel formation when VDS = 0 and VGS > Vt is applied
After the channel is induced with the application of VGS > Vt, if a voltage is applied
between drain and source (VDS) current flows through the channel induced, correspondingly
this MOSFET is called an n-channel MOSFET (NMOS). NMOS is created on p-substrate and
the channel is created by inverting the substrate surface from p to n-type hence the channel is
called inversion layer.
The gate and the channel region form a parallel plate capacitor with the oxide layer
acting as insulator (dielectric). The positive gate voltage causes positive charge to accumulate
on top plate (gate) and the negative charge on the bottom plate. An electric field is developed
in the vertical direction which controls the amount of charge in the channel which determines
the channel conductivity in turn the current that flow through the channel when VDS is
applied.

2.1.3 Applying a small VDS

Having induced a channel if a small VDS is applied a current ID flows in the induced
channel as shown in Fig. 2.4. The magnitude of current depends on amount of electrons in the
channel in turn depends on VGS. When VGS = Vt the channel is just formed and current
conduction is negligibly small. When VGS > Vt more electrons are attracted in to the channel
hence conductivity increases. The conduction of the channel is proportional to the excess gate
voltage (VGS – Vt) also known as effective voltage or overdrive voltage. Hence
and
VDS
VGS > Vt
S G D
n+ n+
ID
p – Substrate
Fig. 2.4 Flow of ID when small VDS and VGS > Vt are applied
For small values of VDS that is the channel is continuous and

MOSFET behaves as a linear resistor hence the drain current, ID is linearly proportional to
VDS as shown in Fig. 2.5.
ID
VGS3
VGS2
VGS1 > Vt
VDS
Fig. 2.5 Linear drain current, ID at small value of VDS

2..1.4 Operation as VDS is increased

Let VGS > Vt and is constant, the VDS appears as a voltage drop across the length of
the channel. As we travel from source to drain along the channel the voltage increases from 0
to VDS. Thus the voltage between the gate and points along the channel decreases from VGS at
the source end to VGS – VDS at the drain end. Since the channel depth depends on this
voltage, channel is no longer uniform, rather channel will take tapered form as shown
in Fig. 2.6.
VDS
VGS > Vt
S G D
n+ n+
Tapered channel
p – Substrate
Fig. 2.6 Tapered channel when VDS and VGS > Vt are applied
As VDS is increased channel becomes more tapered and its resistance increases
correspondingly, thus the ID - VDS curve does not continue as a straight line but bends as
shown in Fig. 2.7.
Saturation
ID VDS = VDS sat
region
Curve bends because of
increase in channel VDS > VGS - Vt
VGS > Vt
resistance
(Linear) Curve saturates because
the channel is pinched
off
VDS sat = VGS - Vt VDS

Fig. 2.7 Drain characteristics of enhancement NMOSFET

When VDS is increased such that VDS = VGS - Vt, the channel is said to be pinched off.
Increasing VDS beyond this value has little effect on channel shape and current saturates,
hence MOSFET will enter saturation region as shown in Fig. 2.8. The voltage at which
saturation occurs is denoted as
VDS > VGS - Vt VDS = VGS - Vt
n+ n+
Channel
Source Drain
VDS VDS < VGS - Vt

VDS = 0
Fig. 2.8 Variation in channel with respect to VDS when VGS > Vt
2.1.5 Expression for drain current

2.1.6 Circuit symbol

The circuit symbol of n-channel enhancement MOSFET is shown in Fig. 2.9
D D D D
G B G B G G
S S S S
G  Gate
Simplified symbol when source is
D  Drain connected to the body (bulk)
S  Source
B  Body or Bulk
Fig. 2.9 Different symbols of enhancement NMOSFET
 The spacing between the two vertical lines represent the gate electrode insulated from
the body of the device
 The drain is always positive with respect to source in an n-channel MOSFET
Even though the drain and source are clearly distinguished, in practice the polarity of
the voltage impressed across it determines source and drain
2.2 The ID – VDS characteristics / Output characteristics / Drain characteristics

The circuit diagram of MOSFET to plot ID – VDS characteristics and the ID – VDS
characteristics are shown in Fig. 2.10.
ID
+ RD
IG = 0
VDS VDD
+
VGG VGS
- -
(a)

VDS = VDS sat = VGS - Vt

VGS4 > VGS3 > VGS2 > VGS1
ID Saturation region
VDS > VGS - Vt
Triode / Ohmic / VGS4
Linear region
VDS = VGS - Vt VGS3
VDS < VGS - Vt
VGS2
VGS1 > Vt
VDS  VGS - Vt (Cut off) VDS

(b)
Fig. 2.10 (a) Circuit to plot ID - VDS characteristics (b) ID - VDS characteristics of NMOSFET
The characteristic curve indicates that there are three distinct regions of operation
namely the cut off region, the triode / ohmic / linear region and the saturation region.
The saturation region is used to operate MOSFET as an amplifier. The cut off and
triode / ohmic / linear region are used to operate MOSFET as switch (Open switch in cutoff
region and closed switch in triode / ohmic / linear region).
To operate MOSFET in cut off region VGS < Vt and to operate in triode / ohmic /
linear region, first the channel must be induced by applying VGS > Vt and then VDS should be
maintained small, that is VDS < VGS - Vt.
In triode region the ID - VDS characteristics can be described as

To operate MOSFET in saturation region, first the channel must be induced by

applying VGS > Vt and then VDS should be high, that is VDS > VGS - Vt (channel pinched off).
The boundary between the triode / linear / ohmic region and saturation region is
characterized by VDS = VGS - Vt (Boundary).
The saturation value of the current ID is
Thus in saturation drain current is independent of VDS and is determined by the gate
voltage VGS, hence the saturated MOSFET behaves as an ideal current source whose value is
controlled by VGS. The transfer characteristic of MOSFET (ID versus VGS) is shown in Fig.
2.11.
ID
VDS > VGS - Vt
Vt VGS
Fig. 2.11 Transfer characteristics of NMOSFET
The circuit representation of MOSFET in saturation region is shown in Fig. 2.12 and
is called as large signal equivalent circuit model
Fig. 2.12 Large signal equivalent model of NMOSFET
In boundary between triode and saturation region, where VDS = VGS – Vt, the drain
current,

2.2.1 Finite output resistance

In previous section it is learnt that in saturation ID is independent of VDS. Thus a
change in VDS causes a zero change in ID which implies that the incremental resistance
looking into the drain of a saturated MOSFET is infinite. This is an ideal case based on the
premise that once the channel is pinched off at the drain end, further increase in VDS has no
effect on the channel’s shape. But practically it affects the channel where the pinch of point
moves slightly away from the drain towards source which is illustrated in Fig. 2.13.
n+ n+
Channel
Source Drain
- VD Sat = VGS - Vt +- + VDS – VD Sat
L
L - L L
Fig. 2.13 Variation in channel length in saturation region
The voltage across the channel remains constant at (VGS - Vt) = VD Sat and the
additional voltage applied to the drain appears as a voltage drop across the narrow depletion
region between the drain and the end of the channel. This voltage accelerates the electrons
that reach the drain end of the channel and sweeps them across the depletion region into the
drain.
This concept of channel length reduced from L to L - L is known as channel length
modulation. Since ID is inversely proportional to L, ID increases with VDS.
Considering the channel length modulation

The ID - VDS characteristics showing the channel length modulation effect is shown in
Fig. 2.14.
Triode / Ohmic / ID Saturation region

Linear region
VGS4
Slope =
VGS3
VGS2
VGS1 > Vt
-VA = - VDS
Fig. 2.14 ID - VDS characteristics showing the channel length modulation effect
From the figure ID = 0 at VDS = which follows VA =
From the equation it is clear that when channel
length modulation is taken into account ID depends on VDS.

Hence the output resistance
This term is
independent of VDS
By incorporating rO the large signal model can be written as shown in Fig. 2.15.
Fig. 2.15 Large signal model of NMOSFET incorporating rO

2.2.2 The role of the substrate – the body effect

In many applications the source terminal connected to the substrate (body) terminal B,
which results in the pn-junction between the substrate and the induced channel having a
constant zero bias. In such case the substrate does not play any role in circuit operation and
its existence can be ignored.
In ICs the substrate is usually common to many MOS transistors. In order to maintain
the cutoff condition for all the substrate to channel junctions, the substrate is usually
connected to the most negative power supply in an NMOS circuit. (Most positive supply in
PMOS circuit)
The resulting reverse bias voltage between source and body (VSB in an n-channel
device) will have an effect on device operation.
The increase in VSB results in an increase in Vt accordingly to the relationship.
This effect of VSB on Vt and in turn on ID is called as body effect
2.2.3 Temperature effect

Both Vt and K’ are temperature sensitive, Vt decreases by 2 mV for every 1C rise in
temperature. K’ decreases with temperature and is dominant, hence increase in temperature
decreases drain current ID
2.2.4 Breakdown and input protection

As the voltage on the drain is increased and a value is reached at which the pn-
junction between the drain region and substrate suffers avalanche breakdown.
Another breakdown effect that occurs at lower voltage (20V) in modern devices is
called punch through. It occurs in devices with relatively short channels when the drain
voltage is increased to the point that the depletion region surrounding the drain region

extends through the channel to the source. The drain current then increases rapidly (It is not
permanent damage).
Another kind of breakdown occurs when the gate to source voltage exceeds (30 V).
This is the breakdown of the gate oxide and results in permanent damage to the device. To
prevent this usually gate protection devices (clamping diodes) are used at the input terminals
of MOSFET.
2.3 MOSFET circuits at DC

P1. Design the circuit shown in Fig. P1 so that the transistor operates at ID = 0.4mA and
VD = 0.5V. The NMOS transistor has Vt = 0.7 V, n Cox = 100A / V2, L = 1m, W =
32 m. Assume = 0 (neglect channel length modulation).
2.5 V
ID RD
VD
RS
-2.5 V
Fig. P1
Solution :

P2. Design the circuit shown in Fig. P2 to obtain ID = 80A. Find the value of R and VD.
Let NMOS have Vt = 0.6, n Cox = 200A / V2, L = 0.8 m and W = 4 m. Assume
= 0. 3V
VD
Fig. P2
Solution :
P3. Design the circuit shown in Fig. P3 to establish a drain voltage of 0.1 V. What is the
effective resistance between D and S at this operating voltage? Let V t = 1V and
5V
RD
0.1 V
Fig. P3

Solution :
2.4 MOSFET as an amplifier and as a switch

When MOSFET is operated in the saturation region the MOSFET acts as a voltage
controlled current source (that is iD  Vgs), thus the saturated MOSFET can be used to
implement a Transconductance amplifier. But we are interested in a linear amplification
means the output signal iD linearly dependent on input voltage Vgs, hence we need a way to
achieve this since ID relationship is highly non linear (square law) to Vgs.
The technique used here to obtain linear amplification from a fundamentally non
linear device is that of DC biasing the MOSFET to operate at certain V GS at a corresponding
ID and then superimposing the voltage signal to be amplified by keeping the applied signal vgs
small, the resulting change in drain current can be made linear with respect to vgs.
2.4.1 Large signal operation – The transfer characteristics

The basic structure of the most commonly used common source MOSFET amplifier is
shown in Fig. 2.16.
Fig. 2.16 Basic structure of common source MOSFET amplifier
From the circuit we can write that in this way

Transconductance amplifier can be converted into voltage amplifier.

2.4.2 Graphical derivation of the transfer characteristics

The ID - VDS characteristics with DC load line drawn is shown in Fig. 2.17 and
transfer characteristics showing operation as amplifier biased at point Q is shown in Fig.
2.18.
To draw the DC load line consider the expression for VO
iD Saturation region
Triode / Ohmic /
Linear region
VGS4
C VGS3
B
Q VGS2
VGS1 > Vt
A
VDS = VO
Fig. 2.17 ID - VDS characteristics with DC load line drawn
Fig. 2.18 Transfer characteristics showing operation as amplifier biased at point Q

From the transfer characteristics when Vi < Vt, MOSFET will be cutoff and iD = 0
hence VO = VDD point ‘A’ in transfer curve.
As Vi increases beyond Vt, the transistor turns on, iD increases and VO decreases.
Since VO will be initially high transistor will be operating in the saturation region. This
corresponds to segment of the load line from A to B and the point identified in this region of
operation is labeled as Q – operating point.
Saturation region operation continues until VO decreases to the point that it is below
Vi by Vt. At this point VDS = VGS – Vt and the device enters triode region, indicated as point
‘B’. For Vi > ViB, the transistor is driven more deeper into the triode region.
At Point ‘C’ when Vi = VDD, output voltage VOC will be very small.
2.5 Operation as a switch

When the MOSFET is used as a switch, it is operated at the extreme points of the
transfer curve.
The device is turned off by keeping Vi < Vt with VO = VDD, then MOSFET behaves as
open switch.
The device is operated by applying Vi = VDD, with VO very small, then MOSFET
behaves as closed switch.
2.6 Operation as a linear amplifier

To operate MOSFET as an amplifier, the device will be driven in saturation region.
The device will be biased at point Q selected in the middle of curve (to have maximum swing
in output signal). The voltage signal to be amplified is now super imposed on the DC voltage
and input is kept sufficiently small so that operation of the device is very much linear.
The voltage gain of the amplifier,
If the operating point Q selected is close to VDD, the positive signal of output will be
clipped off, since device enters triode region. If Q point is selected close to 0the negative
signal of output will be clipped since device enters in to cutoff region. Hence the Q point
should be selected in middle of the graph.

2.7 Biasing in MOS amplifier circuits

In a MOSFET amplifier the establishment of an appropriate DC operating point for
the transistor is known as biasing. An appropriate DC operating point or bias point is
characterized by a stable and predictable DC drain current ID and by a DC drain to source
voltage VDS that ensures operation in the saturation region for all expected input signal levels.
2.7.1 Biasing by fixing VGS

The most straight forward approach to biasing a MOSFET is to fix its gate to source
voltage VGS to the value required to provide the desired ID. This voltage value can be derived
from the power supply voltage VDD using appropriate voltage divider network or by using
another voltage source. But this method of biasing is not a good approach because
The values of Vt, Cox and vary among devices manufactured by same manufacturers.
Further Vt and n depend on temperature, hence if we fix VGS, ID will not be constant. ID
becomes very much temperature dependent.
2.7.2 Biasing by fixing VG and connecting a resistance in the source

The circuit diagram of biasing by fixing VG and connecting a resistance in the source
is shown in Fig. 2.19 which is an excellent biasing circuit.
Fig. 2.19 Biasing by fixing VG and connecting a resistance in the source
If VG is much greater than VGS, ID will be mostly determined by the values of VG and
RS.

Even if VG is not larger than VGS, RS provides negative feedback which stabilize the
bias current ID which is shown in Fig. 2.20.
ID ID VGS
VS
Fig. 2.20 Negative feedback to stabilize ID
For any reason of ID decreases, VS = ID RS increases, hence VGS = VG – VS decreases,

hence ID decreases which means ID is constant.
RS is named as degeneration resistance. The effectiveness of this biasing scheme is
illustrated in Fig. 2.21.
Fig. 2.21 Effect of RS on stability of Q point
Two possible practical implementations of this biasing circuit are shown in Fig. 2.22.
Fig. 2.22 Practical implementations of biasing by fixing VG and connecting a resistance in

the source

2.7.3 Biasing using a drain to gate feedback resistor

The biasing method of using drain to source feedback resistor is shown in Fig. 2.23.
Fig. 2.23 Biasing using drain to source feedback resistor
From equation if ID tries to increase, VGS has to decrease since VDD is constant,
hence ID remains constant
2.7.4 Biasing using constant current source

The most effective scheme of biasing a MOSFET amplifier is by using constant
current source since the operating point is very much stable. The MOSFET biased with
constant current source and current mirror circuit to produce constant current source for
biasing are shown in Fig. 2.24.
(a)
(b)
Fig. 2.24 (a) MOSFET biased with constant current source (b) Current Mirror

In the current mirror circuit, the drain of transistor Q1 is shorted to the gate and thus
operating in the saturation region, hence
Now consider transistor Q2, it has the same VGS as Q1 hence it is assumed that Q2 is
also operating in saturation region. The drain current, ID2 of Q2 which is the desired current
‘I’ of the current source will be
Problems :
P1. Design a MOSFET biasing circuit by fixing VG and connecting a resistance in the
source to establish a DC drain current ID = 0.5 mA. The MOSFET has Vt = 1V,
. Assume  = 0 and VDD = 15 V.
Solution :

P2. Design the circuit shown in Fig. P2 to operate at a DC drain current of 0.5 mA and VD
= 2V. Let Vt = 1V, , = 0 and VDD = VSS = 5V.
Fig. P2
Solution :

P3. Design the circuit shown in Fig. P3 to operate at a DC drain current of 0.5 mA and
VDD = 5V. Let Vt = 1V, , = 0.
Fig. P3
Solution :

P4. Design a current mirror circuit to bias a MOSFET amplifier at a constant current of
1mA. Let VDD = VSS = 5V, Vt = 1V, , = 0.
Solution :

1. What should be the condition of VGS and VDS in triode region?
2. In which region the MOSFET is operated as open and closed switch.
3. Draw the small signal equivalent circuit model of the N channel MOSFET and write
the expression for rO.
4. A large feedback resistance is connected from drain to gate in a MOSFET. What is
the DC voltage at the gate.
5. What is the effect of temperature on MOSFET performance?
6. Discuss the effect of temperature on drain current in NMOSFET.
7. A n-channel MOSFET has , and overdrive voltage of 0.5V. Find
the on state resistance of the device in triode region.

8. An NMOSFET operates in _______ region if VDS < (VGS – Vt) and in _______ region
when VDS > (VGS – Vt)
10. Draw a current mirror circuit.
11. In a MOSFET, , ID = 100A in saturation and Vt = 0.7V.
Compute the gate to source voltage, VGS.

1. Using transfer characteristics explain the working of MOSFET as an amplifier and
switch.
2. Design the biasing circuit using a drain to gate feedback resistor to operate at a DC
drain current of 0.5 mA. Assuming VDD = 5V, Kn’ W/L = 1mA /V2, Vt =1V and = 0.
3. Draw drain characteristics of n channel enhancement MOSFET and explain its
different regions of operation using relevant voltages and drain current expressions.
4. Explain briefly with neat diagram the operation of enhancement type MOSFET with
its drain characteristics.
5. Using basic structure of common source amplifier, discuss the transfer characteristics
of the amplifier.
6. With neat circuit diagram and relevant expression explain constant current source
biasing of MOSFET (using current mirror)
7. Draw the basic structure of the common source amplifier and explain the large signal
operation using the transfer characteristics. Clearly show the different regions of
operation along with input and output waveforms.

8. Design the circuit shown in Fig. 8.a so that the transistor operates at ID = 0.4mA and
VD = 0.5V. The NMOS transistor has Vt = 0.7 V, n Cox = 100A / V2, L = 1m, W =
32 m. Assume = 0 (neglect channel length modulation).
2.5 V
ID RD
VD
RS
-2.5 V
Fig. 8.a
9. Design a MOSFET biasing circuit by fixing VG and connecting a resistance in the
source to establish a DC drain current ID = 0.5 mA. The MOSFET has Vt = 1V,
, = 0 and VDD = 15 V. (Assume equal voltages across RD and RS)
10. Design the circuit shown in Fig. 10.a to obtain ID = 80A. Find the value of R and VD.
Let NMOS have Vt = 0.6, n Cox = 200A / V2, L = 0.8 m and W = 4 m. Assume
= 0. 3V
R
VD
Fig. 10.a
11. Design the circuit shown in Fig. P3 to establish a drain voltage of 0.1 V. What is the
effective resistance between D and S at this operating voltage? Let V t = 1V and
5V
RD
0.1 V
Fig. P3

Unit – 3 Small Signal Operation and Models

CO 3 : Analyze characteristics of MOSFET amplifiers using small signal model at low and
high frequencies. (L2)
In the previous chapter it is discussed that linear amplification can be obtained by

biasing the MOSFET to operate in the saturation region and by keeping the input signal
amplitude small. In this chapter the small signal operation of MOSFET is discussed in detail.
Consider a conceptual common source amplifier circuit shown in Fig. 3.1 where the DC and
input ac signal to be amplified is applied.
VDD
RD
Fig. 3.1 Conceptual common source amplifier
3.1 DC Bias point

The DC bias current can be obtained by setting
neglecting channel length modulation ( =0)
DC voltage at the drain,

To ensure saturation region operation,
Since the total voltage at the drain will have a signal component super imposed on
should be sufficiently greater than to allow for the required signal
swing

3.1.1 The signal current in the drain terminal

Consider the situation with the input signal applied. The total instantaneous gate
to source voltage will be resulting in a total drain current
DC bias current Current component directly Current proportional

proportional to to square of
The first term in the equation is DC bias current, the second term is directly
proportional to the applied input signal and the third term in the equation is
undesirable since it is non linear distortion. To reduce this non linear distortion the input
signal should be kept small so that
If this small signal condition is satisfied then the non linear distortion can be
neglected and can be expressed as

3.1.2 The voltage gain

Referring to the Fig. 3.1
Under the small signal condition it can be written as
Thus the signal component of the drain voltage is
Negative sign indicates 180 out of phase of output signal with input signal
The total instantaneous voltages and are shown in Fig. 3.2.
Fig. 3.2 Total instantaneous voltages and
3.1.3 Separating the DC analysis and signal analysis

So far the discussion is done with both AC and DC signals together, if they are
separated the analysis can be greatly simplified. That is after a stable DC operating point is
established, the signal analysis can be done by ignoring DC quantities.
3.1.4 Small signal equivalent circuit models

From the signal point of view, the MOSFET behaves as a voltage controlled current
source. It accepts a signal between gate and source and provides a current at the

drain. The input resistance is very high, ideally infinity and output resistance seen from drain
terminal is , putting all together we arrive at the small signal model or small signal
equivalent circuit of the MOSFET as shown in Fig. 3.3.
Fig. 3.3 Small signal model of MOSFET
The equivalent circuit drawn by replacing the MOSFET by its small signal model is
shown in Fig.3.4.
VDD
RD
Fig. 3.4 Equivalent circuit drawn by replacing MOSFET by its small signal model
3.1.5 The Transconductance

3.1.6 The T equivalent circuit model

Through a simple circuit transformation it is possible to develop an alternative
equivalent circuit model for the MOSFET. The development of such model is known as
T – Model shown in Fig. 3.5.
Fig. 3.5 Development of T – Model

The final T – Model is shown in Fig. 3.6
Fig. 3.6 Final T – Model of MOSFET
3.2 Common source (CS) amplifier

The common source amplifier biased using constant current source in which the input
signal is applied to gate and output is observed at drain terminal is shown in Fig. 3.7. The
source terminal is held common with respect to input and output.
Fig. 3.7 Common source amplifier biased with constant current source

The equivalent circuit of the amplifier by replacing the MOSFET by its equivalent
small signal model and transferring all components from circuit on to the equivalent circuit is
shown in Fig. 3.8. All capacitors have to be replaced by short circuit, voltage sources to be
replaced by short circuit and current sources should be replaced by open circuit.
Fig. 3.8 Equivalent circuit of common source amplifier replacing the MOSFET by its
equivalent small signal model

3.2.1 Common source (CS) amplifier with source resistance

The common source amplifier with a source resistance biased using constant current
source is shown in Fig. 3.9. The insertion of source resistance is sometimes beneficial in
having stability of the operating point.
Fig. 3.9 Common source amplifier with source resistance
The equivalent circuit of the amplifier by replacing the MOSFET by its equivalent
small signal T - model (Since the source is not directly connected to ground) and transferring
all components from circuit on to the equivalent circuit is shown in Fig. 3.10.

Fig. 3.10 Equivalent circuit of common source amplifier with source resistance
replacing the MOSFET by its equivalent small signal T – model

3.3 Common gate (CG) amplifier

The common gate amplifier biased using constant current source in which the input
signal is applied to source and output is observed at drain terminal is shown in Fig. 3.11. The
gate terminal is held common with respect to input and output.
Fig. 3.11 Common gate amplifier
The equivalent circuit of the CG amplifier by replacing the MOSFET by its

equivalent small signal T - model (Since the source is not directly connected to ground) and
transferring all components from circuit on to the equivalent circuit is shown in Fig. 3.12.

Fig. 3.12 Equivalent circuit of CG amplifier replacing MOSFET by its equivalent

small signal T – model
Note :
 Common gate amplifier is a non inverting amplifier, that is output signal will be in
phase with the input signal
 Common gate amplifier has low input resistance hence the circuit is
more suitable to feed signal current source

The common gate amplifier with signal current source as input is shown in Fig. 3.13
Fig. 3.13 Common gate amplifier with signal current source as input
3.4 Common drain (CD) amplifier Or Source follower

The common drain amplifier biased using constant current source in which the input
signal is applied to gate and output is observed at source terminal is shown in Fig. 3.14. The
drain terminal is held common with respect to input and output.
Fig. 3.14 Common drain amplifier

The equivalent circuit of the CD amplifier by replacing the MOSFET by its

equivalent small signal T - model and transferring all components from circuit on to the
Fig. 3.15 Equivalent circuit of CD amplifier replacing MOSFET by its equivalent

small signal T – model
3.5 The MOSFET internal capacitances and high frequency model

The MOSFET has many internal capacitances which are not considered in the small
signal model of MOSFET discussed in previous sections. Hence the gain of the amplifier is
assumed to be constant irrespective of input signal frequency, but in reality the gain is
affected by these internal capacitances.
There are basically two types of internal capacitances are there in MOSFET.

1. Gate capacitance : Since the gate material is separated by the channel by an insulator
(SiO2) it forms a parallel plate capacitor called oxide capacitor (Cox)
2. The source – body and drain – body depletion layer capacitances : These are the
capacitances formed by reverse biased pn - junctions of N+ source and P substrate and
N+ drain and P substrate.
These two capacitive effects can be modeled by including capacitances in the
MOSFET model between its four terminals G, D, S and B (bulk). There will be five
capacitances in total Cgs, Cgd, Cgb, Csb and Cdb.
3.5.1 The gate capacitive effect

The gate capacitances can be modeled by the three capacitances Cgs, Cgd and Cgb.
1. When MOSFET is operating in triode region at small VDS the channel will be
uniform. The gate channel capacitance will be WLCox and can be modeled by
dividing equally between source and drain. G
S D
Cgs Cgd
2. When MOSFET operates in saturation region the channel tapered and pinched off
near drain end hence G
S Cgs D
Cgd = 0
3. When MOSFET operates in cutoff region, since there is no channel
4. Additional small capacitance component that should be added to Cgs and Cgd in all the
preceding formulas is the capacitance that that result due to source and drain
diffusions extended slightly under the gate oxide. If the overlap length is LOV then the
overlap capacitance is given by G
S LOV D

3.5.2 The junction capacitances

The depletion layer capacitances of the two reverse biased pn – junctions formed
between each of the source and the drain diffusions and the body can be determined using the
formulas.
The source body capacitance Csb is given by
Similarly the drain body capacitance Cdb is given by
3.5.3 The high frequency MOSFET model

The small signal model of the MOSFET including the internal capacitances which can
be used to analyse the high frequency response of MOSFET amplifier is shown in Fig. 3.16.
Fig. 3.16 High frequency equivalent circuit of MOSFET

When the source is connected to the bulk (body) the model simplifies as shown in Fig. 3.17.
Fig. 3.17 High frequency equivalent circuit of MOSFET when body connected to source
When Cdb is neglected the model simplifies as shown in Fig. 3.18.
Fig. 3.18 High frequency equivalent circuit of MOSFET when body connected to source and
Cdb is neglected
3.5.4 The MOSFET unity gain frequency (fT)

The figure of merit for the high frequency operation of the MOSFET as an amplifier
is the unity gain frequency (fT). This is defined as the frequency at which the short circuit
current gain of the con source configuration becomes unity. The circuit shown in Fig. 3.19 is
to determine the short circuit current gain Io / Ii.
Fig. 3.19 Circuit to determine the short circuit current gain Io / Ii

Note :

3.6 Frequency response of the common source amplifier

In this section the dependence of the gain of the common source amplifier on
frequency of the input signal is discussed. So far while calculating gain it is assumed that the
coupling capacitors, CC1 and CC2 and source bypass capacitor Cs will act as perfect short
circuit at all frequencies. Also the internal capacitances Cgs and Cgd were neglected since their
values are sufficiently small and act as open circuit for all frequencies. The common source
amplifier and the frequency response of the amplifier are shown in Fig. 3.20 and Fig. 3.21
respectively.
Fig. 3.20 Common source amplifier
Midband
All capacitances can be neglected
Low High
frequency frequency
band band
Gain falls off due to the Gain falls off due to

effect CC1, CC2 and Cs the effect Cgs and Cgd
Fig. 3.21 Frequency response of the amplifier

 The gain falls off in the low frequency band due to higher impedance of coupling
capacitors CC1 and CC2 and by pass capacitor Cs
 The gain falls off in the high frequency band due to lower impedance of junction
capacitors (internal capacitors) Cgs and Cgd
 The 3 dB bandwidth of amplifier,
 The midband gain,
 The figure of merit of the amplifier is gain bandwidth product,
3.6.1 High frequency response

The high frequency response of the amplifier is shown in Fig. 3.22
Fig. 3.22 High frequency response of the amplifier
3.6.2 Low frequency response

The low frequency response of the amplifier is shown in Fig. 3.23
Fig. 3.23 Low frequency response of the amplifier

Due to the effect of coupling capacitor CC1 the off frequency
Due to the effect of source by pass capacitor Cs the off frequency
Due to the effect of coupling capacitor CC2 the off frequency
Since is higher than and ,
Problems :
P1. For the common source amplifier shown in Fig. P1, if Rsig = 1K , RG = 4.7M ,
RD = 10K , I = 0.5 mA, CS = 50F, CC1 = CC2 = 0.1 F, RL = 15K , VDD = 15V and
VSS = -10V, find Rin, Rout, AV, AVO and GV. Given VA = 50V, and
= 0.
Fig. P1
Solution :
Replacing MOSFET by its appropriate model and drawing the equivalent circuit

P2. In a common gate amplifier if Rsig = 1K , RD = 10K , I = 0.5 mA, CC1 = CC2 = 0.1
F, RL = 100 K , VDD = 15V and VSS = -10V, find Rin, Rout, AV, AVO and GV. Given
and = 0. Draw the circuit diagram and equivalent circuit
replacing MOSFET by its appropriate model.

Solution :

Replacing MOSFET by its appropriate model and drawing the equivalent circuit
P3. In a common source MOSFET amplifier if Rsig = 1K , RG = 4.7 M , Cgs = 1pF, Cgd
= 0.4 pF, RL = 15 K , RD = 10 K , ID = 0.5 mA, and = 0, VA =
50V, calculate 3 dB upper frequency fH.
Solution :

P4. Calculate unity gain frequency (fT) for an n - channel MOSFET, given Cgs = 30 fF,

Cgd = 2 fF, and ID = 0.5 mA.
Solution :
P5. Find midband gain AM and the upper 3 dB frequency fH of a common source amplifier
fed with a signal source having an internal resistance Rsig = 100 K . The amplifier
has RG = 4.7 M , RD = RL = 15 K . gm = 1mA / V, ro = 150 K , Cgs = 1 pF and Cgd
= 0.4 pF.
Solution :

1. In a MOSFET circuit if and ID = 0.5 mA, calculate gm.
2. Calculate fT for n-channel MOSFET for the specifications given Cgs = 44.7 fF and Cgd

= 3.72 fF, and ID = 0.2 mA.
3. Sketch the frequency response of common source amplifier and mark different
regions.
4. Draw relevant diagram to determine short circuit current gain Io / Ii on NMOSFET.
Write the expression for fT.
5. Give reasons for fall of gain at low and high frequencies in a CS amplifier.
6. An n-channel MOSFET has Cgs = 30 fF and Cgd = 2 fF, gm = 0.4 mA / V and

calculate the unity gain frequency fT.
7. Draw the T-Model of NMOSFET including ro.

8. Calculate fL of a CS amplifier in which gm = 1 m and CS = 1.6 F.
9. Draw the high frequency model of NMOSFET.
10. A n-channel MOSFET is used as an amplifier with a drain resistance of 20K . If
biasing voltages are VGS = 4V, VDS = 5V, Vt = 0.8V, and for
MOSFET, compute gm and AV.

1. Show that Transconductance of MOSFET is proportional to the square root of the DC
bias current.
2. Derive an expression for the overall voltage gain of common source amplifier.
3. Find mid band gain AM and the upper 3 dB frequency fH of a common source
amplifier fed with a signal source having an internal resistance Rsig = 100 K . The
amplifier has RG = 4.7 M , RD = RL = 15 K . gm = 1mA / V, ro = 150 K , Cgs = 1
pF and Cgd = 0.4 pF.
4. With the help of neat circuit diagram and ac equivalent circuit which uses small signal
model of NMOSFET, obtain the expression for Rin, AV, Rout of a CS amplifier.
5. Discuss the MOSFET internal capacitances with relevant diagram.
6. In a common gate amplifier if Rsig = 100 , RD = 10K , I = 0.5 mA, CC1 = CC2 = 0.1
F, RL = 100 K , VDD = 15V and VSS = -10V, find Rin, Rout, AV, AVO and GV. Given

and = 0. Draw the circuit diagram and equivalent circuit

7. With the help of neat circuit diagram and ac equivalent circuit which uses small signal
model of NMOSFET, obtain the expression for Rin, Rout, AV, AVO and GV of a
common source amplifier.
8. With the help of high frequency model on NMOSFET, obtain the expression for unity
gain frequency fT and hence calculate fT for the NMOSFET which has Cgs = 24.7 fF
and Cgd = 1.72 fF and ID = 100 A.
9. With the help of frequency response curve of common source amplifier, explain the
reason for reduction in gain in low and high frequency region.
10. Discuss the MOSFET internal capacitances with relevant diagram and draw the high
frequency model of MOSFET.
11. In a common drain amplifier if Rsig = 100 , RG = 5.3 M , ID = 0.5 mA, CC1 = CC2 =
0.1 F, RL = 100 K , VDD = 15V and VSS = -10V, find Rin, Rout, AV, AVO and GV.
Given and = 0. Draw the circuit diagram and equivalent circuit

Unit – 4 MOS Differential Amplifier

CO 3 : Analyze and evaluate MOS differential Amplifiers. (L2)
Differential amplifier is the most important building block of analog integrated

circuit. The input stage of operation amplifier (OP-Amp) is a differential amplifier. The
differential amplifier shown in Fig. 4.1 is one which amplifies the difference of input signals.
Amplifier (A)
Fig. 4.1 Block diagram of differential amplifier
4.1 The MOS differential pair

Figure 4.2 shows the basic MOS differential pair configuration. It consists of two
matched transistors Q1 and Q2, whose sources are connected together and biased by a constant
current source I. The drain of each MOSFET is connected to supply VDD through resistance
RD.
Fig. 4.2 Basic MOS differential pair configuration

4.1.1 Operation with a common mode input voltage

Consider the MOS differential pair shown in Fig. 4.3 with the inputs shorted and a
common mode input VCM is applied that is VG1 = VG2 = VCM. Since Q1 and Q2 are identical it
follows from symmetry that the current I will divide equally between the two transistors.
Fig. 4.3 MOS differential pair with common mode input voltage VCM
Now if the common mode voltage VCM is varied, the current I will divide equally
between Q1 and Q2 as long as the transistors remain in saturation region, hence the output
voltage will be zero. Thus the differential pair rejects the common mode input signal VCM.

Input common mode range

Input common mode range is the range of VCM over which the differential pair
operates properly.
The highest value of VCM is limited by the requirement that Q1 and Q2 remain in
saturation then
The lowest value of VCM is determined by the need to allow for a sufficient voltage
across current source I for it to operate properly. If a voltage VCS is needed across the current
source then
4.1.2 Operation with a differential input voltage

Consider the MOS differential pair shown in Fig. 4.4 with a differential input voltage
by grounding the gate of Q2 (VGS2 = 0) and applying a signal Vid to the gate of Q1
Fig. 4.4 MOS differential pair with differential input voltage Vid

Assume that vGS1 is fixed such that the entire current I flows through Q1 and vGS2 = Vt then
Thus the current I can be steered from one transistor to other by varying Vid in the
range
Problems :
P1. In a MOS differential amplifier with a common mode voltage, VCM applied. Let VDD
= VSS = 1.5 V, , Vt = 0.5V, I = 0.4mA, RD = 2.5 K , = 0. Find
(i) VOV and VGS

(ii) If vCM = 0, Find VS, iD1, iD2, vD1 and vD2
(iii) If vCM = +1V, repeat (ii)
(iv) If vCM = -0.2V, repeat (ii)
(v) vCM max
(vi) If VCS = 0.4V, VCM min, VS
Solution :

(i)
(ii)
(iii)
(iv)
(v)
(vi)
P2. In a MOS differential amplifier if VDD = VSS = 1.5 V, , Vt = 0.5V, I
= 0.4mA, RD = 2.5 K , = 0. Find

(i) vid that cause Q1 to conduct I, vD1 and vD2

(ii) vid that cause Q2 to conduct I, vD1 and vD2
(iii) Range of the differential output voltage (vD2 – vD1)
Solution :
(i)
(ii)
(iii)
4.2 Small signal operation of the MOS differential pair

In this section we will discuss the MOS differential pair as amplifier.
4.2.1 Differential gain

The MOS differential amplifier with a common mode voltage applied to set the DC
bias voltage at the gates and with vid applied in a complementary manner is shown in Fig. 4.5

Fig. 4.5 MOS differential amplifier with a common mode voltage applied to set the DC bias
voltage at the gates and with vid applied in a complementary manner
and
VCM denotes a common mode DC voltage within the input common mode range of
the differential amplifier. Typically VCM is at the middle value of power supplies, when two
complementary supplies are utilised VCM = 0.
Equivalent circuit for small signal analysis is shown in Fig. 4.6.
Fig. 4.6 Equivalent circuit for small signal analysis

Effect of the MOSFET's ro

The MOS differential amplifier with rO and RSS and the equivalent circuit is shown in
Fig. 4.7
Fig. 4.7 MOS differential amplifier with rO and RSS and equivalent circuit

4.2.2 Common mode gain and common mode rejection ratio (CMRR)
The common mode
The MOS differential amplifier with common mode signal vicm applied and equivalent
circuit is shown in Fig. 4.8.
Fig. 4.8 MOS differential amplifier with common mode signal vicm applied and equivalent
circuit
The symmetry of the circuit enables us to break it into two identical halves known as
CM half circuit.
Neglecting the effect of rO we can write the expression for gain as
Common Source amplifier with RS,
discussed in unit - III
i) When the output of the differential pair is taken single endedly

ii) When output is taken differentially
Effect of RD mismatch on CMRR

Assume the two drain resistances exhibit a mismatch of RD, and then the common
mode rejection ratio will be finite even if the output is taken differentially. Let us assume the
drain resistance connected to transistor Q1 is RD and that of Q2 is RD + RD.
 
Effect of gm mismatch on CMRR

Problems :
P1. A MOS differential pair is operated at a total bias current of 0.8mA, using transistors
with a ratio of 100,  , VA = 20V and RD = 5K . Find VOV, gm,
rO and Ad.
Solution :


P2. A MOS differential pair operated at a bias current of 0.8mA employs transistor with a
= 100 and  , using RD = 5K and RSS = 25K .
i) Find the differential gain, common mode gain and CMRR (in dB) if the output
is taken single endedly and the circuit is perfectly matched.
ii) Repeat (i) when the output is taken differentially
iii) Repeat (i) when the output is taken differentially when drain resistance have
1% mismatch
iv) Repeat (i) when the output is taken differentially when gm have 2% mismatch
Solution :

i)
ii)


iii)
iv)
4.3 Other non ideal characteristics of the differential amplifier

4.3.1 Input offset voltage of the MOS differential pair
Consider the basic MOS differential amplifier with both inputs grounded as shown in
Fig. 4.9. If the two sides of the differential pair were perfectly matched (Q1 and Q2 identical
and RD1 = RD2 = RD), then current I would split equally between Q1 and Q2 and VO would be
zero. Practical circuits exhibit mismatches that result in a DC output voltage VO even with
both inputs grounded which is called output offset voltage. More commonly this VO is
divided by the differential gain of the amplifier, Ad to obtain a quantity known as the input
offset voltage, VOS, . Obviously if a voltage -VOS between the input terminals of the
differential amplifier, then the output voltage will be reduced to zero.
Fig. 4.9 MOS differential amplifier with both inputs grounded

Three factors contribute to the DC offset voltage of the amplifier, mismatch in R D

(load resistance), mismatch in and mismatch in Vt.
Now let us consider the case where Q1 and Q2 are perfectly matched but RD1 and RD2
show a mismatch ΔRD that is
Now consider the effect of mismatch in the ratios of Q1 and Q2 expressed as
Such a mismatch causes the current I to no longer divide equally between Q1 and Q2 hence

Now we consider the effect of a mismatch between the two threshold voltages

4.3.2 Input common mode range

The input common mode range of a differential pair is the range of the input voltage
over which the differential pair behaves as a linear amplifier for differential input
signals. The upper limit of the common mode range is determined by Q1 and Q2 leaving the
saturation region and entering the triode region. The upper limit is equal to V t volts above the
voltage at the drains of Q1 and Q2. The lower limit is determined by the transistor that
supplies the biasing current I leaving its active region and of operation and thus no longer
functioning as a constant current source.
Problems :
P1. A MOS differential pair operated at a bias current of 0.8mA employs transistor with a
= 100 and  , using RD = 5K and RSS = 25K . Find the three
components of the input offset voltage if also
obtain the total VOS.

Solution :

4.4 The differential amplifier with active load

To increase the gain of the amplifier RD should be increased, but it has impact on the
operating point, hence replacing RD by constant current source results in much higher gain
and saving in chip area.
4.4.1 Differential to single ended conversion

Fig. 4.10 illustrates the simplest differential to single ended conversion. It consists of
simply ignoring the drain current signal of Q1 and eliminating its drain resistor and taking the
output between the drain of Q2 and ground.
Fig. 4.10 Differential to single ended conversion of MOS differential amplifier
If output is taken between two drains the differential gain will be double and much
reduced common mode gain of output taken at one of the drain with respect to ground.
4.4.2 The active loaded MOS differential pair

The active loaded MOS differential pair is shown in Fig. 4.11. The differential pair is
formed by transistor Q1 and Q2 and in place of RD current mirror formed by Q3 and Q4 (active
load) is connected.
Fig. 4.11 Active loaded MOS differential pair
Assume the two input terminals are connected to a DC voltage equal to the common
mode equilibrium value, in this case 0V as shown in Fig. 4.12.
Fig. 4.12 The circuit at equilibrium assuming perfect matching
Assuming perfect matching the bias current I divide equally between Q1 and Q2. The
drain current of Q1 is fed to the input transistor of the mirror, Q3. Thus a replica of this
current is provided by the output transistor of the mirror Q4. Observe at the output node the
two currents balance each other out, leaving a zero current to flow out to the next stage or
load. If Q4 is perfectly matched with Q3, the drain voltages of both the MOS will be same.
Hence the output voltage at equilibrium is . But in practical case there will always
be mismatches which cause a large deviation in output voltage from the ideal value.
Consider the circuit with a differential input voltage applied as shown in Fig. 4.13
Fig. 4.13 The circuit with a differential input signal applied
Since we are doing small signal analysis DC sources are removed and the output
resistance rO of all transistors is ignored. Transistor Q1 will conduct a drain signal current
and transistor Q2 will conduct equal and opposite current i. The drain signal
current i of transistor Q1 is fed to the input of the Q3 - Q4 mirror, which responds by

providing a replica in the drain of Q4. At the output node there are two currents each equal to
i which sum together to form 2i hence there is no loss of gain even though the output is single
ended. If load is connected the current 2i will flow through it and determines vO.
4.4.3 Differential gain of the active loaded MOS differential pair

The output resistance rO of the transistor plays a significant role in the operation of
active loaded amplifiers. Since the circuit is not symmetrical, let us find the short circuit
transconductance Gm and the output resistance RO, then the gain will be determined by GmRO.
Determining the transconductance Gm

Fig. 4.14 is the circuit for determining Gm. Note that the output is short circuited to the
ground to find Gm as iO / vid.
Fig. 4.14 Circuit for determining Gm
Even though the circuit is not symmetrical, when the output is shorted to ground, the
circuit becomes almost symmetrical. This is because the voltage between the drain of Q1 and
ground is very small because the low resistance between the node and ground which is equal
to 1 / gm3. Hence we can assume a virtual ground at source of Q1 and Q2, in this way the
equivalent circuit is written.
The voltage vg3 that develops at the common gate line of the mirror can be found as
This voltage controls the drain current of Q4 resulting in a current of . Note

that the ground at the output note causes the currents in rO2 and rO4 to be zero.
Hence the output current iO will be
Substituting for vgs
Determining the output resistance RO

Fig. 4.15 shows the circuit for determining RO.
Fig. 4.15 Circuit for determining RO
The current i that enters Q2 must exist at its source. It then enters Q1 existing at the
drain to feed the feed the Q3 - Q4 mirror. Since of transistor Q3 is much smaller than
rO3, most of the current i will flow in to the drain of Q4 which determines the relation
between i and vx
Now Q2 is a common gate (CG) transistor has in its source the input resistance of Q1
which is connected in the CG configuration (Q1) with a small resistance in the drain
(approximately ) thus its input resistance is approximately
From the circuit shown in Fig. 4.15, we can write at the output node
Substituting for RO2
Determining the differential gain
4.4.4 Common mode gain and CMRR

Fig. 4.16 shows the circuit for determining common mode gain applied with common
mode signal vicm and with the power supplies eliminated except of course the output
resistance RSS of the bias current source I.
Fig. 4.16 Circuit to determine common mode gain
Even though the output is single ended, the active loaded MOS differential has low
common mode gain and correspondingly high CMRR. Even though the circuit is not
symmetrical and hence we cannot use the common mode half circuit, we can split RSS equally
between Q1 and Q2 as shown in Fig. 4.16. It can now be seen that each of Q1 and Q2 is a
common source transistor with a large source degeneration resistance 2RSS. Since 2RSS is
much larger than of each of Q1 and Q2, the signal at the source terminals will be
approximately equal to vicm.
Note that RO1 will be much greater than the parallel resistance introduced by
Q3
Similarly RO2 will be much greater than rO4. Hence RO1and RO2 can be easily neglected
while finding the total resistance between each of the drain nodes and ground.
The current i1 is passed through and as a result produces a voltage vg3.
Transistor rO4 senses this voltage and hence provides a drain current i4
At the output node the current difference between i4 and i2 passes through rO4 (Since
RO2 >> rO4) to provide vO
Substituting for i1 and i2 and setting gm3 = gm4 it can be simplified with manipulation
as
Since RSS is usually large Acm will be small
Problem :
P1. An active loaded MOS differential amplifier is specified as follows,
Solution :
1. Write the circuit diagram of MOS differential pair.
2. Define the terms differential gain and input offset voltage of differential MOS pair.
3. Define the term CMRR of differential MOS pair and write the expression for CMRR.
4. A MOS differential pair is operated at a total bias current of 0.8mA. Using MOSFET
with a W/L ratio of 100. nCox = 0.2mA/V2 rO = 50K and RD = 5K . Find gm.
5. Draw the diagram of MOS differential pair to represent the output DC offset voltage.

1. With suitable diagram and analysis explain the operation of MOS differential pair
with differential mode input voltage.
2. Explain common mode gain and common mode rejection ratio of a MOS differential
pair. Also obtain expression for CMRR.
3. An active loaded MOS differential amplifier is specified as follows,
4. With a neat diagram, deduce an expression for (gm) Transconductance, output

resistance (RO), common mode rejection ratio (CMRR) of active loaded MOS
differential pair.
5. With the help of neat circuit diagrams, explain the working of MOS differential pair
for common mode input voltage and differential input voltage.
6. A MOS differential pair operated at a bias current of 0.8mA employs transistor with a
= 100 and  , using RD = 5K and RSS = 25K .
a. Find the differential gain, common mode gain and CMRR (in dB) if the output
is taken single endedly and the circuit is perfectly matched.
b. Repeat (a) when the output is taken differentially
c. Repeat (a) when the output is taken differentially when drain resistance have
1% mismatch
d. Repeat (a) when the output is taken differentially when gm have 2% mismatch
7. Draw the basic MOS differential pair circuit and show how it can be modified to
operate with a common mode input voltage Vcm. Derive an expression for the voltage
at each drain terminal VD.
8. With relevant diagram derive an expression for CMRR of MOS differential pair.
9. Draw the circuit diagram of of a resistively loaded MOS differential pair and explain
its working.
Unit – 5 Feedback Amplifiers and Power Amplifiers

CO 5 : Compare different negative feedback topologies. (L1)
CO 6 : Analyze and evaluate the performance of power amplifiers. (L2)
Feedback is a process of combining a part of output signal with input signal. There are
two types of feedback namely positive feedback (regenerative feedback) and negative
feedback (degenerative feedback).
Positive feedback (Regenerative feedback)

In positive feedback the signal fed back will be in phase with input signal (additive
with input signal), positive feedback will be employed in oscillators.
Negative feedback (Degenerative feedback)

In negative feedback the signal fed back will be out of phase with input signal
(subtractive with input signal), Negative feedback will be employed in amplifiers to improve
the characteristics of amplifiers.
5.1 The general feedback structure

The general structure of negative feedback is shown in Fig. 5.1. It consists of the basic
amplifier with gain A, feedback network with feedback factor,  to select the portion of
output signal and a mixer to combine the source signal and the fed back signal.
Mixer
Basic

+ Amplifier (A)
-
Feedback
network ()
Fig. 5.1 General structure of negative feedback
 





 
From the expression the gain of the feedback amplifier is determined by the feedback
network, which consists of only passive components hence the gain is more stable with
feedback.
5.2 Properties of negative feedback

1. Gain desensitivity

   
 
 



Hence the percentage change in Af is smaller than the percentage change in A.
2. Bandwidth extension
Consider an amplifier whose high frequency response is characterized by a single
pole. Its gain at mid and high frequencies can be expressed as
Application of negative feedback with a frequency independent factor () around this
amplifier results in a closed loop gain Af(s) given by



Hence the bandwidth of the amplifier is increased by the same factor by which its
midband gain is decreased.
3. Noise reduction
Negative feedback can be employed to reduce the noise in an amplifier or to increase
the noise to signal ratio
Vn
Vs A1 Vo
Fig. 5.2 Amplifier without feedback
Vn
+ +
Vs A2 A1 Vo
Vo
- -
- +
Fig. 5.3 Amplifier with feedback
In the amplifier without feedback shown in Fig. 5.2 the signal to noise ratio is given
by
Whereas in the amplifier with feedback shown in Fig. 5.3
 
Hence signal to noise ratio with feedback increases
4. Reduction in non linear distortion

Vo (V)
(a)
(b)
Vi (V)
In the graph shown in figure curve (a) represents amplifier transfer characteristics
without feedback and curve (b) represents amplifier transfer characteristics with
feedback. The amplifier characteristic is more linear with feedback compared to
without feedback.
5.3 Four basic feedback topologies

Based on the quantity to be amplified (voltage or current) and on the desired form of
output (voltage or current), amplifiers can be classified into four categories. In this section the
appropriate feedback topologies for these amplifiers is discussed.
1. Series Shunt feedback

The block diagram of Series Shunt feedback topology is shown in Fig. 5.4
RS
+ +
Basic Voltage
RL VO
VS amplifier
- + -
- Vf
Feedback
network
Fig. 5.4 Series Shunt feedback topology
Basic Amplifier : Voltage amplifier

Signal sampled : Voltage
Signal mixed : Voltage
Ideal input resistance (Ri) : 
Ideal output resistance (Ro) : 0
2. Shunt Series feedback

The block diagram of Shunt Series feedback topology is shown in Fig. 5.5
Basic Current IO
IS RS amplifier RL
If If
IO
Feedback
network
Fig. 5.5 Shunt Series feedback topology
Basic Amplifier : Current amplifier

Signal sampled : Current
Signal mixed : Current
Ideal input resistance (Ri) : 0
Ideal output resistance (Ro) : 
3. Series Series feedback

The block diagram of Series Series feedback topology is shown in Fig. 5.6
RS
+
Basic IO
VS Transconductance RL
- + amplifier
- Vf
IO
Feedback
network
Fig. 5.6 Series Series feedback topology
Basic Amplifier : Transconductance amplifier

Signal sampled : Current
Signal mixed : Voltage
Ideal input resistance (Ri) : 
Ideal output resistance (Ro) : 
4. Shunt Shunt feedback

The block diagram of Shunt Shunt feedback topology is shown in Fig. 5.7
Basic
RS Transresistance RL VO
IS
amplifier
If If
Feedback
network
Fig. 5.7 Shunt Shunt feedback topology
Basic Amplifier : Transresistance amplifier

Signal sampled : Voltage
Signal mixed : Current
Ideal input resistance (Ri) : 0
Ideal output resistance (Ro) : 0
5.4 Series - Shunt feedback amplifier

The series - shunt feedback amplifier is shown in Fig. 5.8.
Ii RO
+ + + +
Ri AVi
VS Vi VO
- - + - -
-
VO Basic Amplifier
Rif ROf
+ +
VO VO
- -
Feedback Network
Fig. 5.8 Series - Shunt feedback amplifier
 


To find output resistance, ROf Set VS = 0, apply a test voltage Vt at the output
terminals which drives a current I, then
RO
I
AVi Vt
+
VS = 0 Ri
Vi
-
- Vf +
Vf = VO
 

5.5 Series - Series feedback amplifier

The series - series feedback amplifier is shown in Fig. 5.9.
Ii IO
+ +
VS Vi Ri RO
AVi
- - + -
IO
Rif ROf
+
IO IO
-
Fig. 5.9 Series - Series feedback amplifier





5.6 Shunt - Series feedback amplifier

The shunt - series feedback amplifier is shown in Fig. 5.10.
Ii IO
IS Ri AIi RO
If
Rif ROf
IO IO
Fig. 5.10 Shunt - Series feedback amplifier


5.7 Shunt - Shunt feedback amplifier

The shunt - shunt feedback amplifier is shown in Fig. 5.11.
Ii
RO
IS Ri AIi VO
If
Rif ROf
VO
Fig. 5.11 Shunt - Shunt feedback amplifier
Problems :
P1. An amplifier has bandwidth of 200 KHz and voltage gain of 1000. What should be the
amount of feedback if the bandwidth received is 1 MHz.
Solution :
P2. An amplifier with a voltage gain of 100 and bandwidth of 100 KHz is provided with
3% negative feedback. What are the values of gain and bandwidth after feedback.
Solution :
P3. Calculate the loop gain (A) of a negative feedback amplifier if Af = 20 and  = 1%.
Solution :
P4. In a series shunt feedback amplifier, the basic voltage amplifier has gain 120, input
resistance 1M and output resistance 75 , if 0.2% of output signal is fed back to the
input, what will be the modified gain, input resistance and output resistance.
Solution :
Output Stages and Power Amplifiers

An important function of the output stage is to provide the amplifier with a low output
resistance so that it can deliver the output signal to the load without loss of gain. Since the
output stage is the final stage of the amplifier, it usually deals with relatively large signals
hence the small signal approximations and models are not applicable. The most challenging
requirement in the design of the output stage is that it delivers the required amount of power
to the load in an efficient manner. This implies the power dissipated in the output stage
transistors must be as low as possible. Also high power conversion efficiency also may be
required to prolong the life of batteries employed in battery powered circuits.
5.8 Classification of output stages

Output stages are classified according to the collector current waveform that results
when an input signal is applied.
Class - A Stage
The Class - A stage is biased at a current

IC greater than the amplitude of the
signal current, . Thus the transistor in a
Class - A stage conducts for the entire
cycle of input signal 360 as shown in
Fig. 5.12. The output is distortion less in
Class - A mode but power efficiency is
Fig. 5.12 Collector current in Class - A
Stage more (30%)
Class - B Stage
The Class - B stage is biased at zero
current, hence transistor conducts for
only 180 that is half the cycle of input
sine wave as shown in Fig. 5.13. Since
transistor conducts half the cycle of input
Fig. 5.13 Collector current in Class - B power efficiency is good and the output
Stage will be distorted.
To overcome this problem one more transistor will be used in Class - B mode to obtain the
negative half cycle.
Class - AB Stage
An intermediate class between A and
B appropriately named Class - AB
involves biasing the transistor at a non
zero dc current much smaller than the
peak current of the sine wave signal.
Fig. 5.14 Collector current in Class - AB As a result transistor conducts for an
Stage
interval slightly greater than half a
cycle as shown in Fig. 5.14.
The resulting conduction angle is greater than 180 but much less than 360.
Class - C Stage
In Class - C stage the transistor
conducts for an interval shorter than
that of a half cycle, that is the
conduction angle is less than 180 as
shown in Fig. 5.15 hence the collector
Fig. 5.15 Collector current in Class - C current is periodically pulsating
Stage
waveform.
In class - C stage the power efficiency is very good but output is distorted. To overcome this
problem parallel LC circuit is used at output tuned to the frequency of the input signal.
5.9 Class - A Output stage

Consider the class - A output stage or emitter follower shown in Fig. 5.16.
Fig. 5.16 Class - A Output stage
The transistor Q1 is biased with a constant current I supplied by transistor Q2. Since
the emitter current the bias current I must be greater than the largest negative
load current. Otherwise Q1 cuts off and Class - A operation will no longer be maintained. The
transfer characteristic of the emitter follower is shown in Fig. 5.17.
Fig. 5.17 Transfer characteristic of Class - A Output stage
From the circuit we can write that
The positive limit of the linear region is determined by the saturation of Q1
In the negative direction depending on the value of I and R L, the limit of the linear
region is determined either by Q1 turning off
or by Q2 saturating
this is achieved provided the bias current I is greater than the magnitude of the
corresponding load current
Signal waveform
Consider the operation of emitter follower circuit shown in Fig. 5.16 for sine wave
input. Neglecting VCESat, if the bias current I is properly selected, the output voltage can
swing from –VCC to +VCC with the quiescent value being zero and the corresponding
waveforms VCE1 = VCC –vO are shown in Fig. 5.18. Assuming that the bias current I is
selected to allow a maximum negative load current of the collector current of Q1
and instantaneous power dissipation in Q1, is also shown in Fig. 5.18.
Fig. 5.18 Maximum signal waveforms of Class - A output stage
Power dissipation
When input is zero, the maximum power dissipation in Q1 is VCC I hence the
transistor Q1 must be capable of withstanding this power. When R L = , is constant
and the instantaneous power dissipation in Q1 will depend on the instantaneous value of vO.
The maximum power dissipation will occur when vO = -VCC, for this case VCE1 = 2 VCC and
pD1 = 2 VCC I.
When RL = 0, the load current will be infinity, hence current through Q1 is very large
resulting in large power dissipation, if this condition persist for long duration Q1 may burn
up. The maximum power dissipation of Q2 is also 2 VCC I.
Power conversion efficiency

The power conversion efficiency of an output stage is defined as
In a voltage follower assuming the output voltage will take up the maximum value
and minimum value

Hence Class - A output stage is rarely used in high power applications
5.10 Transformer coupled power amplifier

The RC coupled Class - A amplifier discussed in previous section has ideal efficiency
of 25 %. To improve efficiency the transformer coupled class - A power amplifier is
preferred in which a transformer is used to couple ac power to the load. By adjusting the turn
ratio of the primary winding to the secondary winding the source and load impedances can be
matched for maximum power transfer. The transformed coupled power amplifier is shown in
Fig. 5.19 and the DC and AC load line is shown in Fig. 5.20.
Fig. 5.19 Transformer coupled power amplifier
The impedance matching of the transistor is
Fig. 5.20 DC and AC load line of transformer coupled amplifier
DC load line is drawn assuming DC resistance of primary winding of transformer as
zero, hence slope is infinity. AC load line is drawn with slope where is ac
resistance of the primary winding.
5.11 Class - B Transformer coupled amplifier

In the class - B amplifier, the operating point is located in the cutoff region therefore
the transistor conducts only for 180 or half of the input signal, hence efficiency is more.
However to get the output signal for the complete cycle of the input signal, two transistors are
connected in push pull configuration as shown in Fig. 5.21.
The transistors are biased such that in the absence of the input signal both transistors
remain in cut off region hence efficiency is more.
The current flowing through each transistor in Class - B amplifier is shown in Fig.
5.22.
Fig. 5.21 Class - B Transformer coupled amplifier
Fig. 5.22 Current flowing through each transistor in Class - B amplifier
The efficiency of transformer coupled amplifier,
5.12 Class - B output stage

The class - B output stage is shown in Fig. 5.23 which consists of complementary pair
of transistors (an NPN and PNP transistors) connected in such a way that both cannot conduct
simultaneously.
Fig. 5.23 Class - B Output stage
Circuit operation
When Vi = 0, both transistors are in cut off and the output voltage, VO = 0. As input
increases in positive direction and exceeds 0.5 V (V) QN conducts and operates as emitter
follower, that is VO = Vi – VbeN and QN supplies load current. When input increases in
negative direction by more than 0.5 V, QP turns on and acts as emitter follower and supplies
load current, the output voltage, VO = Vi + VEBP or VO = Vi - VBEP
Transfer characteristics
The transfer characteristics of Class - B output stage is shown in Fig. 5.24. From the
figure it is clear that near origin both transistors will be cutoff and VO = 0. This dead band
results with cross over distortion is shown in Fig. 5.25.
Fig. 5.24 Transfer characteristics of Class - B output stage
Fig. 5.25 Cross over distortion (dead zone) in class - B output stage
Power conversion efficiency
Neglecting cross over distortion, the average load power,
Average power drawn from each power supply,
Maximum conversion efficiency of class - B output stage is 78.5 %.
Power dissipation
The maximum power dissipation in NPN transistor and PNP transistor is,
5.13 Class - AB output stage

The crossover distortion of class - B output stage can be eliminated by biasing the
complementary output transistor at a small non zero current. The result is class - AB output
stage which is shown in Fig. 5.26.
Fig. 5.26 Class - AB output stage
A bias voltage VBB is applied between the base of QN and QP. When input, Vi = 0 the
output VO = 0 and voltage appears across base to emitter junction of each of QN and QP.
Circuit operation
When Vi goes positive, the voltage at the base of QN increases by the same amount
and the output becomes positive
The positive VO causes a current IL to flow through RL and thus IN must increase that
is
The increase in iN will increase VBEN, since the voltage between the two bases remain
constant at VBB, the increase in VBEN results in decrease in VEBP and hence iP hence
Thus as iN increases, iP decreases by the same ratio while the product remains constant
combining equation and yields
From the equation discussed above, it can be seen that for positive output voltages the
load current is supplied by QN and mean while QP conducts a current that decreases as VO
increases which can be neglected for large VO. For negative input voltage the opposite
occurs.
The transfer characteristics of Class - AB output stage is shown in Fig. 5.27.
Fig. 5.27 Transfer characteristics of Class - AB output stage
The class - AB output stage operates almost in the same manner as class - B with an
exception that for small Vi both transistors conduct and as Vi increases or decreases one of
the two transistors take over the operation. Since the transition is smooth cross over distortion
will be eliminated.
The power relationship in the class - AB output stage is almost identical to those
discussed for class - B output stage. The only difference is under quiescent conditions class -
AB circuit dissipates a power of VCC IQ per transistor and since IQ is usually much smaller
than the peak current the quiescent power is negligible.
Output resistance
The equivalent circuit of class - AB output stage to determine output resistance is
shown in Fig. 5.28.
Fig. 5.28 Equivalent circuit to determine output resistance
Problems :
P1. A transformer coupled class - A power amplifier supplies power to an 80 load
connected across the secondary of a step down transformer having a turn ration 5:1.
Determine the maximum power output for a zero signal collector of 120 mA.
Solution :
P2. A Class - B push pull amplifier is supplied with VCC = 50 V, the signal brings the
collector voltage down to Vmin = 5 V. The total dissipation from both transistors is 40
W. Find the total power and conversion efficiency.
Solution :
6. A Class - B push pull amplifier is supplied with VCC = 50 V, the signal brings the
collector voltage down to Vmin = 5 V. The total dissipation from both transistors is 40
W. Find the total power and conversion efficiency.
7. Mention any two advantages of negative feedback amplifier.
8. What is the maximum conversion efficiency of class - A power amplifier (transformer
coupled) and class - B push pull amplifier?
9. Define the terms i) Gain de-sensitivity and ii) Bandwidth extension as applicable to
negative feedback.
10. An amplifier has a bandwidth of 200 KHz and voltage gain of 1000. What should be
the amount of feedback with the bandwidth received is 1 MHz.
11. An amplifier with a voltage gain of 100 and bandwidth of 100 KHz is provided with 3
% negative feedback. What are the values of gain and bandwidth after feedback?
12. Draw the general structure of a negative feedback amplifier.
13. The theoretical value of of transformer coupled class A power amplifier is ______
and that of class B power amplifier is ________.
14. Calculate the open loop gain (A) of a negative feedback amplifier if Af = 20 and  =
1%.
15. How cross over distortion is reduced in Class AB amplifiers?
16. In feedback amplifiers, feedback factor of the feedback network is represented by
_________ and is less than or equal to ________.

1. Derive the equations for the input and output impedance for the series shunt feedback
amplifier.
2. A transformer coupled class - A power amplifier supplies power to an 80 load
connected across the secondary of a step down transformer having a turn ration 5:1.
Determine the maximum power output for a zero signal collector of 120 mA.
3. Draw the general block diagram of feedback amplifier and derive the expression for
gain with feedback.
4. With the help of neat sketches, explain the classification of output stages.
5. With the help of neat figure, discuss the operation of transformer coupled output
stage.
6. With neat sketch, explain transformer coupled class - B push pull amplifier.
7. Compare class - A and transformer coupled class - A output stages.
8. Discuss different types of feedback topologies.
9. With neat circuit diagram and transfer characteristics, explain class - B output stage
and show how cross over distortion can be reduced.
10. Discuss transformer coupled class - A output stage and explain the advantages of it
over class - A output stage.

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3REC01 Analog Electronic Circuits

III Semester B.E., Electronics & Communication Engg.

Department Of Electronics & Communication EngG.

SIDDAGANGA INSTITUTE OF TECHNOLOGY

ANALOG ELECTRONIC CIRCUITS

Contact Hours/ Week : 3 (L) Credits :3

Course pre-requisite: Basic Electronics and Foundations of Electrical Engineering

Course Objectives: This subject enables the students to learn about:

Unit-2 MOS Field Effect Transistor 33

Unit-3 Small signal operations and models 59

Unit-4 MOS differential amplifier 84

Unit-5 Feedback amplifiers and Power amplifiers 111

Unit – 1 Applications of Diode

After studying this course the student should be able to

1.1 Full wave rectifier with capacitor filter

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 1

VDC Vo without ‘C’ filter

Fig. 1.3 Full wave rectifier with ‘C’ filter waveform

1.1.1 Expression for ripple factor

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 2

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 3

P2. In a full wave rectifier if C = 1000 F and RL = 1 K , calculate ripple factor.

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 4

1.2 Clipping circuits

Steps to be followed to analyse clipping circuit

1.2.1 Two level Series clippers

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 5

1.2.2 Two level Shunt Clippers

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 6

3. To pass portion of positive peak between (VR1-V) and (VR2+V) level

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 7

1.2.3 Design : Selection of resistance R

Fig. 1.10 Example clipping circuit

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 8

Fig. 1.11 Equivalent circuit when diode is ON

Fig. 1.12 Equivalent circuit when diode is OFF

Substituting for K in equation from equation

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 9

Input / Output waveform

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 10

Input / output waveform and transfer characteristics

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 11

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 12

1.3 Clamping circuits

1.3.1 Negative clampers

Fig. 1.14 Equivalent circuit during Vi = + Vm

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 13

Fig. 1.15 Equivalent circuit during Vi = - Vm

2. Positive peak clamped to positive reference level

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 14

Fig. 1.17 Equivalent circuit during Vi = + Vm

Fig. 1.18 Equivalent circuit during Vi = - Vm

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 15

3. Positive peak clamped to negative reference level

Fig. 1.20 Equivalent circuit during Vi = + Vm

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 16

Fig. 1.21 Equivalent circuit during Vi = - Vm

1.3.2 Positive clampers

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 17

Fig. 1.23 Equivalent circuit during Vi = - Vm

Fig. 1.24 Equivalent circuit during Vi = + Vm

K. V. Jyothi Prakash, Dept. of E&C Engg., SIT, Tumakuru – 572 103 18

5. Negative peak clamped to negative reference level

Fig. 1.26 Equivalent circuit during Vi = - Vm