A Compact, Low Input Capacitance Neural Recording

Amplifier with Cin/Gain of 20fF.V/V

Kian Ann Ng and Yong Ping Xu

Dept of Electrical and Computer Engineering,
National University of Singapore, Singapore
elenka@nus.edu.sg

Abstract— This paper presents a compact and low input

capacitance neural recording amplifier. By replacing a single
feedback capacitor with a clamped T-capacitor network, the
proposed amplifier can achieve same mid-band gain with less
input capacitance, resulting in a smaller silicon area and higher
input impedance. Fabricated in 0.35µm CMOS, the amplifier
occupies merely 0.056mm2. It achieves 38.1-dB mid-band gain
with 1.6pF input capacitance, and hence has a Cin/Gain ratio of
20fF.V/V. It has an input referred noise of 6.72µVrms over 8.4-
kHz bandwidth and NEF of 4, and consumes 6µW. In-vivo
recordings from an animal experiment are also demonstrated.
I. INTRODUCTION
Neural signal recording is an essential part of modern
neural science research. Neural recording systems are
commonly constructed with multi-electrode arrays with a
capacitively coupled amplifier [1], shown in Fig. 1, as the
analog front end. The gain of the amplifier is set by the input
to feedback capacitance ratio (Cin/Cfb) which is usually large.
Previously reported neural recording amplifiers [1-4] have
achieved gains around 40dB with an input capacitance
ranging from 10pF to 20pF. Input capacitance can be reduced,
but at the expense of reduced gain [5]. Most amplifiers occupy
no less than 0.1mm2 of silicon area of which a high percentage
is occupied by the input capacitors. In applications where a
large number of recording channels are needed, the front-end
recording amplifiers would occupy a significant amount of
chip area. Thus it is necessary to minimize the area of the
recording amplifier.
The large input capacitance (10-20pF) also translates to an
equivalent input impedance of 8-16MΩ at 1-kHz to the neural
signal source. On the other hand, the impedance of various
types of microelectrodes is typically in the range of 100kΩ to
6MΩ at 1-kHz. This forms a voltage divider at the input of the
amplifier that attenuates the received neural signal. For
chronic neural recording, there is also problem of tissue
fibrosis which will increase electrode impedance and cause
further attenuation. As the source and input impedances are of
the same order of magnitude, the effective common mode
rejection ratio will also be degraded if the neural signal and
C fb  Cu
C
Gain  in  M
C fb
1
f HPF 
2C fb R pseu
 1 
f LPF  g m  
 MC 
 L
Total No. of Cu  2(Gain  1)
Fig. 1. Schematic of the conventional capacitively coupled neural recording
amplifier [1].
reference signal impedances are slightly mismatched. Hence,
there is a need to increase the input impedance of the neural
recording amplifier.
As mentioned above, the mid-band gain of capacitive
coupled recording amplifiers is determined by the ratio of
input to feedback capacitance. This imposes a direct trade-off
between input capacitance and the chip area versus the
amplifier gain. To obtain a large mid-band gain, we can either
increase the input capacitance or lower the feedback
capacitance. The former will directly decrease the input
impedance and increase the silicon area, while the latter is
limited by the parasitic capacitance, mismatch and the
constraint of the process technology. On the other hand, to
reduce the input capacitance (and area), the mid-band gain has
to be reduced [5] if the feedback capacitor is constrained as
mentioned before. Thus a trade-off is unavoidable. Such a
trade-off can be characterized by the input capacitance to gain
ratio, Cin/Gain (fF.V/V). A low ratio means that a smaller
input capacitance, and hence less area is required to
implement the given gain. State-of-the-art solutions were
commonly implemented with feedback capacitors of 100fF to
200fF [3-5]. With the minimum feedback capacitor being

The authors would like to thank the funding support from

A*Star Singapore under Project 102 152 0023.

328
fixed, the only way to reduce the input capacitance and area is
to reduce the front-end gain [5], but this requires additional
performance optimization in the subsequent signal R fb
conditioning stages. Due to these constraints, the Cin/Gain Gain 
ratio of state-of-the-art neural amplifiers is no less than R IN
100fF.V/V. 2 R1 R2
R fb  R1  R2 
This paper reports a capacitively coupled neural amplifier R3
that relaxes the input capacitance (and area) versus gain
constraint. The proposed method can be used to either achieve
a medium amplifier gain specification with much smaller Fig. 2. Schematic of a closed loop amplifier with T-resistor feedback
input capacitance and silicon area (as demonstrated in this path
paper) or a higher mid-band gain without the penalty of
increased input capacitance and silicon area . The concept of
the proposed method is described in section II and the detailed
circuit implementation as well as the noise optimization is
discussed in section III. Section IV presents measurement
results of the amplifier together with in-vivo neural
recordings.

II. NEURAL AMPLIFIER TOPOLOGY

Inserting a T-resistor network in the feedback path of an
amplifier depicted in Fig. 2 is a known method to increase the
closed loop gain of an amplifier circuit requiring high input
impedance. The T-resistor network implements a large
overall feedback resistor without using very large individual
resistor in the network, to achieve high gain while
maintaining the input impedance. We extend this concept to
the capacitively coupled amplifier. The feedback capacitance
in the amplifier depicted in Fig.1 can be replaced with a T-
capacitor network. Fig. 3 illustrates the proposed capacitively
coupled neural amplifier. Voltage clamps are added to the
floating nodes. The effective feedback capacitance, mid-band
gain, low and high 3dB cutoff frequencies of the proposed
amplifier are given in (1), (2), (3) and (4), respectively. Note
that all capacitors are implemented with multiples of a unit
capacitor, Cu.
Cu
C fb 
2( N  1)
Cin
Gain   2M ( N  1)
C fb
1 To eliminate possible accumulation of parasitic charges on
f HPF 
2C fb R pseu
 1 
f LPF  g m  
 2 M ( N  1)C L
Gain
Total No. of Cu needed   ( N  4)
N 1
By inserting an AC shunt path via C4 in the feedback path,
the effective feedback capacitance Cfb can be reduced as given
by (1). Thus a small feedback capacitance can be realized
using conventionally sized unit capacitors (Cu) that do not
suffer from the problems associated with small size capacitors,
as mentioned earlier. As a result, an additional gain factor of
2(N+1) can be obtained as compared with the conventional
design where only a single Cu is employed in the feedback
Fig. 3. Schematic of the proposed neural recording amplifier with T-
capacitor feedback network
path. Thus to achieve the same mid-band gain, the input
capacitance, Cin can be reduced by the same factor of 2(N+1).
Although more capacitors are used in the feedback path, the
total number of unit capacitors needed to implement a given
gain is in fact reduced. For instance, if the gain is 38.1-dB
(80V/V), N is 4 and according to (5), the total number of Cu
needed in the proposed amplifier is 24Cu compared with
162Cu in the conventional recording amplifier. This represents
a 6.7 times reduction for the total capacitance. The theoretical
value of N that allows the amplifier to be implemented with
the minimal number of unit capacitors is found to N=Gain½-1.
However, additional parasitic capacitances, and input-referred
noise requirement will limit the practical value of N.
the floating nodes (A1 and A2) during the fabrication process
or due to external electric fields, reversely biased low leakage
diodes (D1 and D2, D3 and D4) are connected to the floating
nodes. These diodes remain in reverse bias during normal
operation and provide leakage paths to discharge any induced
charge on the floating nodes, keeping the bias voltages on A1
and A2 within the operating voltage range. The diodes are
implemented with minimum size and the extremely low
leakage current and have no impact on normal operation.
III. NEURAL AMPLIFIER DESIGN
In this work, N is set to 4 and the mid-band gain of 38.1-
dB (80V/V) is implemented with an input capacitance of
1.6pF and unit capacitance of 200fF. Compared with the prior

329
art with similar mid-band gain, around 6 to 12 times reduction
in input capacitance is achieved without using very small unit
capacitors in the feedback path. The following sub-sections
will describe the design of the operational transconductance
amplifier (OTA) as well as the noise optimization procedure
associated with low input capacitances.

A. OTA design
The neural amplifier requires a power efficient low noise
operational amplifier which determines the overall noise
efficiency factor [1]. The telescopic cascode OTA of Fig. 4(a)
is selected as the active operational amplifier as it has the
lowest input referred noise level for a given bias current
compared to other types of basic amplifiers. Though it has a
low output swing, it is suitable for the front end amplifier as
the typical output swing after amplification is a maximum of Fig. 4. (a) Schematic of the Telescopic cascode OTA circuit (b)
+/-40mV for a 500µV neural signal. The W/L ratio of the Simulated noise optimization curves for different input gate dimensions
input differential pair formed by M1 and M2 are sized to work and noise bandwidths.
in weak inversion and is optimized for low input referred
noise as described in the next section. Transistors M5-M10 are
designed to operate in strong inversion and their noise
contribution of the overall amplifier is less than 20% of the
total input referred noise. The simulated input referred noise
floor at 10-kHz is 36.8nV/√Hz. The resistor Rc and capacitor
Cc provides frequency compensation to allow the OTA to
provide a phase margin of at least 60o for a capacitive load of
2pF.

B. Input referred noise minimization

The reduced input capacitance will cause the OTA input-
referred noise to be further amplified by the increased ratio of
OTA’s input parasitic capacitance to input capacitance [1]. Fig. 5. Die Microphotograph of the proposed neural amplifier.
Hence, noise optimization is performed by trading off flicker
noise increase versus reduction of total multiplied noise via
tuning the size of the input differential pair over the 100Hz-
9kHz signal bandwidth. Fig. 4(b) shows a plot of simulated
RMS noise performance for different noise bandwidths versus
input transistor gate length. The gate width is maintained such
that the input differential pair maintains a high gm/ID (>23) for
all values of gate length. The target 0.35µm process
parameters were used for the simulation. Taking process
variations into consideration, a final gate length of 0.7µm and
width of 105.6µm (gm/ID=24.7) is chosen for the input
transistor pair in this design

IV. MEASUREMENT RESULTS

The amplifier was fabricated in a standard 0.35µm CMOS
process and the chip microphotograph is shown in Fig. 5. All
capacitors were implemented with poly-poly capacitors having
area capacitance of 0.9fF/µm2. The complete amplifier only
occupies 0.056mm2,of which 50% of the area being occupied
by the two 1.6pF input capacitors with some layout overhead.
For electrical characterization, the output of the neural
amplifier was connected to an on-chip low-noise AC coupled
buffer with 20dB gain and 5-mHz low side cutoff frequency. Fig. 6. AC response and input referred noise PSD plot.
All parametric measures were taken from the output of this
buffer. The low side 3-dB cutoff frequency of the neural shows the AC frequency response and input referred noise
amplifier was tuned by supplying a voltage to the gates of the PSD when the low side 3-dB cutoff frequency is set at 1.4-Hz
pseudo-resistors. This voltage is generated by an on-chip (although in neural recording application, the low side cutoff
bandgap reference with an external tunable resistor. Fig. 6 frequency only needs to be at 100-Hz). The total input referred

330
 PSRR=55dB
CMRR=74dB

Fig. 8. Recorded neural signal at the output of the proposed amplifier

Fig. 7. CMRR and PSRR response. when the sciatic nerve is consecutively pinched thrice.
TABLE II
SUMMARY OF PERFORMANCE AND COMPARISON WITH THE STATE OF THE ART

Parameter [3] [4] [5] This work I. CONCLUSION

A neural amplifier with compact area, low input
CMOS Technology 0.18µm 0.18µm 0.35µm 0.35µm
capacitance and micro-power consumption is demonstrated.
Input capacitance(pF) 10 20 4.5 1.6 By introducing a T-capacitor network in the feedback
Gain(dB) 40 39.4 33 38.1 network, the proposed neural amplifier topology have a much
Cin/Gain (fF.V/V) 100 200 100 20 relaxed input capacitance (and area) versus gain constraint.
Operating 16- 10 - 0.5 - For a gain of 38.1-dB, this neural amplifier only occupies
1.4-8.5k
Bandwidth(Hz) 5.3k 7.2k 10k 0.056mm2 and has only 1.6pF of input loading capacitance,
Amplifier Area(mm ) 2
0.116 0.065* 0.02 0.056 achieving the lowest Cin/Gain ratio of 20fF.V/V. Consuming
Input Referred
5.29 3.5 6.08
14.4 2µA, it has an input referred noise of 6.72µVrms over 8.4-kHz
noise(µVrms) (6.72) (100Hz-8.5-kHz ) bandwidth and NEF of 4. An in-vivo
16- 10- 10- 1.4-8.5k
Noise Bandwidth(Hz)
5.3k 7.2k 5k (100-8.5k) recording experiment demonstrates the capability of this
8.5 amplifier as a front end for neural signal acquisition
NEF 6.28 3.5 5.55
(4.0) applications.
Supply voltage (V) 1.8 1.8 3.0 3.0
ACKNOWLEDGMENT
Supply current (µA) 5.0 4.4 2.8 2.0
* Effective area of a single amplifier as 4 amplifiers share a single OTA and a The authors would like to thank Dr Ter Chyan Tan and Ms
single reference input Khadijah Yusoff from the Dept. of Hand & Reconstructive
noise from 100Hz to 8.5kHz is 6.72Vrms, resulting in a NEF Microsurgery, National University Hospital Singapore, for
of 4. The fabricated amplifier has achieved a mid-band gain of assistance in the animal experiment.
38.1dB with 1.6pF input capacitance (equivalent to 99MΩ at
1-kHz), resulting in a Cin/Gain ratio of 20fF.V/V, 5 times less REFERENCES
than the state-of-art [5]. The CMRR and PSRR plots are [1] R. R. Harrison, "The Design of Integrated Circuits to Observe Brain
shown in Fig. 7. The performance summary and comparison Activity," Proc. IEEE , vol.96, no.7, pp.1203-1216, July 2008.
with previous work are given in Table I. [2] Y.P Xu, et al, “A Bonic Link for Peripheral Nerve Repair,” Proc. 34th
IEEE EBMS Annual Intl. Conf., pp.1335-1338, 28 Aug-1 Sept, 2012.
In-vivo neural recordings have also been carried out using [3] L. Jongwoo, et al., "A 64 Channel Programmable Closed-Loop
this amplifier at an animal lab in the National University Neurostimulator With 8 Channel Neural Amplifier and Logarithmic
Hospital, Singapore. A Wistar rat was fully anesthetized and ADC," IEEE J. Solid-State Circuits, vol 45, pp. 1935-1945, Sept.
surgical procedures were made to expose the left side sciatic 2010.
nerve. A single stainless steel recording electrode was rested [4] V.Majidzadeh, A. Schmid, Y. Leblebici, "Energy Efficient Low-Noise
on the surface of a sciatic nerve while the reference electrode Neural Recording Amplifier With Enhanced Noise Efficiency Factor,"
IEEE Trans. Biomedical Circuits and Systems , vol.5, no.3, pp.262-271,
was inserted on a nearby muscle. To elicit action potentials, June 2011.
the sciatic nerve was lightly pinched with tweezers. Fig. 8 [5] F. Shahrokhi, K. Abdelhalim, D. Serletis, P.L. Carlen, R. Genov, "The
shows the output of the proposed amplifier when the sciatic 128-Channel Fully Differential Digital Integrated Neural Recording
nerve was consecutively pinched thrice. and Stimulation Interface," IEEE Trans. Biomedical Circuits and
Systems, vol.4, no.3, pp.149-161, June 2010.

331