End-Sem Exam - Computer Organization and Architecture (Duration - 1 HR and 5 Minutes) (Time - 11am To 12.05pm) Date - 25-April-2021

4/25/2021 End-Sem Exam: Computer Organization and Architecture (Duration: 1 hr and 5 minutes) (Time: 11am to 12.
05pm) Date: 25-April-2021
End-Sem Exam: Computer Organization

and Architecture (Duration: 1 hr and 5
minutes) (Time: 11am to 12.05pm) Date:
25-April-2021
Your email will be recorded when you submit this form.
Not krunal.s@ahduni.edu.in? Switch account
Attempt as many questions as possible: (Each question is 1 Mark) (Time: 11am to

12.05pm)
In reference to the image given below, answer the question:
[P, B, R, E ]
[R, P, D, E ]
[P, B, D, R ]
[P, R, D, E ]
Clear selection
https://docs.google.com/forms/d/e/1FAIpQLSfiLg1vxqyVgbODYdBUQ72ChCuQVQR0LSHSDbiPOLH1dj_ntA/formResponse 1/15
4/25/2021 End-Sem Exam: Computer Organization and Architecture (Duration: 1 hr and 5 minutes) (Time: 11am to 12.05pm) Date: 25-April-2021
Main memory to Cache memory (Set-Associative Mapping): Given to you:

Address issued by CPU is 32 bits; Index is 24 bits; Set size is 4; Each register is 8
bits; What is the size of the cache (overall total number of bits) ? Write your
answer below in the format: 2^XY (Example: 2^14)
2^30
Given to you: The avg access time for DRAM is 100ns; The hit rate of SRAM is
0.95; The access time for SRAM is 7ns. What is the avg access time for SRAM?
1.2 ns
12 ns
6.4 ns
7.4 ns
Clear selection
In Verilog, we are trying to implement an AND2 gate indirectly using a

MUX8to1_1bit. Then what will be the instantiation?
MUX8to1_1bit inst1({1'b1,A,B}, 8'b00010000, F)
MUX8to1_1bit inst1({1'b0, A,B}, 8'b00000001, F)
MUX8to1_1bit inst1({1'b0,A,B}, 8'b00010000, F)
MUX8to1_1bit inst1({1'b0, A,B}, 8'b00001000, F)
Clear selection
G is wire; P is reg; M we donot know
F is wire; G is reg; P is reg;
F is wire; R is wire; Z is reg;
F is wire; P is reg; J is reg
Clear selection
What is generally true for RISC processor?
The RISC instructions are much more closer to high-level programming languages
Each RISC instruction will get executed in fixed number of phases, and hence, can be
easily pipelined
The bit-size and format of the RISC instructions would be variable
The assembly language program length would be smaller in RISC (as compared to
equivalent program in CISC)
G, K, F, M, P, J
F, S, G, K, M, J
A, B, G, K, M, J
A, B, F, G, K, M, J
Clear selection
In handshake (Req and Ack), based data-transfer from sender to receiver…
The receiver will make the Ack L-to-H after the Req goes L-to-H
The receiver will make the Req H-to-L after the Ack goes L-to-H
The receiver will make the Ack H-to-L after the Req goes L-to-H
The sender will make the Ack L-to-H afer the Req goes L-to-H
Clear selection
An FSM has 12 states. The input of FSM is 3-bits. What is needed to implement
next-state logic of the FSM?
four FFs and twelve 128to1MUX_1bit
four FFs and four 16to1MUX_1bit
four FFs and four 128to1MUX_1bit
three FFs and four 8to1MUX_1bit
Clear selection
16H, 17H, 18H, 19H, 1BH, 1CH, 23H, 24H, 0DH, 0FH, 10H, 11H
16H, 17H, 18H, 19H, 1AH, 1BH, 23H, 24H, 0BH, 0CH, 0DH, 0EH
16H, 17H, 18H, 19H, 1AH, 1BH, 23H, 24H, 0FH, 10H, 11H
16H, 17H, 19H, 1AH, 1BH, 22H, 23H, 24H, 0FH, 10H, 11H
Clear selection
Inst15 in MEM phase and Inst12 in EX phase
Inst15 in WB phase and Inst16 in MEM phase
Inst12 in EX phase and Inst13 in WB phase
Inst15 in WB phase and Inst12 in EX phase
Clear selection
In a memory hierarchy diagram, as we move down (top to bottom)…
The per bit cost of the memories, reduces
The density of the memories, increases
The speed of the memories, improves
All options are valid
Clear selection
MISD
SIMD
SISD
MIMD
Clear selection
In micro-programmed control memory, the last few bits in each word, would
indicate…
information related to PC Update based on the values of flags
information related to the address of the next control word to be fetched
information used by the micro-program sequencer
All options are valid
Clear selection
When an interrupt button is pressed, the processor will…
PUSH the PC onto the stack, and then take a jump to the starting location of the ISR
POP the PC onto the stack, and then take a jump to the starting location of the ISR
POP the PC, and returns
Take a jump to the starting location of the ISR
Clear selection
In a Moore FSM, the next-state is a function of?
both present state and inputs of FSM
only present state
only inputs of FSM
only output of FSM
Clear selection
In reference to the image given below, answer the question. Write your answer
below in the format: [W, X, Y, Z]
[E,Q,P,Z]
Main memory to Cache memory (Direct mapping - Block based): Given to you:
Address issued by CPU is 24 bits; Index is 20 bits; Each block has 16 words; Each
register is 16 bits; How many blocks are there in the cache ? Write your answer
below in the format: 2^XY (Example: 2^14)
2^16
During a "miss", we need to be careful before removing the contents of Cache,

because…
Both Main memory and Cache memory, always have old data
Main memory always has the recent data
Cache memory always has old data
Main memory may have old data
Clear selection
Temporal Locality of Mem references
Spatial Locality of Mem references
Both Spatial and Temporal Locality of Mem references
Does not have Locality of Mem references
Clear selection
The are various methods for implementing the next-state logic for FSM. Which
method "directly" implements the state-table (as though it passes the state
values through the next-state logic)
Two Stages of MUXs, where each MUX is multi-bit
AND-OR or K-map based method
Several MUXs, where each MUX is 1-bit
Decoder and OR gates based method
Clear selection
Forwarding the register from ID phase of Inst12 to WB stage of Inst13
Forwarding the ALU answer from EX phase of Inst12 to WB stage of Inst13
Forwarding the ALU answer from EX phase of Inst12 to ID stage of Inst13
Forwarding the ALU answer from MEM phase of Inst12 to IF stage of Inst13
In memory mapped I/O scheme:
The address space allocated to memory slightly reduces
I/O has separately allocated address space
I/O has 8-it address, and memory has 16-bit address
The address space allocated to memory slightly increases
Clear selection
In reference to the image given below, answer the question. Write your answer in
this format: XYH (Example: ABH)
Your answer
We are given that for a stack, the initial SP is FFFFH. Now, after some time, we
see that, the SP is at 8769H. Under this particular condition, the address to read
would be ?
8770H
8760H
876AH
8768H
Clear selection
Given to you 5000 lines of code. From these, 4500 lines of code can be
parallelized using multiple processors. Remaining lines of code need to run
sequentially. As per Amdahl's law, what is the maximum possible speedup?
4.33
50
1.11
10
1011H
1010H
3070H
306AH
Main memory to Cache memory (Direct mapping): Given to you: Address issued
by CPU is 24 bits; Index is 20 bits; Each register is 16 bits; What is the size of the
cache (overall total number of bits) ? Write your answer below in the format:
2^XY (Example: 2^14)
Your answer
"Magnetic Disk, has 8 plates. Both sides of plate has data. There are 2048 tracks,
and 4096 sectors per track. Each sector has 1024 Bytes. What is the total
capacity of this Magnetic Disk?"
2^37 bits
2^38 bits
2^36 bits
2^40 bits
Clear selection
In reference to the image given below, answer the question. Write your answer in
this format: XYH (Example: ABH)
Your answer
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End-Sem Exam - Computer Organization and Architecture (Duration - 1 HR and 5 Minutes) (Time - 11am To 12.05pm) Date - 25-April-2021

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4/25/2021 End-Sem Exam: Computer Organization and Architecture (Duration: 1 hr and 5 minutes) (Time: 11am to 12.

05pm) Date: 25-April-2021

End-Sem Exam: Computer Organization

Not krunal.s@ahduni.edu.in? Switch account

Attempt as many questions as possible: (Each question is 1 Mark) (Time: 11am to

In reference to the image given below, answer the question:

Main memory to Cache memory (Set-Associative Mapping): Given to you:

In Verilog, we are trying to implement an AND2 gate indirectly using a

MUX8to1_1bit inst1({1'b1,A,B}, 8'b00010000, F)

MUX8to1_1bit inst1({1'b0, A,B}, 8'b00000001, F)

MUX8to1_1bit inst1({1'b0,A,B}, 8'b00010000, F)

MUX8to1_1bit inst1({1'b0, A,B}, 8'b00001000, F)

In reference to the image given below, answer the question:

G is wire; P is reg; M we donot know

F is wire; G is reg; P is reg;

F is wire; R is wire; Z is reg;

F is wire; P is reg; J is reg

What is generally true for RISC processor?

The bit-size and format of the RISC instructions would be variable

In reference to the image given below, answer the question:

In handshake (Req and Ack), based data-transfer from sender to receiver…

four FFs and twelve 128to1MUX_1bit

four FFs and four 16to1MUX_1bit

four FFs and four 128to1MUX_1bit

three FFs and four 8to1MUX_1bit

In reference to the image given below, answer the question:

In reference to the image given below, answer the question:

Inst15 in MEM phase and Inst12 in EX phase

Inst15 in WB phase and Inst16 in MEM phase

Inst12 in EX phase and Inst13 in WB phase

Inst15 in WB phase and Inst12 in EX phase

In a memory hierarchy diagram, as we move down (top to bottom)…

The per bit cost of the memories, reduces

The density of the memories, increases

The speed of the memories, improves

All options are valid

In reference to the image given below, answer the question:

information related to PC Update based on the values of flags

information related to the address of the next control word to be fetched

information used by the micro-program sequencer

All options are valid

When an interrupt button is pressed, the processor will…

POP the PC, and returns

Take a jump to the starting location of the ISR

In a Moore FSM, the next-state is a function of?

both present state and inputs of FSM

only present state

only inputs of FSM

only output of FSM

During a "miss", we need to be careful before removing the contents of Cache,

Main memory always has the recent data

Cache memory always has old data

Main memory may have old data

In reference to the image given below, answer the question:

Temporal Locality of Mem references

Spatial Locality of Mem references

Both Spatial and Temporal Locality of Mem references

Does not have Locality of Mem references

Two Stages of MUXs, where each MUX is multi-bit

AND-OR or K-map based method

Several MUXs, where each MUX is 1-bit

Decoder and OR gates based method