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 - ⑳
-

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a
0
0 ⑯

⑧
A

X
 -

----

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-
- -

- ⑧

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 )Mffflli1
,.,,,_.,,._..,.,,... . · =· .·. _
.
-·. #~Y!!iiJr:{_:.:'*''w111:i,:::·.• · :···
___ · - Data Transfer Techniques
· : ,,. 0;,.J

•
Microcomputer consists of nucroprocessor (µP) , Memory and 1/0 devices. Data ·t h may be
input to a microcomputer from mput . •
devices sueh as keyboard, scanner, swid c .es, data
t t 0/P
• sensors etc. s·um·1arIy data may be
monitoring and acquisition devices, ti outpu o
d between evices
two d such
.
as monitor, printer, controllers etc. In short, data can be trans erre ev1ces
such as;
.• .
(z) Micropr~essor and memory
(it) Microprocessor and 1/0 devices
(iii) Memory & 1/0 devices

Mlcroprocessor~======;ii f/0
Devices

Memory

Fig. 8:1

Generally memories are compatible with microprocessors because of same manufacturing

technologies. But the I/0 devices are generally not speed compatible. So a wide variety of 1/0
devices have wide range of speed. Generally the I/0 devices are slower in speed as compared to
µP. And a slower I/0 device cannot respond to µP immediately. To solve the problem of speed
mismatch between µP and I/0 devices, a number of data transfer techniques have been
developed. ·

M-222
,,....~SFER TECHNIQUF.s
;\ 1
;,:ff.
V pata transfer techniques
d da are class1·ri1ed as .
) programme ta transfer •
~:) vMA (Direct Memory Access)
Data Trans,er
" Techmques
.
I

O
J,
Programmed data transfer OMA
Synchronous

t
Synchronous with delay Burst Mode
Asynchronous Cycle Stealing
Interrupt driven
sJ, pRoGRAMMED DATA TRANSFER
n this scheme, data transfer takes P1ace ·between µP and 1/0 device• completely under the
I
control of the program.
. . These programs are stored m · memory. These programs
' are executed by
µP when an I/0 ~evice is rea~y to transfer data. The µP executes 1/0 or memory based instructions
to access the penpheral device• The external device carries out the functions as indicated by the

program inside the micrr=~l<~o=ry=.====)~\. . _ _...1\

_o_!es

Programmed data transfer techniques are used when a relatively small amount of data is to be
transferred. This is due to the reason that generally this data transfer takes place to or from µP
registers.
Programmed data transfer further can be classified into following types ;
8.1.1. SYNCHRONOUS
- (UNCONDITIONAL)
- DATA TRANSFER
This type of transfer will be used when the speed of I/0 device is equal to the speed of µP and
µP assumes that an 1/0 device is always available i.e. ready for data transfer. So µP reads data
from an input port or writes data to an qtP port Start
without checking whether the 1/0 device is ready
or not. For example ; to display data at an LED ·
port, the µP simply enables the port, transfers
data and goes on to execute the next instruction. execute VO or Memory instruction
Whenever data has to be transfered, user
issues a suitable instruction for device. At the
.end of this instruction, data transfer will b_e
th1
complete. Refer the following flow chart for s Stop
scheme.
 M-224 MICROPRocEs
. S()~
In synchronous data transfer scheme, there is no need of control signal.
Following instructions are used for data transfer ;
MOV M, ABoth ese
OUT port addr instructions are used to transfer data from µP to 0/P device
MOV A, MThes instructions are used to transfer
IN port addr data from 1/P device to µP.
This data transfer technique is faster as compared to asynchronous data transfer. But the s \
. h" . Peed
of all the I/0 devices does not match with the speed of µP, so this tee mque 1s rarely used in 1
data transfer. However many memories are compatible in speed with µP so this technique is uto
w1"th compatl"ble memory d .
ev1ces.
8.1.2. SYNCHRONOUS MODE WITH DELAY
-

This type of transfer will be used when the speed of 1/0 device is less than the speed of µP,
The µP provides a ready 1/P line through which external peripheral can reduce the speed of µp_
The ready line is used to delay machine cycle of µP. When 1/0 device is not ready. it makes
READY low. then the µP adds wait states into a machine cycle.
The number of wait states added is fixed. Hence speed of 1/0 device should be constant and
can be predicted. ·
-
8.1.3. ASYNCHRONOUS DATA TRANSFER (CONDITIONAL)
This type of transfer technique is used when speed of 1/0 device does not matches with µP ,
Start

Read Status Register of the Device

No

' s
n
(!
Execute 1/0 or Memory Instruction b
'p

Stop
 'f~SFER TECHNIQUES
p.!l:f~ I
. unPredictable. In this techniqu p
..,ijclS e,µ has toch•·k I ·
lll,... dY 10 transfer data or not. So in th' . ec t 1e n:admess of 1/0 u,
. ,:ea . . . is technique •l p
ii as 1.en [/0 device 1s ready to ace ' executes an 1/0 or a 1m:1 ,
ot1IY
w,, check whether the device is ept r d
or suppl d
Y ata
·
. fhe p P reads the co111c 1"
gister 10 ea Y or not.
re .Jl mis sche~e,_ µ~ sends a start signal to 1/0 .. .
1 f data 1t md1cates its read· b device· When 1/0 device becomes re.,
fer o • mess y se 11d 1· .
1~: for the response .of 1/0 device. As so ~g a si~nal t~ ~LP. In the meanwhile µP r
wa1ong the data. on as it receives lugh status signal from I/0 de,
it trllnsfers

Start
p

,_ Status
Microprocessor VO
.,, Devices
?
Data

Fig. 8.2
In this techni~ue, µ~ is ~aid to be 1/0 bound i.e. 99·9% time of µPis wasted in checking the
l!Jt
status of 1/0 device, which 1s the biggest disadvantage of this technique .
This technique of data transfer is also known as HANDSHAKE Technique. Because some
signals are exchanged between the 1/0 device and µP before the actual data transfer takes place.
'itb The function of handshake signals is to ensure the readiness of the 1/0 device and to synchronize
the timing of data transfer. Handshake signals prevent the µP from reading the same data more
than once, from a slow device and from writing new data before the device has accepted the
previous data . That is why µP keeps waiting for the response ofl/O device for its readiness.
8.1.4. INTERRUPT
-
DRIVEN DATA TRANSFER
The major drawback of asynchronous data transfer technique was the wastage of time of µP
for waiting the readiness of 1/0 device. This technique counters this drawback. In this technique,
µPdoes not check status of 1/0 devices but an 1/0 device sends an interrupt request signal to the
µPwhenever fr is ready to accept or supply data. So in this technique, µP does not check the
readiness of the dev ices. When device becomes ready, it interrupts the µP through a special input
line called interrupt line i.e. 1/0 device interrupts the normal execution of the main program. The
µPenters into a subroutine to transfer data after the completion of the current instruction. Such
subroutine is known as Interrupt Service Subroutine (ISS). The ISS starts from a particular
memory location. The memory location from which ISS starts is called Interrupt Branch Address
OBS). The ms are different for different 1/0 devices. The µP saves the contents of PC on stack
before starting data transfer. After transmitting data, the µP resumes the execution of the main
Program.
The interrupt driven data transfer technique is preferred over asynchronous data transfer
because in this scheme µP does not waste its time in checking the status (readiness) of all 1/0
devices. '

r
 MICROPROCE
M ter and µP First of all µP s d ~S
e.g. Data has to be transferred between AID conver · ' I. en s the s V·
of Conversion Signal (SOC) 10 the AID converter• There after· lbe µP executes ts main Prog ¼1
• d t µP so it takes some tune to comp! . 1rail)
O
As AID• converter is a slow device as compare
· ak an End' of Conversion • (E/C) signal
. h' ete
h Its ask · jS
When 1t completes or becomes ready, it m es ig Which 1.1
connected at INTR pin of µP . jS

r -;.soc
E/C
INTR,... ADC
MiaOJ)rOC8SSO'

.....
-
-,,,,

Fig. 8.3

Interrupt Request Configurations

There are three types of configurations ;
(z) Single Interrupt line
in«
(ii) Multiple Interrupt line
(iii) Vectored Interrupt line in«
(i) Single Interrupt Line : The µP has only one level and several 1/0 devices are connecteo
to µP. These I/O devices are generally connected through a logical-OR circuit. When a device
interrupt;
(a) µP can't identify which device has requested service (i.e. interrupted)
(b) µP can't determine the priority with which device will be serviced first, ff two or mo
of them interrupted simultaneously.

VO
Device 1

dr

VO
Microprocessor .2.
Devlce2

lntenupt
Line
1/0
Device~

Fig. 8.4
,.......--
J{ANSFER TECHNIQUES .\l -227
;;ff. f • • I '

P for the above problems, µP

· Th' d . checks each
. device m· turn " 11 t 1l1t · 1 11 !1, 1" 1111l· 111 1p 1l· d 111 11 111 1 111 ,
d device pollmg. is evice pollmg scheme 1s very 111 111· , 1111 \ 111 1• 111! ' , 1· \t· 1 \ ,!1 1\\
. caJle • I t L' · I h' · ·
1s . Multiple nterrup me• n t 1s hne, µP has several 11 11t · 1111 111 1n l' 1 ,\· 11 11l · I <>,In Il l '
Ju) ted to each interrupt level.
is connec
VO
Device 1

VO
Device2 i - - - - . . J . - -- ----11o1 Microprocessor

VO
Device 3

Interrupt Unes

Fig. 8.5
In this scheme, when a device interrupts the µP, the µP immediately knows which dev ice has
interrupted. It transfers its program to a specific memory location that has been assigned to the
interrupt line after completing its current instruction execution.

VO Vector Bits
Device 1 ..... ,;

Microprocessor

VO ...._
Vector Bits
Device2 ,,

Fig. 8.6

(iii) Vectored Interrupt Line : In this, each ~nterrupting device provides a unique vector
address. The µP goes directly to specified address of Interrupting device.
B.2. OMA (DIRECT MEMORY ACCESS)
In this technique, data transfer takes place between 1/0 device and memory µP does not
- -

-
Participate in this transfer. As the name indicates 'Direct Memory Access', memory is directly
-
-
-

-- -

lccessed by the 1/0 device, we can also say that memory is synchronised to 1/0 device and not to
~e µP. -

-
-
-

This scheme is used when n bulk amount of e data has to be transferred. Programmed data
ransfer technique is slow because each instruction needs to be fetched and executed. Actually this
 M-228 MICROPRo
CF:ss
scheme is used where speed of 1/0 device is greater than and for the same reason, µp is by %
in this scheme. Pas~
th
- -
In this technique, data transfer is controlled by e 1/0 device or a OMA controller
the control of the buses to OMA controller. So controller tran~fers the d_ata between lll~ µp giv~
1

a l/0 device under its control and therefore, OMA controller is used as interface betw rnory a~
--

een th ·1
-
-

devices and µP . e~I

- -
An 1/0 device sends the HOLD signal to the µP. On receiving a HOLD signal µp .
--
the control of buses as soon as current machine cycle is completed (by executi~ . gives~
· · 1 HLDA to indicate
· g zts cur1
instruction) µP sends a hold icknowledge s1gna
-

th . 111

--
received the HOLD request and it will give up its buses after executing its current . at 11 ha1
. . instruct'10
Then 1/0 device takes over the control of buses and directly transfer data to memory O
r read
from memory. sda1,
-
When this data transfer is done under the control of OMA controller and we know th
-

is used as interface between 1/0 devlce_s and µP . So whenever devices becomes ready t~ DM,
- -
-

their requests to the OMA co~trqller. -- ' Yse

↑
HOLD,
HRQ
-
-
8085 HLDA
Microprocessor _/
HLDA
......
. OMA
IC 1 Muses Controller 8257
.,,,. "'l
' ' I\ ' I\
DRO0'., 'DR04
'V ··-·-----------·--

Memory
1/0 ,.__
Device 1

&

1/0
Device4

Fig. 8.7
In response to this, DMA controller
request) 0/P which is connected t HO requests to the 8085 µP by sending high on HRQ i ·
o LD 1/P of µP 80 8 · · ·ts buse,·
a I so ac knowledges by sending HLDA . · 5 µP responds by tristatmg 1
bus master and carries out the d ta signal to DMA controller. Now OMA controller wolr .

I
. . a transfer at 11igh f the se
(accor,d mg to pnority) device. speed between memory and one o
When Data transfer is completed th DM set · ·
' e A controller returns control to the µP bY
l•' , ~sf'ER TECHNIQUES
•~l•
n~,.
1 <){) ~% l ,.
10"' 011 J,JRQ O/P. The µP then regains the M-229
1
~i • (' 1·oO· l "' control of lhe buses and continues j15 normal

~o &i,~
ry .
~th '
el11J

Send HOLOs·,gna1lo Microprocessor

Check HLDA VP

No

Transfer of Data between

Memory and 1/0 Device

Disable HOLD Signal

Stop

DMA controlled data transfer does not require software, so it is faster as compared to
l"grammed data transfer. This technique is used in any system that requires high data transfer
. ~ee.g. floppy disk drive system, hard disk drive system, CRT system high speed ADC etc. It is
of following two types ;
[RQ (H ~ (i). Burst Mode Technique
buse • ~
,ritswor~
1 ..
(u) Cycle Stealing Technique
~esele1• .2,1, BURST MODE TECHNIQUES
· It is the fastest DMA mode. In this mode, UO device withdraws the DMA request only after
bY i the bytes have been transferred. So µP can't executes its own program. l)uring this transfer,
I
 l\lICROPROc t s
M-230 s%
N number of OMA cycles are added into the machine cycle of µP (where N is 1111mber of bn 1'
be transferred), so instruction execution speed of p P is reduced . · es : 1!
Instruction Cycle
I . {

l l l l l l 6
J, l
OMA
OMA :M2
M1 OMA \I
Cycle N ~:
Cycle I Cycle 2
In this technique, OMA controller sends HOLD Signal and waits for HLDA signal. Aft 111
receiving HLDA, OMA controller gains control of the system bus and executes DMA c,,e,r
JC e~ iV
bl

-
Star1

lnlUallze OMA Controller

Sond HOLD Signal to Microprocessor

-

-
Ct10ck HLDA VP

No
-

S
-
Transfer II Byte

-
lncromont Address Register

(')acremen1 B~ite Counler -

No

↓
Olsoblo HOLD Slgnol W

Stop OQI

transfer one byte. After transferring om.: hyte, it. increments address register and decrements byte the
ij(
 .,.o 'li.GCI INIQUI(~
r-,sJtlJI" . . ,
I

(fl> thl8 Wll)' 11 t n 11111fcr" 1,11 lh

f~ 1g1c.,r , 10 .ont rollcr dhcnhlc11 I IOI I) 131111lytu11 11\ltwucu lt11J 111or y IIIIC I 1/C, ih•vke
I{~ ,,~it rt1'
rrlt•i• i,MA
wn nurmu
(J . I xccutl ) II
o. l , , 1l 11111ll ll(I ~Ip ll«' h l111t' k COII Iml 111 I HI M" I i!IHI
10

~;::11,j 9fl!ALINO f l!C~NIOUI! _011 _BINQLI! BYTI! TRANBPl!R OMA

,1 g, a'I cellll iQUC, ()110 byte o( d111u 111 II IIIINlerna.l Ill II tlt uc ll litl utter 111111 , l>M/\ 1,,011tn 1II• I
••·11 ,111s I1'l request by dlsubli!I¥ IIOLD !ilK11ul, II r(H 1ctlvc11 110 1 I) 11l1<11al nnl y when the t1ex 1
1 s tl " d8 to bo tronslorrcd . So DMA . . . · · . u I1
niir•"'' nee · , . · co1111 ollur "Ive" control of hu11 h11ck to µ , 1
~11 ,cru11Jl:cesslvc byte trunstor, This method rcducc11 l11tcr l'crc11cc in µP'11 actlvltlc11 . 'I hi,,
11toll su can be complotoly ellmlnutcll hy dc8lanlna nn h11crl'ucl nlt ci rcuitry which can ,n.c "I
,1 t.!re11ce
hr f '';c1es oil Iy
when CPU Is not uslna bus "'Ylltt, nt.
,,,..__ __
11
t\) ~C 811rt

lnltlnllzo OMA Controllnr

=
Sond 'HOLD' to Mloroproco1aor

Chock 'HLOA' 1/P

No

Dlsable HLOA Signal

Increment Address Register

Decrement Byte Counter Register

No

Stop

i~' this mOde, DMA controller sends HOLD-signal to the µP and waits for HLDA signal.
1 HL · ·
, ne DMA c g DA signal, DMA controlle~ g~ms control of ~e system bus and ~xecutes only
ytc ~e sy81e111 [cle. After transferring one byte, 1t disables H?LD signal. Now µP gams control on
UOLD s·1gna1ust and
h executes next machine cycle. If count 1s not zero, the OMA controller sends
0
t e µp and transfers next byte of data block.
 MICROPRoc:::,
M-232 tsso
~s
8.3. SERIAL 1/0 DATA TRANSFER
Microprocessor is a parallel device which works on parallel data in parallel for 111 nd
transfer also takes place in parallel form as this is the fasteS t way· ~owever, there aa da~
situations where data transfer has to be accomplished serially, by movmg one bit at a /e 1111 n1any
typical situations in which parallel data transfer is not viable are as follows ; ' · l~
t
(1) Serial mode is preferred in some situations due_ to coS considerations. ~s serial 111
requires only one pair of wires for data transfer,
. 1t reduces
. thed cost hof cabling ' rn·in1ni'
. 1ode
the noise effect and decreases the complexity and brmgs own t e cost of interfac·Ze1 1
ckts needed for serial data transfer. ng
(il) If data are to be transmitted over the transmission lines, the parallel data shall ha
converted into serial form. e.g. telephone network, microwave link etc. veto be
(ii1) Most of the peripheral devices are serial in nature e.g. CRT terminal, magnetic ta
cassette, telephone line, telepril\ter etc. . Pe and
Therefore, serial 1/0 is extensively used for data transmission between peripheral devi
microprocessor. Since microprocessors _perform internal operations in paralle I, that i:e
conversion of data from parallel to serial and vice-versa is required to provide communic ~hy
between the microprocessor and the serial 1/0. The 8085 microprocess~r provides seriat;on 1
communication via SID (Serial Input Data) and SOD (Serial Output Data) Imes. The serial d ~
entered through SID input and serial data is outputted on SOD output. These two line:tai,
specially designed for software controlled serial 1/0 using two instructions RIM & SIM. Bott
these are single byte instructions. The main advantage of serial 1/0 lines is that they facilitated of
transmission in serial form without using any extra hardware. a~
8.3.1. SERIAL OUTPUT DATA (SOD)
The data is serially outputted on this line with the help of SIM instruction. SIM instructi0
sends the contents of accumulator to the output. The data to be output is placed in the MSB ~
accumulator and by rotating the contents ~f accumulator and making bit D6 = 1 (which is seri:I
output Data Enable). Now after the execution of SIM instruction, the carry bit can be transmitted
through bit D position. Same process is employed for other bits also to output the data in seri~
7
form. · ·
So as the SIM instruction sends the contents of the accumulator to the serial output line.
Therefore before executing the SIM instruction, accumulator must be loaded with proper data.
The process of transmitting data is as follows ;
MVI A, 80 H load 80 H to accumulator to output data i.e. in D7 bit and
RAR Rotate the accumulator right by one bit through carry.
Carry D1 ;;ind D7 D6 and Do carry
SIM Output D7
8.3.2. SERIAL INPUT DATA (SID)
The data is serially received through SID line with the help of RIM instruction. The execution
of RIM instruction forces the data on the SID line into MSB position of the accumulator. B!11
executing RAR instruction, D1 bit of accumulator can be shifted to the D6 bit position. 1h 1
process is repeated 8 times to convert the serial data into parallel form .