Q71. If you have both IR drop and congestion how will you fix it?

 Spread macros

 Spread standard cells

 Increase strap width

 Increase number of straps

 Use proper blockage

Q72. Is increasing power line width and providing more number of straps are the
only solution to IR drop?
 Spread macros

 Spread standard cells

 Use proper blockage

Q73. what is tie-high and tie-low cells and where it is used?

Tie-high and Tie-Low cells are used to connect the gate of the transistor to either power or ground.
In deep sub-micron processes, if the gate is connected to power/ground the transistor might be
turned on/off due to power or ground bounce. The suggestion from foundry is to use tie cells for this
purpose. These cells are part of standard-cell library. The cells which require Vdd, comes and
connect to Tie high... (so tie high is a power supply cell). while the cells which wants Vss connects
itself to Tie-low.

Q74. What are the placement optimization methods are used in SOCE and Astro
Tool Design?
 PreplaceOpt

 Inplace Opt

 Post Place Opt

 Incremental Opt
  Timing Driven

 Congestion Driven

Q75. What is Scan chain reordering? How will it impact Physical Design?
Grouping together cells that belong to a same region of the chip to allow scan connections only
between cells of a same region is called scan Clustering. Clustering also allows the degree of
congestion and timing violations to be eliminated.

Types of scan cell ordering

 Cluster based scan cell order

 power - driven scan cell order.

 Power optimized routing constrained scan cell order.

Power driven scan cell order

 Determining the chaining of the scan cells so as to minimize the toggling rate in the scan
chain during shifting operations.

 Identifying the input and output of the scan cells of the scan chain to limit the propagation of
transitions during the scan operations.

 If scan chain wire length is reduced, it will increase the wire ability or reduces the chip die
area while at the same time increasing signal speed by reducing capacitive loading effects
that share register pins with the scan chains.

 After scan synthesis, connecting all the scan cells together may cause routing congestion
during PAR. This cause area overhead an and timing closure issues.

 Scan chain optimization- task of finding a new order for connecting the scan elements such
that the wire length of the scan chain is minimized

Q76. In scan chains if some flip flops are +ve edge triggered and remaining flip
flops are -ve edge triggered how it behaves?
 For designs with both positive and negative clocked flops, the scan insertion tool will always
route the scan chain so that the negative clocked flops come before the positive edge flops
in the chain. This avoids the need of lockup latch.
  For the same clock domain, the negedge flops will always capture the data just captured into
the posedge flops on the posedge of the clock.

 For the multiple clock domains, it all depends upon how the clock trees are balanced. If the
clock domains are completely asynchronous, ATPG has to mask the receiving flops.

Q77. What you mean by scan chain reordering?

Answer1:
Based on timing and congestion the tool optimally places standard cells. While doing so, if scan
chains are detached, it can break the chain ordering (which is done by a scan insertion tool like DFT
compiler from Synopsys) and can reorder to optimize it.... it maintains the number of flops in a chain.

Answer2:
During placement, the optimization may make the scan chain difficult to route due to congestion.
Hence the tool will re-order the chain to reduce congestion. This sometimes increases hold time
problems in the chain. To overcome these buffers may have to be inserted into the scan path. It may
not be able to maintain the scan chain length exactly. It cannot swap cell from different clock
domains.

Q78. What is JTAG?

Answer1:

 JTAG is acronym for "Joint Test Action Group”. This is also called as IEEE 1149.1 standard
for Standard Test Access Port and Boundary-Scan Architecture. This is used as one of the
DFT techniques.

Answer2:

 JTAG (Joint Test Action Group) boundary scan is a method of testing ICs and their
interconnections. This used a shift register built into the chip so that inputs could be shifted in
and the resulting outputs could be shifted out. JTAG requires four I/O pins called clock, input
data, output data, and state machine mode control.

 The uses of JTAG expanded to debugging software for embedded microcontrollers. This
eliminates the need for in-circuit emulators which is costlier. Also JTAG is used in
downloading configuration bit streams to FPGAs.

 JTAG cells are also known as boundary scan cells, are small circuits placed just inside the
I/O cells. The purpose is to enable data to/from the I/O through the boundary scan chain.
The interface to these scan chains are called the TAP (Test Access Port), and the operation
 of the chains and the TAP are controlled by a JTAG controller inside the chip that
implements JTAG.

Q79. What is CTS?

 Clock tree synthesis is a process of balancing clock skew and minimizing insertion delay in
order to meet timing, power requirements and other constraints.

 Clock tree synthesis provides the following features to achieve timing closure:

 Global skew clock tree synthesis

 Local skew clock tree synthesis

 Real clock useful skew clock tree synthesis

 Ideal clock useful skew clock tree synthesis

 Interlock delay balance

 Splitting a clock net to replicate the clock gating cells

 Clock tree optimization

 High-fanout net synthesis

 Concurrent multiple corners (worst-case and best-case) clock tree synthesis

 Concurrent multiple clocks with domain overlap clock tree synthesis

Q80. What are the SDC constraints associated with Clock tree?


 If there are no create_clock statements in the SDC file loaded, CTS will not run. Make sure
you have at least one create_clock in your SDC file. If you define create_clock on a pin that
is not present physically and is only present in the hierarchical netlist, CTS will not be able to
run.

 It is good practice to have set_clock_transition, set_clock_latency, and set_clock_uncertainty

also defined.

 Clock tree synthesis has the following clock tree constraints:

 Maximum transition delay

 Maximum load capacitance

 Maximum fanout

 Maximum buffer level